./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.02.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version dbf71c69 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4e9a4131-f225-4804-84c0-dc676b3b2fdb/bin/uautomizer-J5u9QxTXDZ/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4e9a4131-f225-4804-84c0-dc676b3b2fdb/bin/uautomizer-J5u9QxTXDZ/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4e9a4131-f225-4804-84c0-dc676b3b2fdb/bin/uautomizer-J5u9QxTXDZ/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4e9a4131-f225-4804-84c0-dc676b3b2fdb/bin/uautomizer-J5u9QxTXDZ/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.02.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4e9a4131-f225-4804-84c0-dc676b3b2fdb/bin/uautomizer-J5u9QxTXDZ/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4e9a4131-f225-4804-84c0-dc676b3b2fdb/bin/uautomizer-J5u9QxTXDZ --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 44ef362a593e25f5681bc4a034b065cd86559bd3dd750386bca2a1f270891ccd --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-dbf71c6-m [2022-10-17 10:28:17,001 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-10-17 10:28:17,007 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-10-17 10:28:17,066 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-10-17 10:28:17,067 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-10-17 10:28:17,071 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-10-17 10:28:17,074 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-10-17 10:28:17,081 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-10-17 10:28:17,084 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-10-17 10:28:17,090 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-10-17 10:28:17,091 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-10-17 10:28:17,094 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-10-17 10:28:17,095 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-10-17 10:28:17,098 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-10-17 10:28:17,101 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-10-17 10:28:17,103 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-10-17 10:28:17,105 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-10-17 10:28:17,106 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-10-17 10:28:17,108 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-10-17 10:28:17,117 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-10-17 10:28:17,119 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-10-17 10:28:17,121 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-10-17 10:28:17,126 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-10-17 10:28:17,128 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-10-17 10:28:17,139 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-10-17 10:28:17,140 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-10-17 10:28:17,141 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-10-17 10:28:17,143 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-10-17 10:28:17,144 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-10-17 10:28:17,145 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-10-17 10:28:17,146 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-10-17 10:28:17,149 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-10-17 10:28:17,151 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-10-17 10:28:17,152 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-10-17 10:28:17,154 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-10-17 10:28:17,154 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-10-17 10:28:17,155 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-10-17 10:28:17,155 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-10-17 10:28:17,155 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-10-17 10:28:17,156 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-10-17 10:28:17,157 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-10-17 10:28:17,158 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4e9a4131-f225-4804-84c0-dc676b3b2fdb/bin/uautomizer-J5u9QxTXDZ/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-10-17 10:28:17,214 INFO L113 SettingsManager]: Loading preferences was successful [2022-10-17 10:28:17,215 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-10-17 10:28:17,216 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-10-17 10:28:17,216 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-10-17 10:28:17,217 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-10-17 10:28:17,218 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-10-17 10:28:17,218 INFO L138 SettingsManager]: * Use SBE=true [2022-10-17 10:28:17,218 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-10-17 10:28:17,219 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-10-17 10:28:17,219 INFO L138 SettingsManager]: * Use old map elimination=false [2022-10-17 10:28:17,220 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-10-17 10:28:17,221 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-10-17 10:28:17,221 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-10-17 10:28:17,221 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-10-17 10:28:17,222 INFO L138 SettingsManager]: * sizeof long=4 [2022-10-17 10:28:17,222 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-10-17 10:28:17,222 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-10-17 10:28:17,222 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-10-17 10:28:17,223 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-10-17 10:28:17,223 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-10-17 10:28:17,223 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-10-17 10:28:17,224 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-10-17 10:28:17,224 INFO L138 SettingsManager]: * sizeof long double=12 [2022-10-17 10:28:17,224 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-10-17 10:28:17,224 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-10-17 10:28:17,225 INFO L138 SettingsManager]: * Use constant arrays=true [2022-10-17 10:28:17,233 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-10-17 10:28:17,234 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-10-17 10:28:17,234 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-10-17 10:28:17,234 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-10-17 10:28:17,235 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-10-17 10:28:17,236 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-10-17 10:28:17,236 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4e9a4131-f225-4804-84c0-dc676b3b2fdb/bin/uautomizer-J5u9QxTXDZ/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4e9a4131-f225-4804-84c0-dc676b3b2fdb/bin/uautomizer-J5u9QxTXDZ Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 44ef362a593e25f5681bc4a034b065cd86559bd3dd750386bca2a1f270891ccd [2022-10-17 10:28:17,566 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-10-17 10:28:17,590 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-10-17 10:28:17,593 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-10-17 10:28:17,595 INFO L271 PluginConnector]: Initializing CDTParser... [2022-10-17 10:28:17,596 INFO L275 PluginConnector]: CDTParser initialized [2022-10-17 10:28:17,597 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4e9a4131-f225-4804-84c0-dc676b3b2fdb/bin/uautomizer-J5u9QxTXDZ/../../sv-benchmarks/c/systemc/token_ring.02.cil-1.c [2022-10-17 10:28:17,672 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4e9a4131-f225-4804-84c0-dc676b3b2fdb/bin/uautomizer-J5u9QxTXDZ/data/f847f465b/b5b478c9eb7b4929b7970f4e5024cf73/FLAG2998e89e3 [2022-10-17 10:28:18,230 INFO L306 CDTParser]: Found 1 translation units. [2022-10-17 10:28:18,230 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4e9a4131-f225-4804-84c0-dc676b3b2fdb/sv-benchmarks/c/systemc/token_ring.02.cil-1.c [2022-10-17 10:28:18,243 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4e9a4131-f225-4804-84c0-dc676b3b2fdb/bin/uautomizer-J5u9QxTXDZ/data/f847f465b/b5b478c9eb7b4929b7970f4e5024cf73/FLAG2998e89e3 [2022-10-17 10:28:18,539 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4e9a4131-f225-4804-84c0-dc676b3b2fdb/bin/uautomizer-J5u9QxTXDZ/data/f847f465b/b5b478c9eb7b4929b7970f4e5024cf73 [2022-10-17 10:28:18,542 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-10-17 10:28:18,544 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-10-17 10:28:18,546 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-10-17 10:28:18,546 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-10-17 10:28:18,550 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-10-17 10:28:18,551 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.10 10:28:18" (1/1) ... [2022-10-17 10:28:18,554 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6506cc05 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:28:18, skipping insertion in model container [2022-10-17 10:28:18,554 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.10 10:28:18" (1/1) ... [2022-10-17 10:28:18,562 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-10-17 10:28:18,627 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-10-17 10:28:18,824 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4e9a4131-f225-4804-84c0-dc676b3b2fdb/sv-benchmarks/c/systemc/token_ring.02.cil-1.c[671,684] [2022-10-17 10:28:18,887 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-10-17 10:28:18,898 INFO L203 MainTranslator]: Completed pre-run [2022-10-17 10:28:18,925 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4e9a4131-f225-4804-84c0-dc676b3b2fdb/sv-benchmarks/c/systemc/token_ring.02.cil-1.c[671,684] [2022-10-17 10:28:18,986 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-10-17 10:28:19,006 INFO L208 MainTranslator]: Completed translation [2022-10-17 10:28:19,007 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:28:19 WrapperNode [2022-10-17 10:28:19,007 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-10-17 10:28:19,009 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-10-17 10:28:19,009 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-10-17 10:28:19,009 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-10-17 10:28:19,018 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:28:19" (1/1) ... [2022-10-17 10:28:19,028 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:28:19" (1/1) ... [2022-10-17 10:28:19,068 INFO L138 Inliner]: procedures = 32, calls = 37, calls flagged for inlining = 32, calls inlined = 49, statements flattened = 594 [2022-10-17 10:28:19,069 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-10-17 10:28:19,070 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-10-17 10:28:19,070 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-10-17 10:28:19,070 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-10-17 10:28:19,080 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:28:19" (1/1) ... [2022-10-17 10:28:19,081 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:28:19" (1/1) ... [2022-10-17 10:28:19,085 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:28:19" (1/1) ... [2022-10-17 10:28:19,097 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:28:19" (1/1) ... [2022-10-17 10:28:19,109 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:28:19" (1/1) ... [2022-10-17 10:28:19,130 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:28:19" (1/1) ... [2022-10-17 10:28:19,133 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:28:19" (1/1) ... [2022-10-17 10:28:19,136 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:28:19" (1/1) ... [2022-10-17 10:28:19,142 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-10-17 10:28:19,143 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-10-17 10:28:19,143 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-10-17 10:28:19,144 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-10-17 10:28:19,145 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:28:19" (1/1) ... [2022-10-17 10:28:19,168 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:28:19,184 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4e9a4131-f225-4804-84c0-dc676b3b2fdb/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:28:19,204 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4e9a4131-f225-4804-84c0-dc676b3b2fdb/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:28:19,229 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4e9a4131-f225-4804-84c0-dc676b3b2fdb/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-10-17 10:28:19,264 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-10-17 10:28:19,264 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-10-17 10:28:19,265 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-10-17 10:28:19,265 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-10-17 10:28:19,340 INFO L235 CfgBuilder]: Building ICFG [2022-10-17 10:28:19,342 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-10-17 10:28:20,217 INFO L276 CfgBuilder]: Performing block encoding [2022-10-17 10:28:20,238 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-10-17 10:28:20,245 INFO L300 CfgBuilder]: Removed 5 assume(true) statements. [2022-10-17 10:28:20,248 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 17.10 10:28:20 BoogieIcfgContainer [2022-10-17 10:28:20,248 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-10-17 10:28:20,249 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-10-17 10:28:20,249 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-10-17 10:28:20,254 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-10-17 10:28:20,255 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-10-17 10:28:20,255 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 17.10 10:28:18" (1/3) ... [2022-10-17 10:28:20,256 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@72c59f9c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.10 10:28:20, skipping insertion in model container [2022-10-17 10:28:20,256 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-10-17 10:28:20,257 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:28:19" (2/3) ... [2022-10-17 10:28:20,257 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@72c59f9c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.10 10:28:20, skipping insertion in model container [2022-10-17 10:28:20,257 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-10-17 10:28:20,257 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 17.10 10:28:20" (3/3) ... [2022-10-17 10:28:20,259 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.02.cil-1.c [2022-10-17 10:28:20,348 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-10-17 10:28:20,348 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-10-17 10:28:20,349 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-10-17 10:28:20,349 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-10-17 10:28:20,349 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-10-17 10:28:20,349 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-10-17 10:28:20,349 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-10-17 10:28:20,350 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-10-17 10:28:20,356 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 231 states, 230 states have (on average 1.5347826086956522) internal successors, (353), 230 states have internal predecessors, (353), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:28:20,396 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 184 [2022-10-17 10:28:20,396 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:28:20,396 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:28:20,407 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:28:20,408 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:28:20,408 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-10-17 10:28:20,409 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 231 states, 230 states have (on average 1.5347826086956522) internal successors, (353), 230 states have internal predecessors, (353), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:28:20,423 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 184 [2022-10-17 10:28:20,423 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:28:20,424 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:28:20,427 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:28:20,427 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:28:20,437 INFO L748 eck$LassoCheckResult]: Stem: 219#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 160#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 188#L516true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 185#L224true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 76#L231true assume !(1 == ~m_i~0);~m_st~0 := 2; 3#L231-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 128#L236-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 125#L241-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 28#L344true assume !(0 == ~M_E~0); 181#L344-2true assume !(0 == ~T1_E~0); 155#L349-1true assume !(0 == ~T2_E~0); 37#L354-1true assume 0 == ~E_M~0;~E_M~0 := 1; 192#L359-1true assume !(0 == ~E_1~0); 35#L364-1true assume !(0 == ~E_2~0); 163#L369-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 91#L166true assume 1 == ~m_pc~0; 150#L167true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 166#L177true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27#L178true activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 209#L425true assume !(0 != activate_threads_~tmp~1#1); 225#L425-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 100#L185true assume !(1 == ~t1_pc~0); 40#L185-2true is_transmit1_triggered_~__retres1~1#1 := 0; 60#L196true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 69#L197true activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 65#L433true assume !(0 != activate_threads_~tmp___0~0#1); 164#L433-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 110#L204true assume 1 == ~t2_pc~0; 70#L205true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 129#L215true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 207#L216true activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 18#L441true assume !(0 != activate_threads_~tmp___1~0#1); 94#L441-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 115#L382true assume !(1 == ~M_E~0); 12#L382-2true assume 1 == ~T1_E~0;~T1_E~0 := 2; 82#L387-1true assume !(1 == ~T2_E~0); 189#L392-1true assume !(1 == ~E_M~0); 105#L397-1true assume !(1 == ~E_1~0); 134#L402-1true assume !(1 == ~E_2~0); 95#L407-1true assume { :end_inline_reset_delta_events } true; 177#L553-2true [2022-10-17 10:28:20,439 INFO L750 eck$LassoCheckResult]: Loop: 177#L553-2true assume !false; 230#L554true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 231#L319true assume !true; 31#L334true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 220#L224-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 195#L344-3true assume !(0 == ~M_E~0); 2#L344-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 77#L349-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 30#L354-3true assume 0 == ~E_M~0;~E_M~0 := 1; 102#L359-3true assume 0 == ~E_1~0;~E_1~0 := 1; 75#L364-3true assume 0 == ~E_2~0;~E_2~0 := 1; 73#L369-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 58#L166-12true assume !(1 == ~m_pc~0); 171#L166-14true is_master_triggered_~__retres1~0#1 := 0; 43#L177-4true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 81#L178-4true activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 55#L425-12true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 118#L425-14true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 203#L185-12true assume 1 == ~t1_pc~0; 147#L186-4true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 145#L196-4true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 199#L197-4true activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 196#L433-12true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 135#L433-14true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 198#L204-12true assume !(1 == ~t2_pc~0); 48#L204-14true is_transmit2_triggered_~__retres1~2#1 := 0; 103#L215-4true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41#L216-4true activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 92#L441-12true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 68#L441-14true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29#L382-3true assume 1 == ~M_E~0;~M_E~0 := 2; 78#L382-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 114#L387-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 142#L392-3true assume 1 == ~E_M~0;~E_M~0 := 2; 8#L397-3true assume 1 == ~E_1~0;~E_1~0 := 2; 121#L402-3true assume 1 == ~E_2~0;~E_2~0 := 2; 14#L407-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 7#L254-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 19#L271-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 132#L272-1true start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 107#L572true assume !(0 == start_simulation_~tmp~3#1); 149#L572-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 26#L254-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 79#L271-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 17#L272-2true stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 197#L527true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 86#L534true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 190#L535true start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 183#L585true assume !(0 != start_simulation_~tmp___0~1#1); 177#L553-2true [2022-10-17 10:28:20,445 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:28:20,445 INFO L85 PathProgramCache]: Analyzing trace with hash 332551043, now seen corresponding path program 1 times [2022-10-17 10:28:20,456 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:28:20,456 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [321578903] [2022-10-17 10:28:20,457 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:28:20,457 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:28:20,567 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:28:20,719 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:28:20,720 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:28:20,720 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [321578903] [2022-10-17 10:28:20,721 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [321578903] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:28:20,722 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:28:20,722 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:28:20,724 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2143192061] [2022-10-17 10:28:20,725 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:28:20,731 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:28:20,732 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:28:20,732 INFO L85 PathProgramCache]: Analyzing trace with hash 1618732660, now seen corresponding path program 1 times [2022-10-17 10:28:20,732 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:28:20,733 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1955740505] [2022-10-17 10:28:20,733 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:28:20,733 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:28:20,748 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:28:20,819 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:28:20,819 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:28:20,820 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1955740505] [2022-10-17 10:28:20,820 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1955740505] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:28:20,820 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:28:20,820 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-10-17 10:28:20,821 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [540991240] [2022-10-17 10:28:20,821 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:28:20,822 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:28:20,824 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:28:20,873 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:28:20,874 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:28:20,880 INFO L87 Difference]: Start difference. First operand has 231 states, 230 states have (on average 1.5347826086956522) internal successors, (353), 230 states have internal predecessors, (353), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 3 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:28:20,930 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:28:20,931 INFO L93 Difference]: Finished difference Result 230 states and 340 transitions. [2022-10-17 10:28:20,932 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 230 states and 340 transitions. [2022-10-17 10:28:20,941 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 182 [2022-10-17 10:28:20,950 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 230 states to 225 states and 335 transitions. [2022-10-17 10:28:20,951 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 225 [2022-10-17 10:28:20,953 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 225 [2022-10-17 10:28:20,953 INFO L73 IsDeterministic]: Start isDeterministic. Operand 225 states and 335 transitions. [2022-10-17 10:28:20,955 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:28:20,956 INFO L218 hiAutomatonCegarLoop]: Abstraction has 225 states and 335 transitions. [2022-10-17 10:28:20,976 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 225 states and 335 transitions. [2022-10-17 10:28:21,001 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 225 to 225. [2022-10-17 10:28:21,003 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 225 states, 225 states have (on average 1.488888888888889) internal successors, (335), 224 states have internal predecessors, (335), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:28:21,005 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 225 states to 225 states and 335 transitions. [2022-10-17 10:28:21,007 INFO L240 hiAutomatonCegarLoop]: Abstraction has 225 states and 335 transitions. [2022-10-17 10:28:21,017 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:28:21,021 INFO L428 stractBuchiCegarLoop]: Abstraction has 225 states and 335 transitions. [2022-10-17 10:28:21,021 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-10-17 10:28:21,021 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 225 states and 335 transitions. [2022-10-17 10:28:21,026 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 182 [2022-10-17 10:28:21,026 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:28:21,026 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:28:21,029 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:28:21,030 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:28:21,031 INFO L748 eck$LassoCheckResult]: Stem: 694#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 672#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 673#L516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 683#L224 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 600#L231 assume 1 == ~m_i~0;~m_st~0 := 0; 472#L231-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 473#L236-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 648#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 520#L344 assume !(0 == ~M_E~0); 521#L344-2 assume !(0 == ~T1_E~0); 669#L349-1 assume !(0 == ~T2_E~0); 539#L354-1 assume 0 == ~E_M~0;~E_M~0 := 1; 540#L359-1 assume !(0 == ~E_1~0); 534#L364-1 assume !(0 == ~E_2~0); 535#L369-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 613#L166 assume 1 == ~m_pc~0; 614#L167 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 662#L177 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 518#L178 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 519#L425 assume !(0 != activate_threads_~tmp~1#1); 692#L425-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 623#L185 assume !(1 == ~t1_pc~0); 545#L185-2 is_transmit1_triggered_~__retres1~1#1 := 0; 546#L196 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 583#L197 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 588#L433 assume !(0 != activate_threads_~tmp___0~0#1); 589#L433-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 634#L204 assume 1 == ~t2_pc~0; 592#L205 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 593#L215 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 650#L216 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 501#L441 assume !(0 != activate_threads_~tmp___1~0#1); 502#L441-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 617#L382 assume !(1 == ~M_E~0); 491#L382-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 492#L387-1 assume !(1 == ~T2_E~0); 603#L392-1 assume !(1 == ~E_M~0); 627#L397-1 assume !(1 == ~E_1~0); 628#L402-1 assume !(1 == ~E_2~0); 618#L407-1 assume { :end_inline_reset_delta_events } true; 619#L553-2 [2022-10-17 10:28:21,032 INFO L750 eck$LassoCheckResult]: Loop: 619#L553-2 assume !false; 679#L554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 674#L319 assume !false; 651#L282 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 553#L254 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 554#L271 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 543#L272 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 544#L286 assume !(0 != eval_~tmp~0#1); 526#L334 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 527#L224-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 688#L344-3 assume !(0 == ~M_E~0); 470#L344-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 471#L349-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 524#L354-3 assume 0 == ~E_M~0;~E_M~0 := 1; 525#L359-3 assume 0 == ~E_1~0;~E_1~0 := 1; 599#L364-3 assume 0 == ~E_2~0;~E_2~0 := 1; 597#L369-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 579#L166-12 assume 1 == ~m_pc~0; 580#L167-4 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 549#L177-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 550#L178-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 573#L425-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 574#L425-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 643#L185-12 assume !(1 == ~t1_pc~0); 531#L185-14 is_transmit1_triggered_~__retres1~1#1 := 0; 532#L196-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 660#L197-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 689#L433-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 653#L433-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 654#L204-12 assume 1 == ~t2_pc~0; 675#L205-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 558#L215-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 547#L216-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 548#L441-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 591#L441-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 522#L382-3 assume 1 == ~M_E~0;~M_E~0 := 2; 523#L382-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 601#L387-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 637#L392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 484#L397-3 assume 1 == ~E_1~0;~E_1~0 := 2; 485#L402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 495#L407-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 481#L254-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 482#L271-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 503#L272-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 631#L572 assume !(0 == start_simulation_~tmp~3#1); 542#L572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 515#L254-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 516#L271-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 499#L272-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 500#L527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 609#L534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 610#L535 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 682#L585 assume !(0 != start_simulation_~tmp___0~1#1); 619#L553-2 [2022-10-17 10:28:21,033 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:28:21,033 INFO L85 PathProgramCache]: Analyzing trace with hash 726917829, now seen corresponding path program 1 times [2022-10-17 10:28:21,033 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:28:21,034 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1735445737] [2022-10-17 10:28:21,034 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:28:21,034 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:28:21,063 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:28:21,154 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:28:21,154 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:28:21,154 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1735445737] [2022-10-17 10:28:21,155 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1735445737] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:28:21,155 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:28:21,155 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:28:21,155 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1456086848] [2022-10-17 10:28:21,155 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:28:21,156 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:28:21,156 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:28:21,157 INFO L85 PathProgramCache]: Analyzing trace with hash 1606950136, now seen corresponding path program 1 times [2022-10-17 10:28:21,157 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:28:21,157 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1527751731] [2022-10-17 10:28:21,157 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:28:21,158 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:28:21,192 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:28:21,368 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:28:21,369 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:28:21,369 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1527751731] [2022-10-17 10:28:21,369 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1527751731] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:28:21,370 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:28:21,370 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-10-17 10:28:21,370 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1714251584] [2022-10-17 10:28:21,370 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:28:21,371 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:28:21,371 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:28:21,372 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:28:21,372 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:28:21,372 INFO L87 Difference]: Start difference. First operand 225 states and 335 transitions. cyclomatic complexity: 111 Second operand has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 3 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:28:21,395 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:28:21,396 INFO L93 Difference]: Finished difference Result 225 states and 334 transitions. [2022-10-17 10:28:21,396 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 225 states and 334 transitions. [2022-10-17 10:28:21,399 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 182 [2022-10-17 10:28:21,403 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 225 states to 225 states and 334 transitions. [2022-10-17 10:28:21,403 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 225 [2022-10-17 10:28:21,404 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 225 [2022-10-17 10:28:21,404 INFO L73 IsDeterministic]: Start isDeterministic. Operand 225 states and 334 transitions. [2022-10-17 10:28:21,406 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:28:21,406 INFO L218 hiAutomatonCegarLoop]: Abstraction has 225 states and 334 transitions. [2022-10-17 10:28:21,407 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 225 states and 334 transitions. [2022-10-17 10:28:21,419 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 225 to 225. [2022-10-17 10:28:21,420 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 225 states, 225 states have (on average 1.4844444444444445) internal successors, (334), 224 states have internal predecessors, (334), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:28:21,422 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 225 states to 225 states and 334 transitions. [2022-10-17 10:28:21,422 INFO L240 hiAutomatonCegarLoop]: Abstraction has 225 states and 334 transitions. [2022-10-17 10:28:21,422 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:28:21,423 INFO L428 stractBuchiCegarLoop]: Abstraction has 225 states and 334 transitions. [2022-10-17 10:28:21,423 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-10-17 10:28:21,424 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 225 states and 334 transitions. [2022-10-17 10:28:21,426 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 182 [2022-10-17 10:28:21,426 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:28:21,426 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:28:21,429 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:28:21,429 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:28:21,429 INFO L748 eck$LassoCheckResult]: Stem: 1153#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 1131#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 1132#L516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1142#L224 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1059#L231 assume 1 == ~m_i~0;~m_st~0 := 0; 931#L231-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 932#L236-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1107#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 979#L344 assume !(0 == ~M_E~0); 980#L344-2 assume !(0 == ~T1_E~0); 1128#L349-1 assume !(0 == ~T2_E~0); 998#L354-1 assume 0 == ~E_M~0;~E_M~0 := 1; 999#L359-1 assume !(0 == ~E_1~0); 993#L364-1 assume !(0 == ~E_2~0); 994#L369-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1072#L166 assume 1 == ~m_pc~0; 1073#L167 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1121#L177 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 977#L178 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 978#L425 assume !(0 != activate_threads_~tmp~1#1); 1151#L425-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1082#L185 assume !(1 == ~t1_pc~0); 1004#L185-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1005#L196 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1042#L197 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1047#L433 assume !(0 != activate_threads_~tmp___0~0#1); 1048#L433-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1093#L204 assume 1 == ~t2_pc~0; 1051#L205 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1052#L215 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1109#L216 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 960#L441 assume !(0 != activate_threads_~tmp___1~0#1); 961#L441-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1076#L382 assume !(1 == ~M_E~0); 950#L382-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 951#L387-1 assume !(1 == ~T2_E~0); 1062#L392-1 assume !(1 == ~E_M~0); 1086#L397-1 assume !(1 == ~E_1~0); 1087#L402-1 assume !(1 == ~E_2~0); 1077#L407-1 assume { :end_inline_reset_delta_events } true; 1078#L553-2 [2022-10-17 10:28:21,430 INFO L750 eck$LassoCheckResult]: Loop: 1078#L553-2 assume !false; 1138#L554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1133#L319 assume !false; 1110#L282 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1012#L254 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1013#L271 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1002#L272 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1003#L286 assume !(0 != eval_~tmp~0#1); 985#L334 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 986#L224-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1147#L344-3 assume !(0 == ~M_E~0); 929#L344-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 930#L349-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 983#L354-3 assume 0 == ~E_M~0;~E_M~0 := 1; 984#L359-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1058#L364-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1056#L369-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1038#L166-12 assume !(1 == ~m_pc~0); 1040#L166-14 is_master_triggered_~__retres1~0#1 := 0; 1008#L177-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1009#L178-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1032#L425-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1033#L425-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1102#L185-12 assume 1 == ~t1_pc~0; 1120#L186-4 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 991#L196-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1119#L197-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1148#L433-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1112#L433-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1113#L204-12 assume !(1 == ~t2_pc~0); 1016#L204-14 is_transmit2_triggered_~__retres1~2#1 := 0; 1017#L215-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1006#L216-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1007#L441-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1050#L441-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 981#L382-3 assume 1 == ~M_E~0;~M_E~0 := 2; 982#L382-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1060#L387-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1096#L392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 943#L397-3 assume 1 == ~E_1~0;~E_1~0 := 2; 944#L402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 954#L407-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 940#L254-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 941#L271-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 962#L272-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 1090#L572 assume !(0 == start_simulation_~tmp~3#1); 1001#L572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 974#L254-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 975#L271-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 958#L272-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 959#L527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1068#L534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1069#L535 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 1141#L585 assume !(0 != start_simulation_~tmp___0~1#1); 1078#L553-2 [2022-10-17 10:28:21,431 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:28:21,431 INFO L85 PathProgramCache]: Analyzing trace with hash -1324066169, now seen corresponding path program 1 times [2022-10-17 10:28:21,431 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:28:21,431 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1691975793] [2022-10-17 10:28:21,432 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:28:21,432 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:28:21,450 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:28:21,556 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:28:21,556 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:28:21,557 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1691975793] [2022-10-17 10:28:21,557 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1691975793] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:28:21,557 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:28:21,558 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:28:21,558 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1040583418] [2022-10-17 10:28:21,558 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:28:21,559 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:28:21,559 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:28:21,560 INFO L85 PathProgramCache]: Analyzing trace with hash -1848890247, now seen corresponding path program 1 times [2022-10-17 10:28:21,567 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:28:21,572 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1046886483] [2022-10-17 10:28:21,572 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:28:21,572 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:28:21,601 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:28:21,685 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:28:21,686 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:28:21,686 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1046886483] [2022-10-17 10:28:21,686 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1046886483] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:28:21,687 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:28:21,687 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-10-17 10:28:21,687 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1181964878] [2022-10-17 10:28:21,687 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:28:21,688 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:28:21,688 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:28:21,689 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-10-17 10:28:21,689 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-10-17 10:28:21,689 INFO L87 Difference]: Start difference. First operand 225 states and 334 transitions. cyclomatic complexity: 110 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 3 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:28:21,824 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:28:21,824 INFO L93 Difference]: Finished difference Result 362 states and 534 transitions. [2022-10-17 10:28:21,824 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 362 states and 534 transitions. [2022-10-17 10:28:21,831 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 312 [2022-10-17 10:28:21,840 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 362 states to 362 states and 534 transitions. [2022-10-17 10:28:21,840 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 362 [2022-10-17 10:28:21,842 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 362 [2022-10-17 10:28:21,842 INFO L73 IsDeterministic]: Start isDeterministic. Operand 362 states and 534 transitions. [2022-10-17 10:28:21,852 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:28:21,852 INFO L218 hiAutomatonCegarLoop]: Abstraction has 362 states and 534 transitions. [2022-10-17 10:28:21,857 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 362 states and 534 transitions. [2022-10-17 10:28:21,889 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 362 to 361. [2022-10-17 10:28:21,901 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 361 states, 361 states have (on average 1.4764542936288088) internal successors, (533), 360 states have internal predecessors, (533), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:28:21,903 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 361 states to 361 states and 533 transitions. [2022-10-17 10:28:21,903 INFO L240 hiAutomatonCegarLoop]: Abstraction has 361 states and 533 transitions. [2022-10-17 10:28:21,903 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-10-17 10:28:21,904 INFO L428 stractBuchiCegarLoop]: Abstraction has 361 states and 533 transitions. [2022-10-17 10:28:21,905 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-10-17 10:28:21,905 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 361 states and 533 transitions. [2022-10-17 10:28:21,908 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 312 [2022-10-17 10:28:21,908 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:28:21,908 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:28:21,910 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:28:21,910 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:28:21,911 INFO L748 eck$LassoCheckResult]: Stem: 1776#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 1748#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 1749#L516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1761#L224 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1659#L231 assume 1 == ~m_i~0;~m_st~0 := 0; 1530#L231-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1531#L236-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1716#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1578#L344 assume !(0 == ~M_E~0); 1579#L344-2 assume !(0 == ~T1_E~0); 1743#L349-1 assume !(0 == ~T2_E~0); 1598#L354-1 assume !(0 == ~E_M~0); 1599#L359-1 assume !(0 == ~E_1~0); 1593#L364-1 assume !(0 == ~E_2~0); 1594#L369-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1675#L166 assume 1 == ~m_pc~0; 1676#L167 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1736#L177 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1576#L178 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1577#L425 assume !(0 != activate_threads_~tmp~1#1); 1774#L425-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1685#L185 assume !(1 == ~t1_pc~0); 1604#L185-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1605#L196 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1642#L197 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1647#L433 assume !(0 != activate_threads_~tmp___0~0#1); 1648#L433-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1697#L204 assume 1 == ~t2_pc~0; 1651#L205 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1652#L215 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1718#L216 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1559#L441 assume !(0 != activate_threads_~tmp___1~0#1); 1560#L441-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1679#L382 assume 1 == ~M_E~0;~M_E~0 := 2; 1701#L382-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1826#L387-1 assume !(1 == ~T2_E~0); 1765#L392-1 assume !(1 == ~E_M~0); 1689#L397-1 assume !(1 == ~E_1~0); 1690#L402-1 assume !(1 == ~E_2~0); 1722#L407-1 assume { :end_inline_reset_delta_events } true; 1791#L553-2 [2022-10-17 10:28:21,911 INFO L750 eck$LassoCheckResult]: Loop: 1791#L553-2 assume !false; 1779#L554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1750#L319 assume !false; 1719#L282 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1720#L254 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1746#L271 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1747#L272 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1663#L286 assume !(0 != eval_~tmp~0#1); 1665#L334 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1777#L224-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1778#L344-3 assume !(0 == ~M_E~0); 1528#L344-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1529#L349-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1583#L354-3 assume !(0 == ~E_M~0); 1584#L359-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1658#L364-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1656#L369-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1638#L166-12 assume 1 == ~m_pc~0; 1639#L167-4 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1608#L177-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1609#L178-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1632#L425-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1633#L425-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1707#L185-12 assume !(1 == ~t1_pc~0); 1590#L185-14 is_transmit1_triggered_~__retres1~1#1 := 0; 1591#L196-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1873#L197-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1872#L433-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1871#L433-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1870#L204-12 assume 1 == ~t2_pc~0; 1868#L205-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1867#L215-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1866#L216-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1865#L441-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1864#L441-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1863#L382-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1581#L382-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1862#L387-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1861#L392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1731#L397-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1860#L402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1859#L407-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1856#L254-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1855#L271-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1854#L272-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 1853#L572 assume !(0 == start_simulation_~tmp~3#1); 1601#L572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1573#L254-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1574#L271-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1557#L272-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 1558#L527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1671#L534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1672#L535 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 1766#L585 assume !(0 != start_simulation_~tmp___0~1#1); 1791#L553-2 [2022-10-17 10:28:21,912 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:28:21,912 INFO L85 PathProgramCache]: Analyzing trace with hash -1712870137, now seen corresponding path program 1 times [2022-10-17 10:28:21,912 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:28:21,912 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [562140852] [2022-10-17 10:28:21,912 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:28:21,913 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:28:21,924 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:28:21,956 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:28:21,957 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:28:21,957 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [562140852] [2022-10-17 10:28:21,957 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [562140852] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:28:21,958 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:28:21,958 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-10-17 10:28:21,958 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [397773592] [2022-10-17 10:28:21,958 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:28:21,959 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:28:21,959 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:28:21,960 INFO L85 PathProgramCache]: Analyzing trace with hash 2030596858, now seen corresponding path program 1 times [2022-10-17 10:28:21,960 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:28:21,960 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1156751645] [2022-10-17 10:28:21,960 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:28:21,961 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:28:21,973 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:28:22,023 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:28:22,024 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:28:22,024 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1156751645] [2022-10-17 10:28:22,024 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1156751645] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:28:22,024 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:28:22,025 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-10-17 10:28:22,025 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [461386563] [2022-10-17 10:28:22,025 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:28:22,026 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:28:22,026 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:28:22,026 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:28:22,027 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:28:22,027 INFO L87 Difference]: Start difference. First operand 361 states and 533 transitions. cyclomatic complexity: 174 Second operand has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 2 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:28:22,072 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:28:22,072 INFO L93 Difference]: Finished difference Result 658 states and 955 transitions. [2022-10-17 10:28:22,073 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 658 states and 955 transitions. [2022-10-17 10:28:22,080 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 608 [2022-10-17 10:28:22,087 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 658 states to 658 states and 955 transitions. [2022-10-17 10:28:22,087 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 658 [2022-10-17 10:28:22,112 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 658 [2022-10-17 10:28:22,113 INFO L73 IsDeterministic]: Start isDeterministic. Operand 658 states and 955 transitions. [2022-10-17 10:28:22,114 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:28:22,115 INFO L218 hiAutomatonCegarLoop]: Abstraction has 658 states and 955 transitions. [2022-10-17 10:28:22,116 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 658 states and 955 transitions. [2022-10-17 10:28:22,156 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 658 to 618. [2022-10-17 10:28:22,158 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 618 states, 618 states have (on average 1.4579288025889967) internal successors, (901), 617 states have internal predecessors, (901), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:28:22,164 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 618 states to 618 states and 901 transitions. [2022-10-17 10:28:22,165 INFO L240 hiAutomatonCegarLoop]: Abstraction has 618 states and 901 transitions. [2022-10-17 10:28:22,165 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:28:22,166 INFO L428 stractBuchiCegarLoop]: Abstraction has 618 states and 901 transitions. [2022-10-17 10:28:22,166 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-10-17 10:28:22,167 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 618 states and 901 transitions. [2022-10-17 10:28:22,172 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 568 [2022-10-17 10:28:22,172 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:28:22,172 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:28:22,174 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:28:22,174 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:28:22,176 INFO L748 eck$LassoCheckResult]: Stem: 2842#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 2791#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 2792#L516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2814#L224 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2696#L231 assume 1 == ~m_i~0;~m_st~0 := 0; 2558#L231-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2559#L236-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2758#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2609#L344 assume !(0 == ~M_E~0); 2610#L344-2 assume !(0 == ~T1_E~0); 2786#L349-1 assume !(0 == ~T2_E~0); 2629#L354-1 assume !(0 == ~E_M~0); 2630#L359-1 assume !(0 == ~E_1~0); 2624#L364-1 assume !(0 == ~E_2~0); 2625#L369-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2718#L166 assume !(1 == ~m_pc~0); 2719#L166-2 is_master_triggered_~__retres1~0#1 := 0; 2795#L177 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2607#L178 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2608#L425 assume !(0 != activate_threads_~tmp~1#1); 2831#L425-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2728#L185 assume !(1 == ~t1_pc~0); 2635#L185-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2636#L196 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2674#L197 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2678#L433 assume !(0 != activate_threads_~tmp___0~0#1); 2679#L433-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2741#L204 assume 1 == ~t2_pc~0; 2685#L205 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2686#L215 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2760#L216 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2589#L441 assume !(0 != activate_threads_~tmp___1~0#1); 2590#L441-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2722#L382 assume 1 == ~M_E~0;~M_E~0 := 2; 2577#L382-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2578#L387-1 assume !(1 == ~T2_E~0); 2955#L392-1 assume !(1 == ~E_M~0); 2817#L397-1 assume !(1 == ~E_1~0); 2767#L402-1 assume !(1 == ~E_2~0); 2725#L407-1 assume { :end_inline_reset_delta_events } true; 2726#L553-2 [2022-10-17 10:28:22,178 INFO L750 eck$LassoCheckResult]: Loop: 2726#L553-2 assume !false; 2806#L554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2793#L319 assume !false; 2761#L282 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2645#L254 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2646#L271 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2633#L272 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2634#L286 assume !(0 != eval_~tmp~0#1); 2701#L334 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2960#L224-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2920#L344-3 assume !(0 == ~M_E~0); 2921#L344-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3128#L349-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3127#L354-3 assume !(0 == ~E_M~0); 3126#L359-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3125#L364-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3124#L369-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3123#L166-12 assume !(1 == ~m_pc~0); 3122#L166-14 is_master_triggered_~__retres1~0#1 := 0; 2639#L177-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2640#L178-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2664#L425-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2665#L425-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2752#L185-12 assume 1 == ~t1_pc~0; 2780#L186-4 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2622#L196-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3002#L197-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 3003#L433-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2896#L433-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2897#L204-12 assume 1 == ~t2_pc~0; 2890#L205-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2891#L215-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2886#L216-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2887#L441-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2681#L441-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2682#L382-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2612#L382-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2744#L387-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2745#L392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2570#L397-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2571#L402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3008#L407-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2567#L254-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2568#L271-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2591#L272-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 2737#L572 assume !(0 == start_simulation_~tmp~3#1); 2632#L572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2604#L254-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2605#L271-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2587#L272-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 2588#L527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2707#L534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2708#L535 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 2812#L585 assume !(0 != start_simulation_~tmp___0~1#1); 2726#L553-2 [2022-10-17 10:28:22,178 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:28:22,179 INFO L85 PathProgramCache]: Analyzing trace with hash 524493128, now seen corresponding path program 1 times [2022-10-17 10:28:22,180 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:28:22,180 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1453234941] [2022-10-17 10:28:22,180 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:28:22,181 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:28:22,201 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:28:22,258 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:28:22,258 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:28:22,259 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1453234941] [2022-10-17 10:28:22,259 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1453234941] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:28:22,259 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:28:22,259 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:28:22,260 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1276474927] [2022-10-17 10:28:22,260 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:28:22,260 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:28:22,261 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:28:22,261 INFO L85 PathProgramCache]: Analyzing trace with hash 632360506, now seen corresponding path program 1 times [2022-10-17 10:28:22,261 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:28:22,262 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [990040045] [2022-10-17 10:28:22,262 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:28:22,262 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:28:22,272 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:28:22,318 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:28:22,319 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:28:22,319 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [990040045] [2022-10-17 10:28:22,319 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [990040045] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:28:22,320 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:28:22,320 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-10-17 10:28:22,320 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1462559605] [2022-10-17 10:28:22,320 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:28:22,321 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:28:22,321 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:28:22,322 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-10-17 10:28:22,322 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-10-17 10:28:22,322 INFO L87 Difference]: Start difference. First operand 618 states and 901 transitions. cyclomatic complexity: 287 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 3 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:28:22,482 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:28:22,482 INFO L93 Difference]: Finished difference Result 1401 states and 2004 transitions. [2022-10-17 10:28:22,482 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1401 states and 2004 transitions. [2022-10-17 10:28:22,500 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 1296 [2022-10-17 10:28:22,515 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1401 states to 1401 states and 2004 transitions. [2022-10-17 10:28:22,515 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1401 [2022-10-17 10:28:22,517 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1401 [2022-10-17 10:28:22,518 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1401 states and 2004 transitions. [2022-10-17 10:28:22,520 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:28:22,521 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1401 states and 2004 transitions. [2022-10-17 10:28:22,524 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1401 states and 2004 transitions. [2022-10-17 10:28:22,554 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1401 to 1118. [2022-10-17 10:28:22,557 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1118 states, 1118 states have (on average 1.4445438282647585) internal successors, (1615), 1117 states have internal predecessors, (1615), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:28:22,565 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1118 states to 1118 states and 1615 transitions. [2022-10-17 10:28:22,565 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1118 states and 1615 transitions. [2022-10-17 10:28:22,565 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-10-17 10:28:22,568 INFO L428 stractBuchiCegarLoop]: Abstraction has 1118 states and 1615 transitions. [2022-10-17 10:28:22,569 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-10-17 10:28:22,569 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1118 states and 1615 transitions. [2022-10-17 10:28:22,592 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1067 [2022-10-17 10:28:22,592 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:28:22,592 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:28:22,596 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:28:22,596 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:28:22,597 INFO L748 eck$LassoCheckResult]: Stem: 4851#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 4814#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 4815#L516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4834#L224 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4721#L231 assume 1 == ~m_i~0;~m_st~0 := 0; 4589#L231-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4590#L236-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4785#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4640#L344 assume !(0 == ~M_E~0); 4641#L344-2 assume !(0 == ~T1_E~0); 4809#L349-1 assume !(0 == ~T2_E~0); 4659#L354-1 assume !(0 == ~E_M~0); 4660#L359-1 assume !(0 == ~E_1~0); 4654#L364-1 assume !(0 == ~E_2~0); 4655#L369-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4738#L166 assume !(1 == ~m_pc~0); 4739#L166-2 is_master_triggered_~__retres1~0#1 := 0; 4821#L177 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4638#L178 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 4639#L425 assume !(0 != activate_threads_~tmp~1#1); 4846#L425-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4749#L185 assume !(1 == ~t1_pc~0); 4665#L185-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4666#L196 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4705#L197 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4711#L433 assume !(0 != activate_threads_~tmp___0~0#1); 4712#L433-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4766#L204 assume !(1 == ~t2_pc~0); 4747#L204-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4748#L215 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4787#L216 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4620#L441 assume !(0 != activate_threads_~tmp___1~0#1); 4621#L441-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4741#L382 assume 1 == ~M_E~0;~M_E~0 := 2; 4608#L382-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4609#L387-1 assume !(1 == ~T2_E~0); 4836#L392-1 assume !(1 == ~E_M~0); 4837#L397-1 assume !(1 == ~E_1~0); 4792#L402-1 assume !(1 == ~E_2~0); 4793#L407-1 assume { :end_inline_reset_delta_events } true; 5629#L553-2 [2022-10-17 10:28:22,598 INFO L750 eck$LassoCheckResult]: Loop: 5629#L553-2 assume !false; 5628#L554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4840#L319 assume !false; 5627#L282 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 5623#L254 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 5619#L271 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 5609#L272 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 5606#L286 assume !(0 != eval_~tmp~0#1); 5607#L334 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5653#L224-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5652#L344-3 assume !(0 == ~M_E~0); 4587#L344-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4588#L349-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4644#L354-3 assume !(0 == ~E_M~0); 4645#L359-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4719#L364-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4718#L369-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4701#L166-12 assume !(1 == ~m_pc~0); 4702#L166-14 is_master_triggered_~__retres1~0#1 := 0; 4671#L177-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4672#L178-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 4695#L425-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4696#L425-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4776#L185-12 assume 1 == ~t1_pc~0; 4801#L186-4 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4652#L196-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4800#L197-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4843#L433-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4790#L433-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4791#L204-12 assume !(1 == ~t2_pc~0); 4680#L204-14 is_transmit2_triggered_~__retres1~2#1 := 0; 4681#L215-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4667#L216-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4668#L441-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4713#L441-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4642#L382-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4643#L382-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4720#L387-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4769#L392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4601#L397-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4602#L402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4779#L407-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 5649#L254-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 5648#L271-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 5647#L272-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 5646#L572 assume !(0 == start_simulation_~tmp~3#1); 4662#L572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 5643#L254-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 5640#L271-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 5638#L272-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 5636#L527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5634#L534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5633#L535 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 5630#L585 assume !(0 != start_simulation_~tmp___0~1#1); 5629#L553-2 [2022-10-17 10:28:22,600 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:28:22,600 INFO L85 PathProgramCache]: Analyzing trace with hash -754831607, now seen corresponding path program 1 times [2022-10-17 10:28:22,601 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:28:22,601 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1224111097] [2022-10-17 10:28:22,602 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:28:22,602 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:28:22,614 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:28:22,682 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:28:22,682 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:28:22,682 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1224111097] [2022-10-17 10:28:22,683 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1224111097] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:28:22,683 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:28:22,683 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-10-17 10:28:22,683 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [875295954] [2022-10-17 10:28:22,683 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:28:22,684 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:28:22,684 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:28:22,685 INFO L85 PathProgramCache]: Analyzing trace with hash -1425243525, now seen corresponding path program 1 times [2022-10-17 10:28:22,685 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:28:22,685 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [50005425] [2022-10-17 10:28:22,685 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:28:22,686 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:28:22,702 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:28:22,771 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:28:22,771 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:28:22,772 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [50005425] [2022-10-17 10:28:22,778 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [50005425] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:28:22,779 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:28:22,780 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-10-17 10:28:22,780 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [137236793] [2022-10-17 10:28:22,780 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:28:22,782 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:28:22,782 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:28:22,783 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:28:22,783 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:28:22,784 INFO L87 Difference]: Start difference. First operand 1118 states and 1615 transitions. cyclomatic complexity: 501 Second operand has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 2 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:28:22,825 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:28:22,825 INFO L93 Difference]: Finished difference Result 1641 states and 2364 transitions. [2022-10-17 10:28:22,826 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1641 states and 2364 transitions. [2022-10-17 10:28:22,844 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1591 [2022-10-17 10:28:22,861 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1641 states to 1641 states and 2364 transitions. [2022-10-17 10:28:22,862 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1641 [2022-10-17 10:28:22,865 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1641 [2022-10-17 10:28:22,866 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1641 states and 2364 transitions. [2022-10-17 10:28:22,869 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:28:22,869 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1641 states and 2364 transitions. [2022-10-17 10:28:22,872 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1641 states and 2364 transitions. [2022-10-17 10:28:22,894 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1641 to 1181. [2022-10-17 10:28:22,897 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1181 states, 1181 states have (on average 1.4428450465707028) internal successors, (1704), 1180 states have internal predecessors, (1704), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:28:22,903 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1181 states to 1181 states and 1704 transitions. [2022-10-17 10:28:22,904 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1181 states and 1704 transitions. [2022-10-17 10:28:22,904 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:28:22,906 INFO L428 stractBuchiCegarLoop]: Abstraction has 1181 states and 1704 transitions. [2022-10-17 10:28:22,906 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-10-17 10:28:22,906 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1181 states and 1704 transitions. [2022-10-17 10:28:22,914 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1136 [2022-10-17 10:28:22,914 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:28:22,914 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:28:22,916 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:28:22,916 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:28:22,917 INFO L748 eck$LassoCheckResult]: Stem: 7629#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 7588#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 7589#L516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7608#L224 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7492#L231 assume 1 == ~m_i~0;~m_st~0 := 0; 7357#L231-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7358#L236-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7556#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7408#L344 assume !(0 == ~M_E~0); 7409#L344-2 assume !(0 == ~T1_E~0); 7583#L349-1 assume !(0 == ~T2_E~0); 7428#L354-1 assume !(0 == ~E_M~0); 7429#L359-1 assume !(0 == ~E_1~0); 7423#L364-1 assume !(0 == ~E_2~0); 7424#L369-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7513#L166 assume !(1 == ~m_pc~0); 7514#L166-2 is_master_triggered_~__retres1~0#1 := 0; 7592#L177 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7406#L178 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 7407#L425 assume !(0 != activate_threads_~tmp~1#1); 7624#L425-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7525#L185 assume !(1 == ~t1_pc~0); 7434#L185-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7435#L196 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7474#L197 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 7481#L433 assume !(0 != activate_threads_~tmp___0~0#1); 7482#L433-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7542#L204 assume !(1 == ~t2_pc~0); 7523#L204-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7524#L215 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7558#L216 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 7388#L441 assume !(0 != activate_threads_~tmp___1~0#1); 7389#L441-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7517#L382 assume !(1 == ~M_E~0); 7376#L382-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7377#L387-1 assume !(1 == ~T2_E~0); 7496#L392-1 assume !(1 == ~E_M~0); 7531#L397-1 assume !(1 == ~E_1~0); 7532#L402-1 assume !(1 == ~E_2~0); 7518#L407-1 assume { :end_inline_reset_delta_events } true; 7519#L553-2 [2022-10-17 10:28:22,917 INFO L750 eck$LassoCheckResult]: Loop: 7519#L553-2 assume !false; 8483#L554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7596#L319 assume !false; 7559#L282 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 7444#L254 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 7445#L271 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 8372#L272 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 7497#L286 assume !(0 != eval_~tmp~0#1); 7498#L334 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8535#L224-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7615#L344-3 assume !(0 == ~M_E~0); 7355#L344-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7356#L349-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7412#L354-3 assume !(0 == ~E_M~0); 7413#L359-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7491#L364-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7488#L369-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7471#L166-12 assume !(1 == ~m_pc~0); 7472#L166-14 is_master_triggered_~__retres1~0#1 := 0; 7440#L177-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7441#L178-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 7465#L425-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7466#L425-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7551#L185-12 assume !(1 == ~t1_pc~0); 8503#L185-14 is_transmit1_triggered_~__retres1~1#1 := 0; 8502#L196-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8498#L197-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 8496#L433-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8494#L433-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8492#L204-12 assume !(1 == ~t2_pc~0); 8401#L204-14 is_transmit2_triggered_~__retres1~2#1 := 0; 8482#L215-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7436#L216-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 7437#L441-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7484#L441-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7410#L382-3 assume !(1 == ~M_E~0); 7411#L382-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8392#L387-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8384#L392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8371#L397-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8367#L402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8364#L407-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 8356#L254-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 8353#L271-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 8349#L272-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 7536#L572 assume !(0 == start_simulation_~tmp~3#1); 7538#L572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 8500#L254-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 8497#L271-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 8495#L272-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 8493#L527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8490#L534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8487#L535 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 8485#L585 assume !(0 != start_simulation_~tmp___0~1#1); 7519#L553-2 [2022-10-17 10:28:22,918 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:28:22,918 INFO L85 PathProgramCache]: Analyzing trace with hash 1020175755, now seen corresponding path program 1 times [2022-10-17 10:28:22,918 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:28:22,919 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1969196159] [2022-10-17 10:28:22,919 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:28:22,919 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:28:22,932 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:28:22,984 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:28:22,985 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:28:22,985 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1969196159] [2022-10-17 10:28:22,985 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1969196159] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:28:22,985 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:28:22,986 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-10-17 10:28:22,986 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1207386443] [2022-10-17 10:28:22,986 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:28:22,986 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:28:22,987 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:28:22,987 INFO L85 PathProgramCache]: Analyzing trace with hash -590690946, now seen corresponding path program 1 times [2022-10-17 10:28:22,987 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:28:22,987 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [907152914] [2022-10-17 10:28:22,988 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:28:22,988 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:28:23,004 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:28:23,051 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:28:23,051 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:28:23,052 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [907152914] [2022-10-17 10:28:23,053 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [907152914] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:28:23,053 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:28:23,054 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-10-17 10:28:23,054 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1920463855] [2022-10-17 10:28:23,054 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:28:23,055 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:28:23,055 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:28:23,057 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:28:23,057 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:28:23,058 INFO L87 Difference]: Start difference. First operand 1181 states and 1704 transitions. cyclomatic complexity: 525 Second operand has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 2 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:28:23,082 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:28:23,083 INFO L93 Difference]: Finished difference Result 1181 states and 1678 transitions. [2022-10-17 10:28:23,083 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1181 states and 1678 transitions. [2022-10-17 10:28:23,094 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1136 [2022-10-17 10:28:23,120 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1181 states to 1181 states and 1678 transitions. [2022-10-17 10:28:23,120 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1181 [2022-10-17 10:28:23,121 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1181 [2022-10-17 10:28:23,121 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1181 states and 1678 transitions. [2022-10-17 10:28:23,124 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:28:23,124 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1181 states and 1678 transitions. [2022-10-17 10:28:23,126 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1181 states and 1678 transitions. [2022-10-17 10:28:23,145 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1181 to 1181. [2022-10-17 10:28:23,148 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1181 states, 1181 states have (on average 1.4208298052497883) internal successors, (1678), 1180 states have internal predecessors, (1678), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:28:23,154 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1181 states to 1181 states and 1678 transitions. [2022-10-17 10:28:23,154 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1181 states and 1678 transitions. [2022-10-17 10:28:23,155 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:28:23,158 INFO L428 stractBuchiCegarLoop]: Abstraction has 1181 states and 1678 transitions. [2022-10-17 10:28:23,158 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-10-17 10:28:23,158 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1181 states and 1678 transitions. [2022-10-17 10:28:23,166 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1136 [2022-10-17 10:28:23,166 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:28:23,167 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:28:23,169 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:28:23,169 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:28:23,169 INFO L748 eck$LassoCheckResult]: Stem: 9993#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 9950#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 9951#L516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9972#L224 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9862#L231 assume 1 == ~m_i~0;~m_st~0 := 0; 9728#L231-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9729#L236-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9920#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9778#L344 assume !(0 == ~M_E~0); 9779#L344-2 assume !(0 == ~T1_E~0); 9945#L349-1 assume !(0 == ~T2_E~0); 9797#L354-1 assume !(0 == ~E_M~0); 9798#L359-1 assume !(0 == ~E_1~0); 9792#L364-1 assume !(0 == ~E_2~0); 9793#L369-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9880#L166 assume !(1 == ~m_pc~0); 9881#L166-2 is_master_triggered_~__retres1~0#1 := 0; 9956#L177 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9776#L178 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 9777#L425 assume !(0 != activate_threads_~tmp~1#1); 9990#L425-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9893#L185 assume !(1 == ~t1_pc~0); 9803#L185-2 is_transmit1_triggered_~__retres1~1#1 := 0; 9804#L196 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9844#L197 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 9850#L433 assume !(0 != activate_threads_~tmp___0~0#1); 9851#L433-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9906#L204 assume !(1 == ~t2_pc~0); 9891#L204-2 is_transmit2_triggered_~__retres1~2#1 := 0; 9892#L215 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9922#L216 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 9758#L441 assume !(0 != activate_threads_~tmp___1~0#1); 9759#L441-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9885#L382 assume !(1 == ~M_E~0); 9747#L382-2 assume !(1 == ~T1_E~0); 9748#L387-1 assume !(1 == ~T2_E~0); 9865#L392-1 assume !(1 == ~E_M~0); 9897#L397-1 assume !(1 == ~E_1~0); 9898#L402-1 assume !(1 == ~E_2~0); 9886#L407-1 assume { :end_inline_reset_delta_events } true; 9887#L553-2 [2022-10-17 10:28:23,169 INFO L750 eck$LassoCheckResult]: Loop: 9887#L553-2 assume !false; 10757#L554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9960#L319 assume !false; 10756#L282 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 10754#L254 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 10752#L271 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 9801#L272 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 9802#L286 assume !(0 != eval_~tmp~0#1); 9784#L334 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9785#L224-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9978#L344-3 assume !(0 == ~M_E~0); 9726#L344-5 assume !(0 == ~T1_E~0); 9727#L349-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9782#L354-3 assume !(0 == ~E_M~0); 9783#L359-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9860#L364-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9861#L369-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10886#L166-12 assume !(1 == ~m_pc~0); 9962#L166-14 is_master_triggered_~__retres1~0#1 := 0; 9809#L177-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9810#L178-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 9835#L425-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9836#L425-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9915#L185-12 assume !(1 == ~t1_pc~0); 10861#L185-14 is_transmit1_triggered_~__retres1~1#1 := 0; 9935#L196-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9936#L197-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 9983#L433-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9926#L433-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9927#L204-12 assume !(1 == ~t2_pc~0); 9982#L204-14 is_transmit2_triggered_~__retres1~2#1 := 0; 10799#L215-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10798#L216-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 9882#L441-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9853#L441-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9780#L382-3 assume !(1 == ~M_E~0); 9781#L382-5 assume !(1 == ~T1_E~0); 9863#L387-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9909#L392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 9740#L397-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9741#L402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9751#L407-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 9737#L254-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 9738#L271-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 9760#L272-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 9924#L572 assume !(0 == start_simulation_~tmp~3#1); 10015#L572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 9773#L254-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 9774#L271-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 9756#L272-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 9757#L527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9981#L534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10869#L535 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 10797#L585 assume !(0 != start_simulation_~tmp___0~1#1); 9887#L553-2 [2022-10-17 10:28:23,170 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:28:23,170 INFO L85 PathProgramCache]: Analyzing trace with hash 1077434057, now seen corresponding path program 1 times [2022-10-17 10:28:23,170 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:28:23,170 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [820577273] [2022-10-17 10:28:23,171 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:28:23,171 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:28:23,180 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:28:23,180 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:28:23,192 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:28:23,232 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:28:23,238 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:28:23,238 INFO L85 PathProgramCache]: Analyzing trace with hash 812738366, now seen corresponding path program 1 times [2022-10-17 10:28:23,240 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:28:23,241 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1039471558] [2022-10-17 10:28:23,241 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:28:23,242 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:28:23,260 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:28:23,304 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:28:23,309 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:28:23,311 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1039471558] [2022-10-17 10:28:23,312 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1039471558] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:28:23,314 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:28:23,314 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-10-17 10:28:23,316 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [225800451] [2022-10-17 10:28:23,317 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:28:23,318 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:28:23,318 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:28:23,319 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-10-17 10:28:23,319 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-10-17 10:28:23,321 INFO L87 Difference]: Start difference. First operand 1181 states and 1678 transitions. cyclomatic complexity: 499 Second operand has 5 states, 5 states have (on average 10.8) internal successors, (54), 5 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:28:23,434 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:28:23,434 INFO L93 Difference]: Finished difference Result 2033 states and 2838 transitions. [2022-10-17 10:28:23,434 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2033 states and 2838 transitions. [2022-10-17 10:28:23,454 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1984 [2022-10-17 10:28:23,473 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2033 states to 2033 states and 2838 transitions. [2022-10-17 10:28:23,473 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2033 [2022-10-17 10:28:23,476 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2033 [2022-10-17 10:28:23,476 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2033 states and 2838 transitions. [2022-10-17 10:28:23,480 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:28:23,480 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2033 states and 2838 transitions. [2022-10-17 10:28:23,483 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2033 states and 2838 transitions. [2022-10-17 10:28:23,507 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2033 to 1205. [2022-10-17 10:28:23,511 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1205 states, 1205 states have (on average 1.412448132780083) internal successors, (1702), 1204 states have internal predecessors, (1702), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:28:23,516 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1205 states to 1205 states and 1702 transitions. [2022-10-17 10:28:23,516 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1205 states and 1702 transitions. [2022-10-17 10:28:23,516 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-10-17 10:28:23,519 INFO L428 stractBuchiCegarLoop]: Abstraction has 1205 states and 1702 transitions. [2022-10-17 10:28:23,519 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-10-17 10:28:23,519 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1205 states and 1702 transitions. [2022-10-17 10:28:23,527 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1160 [2022-10-17 10:28:23,527 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:28:23,527 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:28:23,535 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:28:23,535 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:28:23,535 INFO L748 eck$LassoCheckResult]: Stem: 13228#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 13189#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 13190#L516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13207#L224 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13090#L231 assume 1 == ~m_i~0;~m_st~0 := 0; 12958#L231-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12959#L236-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13155#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13009#L344 assume !(0 == ~M_E~0); 13010#L344-2 assume !(0 == ~T1_E~0); 13182#L349-1 assume !(0 == ~T2_E~0); 13028#L354-1 assume !(0 == ~E_M~0); 13029#L359-1 assume !(0 == ~E_1~0); 13023#L364-1 assume !(0 == ~E_2~0); 13024#L369-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13108#L166 assume !(1 == ~m_pc~0); 13109#L166-2 is_master_triggered_~__retres1~0#1 := 0; 13193#L177 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13007#L178 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 13008#L425 assume !(0 != activate_threads_~tmp~1#1); 13223#L425-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13120#L185 assume !(1 == ~t1_pc~0); 13034#L185-2 is_transmit1_triggered_~__retres1~1#1 := 0; 13035#L196 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13072#L197 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 13078#L433 assume !(0 != activate_threads_~tmp___0~0#1); 13079#L433-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13136#L204 assume !(1 == ~t2_pc~0); 13118#L204-2 is_transmit2_triggered_~__retres1~2#1 := 0; 13119#L215 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13157#L216 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 12989#L441 assume !(0 != activate_threads_~tmp___1~0#1); 12990#L441-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13112#L382 assume !(1 == ~M_E~0); 12977#L382-2 assume !(1 == ~T1_E~0); 12978#L387-1 assume !(1 == ~T2_E~0); 13093#L392-1 assume !(1 == ~E_M~0); 13128#L397-1 assume !(1 == ~E_1~0); 13129#L402-1 assume !(1 == ~E_2~0); 13115#L407-1 assume { :end_inline_reset_delta_events } true; 13116#L553-2 [2022-10-17 10:28:23,535 INFO L750 eck$LassoCheckResult]: Loop: 13116#L553-2 assume !false; 13202#L554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13234#L319 assume !false; 13235#L282 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 13781#L254 assume !(0 == ~m_st~0); 13782#L258 assume !(0 == ~t1_st~0); 13783#L262 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 13784#L271 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 13772#L272 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 13773#L286 assume !(0 != eval_~tmp~0#1); 13764#L334 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13765#L224-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13211#L344-3 assume !(0 == ~M_E~0); 13212#L344-5 assume !(0 == ~T1_E~0); 14018#L349-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14017#L354-3 assume !(0 == ~E_M~0); 13123#L359-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13124#L364-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13084#L369-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13068#L166-12 assume !(1 == ~m_pc~0); 13069#L166-14 is_master_triggered_~__retres1~0#1 := 0; 13038#L177-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13039#L178-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 14015#L425-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14014#L425-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13218#L185-12 assume !(1 == ~t1_pc~0); 13219#L185-14 is_transmit1_triggered_~__retres1~1#1 := 0; 13172#L196-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13173#L197-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 14013#L433-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13161#L433-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13162#L204-12 assume !(1 == ~t2_pc~0); 13046#L204-14 is_transmit2_triggered_~__retres1~2#1 := 0; 13047#L215-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13036#L216-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 13037#L441-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 13080#L441-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13011#L382-3 assume !(1 == ~M_E~0); 13012#L382-5 assume !(1 == ~T1_E~0); 13139#L387-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13140#L392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12970#L397-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12971#L402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12981#L407-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 12982#L254-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 14122#L271-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 14084#L272-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 13132#L572 assume !(0 == start_simulation_~tmp~3#1); 13134#L572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 13004#L254-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 13005#L271-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 12987#L272-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 12988#L527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13099#L534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13100#L535 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 13206#L585 assume !(0 != start_simulation_~tmp___0~1#1); 13116#L553-2 [2022-10-17 10:28:23,536 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:28:23,536 INFO L85 PathProgramCache]: Analyzing trace with hash 1077434057, now seen corresponding path program 2 times [2022-10-17 10:28:23,536 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:28:23,536 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2020035110] [2022-10-17 10:28:23,536 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:28:23,537 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:28:23,548 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:28:23,548 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:28:23,553 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:28:23,565 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:28:23,566 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:28:23,566 INFO L85 PathProgramCache]: Analyzing trace with hash -60432105, now seen corresponding path program 1 times [2022-10-17 10:28:23,566 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:28:23,567 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1916307450] [2022-10-17 10:28:23,567 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:28:23,567 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:28:23,581 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:28:23,675 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:28:23,675 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:28:23,675 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1916307450] [2022-10-17 10:28:23,675 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1916307450] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:28:23,676 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:28:23,676 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-10-17 10:28:23,676 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [245024560] [2022-10-17 10:28:23,676 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:28:23,676 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:28:23,677 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:28:23,677 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-10-17 10:28:23,678 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-10-17 10:28:23,678 INFO L87 Difference]: Start difference. First operand 1205 states and 1702 transitions. cyclomatic complexity: 499 Second operand has 5 states, 5 states have (on average 11.2) internal successors, (56), 5 states have internal predecessors, (56), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:28:23,837 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:28:23,838 INFO L93 Difference]: Finished difference Result 2347 states and 3283 transitions. [2022-10-17 10:28:23,838 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2347 states and 3283 transitions. [2022-10-17 10:28:23,858 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2302 [2022-10-17 10:28:23,880 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2347 states to 2347 states and 3283 transitions. [2022-10-17 10:28:23,881 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2347 [2022-10-17 10:28:23,884 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2347 [2022-10-17 10:28:23,884 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2347 states and 3283 transitions. [2022-10-17 10:28:23,889 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:28:23,889 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2347 states and 3283 transitions. [2022-10-17 10:28:23,892 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2347 states and 3283 transitions. [2022-10-17 10:28:23,930 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2347 to 1253. [2022-10-17 10:28:23,933 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1253 states, 1253 states have (on average 1.386272944932163) internal successors, (1737), 1252 states have internal predecessors, (1737), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:28:23,938 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1253 states to 1253 states and 1737 transitions. [2022-10-17 10:28:23,938 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1253 states and 1737 transitions. [2022-10-17 10:28:23,939 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-10-17 10:28:23,940 INFO L428 stractBuchiCegarLoop]: Abstraction has 1253 states and 1737 transitions. [2022-10-17 10:28:23,940 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-10-17 10:28:23,940 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1253 states and 1737 transitions. [2022-10-17 10:28:23,948 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1208 [2022-10-17 10:28:23,948 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:28:23,948 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:28:23,949 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:28:23,949 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:28:23,950 INFO L748 eck$LassoCheckResult]: Stem: 16803#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 16745#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 16746#L516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16772#L224 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16654#L231 assume 1 == ~m_i~0;~m_st~0 := 0; 16523#L231-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16524#L236-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16715#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16573#L344 assume !(0 == ~M_E~0); 16574#L344-2 assume !(0 == ~T1_E~0); 16741#L349-1 assume !(0 == ~T2_E~0); 16593#L354-1 assume !(0 == ~E_M~0); 16594#L359-1 assume !(0 == ~E_1~0); 16588#L364-1 assume !(0 == ~E_2~0); 16589#L369-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16673#L166 assume !(1 == ~m_pc~0); 16674#L166-2 is_master_triggered_~__retres1~0#1 := 0; 16751#L177 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16571#L178 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 16572#L425 assume !(0 != activate_threads_~tmp~1#1); 16794#L425-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16684#L185 assume !(1 == ~t1_pc~0); 16599#L185-2 is_transmit1_triggered_~__retres1~1#1 := 0; 16600#L196 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16637#L197 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 16643#L433 assume !(0 != activate_threads_~tmp___0~0#1); 16644#L433-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16697#L204 assume !(1 == ~t2_pc~0); 16682#L204-2 is_transmit2_triggered_~__retres1~2#1 := 0; 16683#L215 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16717#L216 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 16553#L441 assume !(0 != activate_threads_~tmp___1~0#1); 16554#L441-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16676#L382 assume !(1 == ~M_E~0); 16542#L382-2 assume !(1 == ~T1_E~0); 16543#L387-1 assume !(1 == ~T2_E~0); 16659#L392-1 assume !(1 == ~E_M~0); 16688#L397-1 assume !(1 == ~E_1~0); 16689#L402-1 assume !(1 == ~E_2~0); 16677#L407-1 assume { :end_inline_reset_delta_events } true; 16678#L553-2 [2022-10-17 10:28:23,950 INFO L750 eck$LassoCheckResult]: Loop: 16678#L553-2 assume !false; 17311#L554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17202#L319 assume !false; 17310#L282 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 17308#L254 assume !(0 == ~m_st~0); 17309#L258 assume !(0 == ~t1_st~0); 17306#L262 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 17307#L271 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 17302#L272 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 17303#L286 assume !(0 != eval_~tmp~0#1); 17364#L334 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17363#L224-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17362#L344-3 assume !(0 == ~M_E~0); 17361#L344-5 assume !(0 == ~T1_E~0); 17360#L349-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17359#L354-3 assume !(0 == ~E_M~0); 17358#L359-3 assume 0 == ~E_1~0;~E_1~0 := 1; 17357#L364-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16649#L369-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16634#L166-12 assume !(1 == ~m_pc~0); 16635#L166-14 is_master_triggered_~__retres1~0#1 := 0; 17222#L177-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17220#L178-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 17218#L425-12 assume !(0 != activate_threads_~tmp~1#1); 17216#L425-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17103#L185-12 assume !(1 == ~t1_pc~0); 17098#L185-14 is_transmit1_triggered_~__retres1~1#1 := 0; 17069#L196-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17070#L197-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 17031#L433-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17032#L433-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17011#L204-12 assume !(1 == ~t2_pc~0); 17009#L204-14 is_transmit2_triggered_~__retres1~2#1 := 0; 17007#L215-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17005#L216-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 17003#L441-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 17001#L441-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16999#L382-3 assume !(1 == ~M_E~0); 16998#L382-5 assume !(1 == ~T1_E~0); 16992#L387-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16993#L392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 16986#L397-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16987#L402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16980#L407-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 16981#L254-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 16880#L271-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 16881#L272-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 16828#L572 assume !(0 == start_simulation_~tmp~3#1); 16830#L572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 17319#L254-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 17317#L271-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 17316#L272-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 17315#L527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 17314#L534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 17313#L535 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 17312#L585 assume !(0 != start_simulation_~tmp___0~1#1); 16678#L553-2 [2022-10-17 10:28:23,952 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:28:23,952 INFO L85 PathProgramCache]: Analyzing trace with hash 1077434057, now seen corresponding path program 3 times [2022-10-17 10:28:23,953 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:28:23,953 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [978161185] [2022-10-17 10:28:23,953 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:28:23,953 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:28:23,963 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:28:23,964 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:28:23,970 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:28:23,996 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:28:23,996 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:28:23,997 INFO L85 PathProgramCache]: Analyzing trace with hash -132818663, now seen corresponding path program 1 times [2022-10-17 10:28:23,997 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:28:23,997 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [770369506] [2022-10-17 10:28:23,997 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:28:23,997 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:28:24,006 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:28:24,035 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:28:24,035 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:28:24,035 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [770369506] [2022-10-17 10:28:24,036 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [770369506] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:28:24,036 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:28:24,036 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:28:24,036 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1816836537] [2022-10-17 10:28:24,036 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:28:24,037 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:28:24,037 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:28:24,038 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:28:24,038 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:28:24,038 INFO L87 Difference]: Start difference. First operand 1253 states and 1737 transitions. cyclomatic complexity: 486 Second operand has 3 states, 3 states have (on average 18.666666666666668) internal successors, (56), 3 states have internal predecessors, (56), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:28:24,085 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:28:24,085 INFO L93 Difference]: Finished difference Result 1866 states and 2547 transitions. [2022-10-17 10:28:24,085 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1866 states and 2547 transitions. [2022-10-17 10:28:24,100 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1821 [2022-10-17 10:28:24,114 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1866 states to 1866 states and 2547 transitions. [2022-10-17 10:28:24,114 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1866 [2022-10-17 10:28:24,119 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1866 [2022-10-17 10:28:24,119 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1866 states and 2547 transitions. [2022-10-17 10:28:24,122 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:28:24,122 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1866 states and 2547 transitions. [2022-10-17 10:28:24,125 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1866 states and 2547 transitions. [2022-10-17 10:28:24,171 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1866 to 1804. [2022-10-17 10:28:24,175 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1804 states, 1804 states have (on average 1.3664079822616408) internal successors, (2465), 1803 states have internal predecessors, (2465), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:28:24,182 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1804 states to 1804 states and 2465 transitions. [2022-10-17 10:28:24,183 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1804 states and 2465 transitions. [2022-10-17 10:28:24,183 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:28:24,184 INFO L428 stractBuchiCegarLoop]: Abstraction has 1804 states and 2465 transitions. [2022-10-17 10:28:24,184 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-10-17 10:28:24,184 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1804 states and 2465 transitions. [2022-10-17 10:28:24,192 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1759 [2022-10-17 10:28:24,192 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:28:24,192 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:28:24,193 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:28:24,193 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:28:24,193 INFO L748 eck$LassoCheckResult]: Stem: 19934#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 19879#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 19880#L516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19906#L224 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19781#L231 assume 1 == ~m_i~0;~m_st~0 := 0; 19648#L231-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19649#L236-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19844#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19697#L344 assume !(0 == ~M_E~0); 19698#L344-2 assume !(0 == ~T1_E~0); 19873#L349-1 assume !(0 == ~T2_E~0); 19717#L354-1 assume !(0 == ~E_M~0); 19718#L359-1 assume !(0 == ~E_1~0); 19712#L364-1 assume !(0 == ~E_2~0); 19713#L369-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19802#L166 assume !(1 == ~m_pc~0); 19803#L166-2 is_master_triggered_~__retres1~0#1 := 0; 19886#L177 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19695#L178 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 19696#L425 assume !(0 != activate_threads_~tmp~1#1); 19923#L425-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19814#L185 assume !(1 == ~t1_pc~0); 19723#L185-2 is_transmit1_triggered_~__retres1~1#1 := 0; 19724#L196 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19762#L197 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 19769#L433 assume !(0 != activate_threads_~tmp___0~0#1); 19770#L433-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19827#L204 assume !(1 == ~t2_pc~0); 19812#L204-2 is_transmit2_triggered_~__retres1~2#1 := 0; 19813#L215 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19846#L216 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 19680#L441 assume !(0 != activate_threads_~tmp___1~0#1); 19681#L441-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19805#L382 assume !(1 == ~M_E~0); 19668#L382-2 assume !(1 == ~T1_E~0); 19669#L387-1 assume !(1 == ~T2_E~0); 19786#L392-1 assume !(1 == ~E_M~0); 19818#L397-1 assume !(1 == ~E_1~0); 19819#L402-1 assume !(1 == ~E_2~0); 19806#L407-1 assume { :end_inline_reset_delta_events } true; 19807#L553-2 assume !false; 20522#L554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 20480#L319 [2022-10-17 10:28:24,193 INFO L750 eck$LassoCheckResult]: Loop: 20480#L319 assume !false; 20518#L282 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 20514#L254 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 20509#L271 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 20505#L272 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 20499#L286 assume 0 != eval_~tmp~0#1; 20493#L286-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 20489#L294 assume !(0 != eval_~tmp_ndt_1~0#1); 20485#L291 assume !(0 == ~t1_st~0); 20481#L305 assume !(0 == ~t2_st~0); 20480#L319 [2022-10-17 10:28:24,194 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:28:24,194 INFO L85 PathProgramCache]: Analyzing trace with hash 327016235, now seen corresponding path program 1 times [2022-10-17 10:28:24,194 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:28:24,195 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2070577997] [2022-10-17 10:28:24,195 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:28:24,195 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:28:24,203 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:28:24,203 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:28:24,208 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:28:24,217 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:28:24,217 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:28:24,218 INFO L85 PathProgramCache]: Analyzing trace with hash 698755222, now seen corresponding path program 1 times [2022-10-17 10:28:24,218 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:28:24,218 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1730682202] [2022-10-17 10:28:24,218 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:28:24,218 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:28:24,222 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:28:24,222 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:28:24,224 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:28:24,226 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:28:24,227 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:28:24,227 INFO L85 PathProgramCache]: Analyzing trace with hash 1780390720, now seen corresponding path program 1 times [2022-10-17 10:28:24,228 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:28:24,228 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1374988016] [2022-10-17 10:28:24,228 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:28:24,228 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:28:24,238 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:28:24,264 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:28:24,264 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:28:24,264 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1374988016] [2022-10-17 10:28:24,264 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1374988016] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:28:24,265 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:28:24,265 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:28:24,265 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [23248068] [2022-10-17 10:28:24,265 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:28:24,351 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:28:24,352 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:28:24,352 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:28:24,352 INFO L87 Difference]: Start difference. First operand 1804 states and 2465 transitions. cyclomatic complexity: 664 Second operand has 3 states, 3 states have (on average 17.333333333333332) internal successors, (52), 3 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:28:24,408 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:28:24,408 INFO L93 Difference]: Finished difference Result 3072 states and 4139 transitions. [2022-10-17 10:28:24,409 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3072 states and 4139 transitions. [2022-10-17 10:28:24,428 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2988 [2022-10-17 10:28:24,453 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3072 states to 3072 states and 4139 transitions. [2022-10-17 10:28:24,453 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3072 [2022-10-17 10:28:24,457 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3072 [2022-10-17 10:28:24,457 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3072 states and 4139 transitions. [2022-10-17 10:28:24,463 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:28:24,463 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3072 states and 4139 transitions. [2022-10-17 10:28:24,467 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3072 states and 4139 transitions. [2022-10-17 10:28:24,514 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3072 to 2925. [2022-10-17 10:28:24,521 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2925 states, 2925 states have (on average 1.3552136752136752) internal successors, (3964), 2924 states have internal predecessors, (3964), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:28:24,532 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2925 states to 2925 states and 3964 transitions. [2022-10-17 10:28:24,532 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2925 states and 3964 transitions. [2022-10-17 10:28:24,533 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:28:24,533 INFO L428 stractBuchiCegarLoop]: Abstraction has 2925 states and 3964 transitions. [2022-10-17 10:28:24,534 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-10-17 10:28:24,534 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2925 states and 3964 transitions. [2022-10-17 10:28:24,563 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2841 [2022-10-17 10:28:24,563 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:28:24,563 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:28:24,566 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:28:24,566 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:28:24,566 INFO L748 eck$LassoCheckResult]: Stem: 24825#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 24770#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 24771#L516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 24794#L224 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 24667#L231 assume 1 == ~m_i~0;~m_st~0 := 0; 24532#L231-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 24533#L236-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 24737#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24584#L344 assume !(0 == ~M_E~0); 24585#L344-2 assume !(0 == ~T1_E~0); 24765#L349-1 assume !(0 == ~T2_E~0); 24603#L354-1 assume !(0 == ~E_M~0); 24604#L359-1 assume !(0 == ~E_1~0); 24598#L364-1 assume !(0 == ~E_2~0); 24599#L369-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24688#L166 assume !(1 == ~m_pc~0); 24689#L166-2 is_master_triggered_~__retres1~0#1 := 0; 24776#L177 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24582#L178 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 24583#L425 assume !(0 != activate_threads_~tmp~1#1); 24815#L425-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24830#L185 assume !(1 == ~t1_pc~0); 26482#L185-2 is_transmit1_triggered_~__retres1~1#1 := 0; 26481#L196 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24660#L197 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 24655#L433 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 24656#L433-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24716#L204 assume !(1 == ~t2_pc~0); 24717#L204-2 is_transmit2_triggered_~__retres1~2#1 := 0; 24739#L215 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24740#L216 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 24563#L441 assume !(0 != activate_threads_~tmp___1~0#1); 24564#L441-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24724#L382 assume !(1 == ~M_E~0); 24725#L382-2 assume !(1 == ~T1_E~0); 24672#L387-1 assume !(1 == ~T2_E~0); 24673#L392-1 assume !(1 == ~E_M~0); 24704#L397-1 assume !(1 == ~E_1~0); 24705#L402-1 assume !(1 == ~E_2~0); 26450#L407-1 assume { :end_inline_reset_delta_events } true; 26448#L553-2 assume !false; 26428#L554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 26420#L319 [2022-10-17 10:28:24,567 INFO L750 eck$LassoCheckResult]: Loop: 26420#L319 assume !false; 26417#L282 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 26413#L254 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 26408#L271 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 26405#L272 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 26403#L286 assume 0 != eval_~tmp~0#1; 26398#L286-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 26394#L294 assume !(0 != eval_~tmp_ndt_1~0#1); 26395#L291 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 26443#L308 assume !(0 != eval_~tmp_ndt_2~0#1); 26427#L305 assume !(0 == ~t2_st~0); 26420#L319 [2022-10-17 10:28:24,567 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:28:24,567 INFO L85 PathProgramCache]: Analyzing trace with hash -1720071637, now seen corresponding path program 1 times [2022-10-17 10:28:24,568 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:28:24,568 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [871199883] [2022-10-17 10:28:24,568 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:28:24,568 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:28:24,576 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:28:24,597 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:28:24,597 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:28:24,597 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [871199883] [2022-10-17 10:28:24,599 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [871199883] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:28:24,599 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:28:24,599 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:28:24,599 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1165939534] [2022-10-17 10:28:24,600 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:28:24,600 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:28:24,600 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:28:24,601 INFO L85 PathProgramCache]: Analyzing trace with hash 186468612, now seen corresponding path program 1 times [2022-10-17 10:28:24,601 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:28:24,601 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1154783505] [2022-10-17 10:28:24,601 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:28:24,602 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:28:24,607 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:28:24,608 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:28:24,611 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:28:24,614 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:28:24,717 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:28:24,717 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:28:24,717 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:28:24,718 INFO L87 Difference]: Start difference. First operand 2925 states and 3964 transitions. cyclomatic complexity: 1042 Second operand has 3 states, 3 states have (on average 14.0) internal successors, (42), 3 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:28:24,750 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:28:24,750 INFO L93 Difference]: Finished difference Result 2888 states and 3915 transitions. [2022-10-17 10:28:24,751 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2888 states and 3915 transitions. [2022-10-17 10:28:24,769 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2841 [2022-10-17 10:28:24,793 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2888 states to 2888 states and 3915 transitions. [2022-10-17 10:28:24,794 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2888 [2022-10-17 10:28:24,797 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2888 [2022-10-17 10:28:24,797 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2888 states and 3915 transitions. [2022-10-17 10:28:24,803 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:28:24,804 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2888 states and 3915 transitions. [2022-10-17 10:28:24,808 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2888 states and 3915 transitions. [2022-10-17 10:28:24,865 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2888 to 2888. [2022-10-17 10:28:24,873 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2888 states, 2888 states have (on average 1.3556094182825484) internal successors, (3915), 2887 states have internal predecessors, (3915), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:28:24,882 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2888 states to 2888 states and 3915 transitions. [2022-10-17 10:28:24,883 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2888 states and 3915 transitions. [2022-10-17 10:28:24,883 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:28:24,884 INFO L428 stractBuchiCegarLoop]: Abstraction has 2888 states and 3915 transitions. [2022-10-17 10:28:24,884 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-10-17 10:28:24,884 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2888 states and 3915 transitions. [2022-10-17 10:28:24,897 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2841 [2022-10-17 10:28:24,897 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:28:24,897 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:28:24,898 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:28:24,898 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:28:24,898 INFO L748 eck$LassoCheckResult]: Stem: 30637#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 30581#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 30582#L516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 30606#L224 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 30485#L231 assume 1 == ~m_i~0;~m_st~0 := 0; 30351#L231-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 30352#L236-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 30547#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 30399#L344 assume !(0 == ~M_E~0); 30400#L344-2 assume !(0 == ~T1_E~0); 30575#L349-1 assume !(0 == ~T2_E~0); 30418#L354-1 assume !(0 == ~E_M~0); 30419#L359-1 assume !(0 == ~E_1~0); 30413#L364-1 assume !(0 == ~E_2~0); 30414#L369-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30503#L166 assume !(1 == ~m_pc~0); 30504#L166-2 is_master_triggered_~__retres1~0#1 := 0; 30585#L177 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30397#L178 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 30398#L425 assume !(0 != activate_threads_~tmp~1#1); 30625#L425-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30515#L185 assume !(1 == ~t1_pc~0); 30424#L185-2 is_transmit1_triggered_~__retres1~1#1 := 0; 30425#L196 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30464#L197 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 30469#L433 assume !(0 != activate_threads_~tmp___0~0#1); 30470#L433-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30528#L204 assume !(1 == ~t2_pc~0); 30513#L204-2 is_transmit2_triggered_~__retres1~2#1 := 0; 30514#L215 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30549#L216 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 30379#L441 assume !(0 != activate_threads_~tmp___1~0#1); 30380#L441-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30506#L382 assume !(1 == ~M_E~0); 30369#L382-2 assume !(1 == ~T1_E~0); 30370#L387-1 assume !(1 == ~T2_E~0); 30489#L392-1 assume !(1 == ~E_M~0); 30521#L397-1 assume !(1 == ~E_1~0); 30522#L402-1 assume !(1 == ~E_2~0); 30509#L407-1 assume { :end_inline_reset_delta_events } true; 30510#L553-2 assume !false; 31580#L554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 31578#L319 [2022-10-17 10:28:24,899 INFO L750 eck$LassoCheckResult]: Loop: 31578#L319 assume !false; 31577#L282 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 31575#L254 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 31573#L271 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 31571#L272 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 31569#L286 assume 0 != eval_~tmp~0#1; 31566#L286-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 31563#L294 assume !(0 != eval_~tmp_ndt_1~0#1); 31560#L291 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 31511#L308 assume !(0 != eval_~tmp_ndt_2~0#1); 31559#L305 assume !(0 == ~t2_st~0); 31578#L319 [2022-10-17 10:28:24,899 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:28:24,899 INFO L85 PathProgramCache]: Analyzing trace with hash 327016235, now seen corresponding path program 2 times [2022-10-17 10:28:24,899 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:28:24,902 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [407574916] [2022-10-17 10:28:24,902 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:28:24,902 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:28:24,911 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:28:24,912 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:28:24,917 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:28:24,926 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:28:24,927 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:28:24,927 INFO L85 PathProgramCache]: Analyzing trace with hash 186468612, now seen corresponding path program 2 times [2022-10-17 10:28:24,927 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:28:24,927 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1562293916] [2022-10-17 10:28:24,928 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:28:24,928 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:28:24,932 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:28:24,932 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:28:24,934 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:28:24,936 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:28:24,939 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:28:24,939 INFO L85 PathProgramCache]: Analyzing trace with hash -642569318, now seen corresponding path program 1 times [2022-10-17 10:28:24,939 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:28:24,939 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [498221419] [2022-10-17 10:28:24,940 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:28:24,940 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:28:24,950 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:28:24,979 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:28:24,979 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:28:24,980 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [498221419] [2022-10-17 10:28:24,980 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [498221419] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:28:24,980 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:28:24,980 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-10-17 10:28:24,981 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2111274192] [2022-10-17 10:28:24,981 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:28:25,065 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:28:25,066 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:28:25,066 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:28:25,066 INFO L87 Difference]: Start difference. First operand 2888 states and 3915 transitions. cyclomatic complexity: 1030 Second operand has 3 states, 2 states have (on average 26.5) internal successors, (53), 3 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:28:25,126 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:28:25,126 INFO L93 Difference]: Finished difference Result 4907 states and 6588 transitions. [2022-10-17 10:28:25,126 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4907 states and 6588 transitions. [2022-10-17 10:28:25,154 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 4856 [2022-10-17 10:28:25,195 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4907 states to 4907 states and 6588 transitions. [2022-10-17 10:28:25,195 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4907 [2022-10-17 10:28:25,201 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4907 [2022-10-17 10:28:25,201 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4907 states and 6588 transitions. [2022-10-17 10:28:25,210 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:28:25,211 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4907 states and 6588 transitions. [2022-10-17 10:28:25,217 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4907 states and 6588 transitions. [2022-10-17 10:28:25,324 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4907 to 4851. [2022-10-17 10:28:25,335 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4851 states, 4851 states have (on average 1.3465264893836322) internal successors, (6532), 4850 states have internal predecessors, (6532), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:28:25,352 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4851 states to 4851 states and 6532 transitions. [2022-10-17 10:28:25,352 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4851 states and 6532 transitions. [2022-10-17 10:28:25,353 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:28:25,354 INFO L428 stractBuchiCegarLoop]: Abstraction has 4851 states and 6532 transitions. [2022-10-17 10:28:25,354 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-10-17 10:28:25,354 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4851 states and 6532 transitions. [2022-10-17 10:28:25,376 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 4800 [2022-10-17 10:28:25,376 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:28:25,376 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:28:25,377 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:28:25,377 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:28:25,377 INFO L748 eck$LassoCheckResult]: Stem: 38450#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 38394#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 38395#L516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 38424#L224 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 38285#L231 assume 1 == ~m_i~0;~m_st~0 := 0; 38154#L231-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 38155#L236-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 38360#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 38203#L344 assume !(0 == ~M_E~0); 38204#L344-2 assume !(0 == ~T1_E~0); 38389#L349-1 assume !(0 == ~T2_E~0); 38223#L354-1 assume !(0 == ~E_M~0); 38224#L359-1 assume !(0 == ~E_1~0); 38218#L364-1 assume !(0 == ~E_2~0); 38219#L369-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 38309#L166 assume !(1 == ~m_pc~0); 38310#L166-2 is_master_triggered_~__retres1~0#1 := 0; 38401#L177 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 38201#L178 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 38202#L425 assume !(0 != activate_threads_~tmp~1#1); 38445#L425-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38322#L185 assume !(1 == ~t1_pc~0); 38229#L185-2 is_transmit1_triggered_~__retres1~1#1 := 0; 38230#L196 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38267#L197 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 38273#L433 assume !(0 != activate_threads_~tmp___0~0#1); 38274#L433-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38338#L204 assume !(1 == ~t2_pc~0); 38320#L204-2 is_transmit2_triggered_~__retres1~2#1 := 0; 38321#L215 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38362#L216 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 38183#L441 assume !(0 != activate_threads_~tmp___1~0#1); 38184#L441-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38314#L382 assume !(1 == ~M_E~0); 38172#L382-2 assume !(1 == ~T1_E~0); 38173#L387-1 assume !(1 == ~T2_E~0); 38292#L392-1 assume !(1 == ~E_M~0); 38328#L397-1 assume !(1 == ~E_1~0); 38329#L402-1 assume !(1 == ~E_2~0); 38315#L407-1 assume { :end_inline_reset_delta_events } true; 38316#L553-2 assume !false; 40603#L554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40601#L319 [2022-10-17 10:28:25,378 INFO L750 eck$LassoCheckResult]: Loop: 40601#L319 assume !false; 40598#L282 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 40594#L254 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 40592#L271 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 40590#L272 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 40572#L286 assume 0 != eval_~tmp~0#1; 40567#L286-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 40564#L294 assume !(0 != eval_~tmp_ndt_1~0#1); 40558#L291 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 40536#L308 assume !(0 != eval_~tmp_ndt_2~0#1); 40556#L305 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 40602#L322 assume !(0 != eval_~tmp_ndt_3~0#1); 40601#L319 [2022-10-17 10:28:25,378 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:28:25,378 INFO L85 PathProgramCache]: Analyzing trace with hash 327016235, now seen corresponding path program 3 times [2022-10-17 10:28:25,379 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:28:25,379 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1988526316] [2022-10-17 10:28:25,379 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:28:25,379 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:28:25,393 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:28:25,393 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:28:25,400 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:28:25,414 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:28:25,414 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:28:25,414 INFO L85 PathProgramCache]: Analyzing trace with hash 1485556888, now seen corresponding path program 1 times [2022-10-17 10:28:25,415 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:28:25,415 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1114282337] [2022-10-17 10:28:25,415 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:28:25,415 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:28:25,421 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:28:25,421 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:28:25,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:28:25,428 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:28:25,428 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:28:25,429 INFO L85 PathProgramCache]: Analyzing trace with hash 1555184834, now seen corresponding path program 1 times [2022-10-17 10:28:25,429 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:28:25,429 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1197937531] [2022-10-17 10:28:25,429 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:28:25,429 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:28:25,448 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:28:25,449 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:28:25,455 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:28:25,465 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:28:26,556 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:28:26,556 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:28:26,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:28:26,737 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 17.10 10:28:26 BoogieIcfgContainer [2022-10-17 10:28:26,741 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2022-10-17 10:28:26,742 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-10-17 10:28:26,742 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-10-17 10:28:26,742 INFO L275 PluginConnector]: Witness Printer initialized [2022-10-17 10:28:26,743 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 17.10 10:28:20" (3/4) ... [2022-10-17 10:28:26,746 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2022-10-17 10:28:26,833 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4e9a4131-f225-4804-84c0-dc676b3b2fdb/bin/uautomizer-J5u9QxTXDZ/witness.graphml [2022-10-17 10:28:26,834 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-10-17 10:28:26,835 INFO L158 Benchmark]: Toolchain (without parser) took 8290.57ms. Allocated memory was 92.3MB in the beginning and 167.8MB in the end (delta: 75.5MB). Free memory was 68.0MB in the beginning and 66.4MB in the end (delta: 1.6MB). Peak memory consumption was 76.2MB. Max. memory is 16.1GB. [2022-10-17 10:28:26,835 INFO L158 Benchmark]: CDTParser took 0.32ms. Allocated memory is still 92.3MB. Free memory is still 63.7MB. There was no memory consumed. Max. memory is 16.1GB. [2022-10-17 10:28:26,835 INFO L158 Benchmark]: CACSL2BoogieTranslator took 462.13ms. Allocated memory is still 92.3MB. Free memory was 67.7MB in the beginning and 62.0MB in the end (delta: 5.7MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2022-10-17 10:28:26,836 INFO L158 Benchmark]: Boogie Procedure Inliner took 60.51ms. Allocated memory is still 92.3MB. Free memory was 62.0MB in the beginning and 59.0MB in the end (delta: 3.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-10-17 10:28:26,836 INFO L158 Benchmark]: Boogie Preprocessor took 72.51ms. Allocated memory is still 92.3MB. Free memory was 59.0MB in the beginning and 56.5MB in the end (delta: 2.5MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-10-17 10:28:26,837 INFO L158 Benchmark]: RCFGBuilder took 1105.20ms. Allocated memory was 92.3MB in the beginning and 115.3MB in the end (delta: 23.1MB). Free memory was 56.3MB in the beginning and 72.3MB in the end (delta: -16.0MB). Peak memory consumption was 18.1MB. Max. memory is 16.1GB. [2022-10-17 10:28:26,838 INFO L158 Benchmark]: BuchiAutomizer took 6492.33ms. Allocated memory was 115.3MB in the beginning and 167.8MB in the end (delta: 52.4MB). Free memory was 72.3MB in the beginning and 71.7MB in the end (delta: 694.0kB). Peak memory consumption was 53.4MB. Max. memory is 16.1GB. [2022-10-17 10:28:26,838 INFO L158 Benchmark]: Witness Printer took 91.83ms. Allocated memory is still 167.8MB. Free memory was 71.7MB in the beginning and 66.4MB in the end (delta: 5.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2022-10-17 10:28:26,841 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.32ms. Allocated memory is still 92.3MB. Free memory is still 63.7MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 462.13ms. Allocated memory is still 92.3MB. Free memory was 67.7MB in the beginning and 62.0MB in the end (delta: 5.7MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 60.51ms. Allocated memory is still 92.3MB. Free memory was 62.0MB in the beginning and 59.0MB in the end (delta: 3.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 72.51ms. Allocated memory is still 92.3MB. Free memory was 59.0MB in the beginning and 56.5MB in the end (delta: 2.5MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 1105.20ms. Allocated memory was 92.3MB in the beginning and 115.3MB in the end (delta: 23.1MB). Free memory was 56.3MB in the beginning and 72.3MB in the end (delta: -16.0MB). Peak memory consumption was 18.1MB. Max. memory is 16.1GB. * BuchiAutomizer took 6492.33ms. Allocated memory was 115.3MB in the beginning and 167.8MB in the end (delta: 52.4MB). Free memory was 72.3MB in the beginning and 71.7MB in the end (delta: 694.0kB). Peak memory consumption was 53.4MB. Max. memory is 16.1GB. * Witness Printer took 91.83ms. Allocated memory is still 167.8MB. Free memory was 71.7MB in the beginning and 66.4MB in the end (delta: 5.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 13 terminating modules (13 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.13 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 4851 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 6.2s and 14 iterations. TraceHistogramMax:1. Analysis of lassos took 3.6s. Construction of modules took 0.4s. Büchi inclusion checks took 1.9s. Highest rank in rank-based complementation 0. Minimization of det autom 13. Minimization of nondet autom 0. Automata minimization 0.7s AutomataMinimizationTime, 13 MinimizatonAttempts, 2971 StatesRemovedByMinimization, 9 NontrivialMinimizations. Non-live state removal took 0.4s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 5176 SdHoareTripleChecker+Valid, 0.5s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 5176 mSDsluCounter, 8821 SdHoareTripleChecker+Invalid, 0.4s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 4401 mSDsCounter, 120 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 329 IncrementalHoareTripleChecker+Invalid, 449 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 120 mSolverCounterUnsat, 4420 mSDtfsCounter, 329 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc2 concLT0 SILN1 SILU0 SILI7 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 281]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int m_st ; [L28] int t1_st ; [L29] int t2_st ; [L30] int m_i ; [L31] int t1_i ; [L32] int t2_i ; [L33] int M_E = 2; [L34] int T1_E = 2; [L35] int T2_E = 2; [L36] int E_M = 2; [L37] int E_1 = 2; [L38] int E_2 = 2; [L43] int token ; [L45] int local ; VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, token=0] [L598] int __retres1 ; [L602] CALL init_model() [L512] m_i = 1 [L513] t1_i = 1 [L514] t2_i = 1 VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L602] RET init_model() [L603] CALL start_simulation() [L539] int kernel_st ; [L540] int tmp ; [L541] int tmp___0 ; [L545] kernel_st = 0 [L546] FCALL update_channels() [L547] CALL init_threads() [L231] COND TRUE m_i == 1 [L232] m_st = 0 VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L236] COND TRUE t1_i == 1 [L237] t1_st = 0 VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L241] COND TRUE t2_i == 1 [L242] t2_st = 0 VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L547] RET init_threads() [L548] CALL fire_delta_events() [L344] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L349] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L354] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L359] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L364] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L369] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L548] RET fire_delta_events() [L549] CALL activate_threads() [L417] int tmp ; [L418] int tmp___0 ; [L419] int tmp___1 ; [L423] CALL, EXPR is_master_triggered() [L163] int __retres1 ; VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L166] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L176] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L178] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L423] RET, EXPR is_master_triggered() [L423] tmp = is_master_triggered() [L425] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=0, token=0] [L431] CALL, EXPR is_transmit1_triggered() [L182] int __retres1 ; VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L185] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L195] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L197] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L431] RET, EXPR is_transmit1_triggered() [L431] tmp___0 = is_transmit1_triggered() [L433] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=0, tmp___0=0, token=0] [L439] CALL, EXPR is_transmit2_triggered() [L201] int __retres1 ; VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L204] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L214] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L216] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L439] RET, EXPR is_transmit2_triggered() [L439] tmp___1 = is_transmit2_triggered() [L441] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=0, tmp___0=0, tmp___1=0, token=0] [L549] RET activate_threads() [L550] CALL reset_delta_events() [L382] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L387] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L392] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L397] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L402] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L407] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L550] RET reset_delta_events() [L553] COND TRUE 1 VAL [E_1=2, E_2=2, E_M=2, kernel_st=0, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L556] kernel_st = 1 [L557] CALL eval() [L277] int tmp ; VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] Loop: [L281] COND TRUE 1 [L284] CALL, EXPR exists_runnable_thread() [L251] int __retres1 ; [L254] COND TRUE m_st == 0 [L255] __retres1 = 1 [L272] return (__retres1); [L284] RET, EXPR exists_runnable_thread() [L284] tmp = exists_runnable_thread() [L286] COND TRUE \read(tmp) [L291] COND TRUE m_st == 0 [L292] int tmp_ndt_1; [L293] tmp_ndt_1 = __VERIFIER_nondet_int() [L294] COND FALSE !(\read(tmp_ndt_1)) [L305] COND TRUE t1_st == 0 [L306] int tmp_ndt_2; [L307] tmp_ndt_2 = __VERIFIER_nondet_int() [L308] COND FALSE !(\read(tmp_ndt_2)) [L319] COND TRUE t2_st == 0 [L320] int tmp_ndt_3; [L321] tmp_ndt_3 = __VERIFIER_nondet_int() [L322] COND FALSE !(\read(tmp_ndt_3)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 281]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int m_st ; [L28] int t1_st ; [L29] int t2_st ; [L30] int m_i ; [L31] int t1_i ; [L32] int t2_i ; [L33] int M_E = 2; [L34] int T1_E = 2; [L35] int T2_E = 2; [L36] int E_M = 2; [L37] int E_1 = 2; [L38] int E_2 = 2; [L43] int token ; [L45] int local ; VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, token=0] [L598] int __retres1 ; [L602] CALL init_model() [L512] m_i = 1 [L513] t1_i = 1 [L514] t2_i = 1 VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L602] RET init_model() [L603] CALL start_simulation() [L539] int kernel_st ; [L540] int tmp ; [L541] int tmp___0 ; [L545] kernel_st = 0 [L546] FCALL update_channels() [L547] CALL init_threads() [L231] COND TRUE m_i == 1 [L232] m_st = 0 VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L236] COND TRUE t1_i == 1 [L237] t1_st = 0 VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L241] COND TRUE t2_i == 1 [L242] t2_st = 0 VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L547] RET init_threads() [L548] CALL fire_delta_events() [L344] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L349] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L354] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L359] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L364] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L369] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L548] RET fire_delta_events() [L549] CALL activate_threads() [L417] int tmp ; [L418] int tmp___0 ; [L419] int tmp___1 ; [L423] CALL, EXPR is_master_triggered() [L163] int __retres1 ; VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L166] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L176] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L178] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L423] RET, EXPR is_master_triggered() [L423] tmp = is_master_triggered() [L425] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=0, token=0] [L431] CALL, EXPR is_transmit1_triggered() [L182] int __retres1 ; VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L185] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L195] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L197] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L431] RET, EXPR is_transmit1_triggered() [L431] tmp___0 = is_transmit1_triggered() [L433] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=0, tmp___0=0, token=0] [L439] CALL, EXPR is_transmit2_triggered() [L201] int __retres1 ; VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L204] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L214] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L216] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L439] RET, EXPR is_transmit2_triggered() [L439] tmp___1 = is_transmit2_triggered() [L441] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=0, tmp___0=0, tmp___1=0, token=0] [L549] RET activate_threads() [L550] CALL reset_delta_events() [L382] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L387] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L392] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L397] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L402] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L407] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L550] RET reset_delta_events() [L553] COND TRUE 1 VAL [E_1=2, E_2=2, E_M=2, kernel_st=0, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L556] kernel_st = 1 [L557] CALL eval() [L277] int tmp ; VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] Loop: [L281] COND TRUE 1 [L284] CALL, EXPR exists_runnable_thread() [L251] int __retres1 ; [L254] COND TRUE m_st == 0 [L255] __retres1 = 1 [L272] return (__retres1); [L284] RET, EXPR exists_runnable_thread() [L284] tmp = exists_runnable_thread() [L286] COND TRUE \read(tmp) [L291] COND TRUE m_st == 0 [L292] int tmp_ndt_1; [L293] tmp_ndt_1 = __VERIFIER_nondet_int() [L294] COND FALSE !(\read(tmp_ndt_1)) [L305] COND TRUE t1_st == 0 [L306] int tmp_ndt_2; [L307] tmp_ndt_2 = __VERIFIER_nondet_int() [L308] COND FALSE !(\read(tmp_ndt_2)) [L319] COND TRUE t2_st == 0 [L320] int tmp_ndt_3; [L321] tmp_ndt_3 = __VERIFIER_nondet_int() [L322] COND FALSE !(\read(tmp_ndt_3)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2022-10-17 10:28:26,955 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4e9a4131-f225-4804-84c0-dc676b3b2fdb/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)