./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.02.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version dbf71c69 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_78788a82-ad02-4763-9196-a0d98a202eca/bin/uautomizer-J5u9QxTXDZ/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_78788a82-ad02-4763-9196-a0d98a202eca/bin/uautomizer-J5u9QxTXDZ/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_78788a82-ad02-4763-9196-a0d98a202eca/bin/uautomizer-J5u9QxTXDZ/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_78788a82-ad02-4763-9196-a0d98a202eca/bin/uautomizer-J5u9QxTXDZ/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.02.cil-2.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_78788a82-ad02-4763-9196-a0d98a202eca/bin/uautomizer-J5u9QxTXDZ/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_78788a82-ad02-4763-9196-a0d98a202eca/bin/uautomizer-J5u9QxTXDZ --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash bc8487f898950b83c481f83a71342af68752fb6e7598d76df123761c32c89f72 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-dbf71c6-m [2022-10-17 10:14:58,005 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-10-17 10:14:58,008 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-10-17 10:14:58,064 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-10-17 10:14:58,065 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-10-17 10:14:58,069 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-10-17 10:14:58,072 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-10-17 10:14:58,078 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-10-17 10:14:58,080 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-10-17 10:14:58,086 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-10-17 10:14:58,087 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-10-17 10:14:58,090 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-10-17 10:14:58,091 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-10-17 10:14:58,093 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-10-17 10:14:58,095 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-10-17 10:14:58,097 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-10-17 10:14:58,099 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-10-17 10:14:58,100 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-10-17 10:14:58,102 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-10-17 10:14:58,110 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-10-17 10:14:58,112 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-10-17 10:14:58,114 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-10-17 10:14:58,119 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-10-17 10:14:58,120 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-10-17 10:14:58,130 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-10-17 10:14:58,131 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-10-17 10:14:58,131 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-10-17 10:14:58,133 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-10-17 10:14:58,134 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-10-17 10:14:58,136 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-10-17 10:14:58,136 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-10-17 10:14:58,137 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-10-17 10:14:58,140 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-10-17 10:14:58,141 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-10-17 10:14:58,143 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-10-17 10:14:58,143 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-10-17 10:14:58,144 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-10-17 10:14:58,144 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-10-17 10:14:58,144 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-10-17 10:14:58,145 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-10-17 10:14:58,146 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-10-17 10:14:58,147 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_78788a82-ad02-4763-9196-a0d98a202eca/bin/uautomizer-J5u9QxTXDZ/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-10-17 10:14:58,190 INFO L113 SettingsManager]: Loading preferences was successful [2022-10-17 10:14:58,190 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-10-17 10:14:58,191 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-10-17 10:14:58,191 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-10-17 10:14:58,193 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-10-17 10:14:58,193 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-10-17 10:14:58,193 INFO L138 SettingsManager]: * Use SBE=true [2022-10-17 10:14:58,193 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-10-17 10:14:58,194 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-10-17 10:14:58,194 INFO L138 SettingsManager]: * Use old map elimination=false [2022-10-17 10:14:58,195 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-10-17 10:14:58,195 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-10-17 10:14:58,196 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-10-17 10:14:58,196 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-10-17 10:14:58,196 INFO L138 SettingsManager]: * sizeof long=4 [2022-10-17 10:14:58,196 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-10-17 10:14:58,197 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-10-17 10:14:58,197 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-10-17 10:14:58,197 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-10-17 10:14:58,197 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-10-17 10:14:58,197 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-10-17 10:14:58,198 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-10-17 10:14:58,198 INFO L138 SettingsManager]: * sizeof long double=12 [2022-10-17 10:14:58,198 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-10-17 10:14:58,198 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-10-17 10:14:58,199 INFO L138 SettingsManager]: * Use constant arrays=true [2022-10-17 10:14:58,199 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-10-17 10:14:58,199 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-10-17 10:14:58,199 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-10-17 10:14:58,200 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-10-17 10:14:58,200 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-10-17 10:14:58,201 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-10-17 10:14:58,201 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_78788a82-ad02-4763-9196-a0d98a202eca/bin/uautomizer-J5u9QxTXDZ/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_78788a82-ad02-4763-9196-a0d98a202eca/bin/uautomizer-J5u9QxTXDZ Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> bc8487f898950b83c481f83a71342af68752fb6e7598d76df123761c32c89f72 [2022-10-17 10:14:58,469 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-10-17 10:14:58,497 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-10-17 10:14:58,499 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-10-17 10:14:58,500 INFO L271 PluginConnector]: Initializing CDTParser... [2022-10-17 10:14:58,501 INFO L275 PluginConnector]: CDTParser initialized [2022-10-17 10:14:58,503 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_78788a82-ad02-4763-9196-a0d98a202eca/bin/uautomizer-J5u9QxTXDZ/../../sv-benchmarks/c/systemc/token_ring.02.cil-2.c [2022-10-17 10:14:58,576 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_78788a82-ad02-4763-9196-a0d98a202eca/bin/uautomizer-J5u9QxTXDZ/data/c5c1d512c/57fe8692856944d7ab21aec1d76990a0/FLAG5250f7f38 [2022-10-17 10:14:59,013 INFO L306 CDTParser]: Found 1 translation units. [2022-10-17 10:14:59,013 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_78788a82-ad02-4763-9196-a0d98a202eca/sv-benchmarks/c/systemc/token_ring.02.cil-2.c [2022-10-17 10:14:59,023 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_78788a82-ad02-4763-9196-a0d98a202eca/bin/uautomizer-J5u9QxTXDZ/data/c5c1d512c/57fe8692856944d7ab21aec1d76990a0/FLAG5250f7f38 [2022-10-17 10:14:59,394 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_78788a82-ad02-4763-9196-a0d98a202eca/bin/uautomizer-J5u9QxTXDZ/data/c5c1d512c/57fe8692856944d7ab21aec1d76990a0 [2022-10-17 10:14:59,397 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-10-17 10:14:59,398 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-10-17 10:14:59,400 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-10-17 10:14:59,400 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-10-17 10:14:59,404 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-10-17 10:14:59,404 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.10 10:14:59" (1/1) ... [2022-10-17 10:14:59,405 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7bc67159 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:14:59, skipping insertion in model container [2022-10-17 10:14:59,406 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.10 10:14:59" (1/1) ... [2022-10-17 10:14:59,413 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-10-17 10:14:59,444 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-10-17 10:14:59,665 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_78788a82-ad02-4763-9196-a0d98a202eca/sv-benchmarks/c/systemc/token_ring.02.cil-2.c[671,684] [2022-10-17 10:14:59,754 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-10-17 10:14:59,765 INFO L203 MainTranslator]: Completed pre-run [2022-10-17 10:14:59,777 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_78788a82-ad02-4763-9196-a0d98a202eca/sv-benchmarks/c/systemc/token_ring.02.cil-2.c[671,684] [2022-10-17 10:14:59,805 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-10-17 10:14:59,822 INFO L208 MainTranslator]: Completed translation [2022-10-17 10:14:59,824 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:14:59 WrapperNode [2022-10-17 10:14:59,824 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-10-17 10:14:59,825 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-10-17 10:14:59,826 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-10-17 10:14:59,826 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-10-17 10:14:59,834 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:14:59" (1/1) ... [2022-10-17 10:14:59,848 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:14:59" (1/1) ... [2022-10-17 10:14:59,910 INFO L138 Inliner]: procedures = 32, calls = 38, calls flagged for inlining = 33, calls inlined = 50, statements flattened = 606 [2022-10-17 10:14:59,910 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-10-17 10:14:59,911 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-10-17 10:14:59,911 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-10-17 10:14:59,911 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-10-17 10:14:59,920 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:14:59" (1/1) ... [2022-10-17 10:14:59,920 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:14:59" (1/1) ... [2022-10-17 10:14:59,924 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:14:59" (1/1) ... [2022-10-17 10:14:59,924 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:14:59" (1/1) ... [2022-10-17 10:14:59,935 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:14:59" (1/1) ... [2022-10-17 10:14:59,946 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:14:59" (1/1) ... [2022-10-17 10:14:59,950 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:14:59" (1/1) ... [2022-10-17 10:14:59,953 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:14:59" (1/1) ... [2022-10-17 10:14:59,974 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-10-17 10:14:59,975 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-10-17 10:14:59,975 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-10-17 10:14:59,975 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-10-17 10:14:59,977 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:14:59" (1/1) ... [2022-10-17 10:14:59,984 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:14:59,999 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_78788a82-ad02-4763-9196-a0d98a202eca/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:15:00,012 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_78788a82-ad02-4763-9196-a0d98a202eca/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:15:00,030 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_78788a82-ad02-4763-9196-a0d98a202eca/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-10-17 10:15:00,060 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-10-17 10:15:00,060 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-10-17 10:15:00,060 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-10-17 10:15:00,060 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-10-17 10:15:00,135 INFO L235 CfgBuilder]: Building ICFG [2022-10-17 10:15:00,137 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-10-17 10:15:00,873 INFO L276 CfgBuilder]: Performing block encoding [2022-10-17 10:15:00,884 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-10-17 10:15:00,884 INFO L300 CfgBuilder]: Removed 5 assume(true) statements. [2022-10-17 10:15:00,887 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 17.10 10:15:00 BoogieIcfgContainer [2022-10-17 10:15:00,887 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-10-17 10:15:00,888 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-10-17 10:15:00,889 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-10-17 10:15:00,895 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-10-17 10:15:00,896 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-10-17 10:15:00,896 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 17.10 10:14:59" (1/3) ... [2022-10-17 10:15:00,897 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@27cb6fe2 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.10 10:15:00, skipping insertion in model container [2022-10-17 10:15:00,898 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-10-17 10:15:00,898 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:14:59" (2/3) ... [2022-10-17 10:15:00,898 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@27cb6fe2 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.10 10:15:00, skipping insertion in model container [2022-10-17 10:15:00,898 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-10-17 10:15:00,898 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 17.10 10:15:00" (3/3) ... [2022-10-17 10:15:00,900 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.02.cil-2.c [2022-10-17 10:15:00,990 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-10-17 10:15:00,990 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-10-17 10:15:00,990 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-10-17 10:15:00,990 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-10-17 10:15:00,991 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-10-17 10:15:00,991 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-10-17 10:15:00,991 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-10-17 10:15:00,991 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-10-17 10:15:00,998 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 238 states, 237 states have (on average 1.540084388185654) internal successors, (365), 237 states have internal predecessors, (365), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:15:01,036 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 191 [2022-10-17 10:15:01,036 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:15:01,036 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:15:01,047 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:15:01,047 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:15:01,047 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-10-17 10:15:01,049 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 238 states, 237 states have (on average 1.540084388185654) internal successors, (365), 237 states have internal predecessors, (365), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:15:01,070 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 191 [2022-10-17 10:15:01,070 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:15:01,071 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:15:01,097 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:15:01,097 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:15:01,106 INFO L748 eck$LassoCheckResult]: Stem: 226#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 150#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 152#L528true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 161#L236true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 179#L243true assume !(1 == ~m_i~0);~m_st~0 := 2; 109#L243-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 176#L248-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 15#L253-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 191#L356true assume !(0 == ~M_E~0); 67#L356-2true assume !(0 == ~T1_E~0); 133#L361-1true assume !(0 == ~T2_E~0); 131#L366-1true assume 0 == ~E_M~0;~E_M~0 := 1; 125#L371-1true assume !(0 == ~E_1~0); 48#L376-1true assume !(0 == ~E_2~0); 83#L381-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18#L178true assume 1 == ~m_pc~0; 231#L179true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 69#L189true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 162#L190true activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 117#L437true assume !(0 != activate_threads_~tmp~1#1); 28#L437-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 56#L197true assume !(1 == ~t1_pc~0); 208#L197-2true is_transmit1_triggered_~__retres1~1#1 := 0; 210#L208true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 216#L209true activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 25#L445true assume !(0 != activate_threads_~tmp___0~0#1); 188#L445-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 209#L216true assume 1 == ~t2_pc~0; 14#L217true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 78#L227true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 68#L228true activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 153#L453true assume !(0 != activate_threads_~tmp___1~0#1); 124#L453-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 128#L394true assume !(1 == ~M_E~0); 204#L394-2true assume 1 == ~T1_E~0;~T1_E~0 := 2; 100#L399-1true assume !(1 == ~T2_E~0); 220#L404-1true assume !(1 == ~E_M~0); 37#L409-1true assume !(1 == ~E_1~0); 159#L414-1true assume !(1 == ~E_2~0); 102#L419-1true assume { :end_inline_reset_delta_events } true; 163#L565-2true [2022-10-17 10:15:01,124 INFO L750 eck$LassoCheckResult]: Loop: 163#L565-2true assume !false; 91#L566true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 123#L331true assume !true; 32#L346true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 107#L236-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 184#L356-3true assume !(0 == ~M_E~0); 147#L356-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 119#L361-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 171#L366-3true assume 0 == ~E_M~0;~E_M~0 := 1; 145#L371-3true assume 0 == ~E_1~0;~E_1~0 := 1; 84#L376-3true assume 0 == ~E_2~0;~E_2~0 := 1; 118#L381-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 82#L178-12true assume !(1 == ~m_pc~0); 3#L178-14true is_master_triggered_~__retres1~0#1 := 0; 101#L189-4true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 143#L190-4true activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 189#L437-12true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 90#L437-14true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 140#L197-12true assume 1 == ~t1_pc~0; 149#L198-4true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 41#L208-4true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 215#L209-4true activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2#L445-12true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 49#L445-14true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 39#L216-12true assume !(1 == ~t2_pc~0); 106#L216-14true is_transmit2_triggered_~__retres1~2#1 := 0; 63#L227-4true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21#L228-4true activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 34#L453-12true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 183#L453-14true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 238#L394-3true assume 1 == ~M_E~0;~M_E~0 := 2; 212#L394-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 12#L399-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 232#L404-3true assume 1 == ~E_M~0;~E_M~0 := 2; 59#L409-3true assume 1 == ~E_1~0;~E_1~0 := 2; 182#L414-3true assume 1 == ~E_2~0;~E_2~0 := 2; 165#L419-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 138#L266-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 54#L283-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 36#L284-1true start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 158#L584true assume !(0 == start_simulation_~tmp~3#1); 104#L584-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 111#L266-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 129#L283-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 137#L284-2true stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 40#L539true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 24#L546true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 148#L547true start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 94#L597true assume !(0 != start_simulation_~tmp___0~1#1); 163#L565-2true [2022-10-17 10:15:01,130 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:15:01,131 INFO L85 PathProgramCache]: Analyzing trace with hash 332551043, now seen corresponding path program 1 times [2022-10-17 10:15:01,156 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:15:01,156 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [891602725] [2022-10-17 10:15:01,157 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:15:01,176 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:15:01,281 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:15:01,414 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:15:01,415 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:15:01,415 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [891602725] [2022-10-17 10:15:01,416 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [891602725] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:15:01,416 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:15:01,416 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:15:01,418 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1633182015] [2022-10-17 10:15:01,419 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:15:01,424 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:15:01,425 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:15:01,426 INFO L85 PathProgramCache]: Analyzing trace with hash -321205323, now seen corresponding path program 1 times [2022-10-17 10:15:01,426 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:15:01,426 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [818309876] [2022-10-17 10:15:01,427 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:15:01,427 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:15:01,442 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:15:01,470 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:15:01,471 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:15:01,471 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [818309876] [2022-10-17 10:15:01,471 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [818309876] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:15:01,472 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:15:01,472 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-10-17 10:15:01,472 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2051261255] [2022-10-17 10:15:01,472 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:15:01,474 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:15:01,475 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:15:01,507 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:15:01,508 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:15:01,511 INFO L87 Difference]: Start difference. First operand has 238 states, 237 states have (on average 1.540084388185654) internal successors, (365), 237 states have internal predecessors, (365), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 3 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:15:01,558 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:15:01,558 INFO L93 Difference]: Finished difference Result 236 states and 350 transitions. [2022-10-17 10:15:01,560 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 236 states and 350 transitions. [2022-10-17 10:15:01,577 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 187 [2022-10-17 10:15:01,589 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 236 states to 230 states and 344 transitions. [2022-10-17 10:15:01,590 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 230 [2022-10-17 10:15:01,591 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 230 [2022-10-17 10:15:01,592 INFO L73 IsDeterministic]: Start isDeterministic. Operand 230 states and 344 transitions. [2022-10-17 10:15:01,594 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:15:01,595 INFO L218 hiAutomatonCegarLoop]: Abstraction has 230 states and 344 transitions. [2022-10-17 10:15:01,612 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 230 states and 344 transitions. [2022-10-17 10:15:01,633 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 230 to 230. [2022-10-17 10:15:01,636 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 230 states, 230 states have (on average 1.4956521739130435) internal successors, (344), 229 states have internal predecessors, (344), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:15:01,639 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 230 states to 230 states and 344 transitions. [2022-10-17 10:15:01,640 INFO L240 hiAutomatonCegarLoop]: Abstraction has 230 states and 344 transitions. [2022-10-17 10:15:01,648 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:15:01,652 INFO L428 stractBuchiCegarLoop]: Abstraction has 230 states and 344 transitions. [2022-10-17 10:15:01,652 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-10-17 10:15:01,652 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 230 states and 344 transitions. [2022-10-17 10:15:01,655 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 187 [2022-10-17 10:15:01,656 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:15:01,656 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:15:01,658 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:15:01,659 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:15:01,659 INFO L748 eck$LassoCheckResult]: Stem: 712#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 687#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 688#L528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 690#L236 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 696#L243 assume 1 == ~m_i~0;~m_st~0 := 0; 647#L243-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 648#L248-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 513#L253-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 514#L356 assume !(0 == ~M_E~0); 605#L356-2 assume !(0 == ~T1_E~0); 606#L361-1 assume !(0 == ~T2_E~0); 671#L366-1 assume 0 == ~E_M~0;~E_M~0 := 1; 665#L371-1 assume !(0 == ~E_1~0); 580#L376-1 assume !(0 == ~E_2~0); 581#L381-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 517#L178 assume 1 == ~m_pc~0; 518#L179 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 609#L189 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 610#L190 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 657#L437 assume !(0 != activate_threads_~tmp~1#1); 542#L437-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 543#L197 assume !(1 == ~t1_pc~0); 589#L197-2 is_transmit1_triggered_~__retres1~1#1 := 0; 588#L208 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 710#L209 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 535#L445 assume !(0 != activate_threads_~tmp___0~0#1); 536#L445-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 706#L216 assume 1 == ~t2_pc~0; 510#L217 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 511#L227 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 607#L228 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 608#L453 assume !(0 != activate_threads_~tmp___1~0#1); 663#L453-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 664#L394 assume !(1 == ~M_E~0); 669#L394-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 637#L399-1 assume !(1 == ~T2_E~0); 638#L404-1 assume !(1 == ~E_M~0); 560#L409-1 assume !(1 == ~E_1~0); 561#L414-1 assume !(1 == ~E_2~0); 640#L419-1 assume { :end_inline_reset_delta_events } true; 633#L565-2 [2022-10-17 10:15:01,660 INFO L750 eck$LassoCheckResult]: Loop: 633#L565-2 assume !false; 629#L566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 521#L331 assume !false; 631#L294 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 492#L266 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 488#L283 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 578#L284 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 579#L298 assume !(0 != eval_~tmp~0#1); 550#L346 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 551#L236-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 644#L356-3 assume !(0 == ~M_E~0); 686#L356-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 658#L361-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 659#L366-3 assume 0 == ~E_M~0;~E_M~0 := 1; 683#L371-3 assume 0 == ~E_1~0;~E_1~0 := 1; 621#L376-3 assume 0 == ~E_2~0;~E_2~0 := 1; 622#L381-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 620#L178-12 assume !(1 == ~m_pc~0); 485#L178-14 is_master_triggered_~__retres1~0#1 := 0; 486#L189-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 639#L190-4 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 682#L437-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 627#L437-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 628#L197-12 assume !(1 == ~t1_pc~0); 676#L197-14 is_transmit1_triggered_~__retres1~1#1 := 0; 566#L208-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 567#L209-4 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 483#L445-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 484#L445-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 562#L216-12 assume 1 == ~t2_pc~0; 563#L217-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 600#L227-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 526#L228-4 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 527#L453-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 555#L453-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 705#L394-3 assume 1 == ~M_E~0;~M_E~0 := 2; 711#L394-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 506#L399-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 507#L404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 594#L409-3 assume 1 == ~E_1~0;~E_1~0 := 2; 595#L414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 699#L419-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 675#L266-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 496#L283-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 558#L284-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 559#L584 assume !(0 == start_simulation_~tmp~3#1); 583#L584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 642#L266-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 650#L283-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 670#L284-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 565#L539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 533#L546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 534#L547 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 632#L597 assume !(0 != start_simulation_~tmp___0~1#1); 633#L565-2 [2022-10-17 10:15:01,660 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:15:01,661 INFO L85 PathProgramCache]: Analyzing trace with hash 726917829, now seen corresponding path program 1 times [2022-10-17 10:15:01,661 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:15:01,661 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [123947992] [2022-10-17 10:15:01,662 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:15:01,662 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:15:01,681 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:15:01,743 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:15:01,744 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:15:01,744 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [123947992] [2022-10-17 10:15:01,744 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [123947992] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:15:01,745 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:15:01,745 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:15:01,745 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1231198470] [2022-10-17 10:15:01,745 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:15:01,746 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:15:01,747 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:15:01,747 INFO L85 PathProgramCache]: Analyzing trace with hash 175779481, now seen corresponding path program 1 times [2022-10-17 10:15:01,747 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:15:01,748 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2013585905] [2022-10-17 10:15:01,748 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:15:01,748 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:15:01,780 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:15:01,905 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:15:01,905 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:15:01,906 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2013585905] [2022-10-17 10:15:01,906 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2013585905] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:15:01,908 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:15:01,908 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-10-17 10:15:01,909 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2060496112] [2022-10-17 10:15:01,909 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:15:01,910 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:15:01,917 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:15:01,918 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:15:01,918 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:15:01,918 INFO L87 Difference]: Start difference. First operand 230 states and 344 transitions. cyclomatic complexity: 115 Second operand has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 3 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:15:01,945 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:15:01,946 INFO L93 Difference]: Finished difference Result 230 states and 343 transitions. [2022-10-17 10:15:01,946 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 230 states and 343 transitions. [2022-10-17 10:15:01,949 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 187 [2022-10-17 10:15:01,952 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 230 states to 230 states and 343 transitions. [2022-10-17 10:15:01,952 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 230 [2022-10-17 10:15:01,953 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 230 [2022-10-17 10:15:01,954 INFO L73 IsDeterministic]: Start isDeterministic. Operand 230 states and 343 transitions. [2022-10-17 10:15:01,955 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:15:01,956 INFO L218 hiAutomatonCegarLoop]: Abstraction has 230 states and 343 transitions. [2022-10-17 10:15:01,957 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 230 states and 343 transitions. [2022-10-17 10:15:01,980 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 230 to 230. [2022-10-17 10:15:01,981 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 230 states, 230 states have (on average 1.491304347826087) internal successors, (343), 229 states have internal predecessors, (343), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:15:01,983 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 230 states to 230 states and 343 transitions. [2022-10-17 10:15:01,985 INFO L240 hiAutomatonCegarLoop]: Abstraction has 230 states and 343 transitions. [2022-10-17 10:15:01,986 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:15:01,987 INFO L428 stractBuchiCegarLoop]: Abstraction has 230 states and 343 transitions. [2022-10-17 10:15:01,987 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-10-17 10:15:01,988 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 230 states and 343 transitions. [2022-10-17 10:15:01,994 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 187 [2022-10-17 10:15:01,995 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:15:01,995 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:15:01,997 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:15:02,000 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:15:02,001 INFO L748 eck$LassoCheckResult]: Stem: 1181#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 1156#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 1157#L528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1159#L236 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1165#L243 assume 1 == ~m_i~0;~m_st~0 := 0; 1116#L243-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1117#L248-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 982#L253-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 983#L356 assume !(0 == ~M_E~0); 1074#L356-2 assume !(0 == ~T1_E~0); 1075#L361-1 assume !(0 == ~T2_E~0); 1140#L366-1 assume 0 == ~E_M~0;~E_M~0 := 1; 1134#L371-1 assume !(0 == ~E_1~0); 1049#L376-1 assume !(0 == ~E_2~0); 1050#L381-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 986#L178 assume 1 == ~m_pc~0; 987#L179 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1078#L189 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1079#L190 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1126#L437 assume !(0 != activate_threads_~tmp~1#1); 1011#L437-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1012#L197 assume !(1 == ~t1_pc~0); 1058#L197-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1057#L208 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1179#L209 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1004#L445 assume !(0 != activate_threads_~tmp___0~0#1); 1005#L445-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1175#L216 assume 1 == ~t2_pc~0; 979#L217 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 980#L227 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1076#L228 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1077#L453 assume !(0 != activate_threads_~tmp___1~0#1); 1132#L453-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1133#L394 assume !(1 == ~M_E~0); 1138#L394-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1106#L399-1 assume !(1 == ~T2_E~0); 1107#L404-1 assume !(1 == ~E_M~0); 1029#L409-1 assume !(1 == ~E_1~0); 1030#L414-1 assume !(1 == ~E_2~0); 1109#L419-1 assume { :end_inline_reset_delta_events } true; 1102#L565-2 [2022-10-17 10:15:02,001 INFO L750 eck$LassoCheckResult]: Loop: 1102#L565-2 assume !false; 1098#L566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 990#L331 assume !false; 1100#L294 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 961#L266 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 957#L283 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1047#L284 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1048#L298 assume !(0 != eval_~tmp~0#1); 1019#L346 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1020#L236-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1113#L356-3 assume !(0 == ~M_E~0); 1155#L356-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1127#L361-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1128#L366-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1152#L371-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1090#L376-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1091#L381-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1089#L178-12 assume 1 == ~m_pc~0; 1059#L179-4 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 955#L189-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1108#L190-4 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1151#L437-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1096#L437-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1097#L197-12 assume !(1 == ~t1_pc~0); 1145#L197-14 is_transmit1_triggered_~__retres1~1#1 := 0; 1035#L208-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1036#L209-4 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 952#L445-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 953#L445-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1031#L216-12 assume 1 == ~t2_pc~0; 1032#L217-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1069#L227-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 995#L228-4 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 996#L453-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1024#L453-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1174#L394-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1180#L394-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 975#L399-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 976#L404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1063#L409-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1064#L414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1168#L419-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1144#L266-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 965#L283-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1027#L284-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 1028#L584 assume !(0 == start_simulation_~tmp~3#1); 1052#L584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1111#L266-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1119#L283-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1139#L284-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 1034#L539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1002#L546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1003#L547 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 1101#L597 assume !(0 != start_simulation_~tmp___0~1#1); 1102#L565-2 [2022-10-17 10:15:02,002 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:15:02,003 INFO L85 PathProgramCache]: Analyzing trace with hash -1324066169, now seen corresponding path program 1 times [2022-10-17 10:15:02,004 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:15:02,005 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1747794112] [2022-10-17 10:15:02,005 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:15:02,005 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:15:02,033 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:15:02,146 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:15:02,147 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:15:02,147 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1747794112] [2022-10-17 10:15:02,148 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1747794112] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:15:02,148 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:15:02,148 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:15:02,148 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1753752937] [2022-10-17 10:15:02,149 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:15:02,150 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:15:02,151 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:15:02,152 INFO L85 PathProgramCache]: Analyzing trace with hash -949480488, now seen corresponding path program 1 times [2022-10-17 10:15:02,153 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:15:02,153 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [784773737] [2022-10-17 10:15:02,154 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:15:02,155 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:15:02,181 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:15:02,268 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:15:02,269 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:15:02,270 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [784773737] [2022-10-17 10:15:02,271 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [784773737] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:15:02,271 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:15:02,271 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-10-17 10:15:02,271 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1737366558] [2022-10-17 10:15:02,272 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:15:02,273 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:15:02,275 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:15:02,275 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-10-17 10:15:02,276 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-10-17 10:15:02,278 INFO L87 Difference]: Start difference. First operand 230 states and 343 transitions. cyclomatic complexity: 114 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 3 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:15:02,454 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:15:02,454 INFO L93 Difference]: Finished difference Result 372 states and 552 transitions. [2022-10-17 10:15:02,454 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 372 states and 552 transitions. [2022-10-17 10:15:02,460 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 322 [2022-10-17 10:15:02,465 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 372 states to 372 states and 552 transitions. [2022-10-17 10:15:02,465 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 372 [2022-10-17 10:15:02,466 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 372 [2022-10-17 10:15:02,466 INFO L73 IsDeterministic]: Start isDeterministic. Operand 372 states and 552 transitions. [2022-10-17 10:15:02,474 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:15:02,474 INFO L218 hiAutomatonCegarLoop]: Abstraction has 372 states and 552 transitions. [2022-10-17 10:15:02,478 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 372 states and 552 transitions. [2022-10-17 10:15:02,501 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 372 to 371. [2022-10-17 10:15:02,502 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 371 states, 371 states have (on average 1.4851752021563343) internal successors, (551), 370 states have internal predecessors, (551), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:15:02,505 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 371 states to 371 states and 551 transitions. [2022-10-17 10:15:02,505 INFO L240 hiAutomatonCegarLoop]: Abstraction has 371 states and 551 transitions. [2022-10-17 10:15:02,505 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-10-17 10:15:02,506 INFO L428 stractBuchiCegarLoop]: Abstraction has 371 states and 551 transitions. [2022-10-17 10:15:02,507 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-10-17 10:15:02,507 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 371 states and 551 transitions. [2022-10-17 10:15:02,510 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 322 [2022-10-17 10:15:02,510 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:15:02,510 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:15:02,512 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:15:02,512 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:15:02,513 INFO L748 eck$LassoCheckResult]: Stem: 1800#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 1773#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 1774#L528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1776#L236 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1782#L243 assume 1 == ~m_i~0;~m_st~0 := 0; 1730#L243-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1731#L248-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1596#L253-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1597#L356 assume !(0 == ~M_E~0); 1688#L356-2 assume !(0 == ~T1_E~0); 1689#L361-1 assume !(0 == ~T2_E~0); 1756#L366-1 assume !(0 == ~E_M~0); 1749#L371-1 assume !(0 == ~E_1~0); 1663#L376-1 assume !(0 == ~E_2~0); 1664#L381-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1600#L178 assume 1 == ~m_pc~0; 1601#L179 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1692#L189 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1693#L190 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1741#L437 assume !(0 != activate_threads_~tmp~1#1); 1625#L437-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1626#L197 assume !(1 == ~t1_pc~0); 1672#L197-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1671#L208 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1798#L209 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1618#L445 assume !(0 != activate_threads_~tmp___0~0#1); 1619#L445-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1794#L216 assume 1 == ~t2_pc~0; 1593#L217 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1594#L227 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1690#L228 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1691#L453 assume !(0 != activate_threads_~tmp___1~0#1); 1747#L453-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1748#L394 assume 1 == ~M_E~0;~M_E~0 := 2; 1753#L394-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1720#L399-1 assume !(1 == ~T2_E~0); 1721#L404-1 assume !(1 == ~E_M~0); 1643#L409-1 assume !(1 == ~E_1~0); 1644#L414-1 assume !(1 == ~E_2~0); 1723#L419-1 assume { :end_inline_reset_delta_events } true; 1716#L565-2 [2022-10-17 10:15:02,513 INFO L750 eck$LassoCheckResult]: Loop: 1716#L565-2 assume !false; 1712#L566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1604#L331 assume !false; 1714#L294 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1575#L266 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1571#L283 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1661#L284 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1662#L298 assume !(0 != eval_~tmp~0#1); 1633#L346 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1634#L236-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1727#L356-3 assume !(0 == ~M_E~0); 1772#L356-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1742#L361-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1743#L366-3 assume !(0 == ~E_M~0); 1769#L371-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1704#L376-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1705#L381-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1703#L178-12 assume !(1 == ~m_pc~0); 1568#L178-14 is_master_triggered_~__retres1~0#1 := 0; 1569#L189-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1722#L190-4 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1768#L437-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1710#L437-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1711#L197-12 assume !(1 == ~t1_pc~0); 1762#L197-14 is_transmit1_triggered_~__retres1~1#1 := 0; 1649#L208-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1650#L209-4 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1566#L445-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1567#L445-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1646#L216-12 assume !(1 == ~t2_pc~0); 1648#L216-14 is_transmit2_triggered_~__retres1~2#1 := 0; 1683#L227-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1609#L228-4 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1610#L453-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1638#L453-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1791#L394-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1799#L394-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1589#L399-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1590#L404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1677#L409-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1678#L414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1785#L419-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1760#L266-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1579#L283-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1641#L284-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 1642#L584 assume !(0 == start_simulation_~tmp~3#1); 1666#L584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1725#L266-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1733#L283-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1755#L284-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 1645#L539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1613#L546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1614#L547 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 1715#L597 assume !(0 != start_simulation_~tmp___0~1#1); 1716#L565-2 [2022-10-17 10:15:02,521 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:15:02,521 INFO L85 PathProgramCache]: Analyzing trace with hash -1712870137, now seen corresponding path program 1 times [2022-10-17 10:15:02,522 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:15:02,522 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1813005493] [2022-10-17 10:15:02,522 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:15:02,522 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:15:02,543 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:15:02,585 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:15:02,586 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:15:02,587 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1813005493] [2022-10-17 10:15:02,594 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1813005493] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:15:02,594 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:15:02,595 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-10-17 10:15:02,595 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1908809071] [2022-10-17 10:15:02,595 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:15:02,595 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:15:02,596 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:15:02,596 INFO L85 PathProgramCache]: Analyzing trace with hash -1458177828, now seen corresponding path program 1 times [2022-10-17 10:15:02,596 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:15:02,597 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1816652559] [2022-10-17 10:15:02,597 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:15:02,597 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:15:02,609 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:15:02,656 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:15:02,656 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:15:02,656 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1816652559] [2022-10-17 10:15:02,656 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1816652559] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:15:02,657 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:15:02,657 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-10-17 10:15:02,657 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1381825891] [2022-10-17 10:15:02,657 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:15:02,674 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:15:02,675 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:15:02,675 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:15:02,675 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:15:02,676 INFO L87 Difference]: Start difference. First operand 371 states and 551 transitions. cyclomatic complexity: 182 Second operand has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 2 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:15:02,717 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:15:02,718 INFO L93 Difference]: Finished difference Result 668 states and 973 transitions. [2022-10-17 10:15:02,718 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 668 states and 973 transitions. [2022-10-17 10:15:02,726 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 618 [2022-10-17 10:15:02,733 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 668 states to 668 states and 973 transitions. [2022-10-17 10:15:02,734 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 668 [2022-10-17 10:15:02,735 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 668 [2022-10-17 10:15:02,735 INFO L73 IsDeterministic]: Start isDeterministic. Operand 668 states and 973 transitions. [2022-10-17 10:15:02,736 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:15:02,737 INFO L218 hiAutomatonCegarLoop]: Abstraction has 668 states and 973 transitions. [2022-10-17 10:15:02,738 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 668 states and 973 transitions. [2022-10-17 10:15:02,758 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 668 to 628. [2022-10-17 10:15:02,760 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 628 states, 628 states have (on average 1.463375796178344) internal successors, (919), 627 states have internal predecessors, (919), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:15:02,763 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 628 states to 628 states and 919 transitions. [2022-10-17 10:15:02,763 INFO L240 hiAutomatonCegarLoop]: Abstraction has 628 states and 919 transitions. [2022-10-17 10:15:02,764 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:15:02,765 INFO L428 stractBuchiCegarLoop]: Abstraction has 628 states and 919 transitions. [2022-10-17 10:15:02,765 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-10-17 10:15:02,765 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 628 states and 919 transitions. [2022-10-17 10:15:02,770 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 578 [2022-10-17 10:15:02,770 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:15:02,770 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:15:02,772 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:15:02,774 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:15:02,775 INFO L748 eck$LassoCheckResult]: Stem: 2901#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 2845#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 2846#L528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2848#L236 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2856#L243 assume 1 == ~m_i~0;~m_st~0 := 0; 2795#L243-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2796#L248-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2644#L253-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2645#L356 assume !(0 == ~M_E~0); 2738#L356-2 assume !(0 == ~T1_E~0); 2739#L361-1 assume !(0 == ~T2_E~0); 2821#L366-1 assume !(0 == ~E_M~0); 2813#L371-1 assume !(0 == ~E_1~0); 2710#L376-1 assume !(0 == ~E_2~0); 2711#L381-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2648#L178 assume !(1 == ~m_pc~0); 2649#L178-2 is_master_triggered_~__retres1~0#1 := 0; 2743#L189 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2744#L190 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2802#L437 assume !(0 != activate_threads_~tmp~1#1); 2670#L437-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2671#L197 assume !(1 == ~t1_pc~0); 2719#L197-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2718#L208 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2894#L209 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2666#L445 assume !(0 != activate_threads_~tmp___0~0#1); 2667#L445-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2874#L216 assume 1 == ~t2_pc~0; 2641#L217 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2642#L227 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2740#L228 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2741#L453 assume !(0 != activate_threads_~tmp___1~0#1); 2811#L453-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2812#L394 assume 1 == ~M_E~0;~M_E~0 := 2; 2817#L394-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3169#L399-1 assume !(1 == ~T2_E~0); 3168#L404-1 assume !(1 == ~E_M~0); 2897#L409-1 assume !(1 == ~E_1~0); 3167#L414-1 assume !(1 == ~E_2~0); 3166#L419-1 assume { :end_inline_reset_delta_events } true; 2974#L565-2 [2022-10-17 10:15:02,777 INFO L750 eck$LassoCheckResult]: Loop: 2974#L565-2 assume !false; 2975#L566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2953#L331 assume !false; 2954#L294 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2946#L266 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2945#L283 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2708#L284 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2709#L298 assume !(0 != eval_~tmp~0#1); 2678#L346 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2679#L236-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2791#L356-3 assume !(0 == ~M_E~0); 3150#L356-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3211#L361-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3210#L366-3 assume !(0 == ~E_M~0); 3209#L371-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3208#L376-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3207#L381-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3206#L178-12 assume !(1 == ~m_pc~0); 3205#L178-14 is_master_triggered_~__retres1~0#1 := 0; 3204#L189-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3203#L190-4 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 3202#L437-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3201#L437-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3200#L197-12 assume 1 == ~t1_pc~0; 2843#L198-4 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2695#L208-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2696#L209-4 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2614#L445-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2615#L445-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2691#L216-12 assume 1 == ~t2_pc~0; 2692#L217-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3194#L227-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3191#L228-4 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3190#L453-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3189#L453-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3188#L394-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2909#L394-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3187#L399-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3186#L404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2904#L409-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3185#L414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3184#L419-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 3181#L266-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 3180#L283-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 3179#L284-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 3178#L584 assume !(0 == start_simulation_~tmp~3#1); 2713#L584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 3176#L266-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 3174#L283-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 3173#L284-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 3172#L539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3171#L546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3170#L547 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 3165#L597 assume !(0 != start_simulation_~tmp___0~1#1); 2974#L565-2 [2022-10-17 10:15:02,778 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:15:02,778 INFO L85 PathProgramCache]: Analyzing trace with hash 524493128, now seen corresponding path program 1 times [2022-10-17 10:15:02,779 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:15:02,779 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [584617969] [2022-10-17 10:15:02,779 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:15:02,779 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:15:02,805 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:15:02,851 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:15:02,852 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:15:02,852 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [584617969] [2022-10-17 10:15:02,852 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [584617969] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:15:02,853 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:15:02,853 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:15:02,853 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [962361356] [2022-10-17 10:15:02,853 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:15:02,854 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:15:02,854 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:15:02,855 INFO L85 PathProgramCache]: Analyzing trace with hash -1924070118, now seen corresponding path program 1 times [2022-10-17 10:15:02,855 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:15:02,855 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1324842920] [2022-10-17 10:15:02,855 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:15:02,856 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:15:02,873 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:15:02,950 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:15:02,951 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:15:02,951 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1324842920] [2022-10-17 10:15:02,951 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1324842920] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:15:02,951 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:15:02,952 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-10-17 10:15:02,954 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [962178607] [2022-10-17 10:15:02,955 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:15:02,955 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:15:02,955 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:15:02,956 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-10-17 10:15:02,956 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-10-17 10:15:02,957 INFO L87 Difference]: Start difference. First operand 628 states and 919 transitions. cyclomatic complexity: 295 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 3 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:15:03,079 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:15:03,079 INFO L93 Difference]: Finished difference Result 1421 states and 2040 transitions. [2022-10-17 10:15:03,079 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1421 states and 2040 transitions. [2022-10-17 10:15:03,093 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 1316 [2022-10-17 10:15:03,109 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1421 states to 1421 states and 2040 transitions. [2022-10-17 10:15:03,110 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1421 [2022-10-17 10:15:03,112 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1421 [2022-10-17 10:15:03,112 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1421 states and 2040 transitions. [2022-10-17 10:15:03,114 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:15:03,115 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1421 states and 2040 transitions. [2022-10-17 10:15:03,117 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1421 states and 2040 transitions. [2022-10-17 10:15:03,141 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1421 to 1138. [2022-10-17 10:15:03,144 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1138 states, 1138 states have (on average 1.4507908611599296) internal successors, (1651), 1137 states have internal predecessors, (1651), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:15:03,150 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1138 states to 1138 states and 1651 transitions. [2022-10-17 10:15:03,150 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1138 states and 1651 transitions. [2022-10-17 10:15:03,150 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-10-17 10:15:03,154 INFO L428 stractBuchiCegarLoop]: Abstraction has 1138 states and 1651 transitions. [2022-10-17 10:15:03,154 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-10-17 10:15:03,155 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1138 states and 1651 transitions. [2022-10-17 10:15:03,163 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1087 [2022-10-17 10:15:03,164 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:15:03,164 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:15:03,167 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:15:03,168 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:15:03,168 INFO L748 eck$LassoCheckResult]: Stem: 4958#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 4898#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 4899#L528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4901#L236 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4911#L243 assume 1 == ~m_i~0;~m_st~0 := 0; 4849#L243-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4850#L248-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4701#L253-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4702#L356 assume !(0 == ~M_E~0); 4796#L356-2 assume !(0 == ~T1_E~0); 4797#L361-1 assume !(0 == ~T2_E~0); 4876#L366-1 assume !(0 == ~E_M~0); 4867#L371-1 assume !(0 == ~E_1~0); 4768#L376-1 assume !(0 == ~E_2~0); 4769#L381-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4707#L178 assume !(1 == ~m_pc~0); 4708#L178-2 is_master_triggered_~__retres1~0#1 := 0; 4800#L189 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4801#L190 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4856#L437 assume !(0 != activate_threads_~tmp~1#1); 4729#L437-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4730#L197 assume !(1 == ~t1_pc~0); 4777#L197-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4776#L208 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4949#L209 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4723#L445 assume !(0 != activate_threads_~tmp___0~0#1); 4724#L445-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4926#L216 assume !(1 == ~t2_pc~0); 4705#L216-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4706#L227 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4798#L228 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4799#L453 assume !(0 != activate_threads_~tmp___1~0#1); 4865#L453-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4866#L394 assume 1 == ~M_E~0;~M_E~0 := 2; 4871#L394-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4833#L399-1 assume !(1 == ~T2_E~0); 4834#L404-1 assume !(1 == ~E_M~0); 4748#L409-1 assume !(1 == ~E_1~0); 4749#L414-1 assume !(1 == ~E_2~0); 4836#L419-1 assume { :end_inline_reset_delta_events } true; 4829#L565-2 [2022-10-17 10:15:03,170 INFO L750 eck$LassoCheckResult]: Loop: 4829#L565-2 assume !false; 4824#L566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4710#L331 assume !false; 4827#L294 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 4684#L266 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 4680#L283 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 4939#L284 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 4883#L298 assume !(0 != eval_~tmp~0#1); 4884#L346 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4841#L236-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4842#L356-3 assume !(0 == ~M_E~0); 4896#L356-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4860#L361-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4861#L366-3 assume !(0 == ~E_M~0); 4892#L371-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4815#L376-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4816#L381-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4814#L178-12 assume !(1 == ~m_pc~0); 4677#L178-14 is_master_triggered_~__retres1~0#1 := 0; 4678#L189-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4835#L190-4 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4890#L437-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4822#L437-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4823#L197-12 assume !(1 == ~t1_pc~0); 4885#L197-14 is_transmit1_triggered_~__retres1~1#1 := 0; 4897#L208-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4950#L209-4 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4951#L445-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5798#L445-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5797#L216-12 assume !(1 == ~t2_pc~0); 5564#L216-14 is_transmit2_triggered_~__retres1~2#1 := 0; 5796#L227-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5795#L228-4 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4742#L453-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4743#L453-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4923#L394-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4967#L394-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5793#L399-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5792#L404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4962#L409-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5791#L414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5790#L419-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 5787#L266-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 5786#L283-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 5785#L284-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 5784#L584 assume !(0 == start_simulation_~tmp~3#1); 4771#L584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 4846#L266-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 4847#L283-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 5773#L284-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 5772#L539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4721#L546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4722#L547 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 4828#L597 assume !(0 != start_simulation_~tmp___0~1#1); 4829#L565-2 [2022-10-17 10:15:03,171 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:15:03,171 INFO L85 PathProgramCache]: Analyzing trace with hash -754831607, now seen corresponding path program 1 times [2022-10-17 10:15:03,171 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:15:03,172 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1943069637] [2022-10-17 10:15:03,172 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:15:03,172 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:15:03,188 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:15:03,249 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:15:03,250 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:15:03,250 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1943069637] [2022-10-17 10:15:03,251 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1943069637] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:15:03,251 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:15:03,251 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-10-17 10:15:03,251 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1665418271] [2022-10-17 10:15:03,253 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:15:03,253 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:15:03,254 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:15:03,259 INFO L85 PathProgramCache]: Analyzing trace with hash -1458177828, now seen corresponding path program 2 times [2022-10-17 10:15:03,259 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:15:03,260 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1758488246] [2022-10-17 10:15:03,260 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:15:03,260 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:15:03,268 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:15:03,322 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:15:03,322 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:15:03,323 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1758488246] [2022-10-17 10:15:03,329 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1758488246] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:15:03,329 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:15:03,329 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-10-17 10:15:03,330 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1230536750] [2022-10-17 10:15:03,330 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:15:03,330 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:15:03,331 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:15:03,332 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:15:03,332 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:15:03,332 INFO L87 Difference]: Start difference. First operand 1138 states and 1651 transitions. cyclomatic complexity: 517 Second operand has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 2 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:15:03,366 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:15:03,366 INFO L93 Difference]: Finished difference Result 1671 states and 2418 transitions. [2022-10-17 10:15:03,366 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1671 states and 2418 transitions. [2022-10-17 10:15:03,382 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1621 [2022-10-17 10:15:03,399 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1671 states to 1671 states and 2418 transitions. [2022-10-17 10:15:03,399 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1671 [2022-10-17 10:15:03,403 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1671 [2022-10-17 10:15:03,403 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1671 states and 2418 transitions. [2022-10-17 10:15:03,406 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:15:03,406 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1671 states and 2418 transitions. [2022-10-17 10:15:03,408 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1671 states and 2418 transitions. [2022-10-17 10:15:03,431 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1671 to 1201. [2022-10-17 10:15:03,435 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1201 states, 1201 states have (on average 1.4487926727726894) internal successors, (1740), 1200 states have internal predecessors, (1740), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:15:03,441 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1201 states to 1201 states and 1740 transitions. [2022-10-17 10:15:03,441 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1201 states and 1740 transitions. [2022-10-17 10:15:03,442 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:15:03,443 INFO L428 stractBuchiCegarLoop]: Abstraction has 1201 states and 1740 transitions. [2022-10-17 10:15:03,443 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-10-17 10:15:03,444 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1201 states and 1740 transitions. [2022-10-17 10:15:03,452 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1156 [2022-10-17 10:15:03,452 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:15:03,452 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:15:03,454 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:15:03,454 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:15:03,454 INFO L748 eck$LassoCheckResult]: Stem: 7749#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 7706#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 7707#L528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7709#L236 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7716#L243 assume 1 == ~m_i~0;~m_st~0 := 0; 7659#L243-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7660#L248-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7519#L253-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7520#L356 assume !(0 == ~M_E~0); 7612#L356-2 assume !(0 == ~T1_E~0); 7613#L361-1 assume !(0 == ~T2_E~0); 7689#L366-1 assume !(0 == ~E_M~0); 7681#L371-1 assume !(0 == ~E_1~0); 7583#L376-1 assume !(0 == ~E_2~0); 7584#L381-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7525#L178 assume !(1 == ~m_pc~0); 7526#L178-2 is_master_triggered_~__retres1~0#1 := 0; 7616#L189 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7617#L190 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 7671#L437 assume !(0 != activate_threads_~tmp~1#1); 7547#L437-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7548#L197 assume !(1 == ~t1_pc~0); 7593#L197-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7592#L208 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7746#L209 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 7541#L445 assume !(0 != activate_threads_~tmp___0~0#1); 7542#L445-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7732#L216 assume !(1 == ~t2_pc~0); 7523#L216-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7524#L227 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7614#L228 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7615#L453 assume !(0 != activate_threads_~tmp___1~0#1); 7679#L453-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7680#L394 assume !(1 == ~M_E~0); 7687#L394-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7648#L399-1 assume !(1 == ~T2_E~0); 7649#L404-1 assume !(1 == ~E_M~0); 7565#L409-1 assume !(1 == ~E_1~0); 7566#L414-1 assume !(1 == ~E_2~0); 7651#L419-1 assume { :end_inline_reset_delta_events } true; 7644#L565-2 [2022-10-17 10:15:03,454 INFO L750 eck$LassoCheckResult]: Loop: 7644#L565-2 assume !false; 7640#L566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7528#L331 assume !false; 7642#L294 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 7502#L266 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 7498#L283 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 7581#L284 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 7582#L298 assume !(0 != eval_~tmp~0#1); 7555#L346 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7556#L236-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7656#L356-3 assume !(0 == ~M_E~0); 7705#L356-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7672#L361-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7673#L366-3 assume !(0 == ~E_M~0); 7702#L371-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7631#L376-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7632#L381-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7630#L178-12 assume !(1 == ~m_pc~0); 7495#L178-14 is_master_triggered_~__retres1~0#1 := 0; 7496#L189-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7650#L190-4 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 7700#L437-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7638#L437-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7639#L197-12 assume 1 == ~t1_pc~0; 7696#L198-4 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7570#L208-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7571#L209-4 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 7493#L445-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7494#L445-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7585#L216-12 assume !(1 == ~t2_pc~0); 8646#L216-14 is_transmit2_triggered_~__retres1~2#1 := 0; 8645#L227-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8644#L228-4 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 8640#L453-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8638#L453-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8636#L394-3 assume !(1 == ~M_E~0); 8290#L394-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8633#L399-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7753#L404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7600#L409-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7601#L414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7719#L419-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 7720#L266-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 7808#L283-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 7804#L284-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 7799#L584 assume !(0 == start_simulation_~tmp~3#1); 7587#L584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 7653#L266-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 7663#L283-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 7688#L284-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 7569#L539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7539#L546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7540#L547 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 7643#L597 assume !(0 != start_simulation_~tmp___0~1#1); 7644#L565-2 [2022-10-17 10:15:03,455 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:15:03,455 INFO L85 PathProgramCache]: Analyzing trace with hash 1020175755, now seen corresponding path program 1 times [2022-10-17 10:15:03,455 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:15:03,456 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [886385686] [2022-10-17 10:15:03,456 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:15:03,456 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:15:03,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:15:03,522 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:15:03,522 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:15:03,522 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [886385686] [2022-10-17 10:15:03,522 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [886385686] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:15:03,523 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:15:03,523 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-10-17 10:15:03,523 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [16642718] [2022-10-17 10:15:03,523 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:15:03,523 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:15:03,524 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:15:03,524 INFO L85 PathProgramCache]: Analyzing trace with hash -1375650595, now seen corresponding path program 1 times [2022-10-17 10:15:03,524 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:15:03,524 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1368695657] [2022-10-17 10:15:03,525 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:15:03,525 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:15:03,543 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:15:03,577 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:15:03,577 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:15:03,577 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1368695657] [2022-10-17 10:15:03,577 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1368695657] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:15:03,578 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:15:03,578 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-10-17 10:15:03,578 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [815901408] [2022-10-17 10:15:03,578 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:15:03,579 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:15:03,579 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:15:03,579 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:15:03,579 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:15:03,580 INFO L87 Difference]: Start difference. First operand 1201 states and 1740 transitions. cyclomatic complexity: 541 Second operand has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 2 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:15:03,600 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:15:03,601 INFO L93 Difference]: Finished difference Result 1201 states and 1714 transitions. [2022-10-17 10:15:03,601 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1201 states and 1714 transitions. [2022-10-17 10:15:03,612 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1156 [2022-10-17 10:15:03,622 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1201 states to 1201 states and 1714 transitions. [2022-10-17 10:15:03,622 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1201 [2022-10-17 10:15:03,624 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1201 [2022-10-17 10:15:03,624 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1201 states and 1714 transitions. [2022-10-17 10:15:03,626 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:15:03,627 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1201 states and 1714 transitions. [2022-10-17 10:15:03,628 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1201 states and 1714 transitions. [2022-10-17 10:15:03,648 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1201 to 1201. [2022-10-17 10:15:03,651 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1201 states, 1201 states have (on average 1.4271440466278102) internal successors, (1714), 1200 states have internal predecessors, (1714), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:15:03,672 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1201 states to 1201 states and 1714 transitions. [2022-10-17 10:15:03,672 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1201 states and 1714 transitions. [2022-10-17 10:15:03,673 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:15:03,675 INFO L428 stractBuchiCegarLoop]: Abstraction has 1201 states and 1714 transitions. [2022-10-17 10:15:03,676 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-10-17 10:15:03,676 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1201 states and 1714 transitions. [2022-10-17 10:15:03,683 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1156 [2022-10-17 10:15:03,683 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:15:03,683 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:15:03,688 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:15:03,688 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:15:03,694 INFO L748 eck$LassoCheckResult]: Stem: 10153#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 10116#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 10117#L528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10119#L236 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10125#L243 assume 1 == ~m_i~0;~m_st~0 := 0; 10069#L243-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10070#L248-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9930#L253-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9931#L356 assume !(0 == ~M_E~0); 10022#L356-2 assume !(0 == ~T1_E~0); 10023#L361-1 assume !(0 == ~T2_E~0); 10095#L366-1 assume !(0 == ~E_M~0); 10089#L371-1 assume !(0 == ~E_1~0); 9994#L376-1 assume !(0 == ~E_2~0); 9995#L381-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9936#L178 assume !(1 == ~m_pc~0); 9937#L178-2 is_master_triggered_~__retres1~0#1 := 0; 10026#L189 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10027#L190 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 10079#L437 assume !(0 != activate_threads_~tmp~1#1); 9958#L437-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9959#L197 assume !(1 == ~t1_pc~0); 10003#L197-2 is_transmit1_triggered_~__retres1~1#1 := 0; 10002#L208 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10149#L209 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 9952#L445 assume !(0 != activate_threads_~tmp___0~0#1); 9953#L445-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10136#L216 assume !(1 == ~t2_pc~0); 9934#L216-2 is_transmit2_triggered_~__retres1~2#1 := 0; 9935#L227 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10024#L228 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 10025#L453 assume !(0 != activate_threads_~tmp___1~0#1); 10087#L453-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10088#L394 assume !(1 == ~M_E~0); 10093#L394-2 assume !(1 == ~T1_E~0); 10058#L399-1 assume !(1 == ~T2_E~0); 10059#L404-1 assume !(1 == ~E_M~0); 9976#L409-1 assume !(1 == ~E_1~0); 9977#L414-1 assume !(1 == ~E_2~0); 10061#L419-1 assume { :end_inline_reset_delta_events } true; 10053#L565-2 [2022-10-17 10:15:03,695 INFO L750 eck$LassoCheckResult]: Loop: 10053#L565-2 assume !false; 10049#L566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9939#L331 assume !false; 10051#L294 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 9913#L266 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 9909#L283 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 9992#L284 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 9993#L298 assume !(0 != eval_~tmp~0#1); 9966#L346 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9967#L236-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10066#L356-3 assume !(0 == ~M_E~0); 10115#L356-5 assume !(0 == ~T1_E~0); 10080#L361-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10081#L366-3 assume !(0 == ~E_M~0); 10112#L371-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10041#L376-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10042#L381-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10040#L178-12 assume !(1 == ~m_pc~0); 9906#L178-14 is_master_triggered_~__retres1~0#1 := 0; 9907#L189-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10060#L190-4 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 10110#L437-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10047#L437-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10048#L197-12 assume !(1 == ~t1_pc~0); 10104#L197-14 is_transmit1_triggered_~__retres1~1#1 := 0; 9981#L208-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9982#L209-4 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 9904#L445-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9905#L445-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9978#L216-12 assume !(1 == ~t2_pc~0); 9979#L216-14 is_transmit2_triggered_~__retres1~2#1 := 0; 10728#L227-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10726#L228-4 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 10724#L453-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 10722#L453-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10720#L394-3 assume !(1 == ~M_E~0); 10150#L394-5 assume !(1 == ~T1_E~0); 9926#L399-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9927#L404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10010#L409-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10011#L414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10127#L419-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 10103#L266-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 9917#L283-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 9974#L284-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 9975#L584 assume !(0 == start_simulation_~tmp~3#1); 9997#L584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 10063#L266-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 10072#L283-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 10094#L284-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 9980#L539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9950#L546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9951#L547 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 10052#L597 assume !(0 != start_simulation_~tmp___0~1#1); 10053#L565-2 [2022-10-17 10:15:03,695 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:15:03,695 INFO L85 PathProgramCache]: Analyzing trace with hash 1077434057, now seen corresponding path program 1 times [2022-10-17 10:15:03,695 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:15:03,696 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1749644753] [2022-10-17 10:15:03,696 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:15:03,697 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:15:03,706 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:15:03,707 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:15:03,715 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:15:03,757 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:15:03,758 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:15:03,758 INFO L85 PathProgramCache]: Analyzing trace with hash -1743692258, now seen corresponding path program 1 times [2022-10-17 10:15:03,758 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:15:03,759 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1396135358] [2022-10-17 10:15:03,759 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:15:03,759 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:15:03,770 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:15:03,811 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:15:03,811 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:15:03,811 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1396135358] [2022-10-17 10:15:03,812 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1396135358] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:15:03,812 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:15:03,812 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-10-17 10:15:03,812 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2136935662] [2022-10-17 10:15:03,812 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:15:03,813 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:15:03,813 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:15:03,813 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-10-17 10:15:03,814 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-10-17 10:15:03,814 INFO L87 Difference]: Start difference. First operand 1201 states and 1714 transitions. cyclomatic complexity: 515 Second operand has 5 states, 5 states have (on average 10.8) internal successors, (54), 5 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:15:03,915 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:15:03,915 INFO L93 Difference]: Finished difference Result 2073 states and 2910 transitions. [2022-10-17 10:15:03,915 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2073 states and 2910 transitions. [2022-10-17 10:15:03,932 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2024 [2022-10-17 10:15:03,949 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2073 states to 2073 states and 2910 transitions. [2022-10-17 10:15:03,949 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2073 [2022-10-17 10:15:03,951 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2073 [2022-10-17 10:15:03,952 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2073 states and 2910 transitions. [2022-10-17 10:15:03,955 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:15:03,955 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2073 states and 2910 transitions. [2022-10-17 10:15:03,958 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2073 states and 2910 transitions. [2022-10-17 10:15:03,982 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2073 to 1225. [2022-10-17 10:15:03,985 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1225 states, 1225 states have (on average 1.4187755102040815) internal successors, (1738), 1224 states have internal predecessors, (1738), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:15:03,990 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1225 states to 1225 states and 1738 transitions. [2022-10-17 10:15:03,990 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1225 states and 1738 transitions. [2022-10-17 10:15:03,991 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-10-17 10:15:03,993 INFO L428 stractBuchiCegarLoop]: Abstraction has 1225 states and 1738 transitions. [2022-10-17 10:15:03,994 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-10-17 10:15:03,994 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1225 states and 1738 transitions. [2022-10-17 10:15:04,001 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1180 [2022-10-17 10:15:04,001 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:15:04,001 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:15:04,008 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:15:04,008 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:15:04,008 INFO L748 eck$LassoCheckResult]: Stem: 13452#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 13409#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 13410#L528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13412#L236 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13419#L243 assume 1 == ~m_i~0;~m_st~0 := 0; 13367#L243-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13368#L248-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13220#L253-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13221#L356 assume !(0 == ~M_E~0); 13313#L356-2 assume !(0 == ~T1_E~0); 13314#L361-1 assume !(0 == ~T2_E~0); 13391#L366-1 assume !(0 == ~E_M~0); 13384#L371-1 assume !(0 == ~E_1~0); 13284#L376-1 assume !(0 == ~E_2~0); 13285#L381-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13226#L178 assume !(1 == ~m_pc~0); 13227#L178-2 is_master_triggered_~__retres1~0#1 := 0; 13319#L189 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13320#L190 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 13374#L437 assume !(0 != activate_threads_~tmp~1#1); 13248#L437-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13249#L197 assume !(1 == ~t1_pc~0); 13294#L197-2 is_transmit1_triggered_~__retres1~1#1 := 0; 13293#L208 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13449#L209 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 13244#L445 assume !(0 != activate_threads_~tmp___0~0#1); 13245#L445-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13433#L216 assume !(1 == ~t2_pc~0); 13224#L216-2 is_transmit2_triggered_~__retres1~2#1 := 0; 13225#L227 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13315#L228 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 13316#L453 assume !(0 != activate_threads_~tmp___1~0#1); 13382#L453-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13383#L394 assume !(1 == ~M_E~0); 13388#L394-2 assume !(1 == ~T1_E~0); 13353#L399-1 assume !(1 == ~T2_E~0); 13354#L404-1 assume !(1 == ~E_M~0); 13266#L409-1 assume !(1 == ~E_1~0); 13267#L414-1 assume !(1 == ~E_2~0); 13356#L419-1 assume { :end_inline_reset_delta_events } true; 13347#L565-2 [2022-10-17 10:15:04,008 INFO L750 eck$LassoCheckResult]: Loop: 13347#L565-2 assume !false; 13420#L566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13229#L331 assume !false; 14096#L294 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 14091#L266 assume !(0 == ~m_st~0); 14092#L270 assume !(0 == ~t1_st~0); 14093#L274 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 14094#L283 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 13282#L284 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 13283#L298 assume !(0 != eval_~tmp~0#1); 14085#L346 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14084#L236-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13432#L356-3 assume !(0 == ~M_E~0); 13408#L356-5 assume !(0 == ~T1_E~0); 13375#L361-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13376#L366-3 assume !(0 == ~E_M~0); 13405#L371-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13333#L376-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13334#L381-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13332#L178-12 assume !(1 == ~m_pc~0); 13196#L178-14 is_master_triggered_~__retres1~0#1 := 0; 13197#L189-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13355#L190-4 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 13403#L437-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 13339#L437-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13340#L197-12 assume !(1 == ~t1_pc~0); 13398#L197-14 is_transmit1_triggered_~__retres1~1#1 := 0; 13271#L208-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13272#L209-4 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 14047#L445-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13286#L445-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13269#L216-12 assume !(1 == ~t2_pc~0); 13270#L216-14 is_transmit2_triggered_~__retres1~2#1 := 0; 14251#L227-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14250#L228-4 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 14249#L453-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14248#L453-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14247#L394-3 assume !(1 == ~M_E~0); 14041#L394-5 assume !(1 == ~T1_E~0); 14246#L399-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14245#L404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 14244#L409-3 assume 1 == ~E_1~0;~E_1~0 := 2; 14243#L414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14242#L419-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 14239#L266-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 14236#L283-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 13264#L284-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 13265#L584 assume !(0 == start_simulation_~tmp~3#1); 13288#L584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 13358#L266-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 13365#L283-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 13389#L284-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 13268#L539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13238#L546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13239#L547 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 13346#L597 assume !(0 != start_simulation_~tmp___0~1#1); 13347#L565-2 [2022-10-17 10:15:04,009 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:15:04,009 INFO L85 PathProgramCache]: Analyzing trace with hash 1077434057, now seen corresponding path program 2 times [2022-10-17 10:15:04,009 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:15:04,009 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [694553086] [2022-10-17 10:15:04,009 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:15:04,010 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:15:04,020 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:15:04,020 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:15:04,026 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:15:04,038 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:15:04,039 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:15:04,039 INFO L85 PathProgramCache]: Analyzing trace with hash 1678104567, now seen corresponding path program 1 times [2022-10-17 10:15:04,039 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:15:04,039 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1278773647] [2022-10-17 10:15:04,039 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:15:04,039 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:15:04,053 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:15:04,127 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:15:04,128 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:15:04,128 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1278773647] [2022-10-17 10:15:04,128 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1278773647] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:15:04,128 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:15:04,128 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-10-17 10:15:04,128 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [899910666] [2022-10-17 10:15:04,129 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:15:04,129 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:15:04,129 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:15:04,130 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-10-17 10:15:04,130 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-10-17 10:15:04,130 INFO L87 Difference]: Start difference. First operand 1225 states and 1738 transitions. cyclomatic complexity: 515 Second operand has 5 states, 5 states have (on average 11.2) internal successors, (56), 5 states have internal predecessors, (56), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:15:04,280 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:15:04,280 INFO L93 Difference]: Finished difference Result 2407 states and 3391 transitions. [2022-10-17 10:15:04,280 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2407 states and 3391 transitions. [2022-10-17 10:15:04,299 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2362 [2022-10-17 10:15:04,317 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2407 states to 2407 states and 3391 transitions. [2022-10-17 10:15:04,318 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2407 [2022-10-17 10:15:04,321 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2407 [2022-10-17 10:15:04,321 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2407 states and 3391 transitions. [2022-10-17 10:15:04,325 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:15:04,325 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2407 states and 3391 transitions. [2022-10-17 10:15:04,328 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2407 states and 3391 transitions. [2022-10-17 10:15:04,354 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2407 to 1273. [2022-10-17 10:15:04,357 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1273 states, 1273 states have (on average 1.3927729772191673) internal successors, (1773), 1272 states have internal predecessors, (1773), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:15:04,362 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1273 states to 1273 states and 1773 transitions. [2022-10-17 10:15:04,363 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1273 states and 1773 transitions. [2022-10-17 10:15:04,363 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-10-17 10:15:04,364 INFO L428 stractBuchiCegarLoop]: Abstraction has 1273 states and 1773 transitions. [2022-10-17 10:15:04,364 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-10-17 10:15:04,364 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1273 states and 1773 transitions. [2022-10-17 10:15:04,371 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1228 [2022-10-17 10:15:04,372 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:15:04,372 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:15:04,373 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:15:04,373 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:15:04,373 INFO L748 eck$LassoCheckResult]: Stem: 17123#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 17068#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 17069#L528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17071#L236 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17078#L243 assume 1 == ~m_i~0;~m_st~0 := 0; 17017#L243-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17018#L248-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16865#L253-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16866#L356 assume !(0 == ~M_E~0); 16959#L356-2 assume !(0 == ~T1_E~0); 16960#L361-1 assume !(0 == ~T2_E~0); 17046#L366-1 assume !(0 == ~E_M~0); 17039#L371-1 assume !(0 == ~E_1~0); 16929#L376-1 assume !(0 == ~E_2~0); 16930#L381-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16871#L178 assume !(1 == ~m_pc~0); 16872#L178-2 is_master_triggered_~__retres1~0#1 := 0; 16965#L189 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16966#L190 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 17027#L437 assume !(0 != activate_threads_~tmp~1#1); 16893#L437-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16894#L197 assume !(1 == ~t1_pc~0); 16940#L197-2 is_transmit1_triggered_~__retres1~1#1 := 0; 16939#L208 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17115#L209 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 16889#L445 assume !(0 != activate_threads_~tmp___0~0#1); 16890#L445-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17096#L216 assume !(1 == ~t2_pc~0); 16869#L216-2 is_transmit2_triggered_~__retres1~2#1 := 0; 16870#L227 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16961#L228 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 16962#L453 assume !(0 != activate_threads_~tmp___1~0#1); 17037#L453-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17038#L394 assume !(1 == ~M_E~0); 17043#L394-2 assume !(1 == ~T1_E~0); 17003#L399-1 assume !(1 == ~T2_E~0); 17004#L404-1 assume !(1 == ~E_M~0); 16911#L409-1 assume !(1 == ~E_1~0); 16912#L414-1 assume !(1 == ~E_2~0); 17006#L419-1 assume { :end_inline_reset_delta_events } true; 17007#L565-2 [2022-10-17 10:15:04,374 INFO L750 eck$LassoCheckResult]: Loop: 17007#L565-2 assume !false; 17634#L566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17553#L331 assume !false; 17633#L294 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 17631#L266 assume !(0 == ~m_st~0); 17632#L270 assume !(0 == ~t1_st~0); 17629#L274 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 17630#L283 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 17625#L284 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 17626#L298 assume !(0 != eval_~tmp~0#1); 17767#L346 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17766#L236-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17765#L356-3 assume !(0 == ~M_E~0); 17764#L356-5 assume !(0 == ~T1_E~0); 17763#L361-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17762#L366-3 assume !(0 == ~E_M~0); 17761#L371-3 assume 0 == ~E_1~0;~E_1~0 := 1; 17760#L376-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17028#L381-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16979#L178-12 assume !(1 == ~m_pc~0); 16980#L178-14 is_master_triggered_~__retres1~0#1 := 0; 17624#L189-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17623#L190-4 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 17622#L437-12 assume !(0 != activate_threads_~tmp~1#1); 17621#L437-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17620#L197-12 assume !(1 == ~t1_pc~0); 17618#L197-14 is_transmit1_triggered_~__retres1~1#1 := 0; 17617#L208-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17616#L209-4 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 17615#L445-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17614#L445-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17612#L216-12 assume !(1 == ~t2_pc~0); 17429#L216-14 is_transmit2_triggered_~__retres1~2#1 := 0; 17188#L227-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17189#L228-4 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 17180#L453-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 17181#L453-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17173#L394-3 assume !(1 == ~M_E~0); 17172#L394-5 assume !(1 == ~T1_E~0); 17506#L399-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17504#L404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 17502#L409-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17500#L414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 17161#L419-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 17157#L266-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 17153#L283-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 17152#L284-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 17146#L584 assume !(0 == start_simulation_~tmp~3#1); 17148#L584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 17642#L266-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 17640#L283-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 17639#L284-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 17638#L539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 17637#L546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 17636#L547 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 17635#L597 assume !(0 != start_simulation_~tmp___0~1#1); 17007#L565-2 [2022-10-17 10:15:04,374 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:15:04,374 INFO L85 PathProgramCache]: Analyzing trace with hash 1077434057, now seen corresponding path program 3 times [2022-10-17 10:15:04,375 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:15:04,375 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [362826123] [2022-10-17 10:15:04,375 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:15:04,375 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:15:04,383 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:15:04,383 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:15:04,388 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:15:04,396 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:15:04,397 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:15:04,397 INFO L85 PathProgramCache]: Analyzing trace with hash 1605718009, now seen corresponding path program 1 times [2022-10-17 10:15:04,397 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:15:04,397 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1709545646] [2022-10-17 10:15:04,397 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:15:04,398 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:15:04,406 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:15:04,426 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:15:04,426 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:15:04,426 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1709545646] [2022-10-17 10:15:04,426 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1709545646] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:15:04,427 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:15:04,427 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:15:04,427 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1813908383] [2022-10-17 10:15:04,427 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:15:04,428 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:15:04,428 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:15:04,428 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:15:04,428 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:15:04,429 INFO L87 Difference]: Start difference. First operand 1273 states and 1773 transitions. cyclomatic complexity: 502 Second operand has 3 states, 3 states have (on average 18.666666666666668) internal successors, (56), 3 states have internal predecessors, (56), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:15:04,472 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:15:04,473 INFO L93 Difference]: Finished difference Result 1886 states and 2583 transitions. [2022-10-17 10:15:04,473 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1886 states and 2583 transitions. [2022-10-17 10:15:04,485 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1841 [2022-10-17 10:15:04,500 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1886 states to 1886 states and 2583 transitions. [2022-10-17 10:15:04,500 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1886 [2022-10-17 10:15:04,502 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1886 [2022-10-17 10:15:04,502 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1886 states and 2583 transitions. [2022-10-17 10:15:04,505 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:15:04,506 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1886 states and 2583 transitions. [2022-10-17 10:15:04,508 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1886 states and 2583 transitions. [2022-10-17 10:15:04,536 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1886 to 1824. [2022-10-17 10:15:04,540 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1824 states, 1824 states have (on average 1.3711622807017543) internal successors, (2501), 1823 states have internal predecessors, (2501), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:15:04,547 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1824 states to 1824 states and 2501 transitions. [2022-10-17 10:15:04,547 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1824 states and 2501 transitions. [2022-10-17 10:15:04,547 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:15:04,548 INFO L428 stractBuchiCegarLoop]: Abstraction has 1824 states and 2501 transitions. [2022-10-17 10:15:04,548 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-10-17 10:15:04,548 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1824 states and 2501 transitions. [2022-10-17 10:15:04,556 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1779 [2022-10-17 10:15:04,556 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:15:04,557 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:15:04,557 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:15:04,557 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:15:04,558 INFO L748 eck$LassoCheckResult]: Stem: 20281#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 20228#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 20229#L528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20231#L236 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 20238#L243 assume 1 == ~m_i~0;~m_st~0 := 0; 20182#L243-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20183#L248-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20030#L253-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20031#L356 assume !(0 == ~M_E~0); 20124#L356-2 assume !(0 == ~T1_E~0); 20125#L361-1 assume !(0 == ~T2_E~0); 20208#L366-1 assume !(0 == ~E_M~0); 20201#L371-1 assume !(0 == ~E_1~0); 20094#L376-1 assume !(0 == ~E_2~0); 20095#L381-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20036#L178 assume !(1 == ~m_pc~0); 20037#L178-2 is_master_triggered_~__retres1~0#1 := 0; 20128#L189 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20129#L190 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 20192#L437 assume !(0 != activate_threads_~tmp~1#1); 20058#L437-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20059#L197 assume !(1 == ~t1_pc~0); 20105#L197-2 is_transmit1_triggered_~__retres1~1#1 := 0; 20104#L208 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20272#L209 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 20052#L445 assume !(0 != activate_threads_~tmp___0~0#1); 20053#L445-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20258#L216 assume !(1 == ~t2_pc~0); 20034#L216-2 is_transmit2_triggered_~__retres1~2#1 := 0; 20035#L227 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20126#L228 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 20127#L453 assume !(0 != activate_threads_~tmp___1~0#1); 20199#L453-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20200#L394 assume !(1 == ~M_E~0); 20205#L394-2 assume !(1 == ~T1_E~0); 20167#L399-1 assume !(1 == ~T2_E~0); 20168#L404-1 assume !(1 == ~E_M~0); 20075#L409-1 assume !(1 == ~E_1~0); 20076#L414-1 assume !(1 == ~E_2~0); 20170#L419-1 assume { :end_inline_reset_delta_events } true; 20171#L565-2 assume !false; 20877#L566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 20856#L331 [2022-10-17 10:15:04,558 INFO L750 eck$LassoCheckResult]: Loop: 20856#L331 assume !false; 20599#L294 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 20600#L266 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 20873#L283 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 20871#L284 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 20867#L298 assume 0 != eval_~tmp~0#1; 20864#L298-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 20862#L306 assume !(0 != eval_~tmp_ndt_1~0#1); 20860#L303 assume !(0 == ~t1_st~0); 20857#L317 assume !(0 == ~t2_st~0); 20856#L331 [2022-10-17 10:15:04,558 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:15:04,559 INFO L85 PathProgramCache]: Analyzing trace with hash 327016235, now seen corresponding path program 1 times [2022-10-17 10:15:04,559 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:15:04,559 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1994311064] [2022-10-17 10:15:04,559 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:15:04,559 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:15:04,576 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:15:04,576 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:15:04,582 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:15:04,589 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:15:04,590 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:15:04,590 INFO L85 PathProgramCache]: Analyzing trace with hash 698787991, now seen corresponding path program 1 times [2022-10-17 10:15:04,590 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:15:04,591 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1548362579] [2022-10-17 10:15:04,591 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:15:04,591 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:15:04,595 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:15:04,595 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:15:04,597 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:15:04,599 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:15:04,600 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:15:04,600 INFO L85 PathProgramCache]: Analyzing trace with hash 1780423489, now seen corresponding path program 1 times [2022-10-17 10:15:04,600 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:15:04,601 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2040263769] [2022-10-17 10:15:04,601 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:15:04,601 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:15:04,610 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:15:04,634 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:15:04,634 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:15:04,635 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2040263769] [2022-10-17 10:15:04,635 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2040263769] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:15:04,635 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:15:04,635 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:15:04,635 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1081907168] [2022-10-17 10:15:04,636 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:15:04,710 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:15:04,710 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:15:04,711 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:15:04,711 INFO L87 Difference]: Start difference. First operand 1824 states and 2501 transitions. cyclomatic complexity: 680 Second operand has 3 states, 3 states have (on average 17.333333333333332) internal successors, (52), 3 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:15:04,800 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:15:04,800 INFO L93 Difference]: Finished difference Result 3112 states and 4211 transitions. [2022-10-17 10:15:04,801 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3112 states and 4211 transitions. [2022-10-17 10:15:04,821 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3028 [2022-10-17 10:15:04,845 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3112 states to 3112 states and 4211 transitions. [2022-10-17 10:15:04,845 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3112 [2022-10-17 10:15:04,850 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3112 [2022-10-17 10:15:04,851 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3112 states and 4211 transitions. [2022-10-17 10:15:04,856 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:15:04,856 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3112 states and 4211 transitions. [2022-10-17 10:15:04,860 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3112 states and 4211 transitions. [2022-10-17 10:15:04,902 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3112 to 2965. [2022-10-17 10:15:04,908 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2965 states, 2965 states have (on average 1.3612141652613827) internal successors, (4036), 2964 states have internal predecessors, (4036), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:15:04,919 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2965 states to 2965 states and 4036 transitions. [2022-10-17 10:15:04,919 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2965 states and 4036 transitions. [2022-10-17 10:15:04,919 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:15:04,920 INFO L428 stractBuchiCegarLoop]: Abstraction has 2965 states and 4036 transitions. [2022-10-17 10:15:04,920 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-10-17 10:15:04,920 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2965 states and 4036 transitions. [2022-10-17 10:15:04,933 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2881 [2022-10-17 10:15:04,933 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:15:04,933 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:15:04,934 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:15:04,934 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:15:04,935 INFO L748 eck$LassoCheckResult]: Stem: 25238#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 25181#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 25182#L528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 25184#L236 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 25194#L243 assume 1 == ~m_i~0;~m_st~0 := 0; 25134#L243-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 25135#L248-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 26479#L253-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26478#L356 assume !(0 == ~M_E~0); 26477#L356-2 assume !(0 == ~T1_E~0); 26476#L361-1 assume !(0 == ~T2_E~0); 25161#L366-1 assume !(0 == ~E_M~0); 25154#L371-1 assume !(0 == ~E_1~0); 25041#L376-1 assume !(0 == ~E_2~0); 25042#L381-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25097#L178 assume !(1 == ~m_pc~0); 26444#L178-2 is_master_triggered_~__retres1~0#1 := 0; 26442#L189 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25195#L190 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 25196#L437 assume !(0 != activate_threads_~tmp~1#1); 26083#L437-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26081#L197 assume !(1 == ~t1_pc~0); 25052#L197-2 is_transmit1_triggered_~__retres1~1#1 := 0; 25051#L208 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25231#L209 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 24996#L445 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 24997#L445-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26058#L216 assume !(1 == ~t2_pc~0); 26057#L216-2 is_transmit2_triggered_~__retres1~2#1 := 0; 26056#L227 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26055#L228 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 26054#L453 assume !(0 != activate_threads_~tmp___1~0#1); 26053#L453-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26052#L394 assume !(1 == ~M_E~0); 26051#L394-2 assume !(1 == ~T1_E~0); 26050#L399-1 assume !(1 == ~T2_E~0); 26049#L404-1 assume !(1 == ~E_M~0); 25020#L409-1 assume !(1 == ~E_1~0); 25021#L414-1 assume !(1 == ~E_2~0); 25122#L419-1 assume { :end_inline_reset_delta_events } true; 25123#L565-2 assume !false; 26079#L566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 26073#L331 [2022-10-17 10:15:04,935 INFO L750 eck$LassoCheckResult]: Loop: 26073#L331 assume !false; 26071#L294 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 26068#L266 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 26063#L283 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 26044#L284 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 26040#L298 assume 0 != eval_~tmp~0#1; 26036#L298-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 26032#L306 assume !(0 != eval_~tmp_ndt_1~0#1); 26028#L303 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 25967#L320 assume !(0 != eval_~tmp_ndt_2~0#1); 26023#L317 assume !(0 == ~t2_st~0); 26073#L331 [2022-10-17 10:15:04,935 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:15:04,935 INFO L85 PathProgramCache]: Analyzing trace with hash -1720071637, now seen corresponding path program 1 times [2022-10-17 10:15:04,936 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:15:04,936 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [751814153] [2022-10-17 10:15:04,936 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:15:04,936 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:15:04,945 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:15:04,961 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:15:04,961 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:15:04,961 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [751814153] [2022-10-17 10:15:04,962 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [751814153] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:15:04,962 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:15:04,962 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:15:04,964 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1328656974] [2022-10-17 10:15:04,964 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:15:04,965 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:15:04,965 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:15:04,965 INFO L85 PathProgramCache]: Analyzing trace with hash 187484484, now seen corresponding path program 1 times [2022-10-17 10:15:04,965 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:15:04,965 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1806741210] [2022-10-17 10:15:04,966 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:15:04,966 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:15:04,971 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:15:04,971 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:15:04,974 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:15:04,977 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:15:05,063 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:15:05,063 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:15:05,063 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:15:05,064 INFO L87 Difference]: Start difference. First operand 2965 states and 4036 transitions. cyclomatic complexity: 1074 Second operand has 3 states, 3 states have (on average 14.0) internal successors, (42), 3 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:15:05,090 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:15:05,090 INFO L93 Difference]: Finished difference Result 2928 states and 3987 transitions. [2022-10-17 10:15:05,091 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2928 states and 3987 transitions. [2022-10-17 10:15:05,105 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2881 [2022-10-17 10:15:05,134 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2928 states to 2928 states and 3987 transitions. [2022-10-17 10:15:05,134 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2928 [2022-10-17 10:15:05,159 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2928 [2022-10-17 10:15:05,160 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2928 states and 3987 transitions. [2022-10-17 10:15:05,165 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:15:05,165 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2928 states and 3987 transitions. [2022-10-17 10:15:05,168 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2928 states and 3987 transitions. [2022-10-17 10:15:05,217 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2928 to 2928. [2022-10-17 10:15:05,223 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2928 states, 2928 states have (on average 1.3616803278688525) internal successors, (3987), 2927 states have internal predecessors, (3987), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:15:05,232 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2928 states to 2928 states and 3987 transitions. [2022-10-17 10:15:05,232 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2928 states and 3987 transitions. [2022-10-17 10:15:05,232 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:15:05,233 INFO L428 stractBuchiCegarLoop]: Abstraction has 2928 states and 3987 transitions. [2022-10-17 10:15:05,233 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-10-17 10:15:05,233 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2928 states and 3987 transitions. [2022-10-17 10:15:05,246 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2881 [2022-10-17 10:15:05,246 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:15:05,246 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:15:05,247 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:15:05,247 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:15:05,247 INFO L748 eck$LassoCheckResult]: Stem: 31135#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 31081#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 31082#L528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 31084#L236 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 31095#L243 assume 1 == ~m_i~0;~m_st~0 := 0; 31031#L243-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 31032#L248-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 30872#L253-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 30873#L356 assume !(0 == ~M_E~0); 30967#L356-2 assume !(0 == ~T1_E~0); 30968#L361-1 assume !(0 == ~T2_E~0); 31059#L366-1 assume !(0 == ~E_M~0); 31051#L371-1 assume !(0 == ~E_1~0); 30936#L376-1 assume !(0 == ~E_2~0); 30937#L381-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30878#L178 assume !(1 == ~m_pc~0); 30879#L178-2 is_master_triggered_~__retres1~0#1 := 0; 30973#L189 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30974#L190 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 31039#L437 assume !(0 != activate_threads_~tmp~1#1); 30900#L437-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30901#L197 assume !(1 == ~t1_pc~0); 30945#L197-2 is_transmit1_triggered_~__retres1~1#1 := 0; 30944#L208 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31130#L209 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 30896#L445 assume !(0 != activate_threads_~tmp___0~0#1); 30897#L445-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31114#L216 assume !(1 == ~t2_pc~0); 30876#L216-2 is_transmit2_triggered_~__retres1~2#1 := 0; 30877#L227 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30969#L228 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 30970#L453 assume !(0 != activate_threads_~tmp___1~0#1); 31049#L453-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31050#L394 assume !(1 == ~M_E~0); 31055#L394-2 assume !(1 == ~T1_E~0); 31013#L399-1 assume !(1 == ~T2_E~0); 31014#L404-1 assume !(1 == ~E_M~0); 30917#L409-1 assume !(1 == ~E_1~0); 30918#L414-1 assume !(1 == ~E_2~0); 31016#L419-1 assume { :end_inline_reset_delta_events } true; 31017#L565-2 assume !false; 32905#L566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 32426#L331 [2022-10-17 10:15:05,247 INFO L750 eck$LassoCheckResult]: Loop: 32426#L331 assume !false; 32898#L294 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 32893#L266 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 32890#L283 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 32887#L284 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 32884#L298 assume 0 != eval_~tmp~0#1; 32881#L298-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 31018#L306 assume !(0 != eval_~tmp_ndt_1~0#1); 31020#L303 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 32438#L320 assume !(0 != eval_~tmp_ndt_2~0#1); 32447#L317 assume !(0 == ~t2_st~0); 32426#L331 [2022-10-17 10:15:05,248 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:15:05,248 INFO L85 PathProgramCache]: Analyzing trace with hash 327016235, now seen corresponding path program 2 times [2022-10-17 10:15:05,248 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:15:05,250 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1130353374] [2022-10-17 10:15:05,250 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:15:05,251 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:15:05,258 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:15:05,259 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:15:05,266 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:15:05,278 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:15:05,278 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:15:05,278 INFO L85 PathProgramCache]: Analyzing trace with hash 187484484, now seen corresponding path program 2 times [2022-10-17 10:15:05,279 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:15:05,281 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1604461411] [2022-10-17 10:15:05,281 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:15:05,281 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:15:05,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:15:05,285 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:15:05,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:15:05,289 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:15:05,291 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:15:05,291 INFO L85 PathProgramCache]: Analyzing trace with hash -641553446, now seen corresponding path program 1 times [2022-10-17 10:15:05,292 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:15:05,292 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [980915841] [2022-10-17 10:15:05,292 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:15:05,292 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:15:05,300 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:15:05,327 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:15:05,328 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:15:05,328 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [980915841] [2022-10-17 10:15:05,328 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [980915841] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:15:05,328 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:15:05,328 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-10-17 10:15:05,329 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1757554031] [2022-10-17 10:15:05,329 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:15:05,423 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:15:05,423 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:15:05,423 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:15:05,423 INFO L87 Difference]: Start difference. First operand 2928 states and 3987 transitions. cyclomatic complexity: 1062 Second operand has 3 states, 2 states have (on average 26.5) internal successors, (53), 3 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:15:05,486 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:15:05,486 INFO L93 Difference]: Finished difference Result 4987 states and 6732 transitions. [2022-10-17 10:15:05,486 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4987 states and 6732 transitions. [2022-10-17 10:15:05,513 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 4936 [2022-10-17 10:15:05,538 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4987 states to 4987 states and 6732 transitions. [2022-10-17 10:15:05,539 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4987 [2022-10-17 10:15:05,544 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4987 [2022-10-17 10:15:05,544 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4987 states and 6732 transitions. [2022-10-17 10:15:05,552 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:15:05,552 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4987 states and 6732 transitions. [2022-10-17 10:15:05,558 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4987 states and 6732 transitions. [2022-10-17 10:15:05,689 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4987 to 4931. [2022-10-17 10:15:05,698 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4931 states, 4931 states have (on average 1.3538835935915636) internal successors, (6676), 4930 states have internal predecessors, (6676), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:15:05,712 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4931 states to 4931 states and 6676 transitions. [2022-10-17 10:15:05,712 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4931 states and 6676 transitions. [2022-10-17 10:15:05,712 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:15:05,713 INFO L428 stractBuchiCegarLoop]: Abstraction has 4931 states and 6676 transitions. [2022-10-17 10:15:05,713 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-10-17 10:15:05,713 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4931 states and 6676 transitions. [2022-10-17 10:15:05,731 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 4880 [2022-10-17 10:15:05,732 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:15:05,732 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:15:05,732 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:15:05,732 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:15:05,733 INFO L748 eck$LassoCheckResult]: Stem: 39047#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 38995#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 38996#L528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 38998#L236 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 39006#L243 assume 1 == ~m_i~0;~m_st~0 := 0; 38949#L243-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 38950#L248-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 38795#L253-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 38796#L356 assume !(0 == ~M_E~0); 38892#L356-2 assume !(0 == ~T1_E~0); 38893#L361-1 assume !(0 == ~T2_E~0); 38974#L366-1 assume !(0 == ~E_M~0); 38967#L371-1 assume !(0 == ~E_1~0); 38861#L376-1 assume !(0 == ~E_2~0); 38862#L381-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 38801#L178 assume !(1 == ~m_pc~0); 38802#L178-2 is_master_triggered_~__retres1~0#1 := 0; 38896#L189 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 38897#L190 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 38959#L437 assume !(0 != activate_threads_~tmp~1#1); 38824#L437-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38825#L197 assume !(1 == ~t1_pc~0); 38870#L197-2 is_transmit1_triggered_~__retres1~1#1 := 0; 38869#L208 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39042#L209 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 38818#L445 assume !(0 != activate_threads_~tmp___0~0#1); 38819#L445-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 39027#L216 assume !(1 == ~t2_pc~0); 38799#L216-2 is_transmit2_triggered_~__retres1~2#1 := 0; 38800#L227 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38894#L228 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 38895#L453 assume !(0 != activate_threads_~tmp___1~0#1); 38965#L453-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38966#L394 assume !(1 == ~M_E~0); 38971#L394-2 assume !(1 == ~T1_E~0); 38936#L399-1 assume !(1 == ~T2_E~0); 38937#L404-1 assume !(1 == ~E_M~0); 38842#L409-1 assume !(1 == ~E_1~0); 38843#L414-1 assume !(1 == ~E_2~0); 38939#L419-1 assume { :end_inline_reset_delta_events } true; 38940#L565-2 assume !false; 40487#L566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40484#L331 [2022-10-17 10:15:05,733 INFO L750 eck$LassoCheckResult]: Loop: 40484#L331 assume !false; 40482#L294 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 40480#L266 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 40478#L283 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 40476#L284 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 40474#L298 assume 0 != eval_~tmp~0#1; 40473#L298-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 40471#L306 assume !(0 != eval_~tmp_ndt_1~0#1); 40470#L303 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 40425#L320 assume !(0 != eval_~tmp_ndt_2~0#1); 40468#L317 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 40191#L334 assume !(0 != eval_~tmp_ndt_3~0#1); 40484#L331 [2022-10-17 10:15:05,733 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:15:05,733 INFO L85 PathProgramCache]: Analyzing trace with hash 327016235, now seen corresponding path program 3 times [2022-10-17 10:15:05,734 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:15:05,734 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [475036818] [2022-10-17 10:15:05,734 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:15:05,734 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:15:05,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:15:05,741 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:15:05,746 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:15:05,752 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:15:05,752 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:15:05,752 INFO L85 PathProgramCache]: Analyzing trace with hash 1517048953, now seen corresponding path program 1 times [2022-10-17 10:15:05,752 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:15:05,752 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2065134574] [2022-10-17 10:15:05,753 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:15:05,753 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:15:05,756 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:15:05,756 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:15:05,758 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:15:05,760 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:15:05,760 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:15:05,761 INFO L85 PathProgramCache]: Analyzing trace with hash 1586676899, now seen corresponding path program 1 times [2022-10-17 10:15:05,761 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:15:05,761 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [473265184] [2022-10-17 10:15:05,761 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:15:05,761 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:15:05,769 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:15:05,769 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:15:05,774 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:15:05,782 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:15:06,768 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:15:06,768 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:15:06,782 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:15:06,941 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 17.10 10:15:06 BoogieIcfgContainer [2022-10-17 10:15:06,943 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2022-10-17 10:15:06,943 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-10-17 10:15:06,944 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-10-17 10:15:06,944 INFO L275 PluginConnector]: Witness Printer initialized [2022-10-17 10:15:06,944 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 17.10 10:15:00" (3/4) ... [2022-10-17 10:15:06,948 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2022-10-17 10:15:07,037 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_78788a82-ad02-4763-9196-a0d98a202eca/bin/uautomizer-J5u9QxTXDZ/witness.graphml [2022-10-17 10:15:07,037 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-10-17 10:15:07,038 INFO L158 Benchmark]: Toolchain (without parser) took 7639.46ms. Allocated memory was 90.2MB in the beginning and 161.5MB in the end (delta: 71.3MB). Free memory was 53.5MB in the beginning and 49.1MB in the end (delta: 4.4MB). Peak memory consumption was 75.0MB. Max. memory is 16.1GB. [2022-10-17 10:15:07,038 INFO L158 Benchmark]: CDTParser took 0.31ms. Allocated memory is still 90.2MB. Free memory was 70.2MB in the beginning and 70.1MB in the end (delta: 73.7kB). There was no memory consumed. Max. memory is 16.1GB. [2022-10-17 10:15:07,039 INFO L158 Benchmark]: CACSL2BoogieTranslator took 424.94ms. Allocated memory was 90.2MB in the beginning and 109.1MB in the end (delta: 18.9MB). Free memory was 53.4MB in the beginning and 80.4MB in the end (delta: -27.0MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2022-10-17 10:15:07,039 INFO L158 Benchmark]: Boogie Procedure Inliner took 84.70ms. Allocated memory is still 109.1MB. Free memory was 80.4MB in the beginning and 77.4MB in the end (delta: 3.0MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-10-17 10:15:07,040 INFO L158 Benchmark]: Boogie Preprocessor took 63.66ms. Allocated memory is still 109.1MB. Free memory was 77.4MB in the beginning and 74.5MB in the end (delta: 2.9MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2022-10-17 10:15:07,040 INFO L158 Benchmark]: RCFGBuilder took 912.42ms. Allocated memory is still 109.1MB. Free memory was 74.5MB in the beginning and 45.2MB in the end (delta: 29.4MB). Peak memory consumption was 29.4MB. Max. memory is 16.1GB. [2022-10-17 10:15:07,041 INFO L158 Benchmark]: BuchiAutomizer took 6054.52ms. Allocated memory was 109.1MB in the beginning and 161.5MB in the end (delta: 52.4MB). Free memory was 45.2MB in the beginning and 54.4MB in the end (delta: -9.2MB). Peak memory consumption was 44.0MB. Max. memory is 16.1GB. [2022-10-17 10:15:07,041 INFO L158 Benchmark]: Witness Printer took 93.64ms. Allocated memory is still 161.5MB. Free memory was 54.4MB in the beginning and 49.1MB in the end (delta: 5.2MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. [2022-10-17 10:15:07,043 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.31ms. Allocated memory is still 90.2MB. Free memory was 70.2MB in the beginning and 70.1MB in the end (delta: 73.7kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 424.94ms. Allocated memory was 90.2MB in the beginning and 109.1MB in the end (delta: 18.9MB). Free memory was 53.4MB in the beginning and 80.4MB in the end (delta: -27.0MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 84.70ms. Allocated memory is still 109.1MB. Free memory was 80.4MB in the beginning and 77.4MB in the end (delta: 3.0MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 63.66ms. Allocated memory is still 109.1MB. Free memory was 77.4MB in the beginning and 74.5MB in the end (delta: 2.9MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * RCFGBuilder took 912.42ms. Allocated memory is still 109.1MB. Free memory was 74.5MB in the beginning and 45.2MB in the end (delta: 29.4MB). Peak memory consumption was 29.4MB. Max. memory is 16.1GB. * BuchiAutomizer took 6054.52ms. Allocated memory was 109.1MB in the beginning and 161.5MB in the end (delta: 52.4MB). Free memory was 45.2MB in the beginning and 54.4MB in the end (delta: -9.2MB). Peak memory consumption was 44.0MB. Max. memory is 16.1GB. * Witness Printer took 93.64ms. Allocated memory is still 161.5MB. Free memory was 54.4MB in the beginning and 49.1MB in the end (delta: 5.2MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 13 terminating modules (13 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.13 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 4931 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 5.8s and 14 iterations. TraceHistogramMax:1. Analysis of lassos took 3.3s. Construction of modules took 0.4s. Büchi inclusion checks took 1.7s. Highest rank in rank-based complementation 0. Minimization of det autom 13. Minimization of nondet autom 0. Automata minimization 0.6s AutomataMinimizationTime, 13 MinimizatonAttempts, 3041 StatesRemovedByMinimization, 9 NontrivialMinimizations. Non-live state removal took 0.3s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 5339 SdHoareTripleChecker+Valid, 0.6s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 5339 mSDsluCounter, 9092 SdHoareTripleChecker+Invalid, 0.4s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 4536 mSDsCounter, 120 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 329 IncrementalHoareTripleChecker+Invalid, 449 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 120 mSolverCounterUnsat, 4556 mSDtfsCounter, 329 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc2 concLT0 SILN1 SILU0 SILI7 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 293]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int m_st ; [L28] int t1_st ; [L29] int t2_st ; [L30] int m_i ; [L31] int t1_i ; [L32] int t2_i ; [L33] int M_E = 2; [L34] int T1_E = 2; [L35] int T2_E = 2; [L36] int E_M = 2; [L37] int E_1 = 2; [L38] int E_2 = 2; [L43] int token ; [L45] int local ; VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, token=0] [L610] int __retres1 ; [L614] CALL init_model() [L524] m_i = 1 [L525] t1_i = 1 [L526] t2_i = 1 VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L614] RET init_model() [L615] CALL start_simulation() [L551] int kernel_st ; [L552] int tmp ; [L553] int tmp___0 ; [L557] kernel_st = 0 [L558] FCALL update_channels() [L559] CALL init_threads() [L243] COND TRUE m_i == 1 [L244] m_st = 0 VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L248] COND TRUE t1_i == 1 [L249] t1_st = 0 VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L253] COND TRUE t2_i == 1 [L254] t2_st = 0 VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L559] RET init_threads() [L560] CALL fire_delta_events() [L356] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L361] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L366] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L371] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L376] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L381] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L560] RET fire_delta_events() [L561] CALL activate_threads() [L429] int tmp ; [L430] int tmp___0 ; [L431] int tmp___1 ; [L435] CALL, EXPR is_master_triggered() [L175] int __retres1 ; VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L178] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L188] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L190] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L435] RET, EXPR is_master_triggered() [L435] tmp = is_master_triggered() [L437] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=0, token=0] [L443] CALL, EXPR is_transmit1_triggered() [L194] int __retres1 ; VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L197] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L207] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L209] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L443] RET, EXPR is_transmit1_triggered() [L443] tmp___0 = is_transmit1_triggered() [L445] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=0, tmp___0=0, token=0] [L451] CALL, EXPR is_transmit2_triggered() [L213] int __retres1 ; VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L216] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L226] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L228] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L451] RET, EXPR is_transmit2_triggered() [L451] tmp___1 = is_transmit2_triggered() [L453] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=0, tmp___0=0, tmp___1=0, token=0] [L561] RET activate_threads() [L562] CALL reset_delta_events() [L394] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L399] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L404] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L409] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L414] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L419] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L562] RET reset_delta_events() [L565] COND TRUE 1 VAL [E_1=2, E_2=2, E_M=2, kernel_st=0, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L568] kernel_st = 1 [L569] CALL eval() [L289] int tmp ; VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] Loop: [L293] COND TRUE 1 [L296] CALL, EXPR exists_runnable_thread() [L263] int __retres1 ; [L266] COND TRUE m_st == 0 [L267] __retres1 = 1 [L284] return (__retres1); [L296] RET, EXPR exists_runnable_thread() [L296] tmp = exists_runnable_thread() [L298] COND TRUE \read(tmp) [L303] COND TRUE m_st == 0 [L304] int tmp_ndt_1; [L305] tmp_ndt_1 = __VERIFIER_nondet_int() [L306] COND FALSE !(\read(tmp_ndt_1)) [L317] COND TRUE t1_st == 0 [L318] int tmp_ndt_2; [L319] tmp_ndt_2 = __VERIFIER_nondet_int() [L320] COND FALSE !(\read(tmp_ndt_2)) [L331] COND TRUE t2_st == 0 [L332] int tmp_ndt_3; [L333] tmp_ndt_3 = __VERIFIER_nondet_int() [L334] COND FALSE !(\read(tmp_ndt_3)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 293]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int m_st ; [L28] int t1_st ; [L29] int t2_st ; [L30] int m_i ; [L31] int t1_i ; [L32] int t2_i ; [L33] int M_E = 2; [L34] int T1_E = 2; [L35] int T2_E = 2; [L36] int E_M = 2; [L37] int E_1 = 2; [L38] int E_2 = 2; [L43] int token ; [L45] int local ; VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, token=0] [L610] int __retres1 ; [L614] CALL init_model() [L524] m_i = 1 [L525] t1_i = 1 [L526] t2_i = 1 VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L614] RET init_model() [L615] CALL start_simulation() [L551] int kernel_st ; [L552] int tmp ; [L553] int tmp___0 ; [L557] kernel_st = 0 [L558] FCALL update_channels() [L559] CALL init_threads() [L243] COND TRUE m_i == 1 [L244] m_st = 0 VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L248] COND TRUE t1_i == 1 [L249] t1_st = 0 VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L253] COND TRUE t2_i == 1 [L254] t2_st = 0 VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L559] RET init_threads() [L560] CALL fire_delta_events() [L356] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L361] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L366] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L371] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L376] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L381] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L560] RET fire_delta_events() [L561] CALL activate_threads() [L429] int tmp ; [L430] int tmp___0 ; [L431] int tmp___1 ; [L435] CALL, EXPR is_master_triggered() [L175] int __retres1 ; VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L178] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L188] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L190] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L435] RET, EXPR is_master_triggered() [L435] tmp = is_master_triggered() [L437] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=0, token=0] [L443] CALL, EXPR is_transmit1_triggered() [L194] int __retres1 ; VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L197] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L207] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L209] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L443] RET, EXPR is_transmit1_triggered() [L443] tmp___0 = is_transmit1_triggered() [L445] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=0, tmp___0=0, token=0] [L451] CALL, EXPR is_transmit2_triggered() [L213] int __retres1 ; VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L216] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L226] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L228] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L451] RET, EXPR is_transmit2_triggered() [L451] tmp___1 = is_transmit2_triggered() [L453] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=0, tmp___0=0, tmp___1=0, token=0] [L561] RET activate_threads() [L562] CALL reset_delta_events() [L394] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L399] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L404] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L409] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L414] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L419] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L562] RET reset_delta_events() [L565] COND TRUE 1 VAL [E_1=2, E_2=2, E_M=2, kernel_st=0, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] [L568] kernel_st = 1 [L569] CALL eval() [L289] int tmp ; VAL [E_1=2, E_2=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, token=0] Loop: [L293] COND TRUE 1 [L296] CALL, EXPR exists_runnable_thread() [L263] int __retres1 ; [L266] COND TRUE m_st == 0 [L267] __retres1 = 1 [L284] return (__retres1); [L296] RET, EXPR exists_runnable_thread() [L296] tmp = exists_runnable_thread() [L298] COND TRUE \read(tmp) [L303] COND TRUE m_st == 0 [L304] int tmp_ndt_1; [L305] tmp_ndt_1 = __VERIFIER_nondet_int() [L306] COND FALSE !(\read(tmp_ndt_1)) [L317] COND TRUE t1_st == 0 [L318] int tmp_ndt_2; [L319] tmp_ndt_2 = __VERIFIER_nondet_int() [L320] COND FALSE !(\read(tmp_ndt_2)) [L331] COND TRUE t2_st == 0 [L332] int tmp_ndt_3; [L333] tmp_ndt_3 = __VERIFIER_nondet_int() [L334] COND FALSE !(\read(tmp_ndt_3)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2022-10-17 10:15:07,193 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_78788a82-ad02-4763-9196-a0d98a202eca/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)