./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.04.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version dbf71c69 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0226a7e4-297f-426f-84a3-9f9bdc583d94/bin/uautomizer-J5u9QxTXDZ/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0226a7e4-297f-426f-84a3-9f9bdc583d94/bin/uautomizer-J5u9QxTXDZ/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0226a7e4-297f-426f-84a3-9f9bdc583d94/bin/uautomizer-J5u9QxTXDZ/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0226a7e4-297f-426f-84a3-9f9bdc583d94/bin/uautomizer-J5u9QxTXDZ/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.04.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0226a7e4-297f-426f-84a3-9f9bdc583d94/bin/uautomizer-J5u9QxTXDZ/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0226a7e4-297f-426f-84a3-9f9bdc583d94/bin/uautomizer-J5u9QxTXDZ --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash d4710f8f3a918a0191222414f5c33a367ff98c09c2e8598fa3213223c4c35dba --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-dbf71c6-m [2022-10-17 10:33:18,350 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-10-17 10:33:18,356 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-10-17 10:33:18,410 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-10-17 10:33:18,411 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-10-17 10:33:18,415 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-10-17 10:33:18,418 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-10-17 10:33:18,423 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-10-17 10:33:18,425 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-10-17 10:33:18,431 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-10-17 10:33:18,432 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-10-17 10:33:18,434 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-10-17 10:33:18,435 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-10-17 10:33:18,437 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-10-17 10:33:18,438 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-10-17 10:33:18,441 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-10-17 10:33:18,442 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-10-17 10:33:18,443 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-10-17 10:33:18,445 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-10-17 10:33:18,452 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-10-17 10:33:18,454 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-10-17 10:33:18,455 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-10-17 10:33:18,458 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-10-17 10:33:18,459 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-10-17 10:33:18,469 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-10-17 10:33:18,470 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-10-17 10:33:18,470 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-10-17 10:33:18,472 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-10-17 10:33:18,473 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-10-17 10:33:18,474 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-10-17 10:33:18,474 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-10-17 10:33:18,476 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-10-17 10:33:18,478 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-10-17 10:33:18,480 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-10-17 10:33:18,481 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-10-17 10:33:18,481 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-10-17 10:33:18,482 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-10-17 10:33:18,482 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-10-17 10:33:18,482 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-10-17 10:33:18,483 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-10-17 10:33:18,484 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-10-17 10:33:18,484 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0226a7e4-297f-426f-84a3-9f9bdc583d94/bin/uautomizer-J5u9QxTXDZ/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-10-17 10:33:18,529 INFO L113 SettingsManager]: Loading preferences was successful [2022-10-17 10:33:18,530 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-10-17 10:33:18,530 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-10-17 10:33:18,531 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-10-17 10:33:18,532 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-10-17 10:33:18,532 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-10-17 10:33:18,532 INFO L138 SettingsManager]: * Use SBE=true [2022-10-17 10:33:18,532 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-10-17 10:33:18,533 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-10-17 10:33:18,533 INFO L138 SettingsManager]: * Use old map elimination=false [2022-10-17 10:33:18,534 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-10-17 10:33:18,534 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-10-17 10:33:18,534 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-10-17 10:33:18,534 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-10-17 10:33:18,535 INFO L138 SettingsManager]: * sizeof long=4 [2022-10-17 10:33:18,535 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-10-17 10:33:18,535 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-10-17 10:33:18,535 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-10-17 10:33:18,535 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-10-17 10:33:18,536 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-10-17 10:33:18,536 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-10-17 10:33:18,536 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-10-17 10:33:18,536 INFO L138 SettingsManager]: * sizeof long double=12 [2022-10-17 10:33:18,536 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-10-17 10:33:18,536 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-10-17 10:33:18,537 INFO L138 SettingsManager]: * Use constant arrays=true [2022-10-17 10:33:18,537 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-10-17 10:33:18,537 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-10-17 10:33:18,537 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-10-17 10:33:18,538 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-10-17 10:33:18,538 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-10-17 10:33:18,539 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-10-17 10:33:18,539 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0226a7e4-297f-426f-84a3-9f9bdc583d94/bin/uautomizer-J5u9QxTXDZ/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0226a7e4-297f-426f-84a3-9f9bdc583d94/bin/uautomizer-J5u9QxTXDZ Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> d4710f8f3a918a0191222414f5c33a367ff98c09c2e8598fa3213223c4c35dba [2022-10-17 10:33:18,787 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-10-17 10:33:18,805 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-10-17 10:33:18,808 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-10-17 10:33:18,809 INFO L271 PluginConnector]: Initializing CDTParser... [2022-10-17 10:33:18,810 INFO L275 PluginConnector]: CDTParser initialized [2022-10-17 10:33:18,811 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0226a7e4-297f-426f-84a3-9f9bdc583d94/bin/uautomizer-J5u9QxTXDZ/../../sv-benchmarks/c/systemc/token_ring.04.cil-1.c [2022-10-17 10:33:18,897 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0226a7e4-297f-426f-84a3-9f9bdc583d94/bin/uautomizer-J5u9QxTXDZ/data/cc122aec5/a470a9785fe547f59f605b38630e5291/FLAGc1be299a2 [2022-10-17 10:33:19,392 INFO L306 CDTParser]: Found 1 translation units. [2022-10-17 10:33:19,393 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0226a7e4-297f-426f-84a3-9f9bdc583d94/sv-benchmarks/c/systemc/token_ring.04.cil-1.c [2022-10-17 10:33:19,404 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0226a7e4-297f-426f-84a3-9f9bdc583d94/bin/uautomizer-J5u9QxTXDZ/data/cc122aec5/a470a9785fe547f59f605b38630e5291/FLAGc1be299a2 [2022-10-17 10:33:19,758 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0226a7e4-297f-426f-84a3-9f9bdc583d94/bin/uautomizer-J5u9QxTXDZ/data/cc122aec5/a470a9785fe547f59f605b38630e5291 [2022-10-17 10:33:19,760 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-10-17 10:33:19,762 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-10-17 10:33:19,763 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-10-17 10:33:19,763 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-10-17 10:33:19,767 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-10-17 10:33:19,767 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.10 10:33:19" (1/1) ... [2022-10-17 10:33:19,769 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@26da2e15 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:33:19, skipping insertion in model container [2022-10-17 10:33:19,769 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.10 10:33:19" (1/1) ... [2022-10-17 10:33:19,776 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-10-17 10:33:19,811 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-10-17 10:33:19,964 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0226a7e4-297f-426f-84a3-9f9bdc583d94/sv-benchmarks/c/systemc/token_ring.04.cil-1.c[671,684] [2022-10-17 10:33:20,058 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-10-17 10:33:20,075 INFO L203 MainTranslator]: Completed pre-run [2022-10-17 10:33:20,093 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0226a7e4-297f-426f-84a3-9f9bdc583d94/sv-benchmarks/c/systemc/token_ring.04.cil-1.c[671,684] [2022-10-17 10:33:20,136 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-10-17 10:33:20,153 INFO L208 MainTranslator]: Completed translation [2022-10-17 10:33:20,154 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:33:20 WrapperNode [2022-10-17 10:33:20,154 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-10-17 10:33:20,156 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-10-17 10:33:20,156 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-10-17 10:33:20,156 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-10-17 10:33:20,162 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:33:20" (1/1) ... [2022-10-17 10:33:20,170 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:33:20" (1/1) ... [2022-10-17 10:33:20,233 INFO L138 Inliner]: procedures = 36, calls = 43, calls flagged for inlining = 38, calls inlined = 77, statements flattened = 1062 [2022-10-17 10:33:20,233 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-10-17 10:33:20,234 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-10-17 10:33:20,234 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-10-17 10:33:20,234 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-10-17 10:33:20,247 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:33:20" (1/1) ... [2022-10-17 10:33:20,258 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:33:20" (1/1) ... [2022-10-17 10:33:20,264 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:33:20" (1/1) ... [2022-10-17 10:33:20,264 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:33:20" (1/1) ... [2022-10-17 10:33:20,297 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:33:20" (1/1) ... [2022-10-17 10:33:20,329 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:33:20" (1/1) ... [2022-10-17 10:33:20,332 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:33:20" (1/1) ... [2022-10-17 10:33:20,344 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:33:20" (1/1) ... [2022-10-17 10:33:20,351 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-10-17 10:33:20,360 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-10-17 10:33:20,361 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-10-17 10:33:20,361 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-10-17 10:33:20,362 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:33:20" (1/1) ... [2022-10-17 10:33:20,368 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:33:20,379 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0226a7e4-297f-426f-84a3-9f9bdc583d94/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:33:20,397 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0226a7e4-297f-426f-84a3-9f9bdc583d94/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:33:20,411 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0226a7e4-297f-426f-84a3-9f9bdc583d94/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-10-17 10:33:20,446 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-10-17 10:33:20,446 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-10-17 10:33:20,446 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-10-17 10:33:20,446 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-10-17 10:33:20,522 INFO L235 CfgBuilder]: Building ICFG [2022-10-17 10:33:20,524 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-10-17 10:33:21,458 INFO L276 CfgBuilder]: Performing block encoding [2022-10-17 10:33:21,475 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-10-17 10:33:21,475 INFO L300 CfgBuilder]: Removed 7 assume(true) statements. [2022-10-17 10:33:21,479 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 17.10 10:33:21 BoogieIcfgContainer [2022-10-17 10:33:21,480 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-10-17 10:33:21,481 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-10-17 10:33:21,482 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-10-17 10:33:21,485 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-10-17 10:33:21,486 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-10-17 10:33:21,486 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 17.10 10:33:19" (1/3) ... [2022-10-17 10:33:21,487 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@41a48c56 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.10 10:33:21, skipping insertion in model container [2022-10-17 10:33:21,488 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-10-17 10:33:21,488 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:33:20" (2/3) ... [2022-10-17 10:33:21,488 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@41a48c56 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.10 10:33:21, skipping insertion in model container [2022-10-17 10:33:21,488 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-10-17 10:33:21,488 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 17.10 10:33:21" (3/3) ... [2022-10-17 10:33:21,492 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.04.cil-1.c [2022-10-17 10:33:21,555 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-10-17 10:33:21,555 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-10-17 10:33:21,555 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-10-17 10:33:21,556 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-10-17 10:33:21,556 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-10-17 10:33:21,556 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-10-17 10:33:21,556 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-10-17 10:33:21,556 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-10-17 10:33:21,563 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 431 states, 430 states have (on average 1.5325581395348837) internal successors, (659), 430 states have internal predecessors, (659), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:33:21,608 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 360 [2022-10-17 10:33:21,608 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:33:21,608 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:33:21,619 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:33:21,620 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:33:21,620 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-10-17 10:33:21,622 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 431 states, 430 states have (on average 1.5325581395348837) internal successors, (659), 430 states have internal predecessors, (659), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:33:21,636 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 360 [2022-10-17 10:33:21,636 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:33:21,636 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:33:21,641 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:33:21,641 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:33:21,650 INFO L748 eck$LassoCheckResult]: Stem: 424#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 362#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 218#L766true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 44#L346true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 75#L353true assume !(1 == ~m_i~0);~m_st~0 := 2; 297#L353-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 367#L358-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 47#L363-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 410#L368-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 122#L373-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 64#L514true assume !(0 == ~M_E~0); 381#L514-2true assume 0 == ~T1_E~0;~T1_E~0 := 1; 326#L519-1true assume !(0 == ~T2_E~0); 39#L524-1true assume !(0 == ~T3_E~0); 105#L529-1true assume !(0 == ~T4_E~0); 329#L534-1true assume !(0 == ~E_M~0); 266#L539-1true assume !(0 == ~E_1~0); 295#L544-1true assume !(0 == ~E_2~0); 296#L549-1true assume !(0 == ~E_3~0); 334#L554-1true assume 0 == ~E_4~0;~E_4~0 := 1; 37#L559-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 175#L250true assume 1 == ~m_pc~0; 395#L251true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 327#L261true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 148#L262true activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 299#L637true assume !(0 != activate_threads_~tmp~1#1); 40#L637-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 55#L269true assume !(1 == ~t1_pc~0); 102#L269-2true is_transmit1_triggered_~__retres1~1#1 := 0; 180#L280true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 119#L281true activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 328#L645true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 146#L645-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 237#L288true assume 1 == ~t2_pc~0; 358#L289true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 250#L299true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 156#L300true activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 259#L653true assume !(0 != activate_threads_~tmp___1~0#1); 312#L653-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 163#L307true assume !(1 == ~t3_pc~0); 225#L307-2true is_transmit3_triggered_~__retres1~3#1 := 0; 209#L318true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 431#L319true activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 307#L661true assume !(0 != activate_threads_~tmp___2~0#1); 129#L661-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 351#L326true assume 1 == ~t4_pc~0; 344#L327true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 161#L337true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 265#L338true activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 308#L669true assume !(0 != activate_threads_~tmp___3~0#1); 263#L669-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 303#L572true assume !(1 == ~M_E~0); 345#L572-2true assume !(1 == ~T1_E~0); 45#L577-1true assume !(1 == ~T2_E~0); 246#L582-1true assume !(1 == ~T3_E~0); 253#L587-1true assume !(1 == ~T4_E~0); 371#L592-1true assume !(1 == ~E_M~0); 13#L597-1true assume 1 == ~E_1~0;~E_1~0 := 2; 411#L602-1true assume !(1 == ~E_2~0); 140#L607-1true assume !(1 == ~E_3~0); 415#L612-1true assume !(1 == ~E_4~0); 104#L617-1true assume { :end_inline_reset_delta_events } true; 429#L803-2true [2022-10-17 10:33:21,652 INFO L750 eck$LassoCheckResult]: Loop: 429#L803-2true assume !false; 219#L804true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 200#L489true assume !true; 388#L504true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 231#L346-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 197#L514-3true assume 0 == ~M_E~0;~M_E~0 := 1; 152#L514-5true assume !(0 == ~T1_E~0); 317#L519-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 243#L524-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 85#L529-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 172#L534-3true assume 0 == ~E_M~0;~E_M~0 := 1; 8#L539-3true assume 0 == ~E_1~0;~E_1~0 := 1; 332#L544-3true assume 0 == ~E_2~0;~E_2~0 := 1; 399#L549-3true assume 0 == ~E_3~0;~E_3~0 := 1; 118#L554-3true assume !(0 == ~E_4~0); 193#L559-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 273#L250-18true assume 1 == ~m_pc~0; 230#L251-6true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 207#L261-6true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 53#L262-6true activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 271#L637-18true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 90#L637-20true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31#L269-18true assume !(1 == ~t1_pc~0); 352#L269-20true is_transmit1_triggered_~__retres1~1#1 := 0; 71#L280-6true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 101#L281-6true activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 184#L645-18true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 289#L645-20true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 111#L288-18true assume !(1 == ~t2_pc~0); 396#L288-20true is_transmit2_triggered_~__retres1~2#1 := 0; 12#L299-6true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 61#L300-6true activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 170#L653-18true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 94#L653-20true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 315#L307-18true assume 1 == ~t3_pc~0; 141#L308-6true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 121#L318-6true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 124#L319-6true activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 84#L661-18true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 347#L661-20true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 274#L326-18true assume 1 == ~t4_pc~0; 365#L327-6true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 285#L337-6true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 245#L338-6true activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6#L669-18true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 368#L669-20true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 419#L572-3true assume 1 == ~M_E~0;~M_E~0 := 2; 93#L572-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 110#L577-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 36#L582-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 370#L587-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 192#L592-3true assume 1 == ~E_M~0;~E_M~0 := 2; 251#L597-3true assume !(1 == ~E_1~0); 133#L602-3true assume 1 == ~E_2~0;~E_2~0 := 2; 323#L607-3true assume 1 == ~E_3~0;~E_3~0 := 2; 99#L612-3true assume 1 == ~E_4~0;~E_4~0 := 2; 195#L617-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 137#L386-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 127#L413-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 372#L414-1true start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 162#L822true assume !(0 == start_simulation_~tmp~3#1); 270#L822-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 394#L386-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 404#L413-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 164#L414-2true stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 23#L777true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 202#L784true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 212#L785true start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 316#L835true assume !(0 != start_simulation_~tmp___0~1#1); 429#L803-2true [2022-10-17 10:33:21,658 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:33:21,658 INFO L85 PathProgramCache]: Analyzing trace with hash 1553035642, now seen corresponding path program 1 times [2022-10-17 10:33:21,680 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:33:21,681 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [285631031] [2022-10-17 10:33:21,681 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:33:21,682 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:33:21,780 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:33:21,931 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:33:21,932 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:33:21,934 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [285631031] [2022-10-17 10:33:21,935 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [285631031] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:33:21,935 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:33:21,935 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:33:21,937 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2127729635] [2022-10-17 10:33:21,938 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:33:21,942 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:33:21,945 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:33:21,946 INFO L85 PathProgramCache]: Analyzing trace with hash -1836170278, now seen corresponding path program 1 times [2022-10-17 10:33:21,946 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:33:21,947 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1024477078] [2022-10-17 10:33:21,947 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:33:21,947 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:33:21,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:33:22,032 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:33:22,032 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:33:22,032 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1024477078] [2022-10-17 10:33:22,033 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1024477078] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:33:22,033 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:33:22,033 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-10-17 10:33:22,034 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1160485738] [2022-10-17 10:33:22,034 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:33:22,036 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:33:22,037 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:33:22,070 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:33:22,071 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:33:22,074 INFO L87 Difference]: Start difference. First operand has 431 states, 430 states have (on average 1.5325581395348837) internal successors, (659), 430 states have internal predecessors, (659), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:33:22,126 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:33:22,127 INFO L93 Difference]: Finished difference Result 430 states and 642 transitions. [2022-10-17 10:33:22,128 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 430 states and 642 transitions. [2022-10-17 10:33:22,133 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 358 [2022-10-17 10:33:22,142 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 430 states to 425 states and 637 transitions. [2022-10-17 10:33:22,144 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 425 [2022-10-17 10:33:22,148 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 425 [2022-10-17 10:33:22,149 INFO L73 IsDeterministic]: Start isDeterministic. Operand 425 states and 637 transitions. [2022-10-17 10:33:22,152 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:33:22,152 INFO L218 hiAutomatonCegarLoop]: Abstraction has 425 states and 637 transitions. [2022-10-17 10:33:22,170 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 425 states and 637 transitions. [2022-10-17 10:33:22,200 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 425 to 425. [2022-10-17 10:33:22,202 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 425 states, 425 states have (on average 1.4988235294117647) internal successors, (637), 424 states have internal predecessors, (637), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:33:22,204 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 425 states to 425 states and 637 transitions. [2022-10-17 10:33:22,205 INFO L240 hiAutomatonCegarLoop]: Abstraction has 425 states and 637 transitions. [2022-10-17 10:33:22,206 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:33:22,210 INFO L428 stractBuchiCegarLoop]: Abstraction has 425 states and 637 transitions. [2022-10-17 10:33:22,210 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-10-17 10:33:22,210 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 425 states and 637 transitions. [2022-10-17 10:33:22,214 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 358 [2022-10-17 10:33:22,217 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:33:22,217 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:33:22,221 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:33:22,228 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:33:22,228 INFO L748 eck$LassoCheckResult]: Stem: 1294#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 1287#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 1205#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 958#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 959#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 1014#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1260#L358-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 964#L363-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 965#L368-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1087#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 996#L514 assume !(0 == ~M_E~0); 997#L514-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1276#L519-1 assume !(0 == ~T2_E~0); 950#L524-1 assume !(0 == ~T3_E~0); 951#L529-1 assume !(0 == ~T4_E~0); 1066#L534-1 assume !(0 == ~E_M~0); 1242#L539-1 assume !(0 == ~E_1~0); 1243#L544-1 assume !(0 == ~E_2~0); 1258#L549-1 assume !(0 == ~E_3~0); 1259#L554-1 assume 0 == ~E_4~0;~E_4~0 := 1; 945#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 946#L250 assume 1 == ~m_pc~0; 1155#L251 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1264#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1120#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1121#L637 assume !(0 != activate_threads_~tmp~1#1); 952#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 953#L269 assume !(1 == ~t1_pc~0); 890#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 889#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1084#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1085#L645 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1117#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1118#L288 assume 1 == ~t2_pc~0; 1220#L289 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1114#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1130#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1131#L653 assume !(0 != activate_threads_~tmp___1~0#1); 1237#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1144#L307 assume !(1 == ~t3_pc~0); 1078#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1079#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1195#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1269#L661 assume !(0 != activate_threads_~tmp___2~0#1); 1093#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1094#L326 assume 1 == ~t4_pc~0; 1283#L327 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 904#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1140#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1241#L669 assume !(0 != activate_threads_~tmp___3~0#1); 1238#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1239#L572 assume !(1 == ~M_E~0); 1265#L572-2 assume !(1 == ~T1_E~0); 960#L577-1 assume !(1 == ~T2_E~0); 961#L582-1 assume !(1 == ~T3_E~0); 1226#L587-1 assume !(1 == ~T4_E~0); 1233#L592-1 assume !(1 == ~E_M~0); 895#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 896#L602-1 assume !(1 == ~E_2~0); 1110#L607-1 assume !(1 == ~E_3~0); 1111#L612-1 assume !(1 == ~E_4~0); 1064#L617-1 assume { :end_inline_reset_delta_events } true; 1065#L803-2 [2022-10-17 10:33:22,229 INFO L750 eck$LassoCheckResult]: Loop: 1065#L803-2 assume !false; 1206#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 988#L489 assume !false; 1183#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1146#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1004#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1060#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1293#L428 assume !(0 != eval_~tmp~0#1); 1291#L504 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1216#L346-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1182#L514-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1124#L514-5 assume !(0 == ~T1_E~0); 1125#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1224#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1034#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1035#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 884#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 885#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1278#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1082#L554-3 assume !(0 == ~E_4~0); 1083#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1180#L250-18 assume 1 == ~m_pc~0; 1214#L251-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1192#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 975#L262-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 976#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1044#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 932#L269-18 assume !(1 == ~t1_pc~0); 933#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 1006#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1007#L281-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1061#L645-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1168#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1070#L288-18 assume 1 == ~t2_pc~0; 1056#L289-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 893#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 894#L300-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 991#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1051#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1052#L307-18 assume 1 == ~t3_pc~0; 1112#L308-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1024#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1086#L319-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1032#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1033#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1247#L326-18 assume 1 == ~t4_pc~0; 1248#L327-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1254#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1225#L338-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 880#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 881#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1288#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1049#L572-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1050#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 943#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 944#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1178#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1179#L597-3 assume !(1 == ~E_1~0); 1099#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1100#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1058#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1059#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1105#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1074#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1091#L414-1 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 1141#L822 assume !(0 == start_simulation_~tmp~3#1); 1143#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1245#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1187#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1145#L414-2 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 916#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 917#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1185#L785 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 1201#L835 assume !(0 != start_simulation_~tmp___0~1#1); 1065#L803-2 [2022-10-17 10:33:22,230 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:33:22,230 INFO L85 PathProgramCache]: Analyzing trace with hash 1119306556, now seen corresponding path program 1 times [2022-10-17 10:33:22,231 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:33:22,231 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1345175249] [2022-10-17 10:33:22,231 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:33:22,231 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:33:22,256 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:33:22,343 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:33:22,343 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:33:22,344 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1345175249] [2022-10-17 10:33:22,344 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1345175249] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:33:22,344 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:33:22,344 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:33:22,345 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1332362384] [2022-10-17 10:33:22,345 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:33:22,345 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:33:22,346 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:33:22,346 INFO L85 PathProgramCache]: Analyzing trace with hash -387617298, now seen corresponding path program 1 times [2022-10-17 10:33:22,346 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:33:22,347 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [310570800] [2022-10-17 10:33:22,347 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:33:22,347 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:33:22,377 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:33:22,489 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:33:22,490 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:33:22,490 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [310570800] [2022-10-17 10:33:22,492 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [310570800] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:33:22,492 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:33:22,492 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:33:22,493 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [51796727] [2022-10-17 10:33:22,493 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:33:22,494 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:33:22,495 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:33:22,495 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:33:22,495 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:33:22,496 INFO L87 Difference]: Start difference. First operand 425 states and 637 transitions. cyclomatic complexity: 213 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:33:22,524 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:33:22,524 INFO L93 Difference]: Finished difference Result 425 states and 636 transitions. [2022-10-17 10:33:22,524 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 425 states and 636 transitions. [2022-10-17 10:33:22,529 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 358 [2022-10-17 10:33:22,534 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 425 states to 425 states and 636 transitions. [2022-10-17 10:33:22,534 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 425 [2022-10-17 10:33:22,535 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 425 [2022-10-17 10:33:22,535 INFO L73 IsDeterministic]: Start isDeterministic. Operand 425 states and 636 transitions. [2022-10-17 10:33:22,538 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:33:22,539 INFO L218 hiAutomatonCegarLoop]: Abstraction has 425 states and 636 transitions. [2022-10-17 10:33:22,540 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 425 states and 636 transitions. [2022-10-17 10:33:22,554 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 425 to 425. [2022-10-17 10:33:22,556 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 425 states, 425 states have (on average 1.4964705882352942) internal successors, (636), 424 states have internal predecessors, (636), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:33:22,573 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 425 states to 425 states and 636 transitions. [2022-10-17 10:33:22,574 INFO L240 hiAutomatonCegarLoop]: Abstraction has 425 states and 636 transitions. [2022-10-17 10:33:22,574 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:33:22,575 INFO L428 stractBuchiCegarLoop]: Abstraction has 425 states and 636 transitions. [2022-10-17 10:33:22,575 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-10-17 10:33:22,575 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 425 states and 636 transitions. [2022-10-17 10:33:22,579 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 358 [2022-10-17 10:33:22,579 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:33:22,579 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:33:22,582 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:33:22,582 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:33:22,582 INFO L748 eck$LassoCheckResult]: Stem: 2151#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 2144#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 2062#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1815#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1816#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 1871#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2117#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1821#L363-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1822#L368-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1944#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1853#L514 assume !(0 == ~M_E~0); 1854#L514-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2133#L519-1 assume !(0 == ~T2_E~0); 1807#L524-1 assume !(0 == ~T3_E~0); 1808#L529-1 assume !(0 == ~T4_E~0); 1923#L534-1 assume !(0 == ~E_M~0); 2099#L539-1 assume !(0 == ~E_1~0); 2100#L544-1 assume !(0 == ~E_2~0); 2115#L549-1 assume !(0 == ~E_3~0); 2116#L554-1 assume 0 == ~E_4~0;~E_4~0 := 1; 1802#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1803#L250 assume 1 == ~m_pc~0; 2012#L251 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2121#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1977#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1978#L637 assume !(0 != activate_threads_~tmp~1#1); 1809#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1810#L269 assume !(1 == ~t1_pc~0); 1747#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1746#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1941#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1942#L645 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1974#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1975#L288 assume 1 == ~t2_pc~0; 2077#L289 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1971#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1987#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1988#L653 assume !(0 != activate_threads_~tmp___1~0#1); 2094#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2001#L307 assume !(1 == ~t3_pc~0); 1935#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1936#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2052#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2126#L661 assume !(0 != activate_threads_~tmp___2~0#1); 1950#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1951#L326 assume 1 == ~t4_pc~0; 2140#L327 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1761#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1997#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2098#L669 assume !(0 != activate_threads_~tmp___3~0#1); 2095#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2096#L572 assume !(1 == ~M_E~0); 2122#L572-2 assume !(1 == ~T1_E~0); 1817#L577-1 assume !(1 == ~T2_E~0); 1818#L582-1 assume !(1 == ~T3_E~0); 2083#L587-1 assume !(1 == ~T4_E~0); 2090#L592-1 assume !(1 == ~E_M~0); 1752#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1753#L602-1 assume !(1 == ~E_2~0); 1967#L607-1 assume !(1 == ~E_3~0); 1968#L612-1 assume !(1 == ~E_4~0); 1921#L617-1 assume { :end_inline_reset_delta_events } true; 1922#L803-2 [2022-10-17 10:33:22,583 INFO L750 eck$LassoCheckResult]: Loop: 1922#L803-2 assume !false; 2063#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1845#L489 assume !false; 2040#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2003#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1861#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1917#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2150#L428 assume !(0 != eval_~tmp~0#1); 2148#L504 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2073#L346-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2039#L514-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1981#L514-5 assume !(0 == ~T1_E~0); 1982#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2081#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1891#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1892#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1741#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1742#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2135#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1939#L554-3 assume !(0 == ~E_4~0); 1940#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2037#L250-18 assume 1 == ~m_pc~0; 2071#L251-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2049#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1832#L262-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1833#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1901#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1789#L269-18 assume !(1 == ~t1_pc~0); 1790#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 1863#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1864#L281-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1918#L645-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2025#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1927#L288-18 assume 1 == ~t2_pc~0; 1913#L289-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1750#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1751#L300-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1848#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1908#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1909#L307-18 assume 1 == ~t3_pc~0; 1969#L308-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1881#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1943#L319-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1889#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1890#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2104#L326-18 assume 1 == ~t4_pc~0; 2105#L327-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2111#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2082#L338-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1737#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1738#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2145#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1906#L572-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1907#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1800#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1801#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2035#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2036#L597-3 assume !(1 == ~E_1~0); 1956#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1957#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1915#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1916#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1962#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1931#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1948#L414-1 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 1998#L822 assume !(0 == start_simulation_~tmp~3#1); 2000#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2102#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2044#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2002#L414-2 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 1773#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1774#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2042#L785 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 2058#L835 assume !(0 != start_simulation_~tmp___0~1#1); 1922#L803-2 [2022-10-17 10:33:22,583 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:33:22,584 INFO L85 PathProgramCache]: Analyzing trace with hash 1078631806, now seen corresponding path program 1 times [2022-10-17 10:33:22,584 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:33:22,584 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [962977911] [2022-10-17 10:33:22,584 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:33:22,585 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:33:22,596 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:33:22,630 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:33:22,631 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:33:22,631 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [962977911] [2022-10-17 10:33:22,631 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [962977911] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:33:22,631 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:33:22,632 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:33:22,632 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1395098770] [2022-10-17 10:33:22,632 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:33:22,632 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:33:22,633 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:33:22,633 INFO L85 PathProgramCache]: Analyzing trace with hash -387617298, now seen corresponding path program 2 times [2022-10-17 10:33:22,633 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:33:22,634 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [102058893] [2022-10-17 10:33:22,634 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:33:22,634 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:33:22,649 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:33:22,732 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:33:22,732 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:33:22,733 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [102058893] [2022-10-17 10:33:22,733 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [102058893] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:33:22,733 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:33:22,733 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:33:22,734 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [177695599] [2022-10-17 10:33:22,734 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:33:22,734 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:33:22,734 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:33:22,735 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:33:22,735 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:33:22,736 INFO L87 Difference]: Start difference. First operand 425 states and 636 transitions. cyclomatic complexity: 212 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:33:22,757 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:33:22,758 INFO L93 Difference]: Finished difference Result 425 states and 635 transitions. [2022-10-17 10:33:22,758 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 425 states and 635 transitions. [2022-10-17 10:33:22,763 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 358 [2022-10-17 10:33:22,772 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 425 states to 425 states and 635 transitions. [2022-10-17 10:33:22,773 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 425 [2022-10-17 10:33:22,774 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 425 [2022-10-17 10:33:22,774 INFO L73 IsDeterministic]: Start isDeterministic. Operand 425 states and 635 transitions. [2022-10-17 10:33:22,778 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:33:22,778 INFO L218 hiAutomatonCegarLoop]: Abstraction has 425 states and 635 transitions. [2022-10-17 10:33:22,779 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 425 states and 635 transitions. [2022-10-17 10:33:22,796 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 425 to 425. [2022-10-17 10:33:22,803 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 425 states, 425 states have (on average 1.4941176470588236) internal successors, (635), 424 states have internal predecessors, (635), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:33:22,805 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 425 states to 425 states and 635 transitions. [2022-10-17 10:33:22,805 INFO L240 hiAutomatonCegarLoop]: Abstraction has 425 states and 635 transitions. [2022-10-17 10:33:22,806 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:33:22,807 INFO L428 stractBuchiCegarLoop]: Abstraction has 425 states and 635 transitions. [2022-10-17 10:33:22,807 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-10-17 10:33:22,807 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 425 states and 635 transitions. [2022-10-17 10:33:22,810 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 358 [2022-10-17 10:33:22,810 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:33:22,810 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:33:22,813 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:33:22,813 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:33:22,814 INFO L748 eck$LassoCheckResult]: Stem: 3008#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 3001#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 2919#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2672#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2673#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 2728#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2974#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2678#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2679#L368-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2801#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2710#L514 assume !(0 == ~M_E~0); 2711#L514-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2990#L519-1 assume !(0 == ~T2_E~0); 2664#L524-1 assume !(0 == ~T3_E~0); 2665#L529-1 assume !(0 == ~T4_E~0); 2780#L534-1 assume !(0 == ~E_M~0); 2956#L539-1 assume !(0 == ~E_1~0); 2957#L544-1 assume !(0 == ~E_2~0); 2972#L549-1 assume !(0 == ~E_3~0); 2973#L554-1 assume 0 == ~E_4~0;~E_4~0 := 1; 2659#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2660#L250 assume 1 == ~m_pc~0; 2869#L251 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2978#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2834#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2835#L637 assume !(0 != activate_threads_~tmp~1#1); 2666#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2667#L269 assume !(1 == ~t1_pc~0); 2604#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2603#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2798#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2799#L645 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2831#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2832#L288 assume 1 == ~t2_pc~0; 2934#L289 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2828#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2844#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2845#L653 assume !(0 != activate_threads_~tmp___1~0#1); 2951#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2858#L307 assume !(1 == ~t3_pc~0); 2792#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2793#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2909#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2983#L661 assume !(0 != activate_threads_~tmp___2~0#1); 2807#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2808#L326 assume 1 == ~t4_pc~0; 2997#L327 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2618#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2854#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2955#L669 assume !(0 != activate_threads_~tmp___3~0#1); 2952#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2953#L572 assume !(1 == ~M_E~0); 2979#L572-2 assume !(1 == ~T1_E~0); 2674#L577-1 assume !(1 == ~T2_E~0); 2675#L582-1 assume !(1 == ~T3_E~0); 2940#L587-1 assume !(1 == ~T4_E~0); 2947#L592-1 assume !(1 == ~E_M~0); 2609#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2610#L602-1 assume !(1 == ~E_2~0); 2824#L607-1 assume !(1 == ~E_3~0); 2825#L612-1 assume !(1 == ~E_4~0); 2778#L617-1 assume { :end_inline_reset_delta_events } true; 2779#L803-2 [2022-10-17 10:33:22,814 INFO L750 eck$LassoCheckResult]: Loop: 2779#L803-2 assume !false; 2920#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2702#L489 assume !false; 2897#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2860#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2718#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2774#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3007#L428 assume !(0 != eval_~tmp~0#1); 3005#L504 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2930#L346-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2896#L514-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2838#L514-5 assume !(0 == ~T1_E~0); 2839#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2938#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2748#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2749#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2598#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2599#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2992#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2796#L554-3 assume !(0 == ~E_4~0); 2797#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2894#L250-18 assume 1 == ~m_pc~0; 2928#L251-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2906#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2689#L262-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2690#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2758#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2646#L269-18 assume !(1 == ~t1_pc~0); 2647#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 2720#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2721#L281-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2775#L645-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2882#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2784#L288-18 assume 1 == ~t2_pc~0; 2770#L289-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2607#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2608#L300-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2705#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2765#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2766#L307-18 assume !(1 == ~t3_pc~0); 2737#L307-20 is_transmit3_triggered_~__retres1~3#1 := 0; 2738#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2800#L319-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2746#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2747#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2961#L326-18 assume 1 == ~t4_pc~0; 2962#L327-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2968#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2939#L338-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2594#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2595#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3002#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2763#L572-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2764#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2657#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2658#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2892#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2893#L597-3 assume !(1 == ~E_1~0); 2813#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2814#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2772#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2773#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2819#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2788#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2805#L414-1 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 2855#L822 assume !(0 == start_simulation_~tmp~3#1); 2857#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2959#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2901#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2859#L414-2 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 2630#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2631#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2899#L785 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 2915#L835 assume !(0 != start_simulation_~tmp___0~1#1); 2779#L803-2 [2022-10-17 10:33:22,814 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:33:22,815 INFO L85 PathProgramCache]: Analyzing trace with hash -308153604, now seen corresponding path program 1 times [2022-10-17 10:33:22,815 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:33:22,815 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1596787903] [2022-10-17 10:33:22,815 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:33:22,816 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:33:22,831 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:33:22,881 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:33:22,882 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:33:22,882 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1596787903] [2022-10-17 10:33:22,882 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1596787903] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:33:22,883 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:33:22,883 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:33:22,883 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1768105085] [2022-10-17 10:33:22,883 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:33:22,884 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:33:22,884 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:33:22,884 INFO L85 PathProgramCache]: Analyzing trace with hash 663831791, now seen corresponding path program 1 times [2022-10-17 10:33:22,884 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:33:22,885 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1120870097] [2022-10-17 10:33:22,885 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:33:22,885 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:33:22,898 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:33:22,933 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:33:22,934 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:33:22,934 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1120870097] [2022-10-17 10:33:22,934 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1120870097] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:33:22,934 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:33:22,935 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:33:22,935 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [293149239] [2022-10-17 10:33:22,935 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:33:22,935 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:33:22,936 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:33:22,936 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:33:22,936 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:33:22,937 INFO L87 Difference]: Start difference. First operand 425 states and 635 transitions. cyclomatic complexity: 211 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:33:22,950 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:33:22,950 INFO L93 Difference]: Finished difference Result 425 states and 634 transitions. [2022-10-17 10:33:22,950 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 425 states and 634 transitions. [2022-10-17 10:33:22,954 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 358 [2022-10-17 10:33:22,958 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 425 states to 425 states and 634 transitions. [2022-10-17 10:33:22,958 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 425 [2022-10-17 10:33:22,959 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 425 [2022-10-17 10:33:22,959 INFO L73 IsDeterministic]: Start isDeterministic. Operand 425 states and 634 transitions. [2022-10-17 10:33:22,960 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:33:22,960 INFO L218 hiAutomatonCegarLoop]: Abstraction has 425 states and 634 transitions. [2022-10-17 10:33:22,961 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 425 states and 634 transitions. [2022-10-17 10:33:22,967 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 425 to 425. [2022-10-17 10:33:22,968 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 425 states, 425 states have (on average 1.4917647058823529) internal successors, (634), 424 states have internal predecessors, (634), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:33:22,970 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 425 states to 425 states and 634 transitions. [2022-10-17 10:33:22,970 INFO L240 hiAutomatonCegarLoop]: Abstraction has 425 states and 634 transitions. [2022-10-17 10:33:22,971 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:33:22,972 INFO L428 stractBuchiCegarLoop]: Abstraction has 425 states and 634 transitions. [2022-10-17 10:33:22,972 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-10-17 10:33:22,972 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 425 states and 634 transitions. [2022-10-17 10:33:22,985 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 358 [2022-10-17 10:33:22,985 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:33:22,985 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:33:22,987 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:33:22,987 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:33:22,988 INFO L748 eck$LassoCheckResult]: Stem: 3865#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 3858#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 3776#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3529#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3530#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 3585#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3832#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3535#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3536#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3659#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3567#L514 assume !(0 == ~M_E~0); 3568#L514-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3847#L519-1 assume !(0 == ~T2_E~0); 3521#L524-1 assume !(0 == ~T3_E~0); 3522#L529-1 assume !(0 == ~T4_E~0); 3637#L534-1 assume !(0 == ~E_M~0); 3813#L539-1 assume !(0 == ~E_1~0); 3814#L544-1 assume !(0 == ~E_2~0); 3829#L549-1 assume !(0 == ~E_3~0); 3830#L554-1 assume 0 == ~E_4~0;~E_4~0 := 1; 3516#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3517#L250 assume 1 == ~m_pc~0; 3729#L251 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3836#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3691#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3692#L637 assume !(0 != activate_threads_~tmp~1#1); 3523#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3524#L269 assume !(1 == ~t1_pc~0); 3461#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3460#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3655#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3656#L645 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3688#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3689#L288 assume 1 == ~t2_pc~0; 3792#L289 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3685#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3701#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3702#L653 assume !(0 != activate_threads_~tmp___1~0#1); 3808#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3716#L307 assume !(1 == ~t3_pc~0); 3649#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3650#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3771#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3840#L661 assume !(0 != activate_threads_~tmp___2~0#1); 3664#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3665#L326 assume 1 == ~t4_pc~0; 3854#L327 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3475#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3714#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3812#L669 assume !(0 != activate_threads_~tmp___3~0#1); 3809#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3810#L572 assume !(1 == ~M_E~0); 3835#L572-2 assume !(1 == ~T1_E~0); 3531#L577-1 assume !(1 == ~T2_E~0); 3532#L582-1 assume !(1 == ~T3_E~0); 3797#L587-1 assume !(1 == ~T4_E~0); 3804#L592-1 assume !(1 == ~E_M~0); 3466#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 3467#L602-1 assume !(1 == ~E_2~0); 3681#L607-1 assume !(1 == ~E_3~0); 3682#L612-1 assume !(1 == ~E_4~0); 3635#L617-1 assume { :end_inline_reset_delta_events } true; 3636#L803-2 [2022-10-17 10:33:22,988 INFO L750 eck$LassoCheckResult]: Loop: 3636#L803-2 assume !false; 3777#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3559#L489 assume !false; 3754#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3717#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3575#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3631#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3864#L428 assume !(0 != eval_~tmp~0#1); 3862#L504 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3787#L346-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3753#L514-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3695#L514-5 assume !(0 == ~T1_E~0); 3696#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3795#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3605#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3606#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3455#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3456#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3849#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3653#L554-3 assume !(0 == ~E_4~0); 3654#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3751#L250-18 assume 1 == ~m_pc~0; 3785#L251-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3763#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3546#L262-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3547#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3615#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3503#L269-18 assume !(1 == ~t1_pc~0); 3504#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 3577#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3578#L281-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3632#L645-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3739#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3641#L288-18 assume 1 == ~t2_pc~0; 3627#L289-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3464#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3465#L300-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3562#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3622#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3623#L307-18 assume 1 == ~t3_pc~0; 3683#L308-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3595#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3657#L319-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3603#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3604#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3818#L326-18 assume 1 == ~t4_pc~0; 3819#L327-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3825#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3796#L338-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3451#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3452#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3859#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3620#L572-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3621#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3514#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3515#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3749#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3750#L597-3 assume !(1 == ~E_1~0); 3670#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3671#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3629#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3630#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3676#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3645#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3662#L414-1 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 3711#L822 assume !(0 == start_simulation_~tmp~3#1); 3713#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3816#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3758#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3715#L414-2 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 3487#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3488#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3756#L785 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 3772#L835 assume !(0 != start_simulation_~tmp___0~1#1); 3636#L803-2 [2022-10-17 10:33:22,989 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:33:22,989 INFO L85 PathProgramCache]: Analyzing trace with hash -1184172610, now seen corresponding path program 1 times [2022-10-17 10:33:22,989 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:33:22,989 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [128611267] [2022-10-17 10:33:22,990 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:33:22,990 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:33:23,005 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:33:23,058 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:33:23,059 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:33:23,059 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [128611267] [2022-10-17 10:33:23,059 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [128611267] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:33:23,059 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:33:23,060 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-10-17 10:33:23,060 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [605981126] [2022-10-17 10:33:23,060 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:33:23,061 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:33:23,061 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:33:23,061 INFO L85 PathProgramCache]: Analyzing trace with hash -387617298, now seen corresponding path program 3 times [2022-10-17 10:33:23,061 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:33:23,062 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1371916111] [2022-10-17 10:33:23,062 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:33:23,062 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:33:23,075 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:33:23,109 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:33:23,110 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:33:23,110 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1371916111] [2022-10-17 10:33:23,110 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1371916111] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:33:23,111 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:33:23,111 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:33:23,111 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [423306740] [2022-10-17 10:33:23,111 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:33:23,112 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:33:23,112 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:33:23,112 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:33:23,113 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:33:23,113 INFO L87 Difference]: Start difference. First operand 425 states and 634 transitions. cyclomatic complexity: 210 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:33:23,133 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:33:23,133 INFO L93 Difference]: Finished difference Result 425 states and 629 transitions. [2022-10-17 10:33:23,133 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 425 states and 629 transitions. [2022-10-17 10:33:23,138 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 358 [2022-10-17 10:33:23,142 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 425 states to 425 states and 629 transitions. [2022-10-17 10:33:23,142 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 425 [2022-10-17 10:33:23,143 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 425 [2022-10-17 10:33:23,143 INFO L73 IsDeterministic]: Start isDeterministic. Operand 425 states and 629 transitions. [2022-10-17 10:33:23,144 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:33:23,144 INFO L218 hiAutomatonCegarLoop]: Abstraction has 425 states and 629 transitions. [2022-10-17 10:33:23,145 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 425 states and 629 transitions. [2022-10-17 10:33:23,152 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 425 to 425. [2022-10-17 10:33:23,153 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 425 states, 425 states have (on average 1.48) internal successors, (629), 424 states have internal predecessors, (629), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:33:23,155 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 425 states to 425 states and 629 transitions. [2022-10-17 10:33:23,156 INFO L240 hiAutomatonCegarLoop]: Abstraction has 425 states and 629 transitions. [2022-10-17 10:33:23,156 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:33:23,157 INFO L428 stractBuchiCegarLoop]: Abstraction has 425 states and 629 transitions. [2022-10-17 10:33:23,157 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-10-17 10:33:23,157 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 425 states and 629 transitions. [2022-10-17 10:33:23,160 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 358 [2022-10-17 10:33:23,161 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:33:23,161 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:33:23,162 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:33:23,163 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:33:23,163 INFO L748 eck$LassoCheckResult]: Stem: 4722#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 4715#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 4633#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4386#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4387#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 4442#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4688#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4392#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4393#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4516#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4424#L514 assume !(0 == ~M_E~0); 4425#L514-2 assume !(0 == ~T1_E~0); 4704#L519-1 assume !(0 == ~T2_E~0); 4378#L524-1 assume !(0 == ~T3_E~0); 4379#L529-1 assume !(0 == ~T4_E~0); 4494#L534-1 assume !(0 == ~E_M~0); 4670#L539-1 assume !(0 == ~E_1~0); 4671#L544-1 assume !(0 == ~E_2~0); 4686#L549-1 assume !(0 == ~E_3~0); 4687#L554-1 assume 0 == ~E_4~0;~E_4~0 := 1; 4373#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4374#L250 assume 1 == ~m_pc~0; 4586#L251 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4692#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4548#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4549#L637 assume !(0 != activate_threads_~tmp~1#1); 4380#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4381#L269 assume !(1 == ~t1_pc~0); 4318#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4317#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4512#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4513#L645 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4545#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4546#L288 assume 1 == ~t2_pc~0; 4648#L289 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4542#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4558#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4559#L653 assume !(0 != activate_threads_~tmp___1~0#1); 4665#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4573#L307 assume !(1 == ~t3_pc~0); 4506#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4507#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4625#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4697#L661 assume !(0 != activate_threads_~tmp___2~0#1); 4521#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4522#L326 assume 1 == ~t4_pc~0; 4711#L327 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4332#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4571#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4669#L669 assume !(0 != activate_threads_~tmp___3~0#1); 4666#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4667#L572 assume !(1 == ~M_E~0); 4693#L572-2 assume !(1 == ~T1_E~0); 4388#L577-1 assume !(1 == ~T2_E~0); 4389#L582-1 assume !(1 == ~T3_E~0); 4655#L587-1 assume !(1 == ~T4_E~0); 4661#L592-1 assume !(1 == ~E_M~0); 4323#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 4324#L602-1 assume !(1 == ~E_2~0); 4538#L607-1 assume !(1 == ~E_3~0); 4539#L612-1 assume !(1 == ~E_4~0); 4492#L617-1 assume { :end_inline_reset_delta_events } true; 4493#L803-2 [2022-10-17 10:33:23,164 INFO L750 eck$LassoCheckResult]: Loop: 4493#L803-2 assume !false; 4635#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4416#L489 assume !false; 4611#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4574#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 4432#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4489#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 4721#L428 assume !(0 != eval_~tmp~0#1); 4719#L504 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4644#L346-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4610#L514-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4553#L514-5 assume !(0 == ~T1_E~0); 4554#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4653#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4462#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4463#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4312#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4313#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4706#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4510#L554-3 assume !(0 == ~E_4~0); 4511#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4608#L250-18 assume 1 == ~m_pc~0; 4642#L251-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4620#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4403#L262-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4404#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4472#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4360#L269-18 assume !(1 == ~t1_pc~0); 4361#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 4434#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4435#L281-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4488#L645-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4596#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4498#L288-18 assume 1 == ~t2_pc~0; 4481#L289-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4321#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4322#L300-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4419#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4479#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4480#L307-18 assume !(1 == ~t3_pc~0); 4449#L307-20 is_transmit3_triggered_~__retres1~3#1 := 0; 4450#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4514#L319-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4460#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4461#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4675#L326-18 assume 1 == ~t4_pc~0; 4676#L327-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4682#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4652#L338-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4308#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4309#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4716#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4475#L572-5 assume !(1 == ~T1_E~0); 4476#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4371#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4372#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4606#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4607#L597-3 assume !(1 == ~E_1~0); 4527#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4528#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4486#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4487#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4533#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 4502#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4519#L414-1 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 4568#L822 assume !(0 == start_simulation_~tmp~3#1); 4570#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4672#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 4615#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4572#L414-2 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 4344#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4345#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4612#L785 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 4629#L835 assume !(0 != start_simulation_~tmp___0~1#1); 4493#L803-2 [2022-10-17 10:33:23,164 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:33:23,164 INFO L85 PathProgramCache]: Analyzing trace with hash 1082208576, now seen corresponding path program 1 times [2022-10-17 10:33:23,165 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:33:23,165 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [15990378] [2022-10-17 10:33:23,165 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:33:23,166 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:33:23,178 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:33:23,241 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:33:23,242 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:33:23,242 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [15990378] [2022-10-17 10:33:23,242 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [15990378] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:33:23,243 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:33:23,243 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:33:23,243 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1546713792] [2022-10-17 10:33:23,243 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:33:23,244 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:33:23,244 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:33:23,244 INFO L85 PathProgramCache]: Analyzing trace with hash 882686509, now seen corresponding path program 1 times [2022-10-17 10:33:23,245 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:33:23,245 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [543214202] [2022-10-17 10:33:23,245 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:33:23,245 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:33:23,258 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:33:23,292 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:33:23,292 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:33:23,292 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [543214202] [2022-10-17 10:33:23,293 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [543214202] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:33:23,293 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:33:23,293 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:33:23,293 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1735684950] [2022-10-17 10:33:23,294 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:33:23,294 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:33:23,294 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:33:23,295 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-10-17 10:33:23,295 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-10-17 10:33:23,295 INFO L87 Difference]: Start difference. First operand 425 states and 629 transitions. cyclomatic complexity: 205 Second operand has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:33:23,414 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:33:23,414 INFO L93 Difference]: Finished difference Result 710 states and 1048 transitions. [2022-10-17 10:33:23,414 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 710 states and 1048 transitions. [2022-10-17 10:33:23,421 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 632 [2022-10-17 10:33:23,427 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 710 states to 710 states and 1048 transitions. [2022-10-17 10:33:23,427 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 710 [2022-10-17 10:33:23,428 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 710 [2022-10-17 10:33:23,428 INFO L73 IsDeterministic]: Start isDeterministic. Operand 710 states and 1048 transitions. [2022-10-17 10:33:23,429 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:33:23,430 INFO L218 hiAutomatonCegarLoop]: Abstraction has 710 states and 1048 transitions. [2022-10-17 10:33:23,432 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 710 states and 1048 transitions. [2022-10-17 10:33:23,448 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 710 to 709. [2022-10-17 10:33:23,449 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 709 states, 709 states have (on average 1.4767277856135401) internal successors, (1047), 708 states have internal predecessors, (1047), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:33:23,453 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 709 states to 709 states and 1047 transitions. [2022-10-17 10:33:23,453 INFO L240 hiAutomatonCegarLoop]: Abstraction has 709 states and 1047 transitions. [2022-10-17 10:33:23,453 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-10-17 10:33:23,455 INFO L428 stractBuchiCegarLoop]: Abstraction has 709 states and 1047 transitions. [2022-10-17 10:33:23,455 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-10-17 10:33:23,455 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 709 states and 1047 transitions. [2022-10-17 10:33:23,460 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 632 [2022-10-17 10:33:23,460 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:33:23,460 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:33:23,461 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:33:23,461 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:33:23,462 INFO L748 eck$LassoCheckResult]: Stem: 5889#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 5875#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 5784#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5531#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5532#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 5587#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5843#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5537#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5538#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5664#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5569#L514 assume !(0 == ~M_E~0); 5570#L514-2 assume !(0 == ~T1_E~0); 5862#L519-1 assume !(0 == ~T2_E~0); 5523#L524-1 assume !(0 == ~T3_E~0); 5524#L529-1 assume !(0 == ~T4_E~0); 5640#L534-1 assume !(0 == ~E_M~0); 5824#L539-1 assume !(0 == ~E_1~0); 5825#L544-1 assume !(0 == ~E_2~0); 5841#L549-1 assume !(0 == ~E_3~0); 5842#L554-1 assume !(0 == ~E_4~0); 5518#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5519#L250 assume 1 == ~m_pc~0; 5734#L251 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5847#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5696#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 5697#L637 assume !(0 != activate_threads_~tmp~1#1); 5525#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5526#L269 assume !(1 == ~t1_pc~0); 5463#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5462#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5660#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5661#L645 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5693#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5694#L288 assume 1 == ~t2_pc~0; 5802#L289 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5690#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5706#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5707#L653 assume !(0 != activate_threads_~tmp___1~0#1); 5819#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5721#L307 assume !(1 == ~t3_pc~0); 5652#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5653#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5776#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5853#L661 assume !(0 != activate_threads_~tmp___2~0#1); 5669#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5670#L326 assume 1 == ~t4_pc~0; 5869#L327 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5477#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5719#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5823#L669 assume !(0 != activate_threads_~tmp___3~0#1); 5820#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5821#L572 assume 1 == ~M_E~0;~M_E~0 := 2; 5848#L572-2 assume !(1 == ~T1_E~0); 5533#L577-1 assume !(1 == ~T2_E~0); 5534#L582-1 assume !(1 == ~T3_E~0); 5809#L587-1 assume !(1 == ~T4_E~0); 5815#L592-1 assume !(1 == ~E_M~0); 5468#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 5469#L602-1 assume !(1 == ~E_2~0); 5686#L607-1 assume !(1 == ~E_3~0); 5687#L612-1 assume !(1 == ~E_4~0); 5638#L617-1 assume { :end_inline_reset_delta_events } true; 5639#L803-2 [2022-10-17 10:33:23,462 INFO L750 eck$LassoCheckResult]: Loop: 5639#L803-2 assume !false; 5786#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5561#L489 assume !false; 5886#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 5887#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 5634#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 5635#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 5884#L428 assume !(0 != eval_~tmp~0#1); 5885#L504 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5797#L346-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5798#L514-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5701#L514-5 assume !(0 == ~T1_E~0); 5702#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5807#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5607#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5608#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5457#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5458#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5864#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5658#L554-3 assume !(0 == ~E_4~0); 5659#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5757#L250-18 assume 1 == ~m_pc~0; 5795#L251-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5771#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5548#L262-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 5549#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5617#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5505#L269-18 assume !(1 == ~t1_pc~0); 5506#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 5579#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5580#L281-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5633#L645-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5745#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5644#L288-18 assume 1 == ~t2_pc~0; 5626#L289-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5466#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5467#L300-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5564#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5624#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5625#L307-18 assume 1 == ~t3_pc~0; 5688#L308-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5595#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5662#L319-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5605#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5606#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5829#L326-18 assume 1 == ~t4_pc~0; 5830#L327-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5837#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5806#L338-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5453#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5454#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5876#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5620#L572-5 assume !(1 == ~T1_E~0); 5621#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5516#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5517#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5755#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5756#L597-3 assume !(1 == ~E_1~0); 5675#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5676#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5631#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5632#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 5681#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 5648#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 5667#L414-1 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 5716#L822 assume !(0 == start_simulation_~tmp~3#1); 5718#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 5826#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 5766#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 5720#L414-2 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 5489#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5490#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5763#L785 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 5780#L835 assume !(0 != start_simulation_~tmp___0~1#1); 5639#L803-2 [2022-10-17 10:33:23,463 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:33:23,463 INFO L85 PathProgramCache]: Analyzing trace with hash -516249280, now seen corresponding path program 1 times [2022-10-17 10:33:23,463 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:33:23,463 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1574654941] [2022-10-17 10:33:23,463 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:33:23,464 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:33:23,493 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:33:23,535 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:33:23,536 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:33:23,536 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1574654941] [2022-10-17 10:33:23,536 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1574654941] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:33:23,536 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:33:23,537 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-10-17 10:33:23,537 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1492068338] [2022-10-17 10:33:23,537 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:33:23,537 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:33:23,538 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:33:23,538 INFO L85 PathProgramCache]: Analyzing trace with hash -168762580, now seen corresponding path program 1 times [2022-10-17 10:33:23,538 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:33:23,538 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2118385022] [2022-10-17 10:33:23,539 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:33:23,539 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:33:23,552 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:33:23,581 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:33:23,581 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:33:23,582 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2118385022] [2022-10-17 10:33:23,582 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2118385022] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:33:23,582 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:33:23,582 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:33:23,582 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [488491418] [2022-10-17 10:33:23,583 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:33:23,583 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:33:23,583 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:33:23,584 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:33:23,584 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:33:23,584 INFO L87 Difference]: Start difference. First operand 709 states and 1047 transitions. cyclomatic complexity: 340 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:33:23,640 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:33:23,641 INFO L93 Difference]: Finished difference Result 1322 states and 1928 transitions. [2022-10-17 10:33:23,641 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1322 states and 1928 transitions. [2022-10-17 10:33:23,654 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1244 [2022-10-17 10:33:23,666 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1322 states to 1322 states and 1928 transitions. [2022-10-17 10:33:23,666 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1322 [2022-10-17 10:33:23,668 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1322 [2022-10-17 10:33:23,668 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1322 states and 1928 transitions. [2022-10-17 10:33:23,670 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:33:23,670 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1322 states and 1928 transitions. [2022-10-17 10:33:23,672 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1322 states and 1928 transitions. [2022-10-17 10:33:23,696 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1322 to 1254. [2022-10-17 10:33:23,699 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1254 states, 1254 states have (on average 1.4625199362041468) internal successors, (1834), 1253 states have internal predecessors, (1834), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:33:23,705 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1254 states to 1254 states and 1834 transitions. [2022-10-17 10:33:23,705 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1254 states and 1834 transitions. [2022-10-17 10:33:23,706 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:33:23,708 INFO L428 stractBuchiCegarLoop]: Abstraction has 1254 states and 1834 transitions. [2022-10-17 10:33:23,708 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-10-17 10:33:23,708 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1254 states and 1834 transitions. [2022-10-17 10:33:23,716 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1176 [2022-10-17 10:33:23,716 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:33:23,717 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:33:23,718 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:33:23,718 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:33:23,722 INFO L748 eck$LassoCheckResult]: Stem: 7964#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 7943#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 7833#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7569#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7570#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 7625#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7903#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7575#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7576#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7699#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7607#L514 assume !(0 == ~M_E~0); 7608#L514-2 assume !(0 == ~T1_E~0); 7928#L519-1 assume !(0 == ~T2_E~0); 7561#L524-1 assume !(0 == ~T3_E~0); 7562#L529-1 assume !(0 == ~T4_E~0); 7676#L534-1 assume !(0 == ~E_M~0); 7880#L539-1 assume !(0 == ~E_1~0); 7881#L544-1 assume !(0 == ~E_2~0); 7901#L549-1 assume !(0 == ~E_3~0); 7902#L554-1 assume !(0 == ~E_4~0); 7556#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7557#L250 assume !(1 == ~m_pc~0); 7774#L250-2 is_master_triggered_~__retres1~0#1 := 0; 7908#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7736#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 7737#L637 assume !(0 != activate_threads_~tmp~1#1); 7563#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7564#L269 assume !(1 == ~t1_pc~0); 7501#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7500#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7696#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7697#L645 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7733#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7734#L288 assume 1 == ~t2_pc~0; 7853#L289 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7726#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7747#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7748#L653 assume !(0 != activate_threads_~tmp___1~0#1); 7873#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7761#L307 assume !(1 == ~t3_pc~0); 7690#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 7691#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7821#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7916#L661 assume !(0 != activate_threads_~tmp___2~0#1); 7706#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7707#L326 assume 1 == ~t4_pc~0; 7938#L327 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7515#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7757#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7879#L669 assume !(0 != activate_threads_~tmp___3~0#1); 7875#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7876#L572 assume 1 == ~M_E~0;~M_E~0 := 2; 7909#L572-2 assume !(1 == ~T1_E~0); 7571#L577-1 assume !(1 == ~T2_E~0); 7572#L582-1 assume !(1 == ~T3_E~0); 7862#L587-1 assume !(1 == ~T4_E~0); 7869#L592-1 assume !(1 == ~E_M~0); 7506#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 7507#L602-1 assume !(1 == ~E_2~0); 7722#L607-1 assume !(1 == ~E_3~0); 7723#L612-1 assume !(1 == ~E_4~0); 7674#L617-1 assume { :end_inline_reset_delta_events } true; 7675#L803-2 [2022-10-17 10:33:23,722 INFO L750 eck$LassoCheckResult]: Loop: 7675#L803-2 assume !false; 8460#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8459#L489 assume !false; 8458#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 8457#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 8444#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 8445#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 7959#L428 assume !(0 != eval_~tmp~0#1); 7960#L504 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7848#L346-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7849#L514-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7741#L514-5 assume !(0 == ~T1_E~0); 7742#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7859#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7645#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7646#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7495#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7496#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7930#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7694#L554-3 assume !(0 == ~E_4~0); 7695#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7802#L250-18 assume !(1 == ~m_pc~0); 7886#L250-20 is_master_triggered_~__retres1~0#1 := 0; 7818#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7586#L262-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 7587#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7655#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7543#L269-18 assume !(1 == ~t1_pc~0); 7544#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 7617#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7618#L281-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7671#L645-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7788#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7682#L288-18 assume 1 == ~t2_pc~0; 7666#L289-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7504#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7505#L300-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7602#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7662#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7663#L307-18 assume !(1 == ~t3_pc~0); 7634#L307-20 is_transmit3_triggered_~__retres1~3#1 := 0; 7635#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7698#L319-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7643#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7644#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7887#L326-18 assume 1 == ~t4_pc~0; 7888#L327-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7897#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7861#L338-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7491#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7492#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7944#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7961#L572-5 assume !(1 == ~T1_E~0); 7681#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7554#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7555#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7800#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7801#L597-3 assume !(1 == ~E_1~0); 7711#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7712#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7668#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7669#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 7717#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 7686#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 7704#L414-1 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 7758#L822 assume !(0 == start_simulation_~tmp~3#1); 7760#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 7956#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 7811#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 7762#L414-2 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 7527#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7528#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7809#L785 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 7827#L835 assume !(0 != start_simulation_~tmp___0~1#1); 7675#L803-2 [2022-10-17 10:33:23,723 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:33:23,723 INFO L85 PathProgramCache]: Analyzing trace with hash -1001423999, now seen corresponding path program 1 times [2022-10-17 10:33:23,723 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:33:23,724 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1890376414] [2022-10-17 10:33:23,724 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:33:23,725 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:33:23,736 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:33:23,780 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:33:23,781 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:33:23,781 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1890376414] [2022-10-17 10:33:23,781 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1890376414] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:33:23,781 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:33:23,781 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-10-17 10:33:23,782 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1517007169] [2022-10-17 10:33:23,782 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:33:23,782 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:33:23,783 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:33:23,783 INFO L85 PathProgramCache]: Analyzing trace with hash 608908014, now seen corresponding path program 1 times [2022-10-17 10:33:23,783 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:33:23,783 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1763281426] [2022-10-17 10:33:23,783 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:33:23,784 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:33:23,793 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:33:23,819 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:33:23,819 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:33:23,819 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1763281426] [2022-10-17 10:33:23,819 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1763281426] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:33:23,820 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:33:23,820 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:33:23,820 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1523000023] [2022-10-17 10:33:23,820 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:33:23,821 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:33:23,821 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:33:23,821 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-10-17 10:33:23,821 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-10-17 10:33:23,822 INFO L87 Difference]: Start difference. First operand 1254 states and 1834 transitions. cyclomatic complexity: 584 Second operand has 5 states, 5 states have (on average 12.4) internal successors, (62), 5 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:33:23,984 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:33:23,985 INFO L93 Difference]: Finished difference Result 3355 states and 4893 transitions. [2022-10-17 10:33:23,985 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3355 states and 4893 transitions. [2022-10-17 10:33:24,030 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3184 [2022-10-17 10:33:24,061 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3355 states to 3355 states and 4893 transitions. [2022-10-17 10:33:24,061 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3355 [2022-10-17 10:33:24,065 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3355 [2022-10-17 10:33:24,065 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3355 states and 4893 transitions. [2022-10-17 10:33:24,071 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:33:24,072 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3355 states and 4893 transitions. [2022-10-17 10:33:24,076 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3355 states and 4893 transitions. [2022-10-17 10:33:24,113 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3355 to 1323. [2022-10-17 10:33:24,116 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1323 states, 1323 states have (on average 1.438397581254724) internal successors, (1903), 1322 states have internal predecessors, (1903), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:33:24,122 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1323 states to 1323 states and 1903 transitions. [2022-10-17 10:33:24,122 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1323 states and 1903 transitions. [2022-10-17 10:33:24,123 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-10-17 10:33:24,126 INFO L428 stractBuchiCegarLoop]: Abstraction has 1323 states and 1903 transitions. [2022-10-17 10:33:24,126 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-10-17 10:33:24,126 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1323 states and 1903 transitions. [2022-10-17 10:33:24,135 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1242 [2022-10-17 10:33:24,135 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:33:24,136 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:33:24,137 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:33:24,137 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:33:24,137 INFO L748 eck$LassoCheckResult]: Stem: 12674#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 12638#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 12477#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12194#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12195#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 12253#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12573#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12200#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12201#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12331#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12235#L514 assume !(0 == ~M_E~0); 12236#L514-2 assume !(0 == ~T1_E~0); 12602#L519-1 assume !(0 == ~T2_E~0); 12186#L524-1 assume !(0 == ~T3_E~0); 12187#L529-1 assume !(0 == ~T4_E~0); 12309#L534-1 assume !(0 == ~E_M~0); 12527#L539-1 assume !(0 == ~E_1~0); 12528#L544-1 assume !(0 == ~E_2~0); 12571#L549-1 assume !(0 == ~E_3~0); 12572#L554-1 assume !(0 == ~E_4~0); 12181#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12182#L250 assume !(1 == ~m_pc~0); 12410#L250-2 is_master_triggered_~__retres1~0#1 := 0; 12578#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12370#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 12371#L637 assume !(0 != activate_threads_~tmp~1#1); 12188#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12189#L269 assume !(1 == ~t1_pc~0); 12123#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12304#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12418#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 12603#L645 assume !(0 != activate_threads_~tmp___0~0#1); 12367#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12368#L288 assume 1 == ~t2_pc~0; 12498#L289 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12361#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12384#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 12385#L653 assume !(0 != activate_threads_~tmp___1~0#1); 12519#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12398#L307 assume !(1 == ~t3_pc~0); 12322#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 12323#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12465#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 12584#L661 assume !(0 != activate_threads_~tmp___2~0#1); 12337#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12338#L326 assume 1 == ~t4_pc~0; 12621#L327 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12139#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12394#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12526#L669 assume !(0 != activate_threads_~tmp___3~0#1); 12522#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12523#L572 assume 1 == ~M_E~0;~M_E~0 := 2; 12579#L572-2 assume !(1 == ~T1_E~0); 12196#L577-1 assume !(1 == ~T2_E~0); 12197#L582-1 assume !(1 == ~T3_E~0); 12507#L587-1 assume !(1 == ~T4_E~0); 12514#L592-1 assume !(1 == ~E_M~0); 12128#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 12129#L602-1 assume !(1 == ~E_2~0); 12357#L607-1 assume !(1 == ~E_3~0); 12358#L612-1 assume !(1 == ~E_4~0); 12307#L617-1 assume { :end_inline_reset_delta_events } true; 12308#L803-2 [2022-10-17 10:33:24,138 INFO L750 eck$LassoCheckResult]: Loop: 12308#L803-2 assume !false; 12677#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12824#L489 assume !false; 12822#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 12820#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 12728#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 12727#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 12725#L428 assume !(0 != eval_~tmp~0#1); 12726#L504 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13425#L346-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13424#L514-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13423#L514-5 assume !(0 == ~T1_E~0); 13422#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13421#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13420#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13419#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 13418#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13417#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13416#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13415#L554-3 assume !(0 == ~E_4~0); 13414#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12538#L250-18 assume !(1 == ~m_pc~0); 12539#L250-20 is_master_triggered_~__retres1~0#1 := 0; 12460#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12461#L262-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 12535#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12536#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12839#L269-18 assume !(1 == ~t1_pc~0); 12627#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 12628#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12302#L281-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 12303#L645-18 assume !(0 != activate_threads_~tmp___0~0#1); 12422#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12314#L288-18 assume 1 == ~t2_pc~0; 12295#L289-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12126#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12127#L300-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 12230#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12291#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12292#L307-18 assume !(1 == ~t3_pc~0); 12262#L307-20 is_transmit3_triggered_~__retres1~3#1 := 0; 12263#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12330#L319-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 12271#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12272#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12540#L326-18 assume 1 == ~t4_pc~0; 12541#L327-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12558#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12506#L338-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12113#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12114#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12640#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12289#L572-5 assume !(1 == ~T1_E~0); 12290#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12179#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12180#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12436#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12437#L597-3 assume !(1 == ~E_1~0); 12344#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12345#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12298#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12299#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 12351#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 12318#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 12335#L414-1 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 12642#L822 assume !(0 == start_simulation_~tmp~3#1); 12521#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 12534#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 12453#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 12399#L414-2 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 12151#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12152#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12451#L785 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 12471#L835 assume !(0 != start_simulation_~tmp___0~1#1); 12308#L803-2 [2022-10-17 10:33:24,138 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:33:24,139 INFO L85 PathProgramCache]: Analyzing trace with hash -299824125, now seen corresponding path program 1 times [2022-10-17 10:33:24,139 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:33:24,139 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1972050057] [2022-10-17 10:33:24,139 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:33:24,139 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:33:24,151 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:33:24,198 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:33:24,199 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:33:24,199 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1972050057] [2022-10-17 10:33:24,200 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1972050057] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:33:24,200 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:33:24,200 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:33:24,200 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1989906857] [2022-10-17 10:33:24,200 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:33:24,201 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:33:24,202 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:33:24,202 INFO L85 PathProgramCache]: Analyzing trace with hash -288485264, now seen corresponding path program 1 times [2022-10-17 10:33:24,202 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:33:24,202 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [188963326] [2022-10-17 10:33:24,202 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:33:24,203 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:33:24,213 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:33:24,249 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:33:24,249 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:33:24,249 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [188963326] [2022-10-17 10:33:24,249 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [188963326] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:33:24,249 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:33:24,250 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:33:24,250 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1992781717] [2022-10-17 10:33:24,250 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:33:24,251 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:33:24,251 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:33:24,251 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-10-17 10:33:24,252 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-10-17 10:33:24,252 INFO L87 Difference]: Start difference. First operand 1323 states and 1903 transitions. cyclomatic complexity: 584 Second operand has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:33:24,397 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:33:24,397 INFO L93 Difference]: Finished difference Result 3026 states and 4300 transitions. [2022-10-17 10:33:24,398 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3026 states and 4300 transitions. [2022-10-17 10:33:24,422 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 2856 [2022-10-17 10:33:24,447 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3026 states to 3026 states and 4300 transitions. [2022-10-17 10:33:24,448 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3026 [2022-10-17 10:33:24,452 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3026 [2022-10-17 10:33:24,452 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3026 states and 4300 transitions. [2022-10-17 10:33:24,457 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:33:24,457 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3026 states and 4300 transitions. [2022-10-17 10:33:24,461 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3026 states and 4300 transitions. [2022-10-17 10:33:24,526 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3026 to 2378. [2022-10-17 10:33:24,529 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2378 states, 2378 states have (on average 1.430613961312027) internal successors, (3402), 2377 states have internal predecessors, (3402), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:33:24,538 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2378 states to 2378 states and 3402 transitions. [2022-10-17 10:33:24,538 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2378 states and 3402 transitions. [2022-10-17 10:33:24,538 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-10-17 10:33:24,539 INFO L428 stractBuchiCegarLoop]: Abstraction has 2378 states and 3402 transitions. [2022-10-17 10:33:24,539 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-10-17 10:33:24,540 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2378 states and 3402 transitions. [2022-10-17 10:33:24,555 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2296 [2022-10-17 10:33:24,555 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:33:24,556 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:33:24,557 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:33:24,557 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:33:24,557 INFO L748 eck$LassoCheckResult]: Stem: 16949#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 16922#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 16812#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16551#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16552#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 16605#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16877#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16557#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16558#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16682#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16587#L514 assume !(0 == ~M_E~0); 16588#L514-2 assume !(0 == ~T1_E~0); 16898#L519-1 assume !(0 == ~T2_E~0); 16543#L524-1 assume !(0 == ~T3_E~0); 16544#L529-1 assume !(0 == ~T4_E~0); 16659#L534-1 assume !(0 == ~E_M~0); 16854#L539-1 assume !(0 == ~E_1~0); 16855#L544-1 assume !(0 == ~E_2~0); 16875#L549-1 assume !(0 == ~E_3~0); 16876#L554-1 assume !(0 == ~E_4~0); 16538#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16539#L250 assume !(1 == ~m_pc~0); 16758#L250-2 is_master_triggered_~__retres1~0#1 := 0; 16881#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16719#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 16720#L637 assume !(0 != activate_threads_~tmp~1#1); 16545#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16546#L269 assume !(1 == ~t1_pc~0); 16482#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 16654#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16952#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 16899#L645 assume !(0 != activate_threads_~tmp___0~0#1); 16716#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16717#L288 assume !(1 == ~t2_pc~0); 16708#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 16709#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16731#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 16732#L653 assume !(0 != activate_threads_~tmp___1~0#1); 16848#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16745#L307 assume !(1 == ~t3_pc~0); 16672#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 16673#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16797#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 16886#L661 assume !(0 != activate_threads_~tmp___2~0#1); 16689#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16690#L326 assume 1 == ~t4_pc~0; 16913#L327 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 16496#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16741#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 16853#L669 assume !(0 != activate_threads_~tmp___3~0#1); 16850#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16851#L572 assume 1 == ~M_E~0;~M_E~0 := 2; 16882#L572-2 assume !(1 == ~T1_E~0); 16914#L577-1 assume !(1 == ~T2_E~0); 16835#L582-1 assume !(1 == ~T3_E~0); 16836#L587-1 assume !(1 == ~T4_E~0); 16926#L592-1 assume !(1 == ~E_M~0); 16927#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 16940#L602-1 assume !(1 == ~E_2~0); 16941#L607-1 assume !(1 == ~E_3~0); 16942#L612-1 assume !(1 == ~E_4~0); 16943#L617-1 assume { :end_inline_reset_delta_events } true; 18639#L803-2 [2022-10-17 10:33:24,557 INFO L750 eck$LassoCheckResult]: Loop: 18639#L803-2 assume !false; 18634#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 18633#L489 assume !false; 18632#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 18631#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 18626#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 18625#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 18623#L428 assume !(0 != eval_~tmp~0#1); 18624#L504 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 18829#L346-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 18828#L514-3 assume 0 == ~M_E~0;~M_E~0 := 1; 18827#L514-5 assume !(0 == ~T1_E~0); 18822#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 18821#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18820#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18819#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 18818#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 18817#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 18816#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 18815#L554-3 assume !(0 == ~E_4~0); 18814#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18813#L250-18 assume !(1 == ~m_pc~0); 18812#L250-20 is_master_triggered_~__retres1~0#1 := 0; 18811#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18810#L262-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 18809#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18808#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18807#L269-18 assume !(1 == ~t1_pc~0); 18804#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 18803#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18802#L281-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 18801#L645-18 assume !(0 != activate_threads_~tmp___0~0#1); 18799#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18798#L288-18 assume !(1 == ~t2_pc~0); 17573#L288-20 is_transmit2_triggered_~__retres1~2#1 := 0; 18796#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18795#L300-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 18794#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18793#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18792#L307-18 assume !(1 == ~t3_pc~0); 18790#L307-20 is_transmit3_triggered_~__retres1~3#1 := 0; 18788#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18786#L319-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 18784#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 18782#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18780#L326-18 assume 1 == ~t4_pc~0; 18777#L327-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 18773#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18771#L338-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 18769#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 18767#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18764#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 16945#L572-5 assume !(1 == ~T1_E~0); 18761#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18760#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18758#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18714#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 18712#L597-3 assume !(1 == ~E_1~0); 18709#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 18705#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 18701#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16650#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 18693#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 18686#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 18683#L414-1 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 18680#L822 assume !(0 == start_simulation_~tmp~3#1); 16849#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 18670#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 18666#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 18663#L414-2 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 18660#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 18659#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18651#L785 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 18645#L835 assume !(0 != start_simulation_~tmp___0~1#1); 18639#L803-2 [2022-10-17 10:33:24,558 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:33:24,558 INFO L85 PathProgramCache]: Analyzing trace with hash -1271498812, now seen corresponding path program 1 times [2022-10-17 10:33:24,558 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:33:24,558 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [88265432] [2022-10-17 10:33:24,558 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:33:24,559 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:33:24,567 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:33:24,605 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:33:24,605 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:33:24,605 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [88265432] [2022-10-17 10:33:24,606 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [88265432] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:33:24,607 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:33:24,607 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-10-17 10:33:24,607 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1660766928] [2022-10-17 10:33:24,608 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:33:24,609 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:33:24,609 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:33:24,609 INFO L85 PathProgramCache]: Analyzing trace with hash -773659983, now seen corresponding path program 1 times [2022-10-17 10:33:24,609 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:33:24,609 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1359086801] [2022-10-17 10:33:24,610 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:33:24,610 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:33:24,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:33:24,649 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:33:24,649 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:33:24,650 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1359086801] [2022-10-17 10:33:24,650 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1359086801] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:33:24,650 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:33:24,650 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:33:24,650 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1024428572] [2022-10-17 10:33:24,650 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:33:24,651 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:33:24,651 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:33:24,652 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:33:24,652 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:33:24,652 INFO L87 Difference]: Start difference. First operand 2378 states and 3402 transitions. cyclomatic complexity: 1028 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:33:24,720 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:33:24,720 INFO L93 Difference]: Finished difference Result 4325 states and 6159 transitions. [2022-10-17 10:33:24,721 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4325 states and 6159 transitions. [2022-10-17 10:33:24,746 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4224 [2022-10-17 10:33:24,780 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4325 states to 4325 states and 6159 transitions. [2022-10-17 10:33:24,780 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4325 [2022-10-17 10:33:24,785 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4325 [2022-10-17 10:33:24,786 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4325 states and 6159 transitions. [2022-10-17 10:33:24,792 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:33:24,793 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4325 states and 6159 transitions. [2022-10-17 10:33:24,798 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4325 states and 6159 transitions. [2022-10-17 10:33:24,871 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4325 to 4309. [2022-10-17 10:33:24,880 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4309 states, 4309 states have (on average 1.4256207936876306) internal successors, (6143), 4308 states have internal predecessors, (6143), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:33:24,896 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4309 states to 4309 states and 6143 transitions. [2022-10-17 10:33:24,896 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4309 states and 6143 transitions. [2022-10-17 10:33:24,897 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:33:24,897 INFO L428 stractBuchiCegarLoop]: Abstraction has 4309 states and 6143 transitions. [2022-10-17 10:33:24,898 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-10-17 10:33:24,898 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4309 states and 6143 transitions. [2022-10-17 10:33:24,945 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4208 [2022-10-17 10:33:24,945 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:33:24,945 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:33:24,946 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:33:24,946 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:33:24,947 INFO L748 eck$LassoCheckResult]: Stem: 23680#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 23639#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 23530#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 23263#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 23264#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 23318#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 23602#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23269#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23270#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 23394#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 23299#L514 assume !(0 == ~M_E~0); 23300#L514-2 assume !(0 == ~T1_E~0); 23620#L519-1 assume !(0 == ~T2_E~0); 23253#L524-1 assume !(0 == ~T3_E~0); 23254#L529-1 assume !(0 == ~T4_E~0); 23371#L534-1 assume !(0 == ~E_M~0); 23581#L539-1 assume !(0 == ~E_1~0); 23582#L544-1 assume !(0 == ~E_2~0); 23600#L549-1 assume !(0 == ~E_3~0); 23601#L554-1 assume !(0 == ~E_4~0); 23248#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23249#L250 assume !(1 == ~m_pc~0); 23471#L250-2 is_master_triggered_~__retres1~0#1 := 0; 23606#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23433#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 23434#L637 assume !(0 != activate_threads_~tmp~1#1); 23255#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23256#L269 assume !(1 == ~t1_pc~0); 23192#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 23366#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23683#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 23621#L645 assume !(0 != activate_threads_~tmp___0~0#1); 23430#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23431#L288 assume !(1 == ~t2_pc~0); 23424#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 23425#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23445#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 23446#L653 assume !(0 != activate_threads_~tmp___1~0#1); 23575#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 23459#L307 assume !(1 == ~t3_pc~0); 23384#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 23385#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23517#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 23611#L661 assume !(0 != activate_threads_~tmp___2~0#1); 23402#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23403#L326 assume !(1 == ~t4_pc~0); 23205#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 23206#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23455#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 23580#L669 assume !(0 != activate_threads_~tmp___3~0#1); 23577#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23578#L572 assume 1 == ~M_E~0;~M_E~0 := 2; 23607#L572-2 assume !(1 == ~T1_E~0); 23265#L577-1 assume !(1 == ~T2_E~0); 23266#L582-1 assume !(1 == ~T3_E~0); 23570#L587-1 assume !(1 == ~T4_E~0); 23571#L592-1 assume !(1 == ~E_M~0); 23197#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 23198#L602-1 assume !(1 == ~E_2~0); 23421#L607-1 assume !(1 == ~E_3~0); 23422#L612-1 assume !(1 == ~E_4~0); 23369#L617-1 assume { :end_inline_reset_delta_events } true; 23370#L803-2 [2022-10-17 10:33:24,947 INFO L750 eck$LassoCheckResult]: Loop: 23370#L803-2 assume !false; 23531#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 23291#L489 assume !false; 23505#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 23461#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 23308#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 23364#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 23674#L428 assume !(0 != eval_~tmp~0#1); 23675#L504 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 26828#L346-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 26827#L514-3 assume 0 == ~M_E~0;~M_E~0 := 1; 26826#L514-5 assume !(0 == ~T1_E~0); 26824#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 26822#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 26821#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 26820#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 26819#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 26817#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 26816#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 26815#L554-3 assume !(0 == ~E_4~0); 26814#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26813#L250-18 assume !(1 == ~m_pc~0); 26812#L250-20 is_master_triggered_~__retres1~0#1 := 0; 26811#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26810#L262-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 26809#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 26807#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26576#L269-18 assume !(1 == ~t1_pc~0); 26573#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 26572#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26571#L281-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 26569#L645-18 assume !(0 != activate_threads_~tmp___0~0#1); 26566#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26564#L288-18 assume !(1 == ~t2_pc~0); 26167#L288-20 is_transmit2_triggered_~__retres1~2#1 := 0; 26563#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26560#L300-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 26558#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 26556#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26554#L307-18 assume !(1 == ~t3_pc~0); 26551#L307-20 is_transmit3_triggered_~__retres1~3#1 := 0; 26494#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26493#L319-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 26491#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 26490#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26488#L326-18 assume !(1 == ~t4_pc~0); 26484#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 26482#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26480#L338-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 26479#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 26474#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26469#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 23352#L572-5 assume !(1 == ~T1_E~0); 23353#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 23246#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 23247#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 23644#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 23567#L597-3 assume !(1 == ~E_1~0); 23409#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23410#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 23362#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 23363#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 23416#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 23380#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 23400#L414-1 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 23456#L822 assume !(0 == start_simulation_~tmp~3#1); 23458#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 23657#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 23509#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 23460#L414-2 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 23218#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 23219#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 23507#L785 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 23523#L835 assume !(0 != start_simulation_~tmp___0~1#1); 23370#L803-2 [2022-10-17 10:33:24,948 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:33:24,948 INFO L85 PathProgramCache]: Analyzing trace with hash 843496709, now seen corresponding path program 1 times [2022-10-17 10:33:24,948 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:33:24,948 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1116457067] [2022-10-17 10:33:24,948 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:33:24,948 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:33:24,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:33:24,994 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:33:24,995 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:33:24,995 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1116457067] [2022-10-17 10:33:24,995 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1116457067] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:33:24,995 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:33:24,995 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-10-17 10:33:24,996 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1249560397] [2022-10-17 10:33:24,996 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:33:24,996 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:33:24,997 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:33:24,997 INFO L85 PathProgramCache]: Analyzing trace with hash -1745334670, now seen corresponding path program 1 times [2022-10-17 10:33:24,997 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:33:24,997 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1522726546] [2022-10-17 10:33:24,997 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:33:24,997 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:33:25,007 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:33:25,048 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:33:25,048 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:33:25,048 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1522726546] [2022-10-17 10:33:25,048 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1522726546] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:33:25,048 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:33:25,049 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:33:25,049 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1755617060] [2022-10-17 10:33:25,049 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:33:25,049 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:33:25,049 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:33:25,050 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:33:25,050 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:33:25,051 INFO L87 Difference]: Start difference. First operand 4309 states and 6143 transitions. cyclomatic complexity: 1842 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:33:25,115 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:33:25,115 INFO L93 Difference]: Finished difference Result 6456 states and 9189 transitions. [2022-10-17 10:33:25,116 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6456 states and 9189 transitions. [2022-10-17 10:33:25,154 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6352 [2022-10-17 10:33:25,200 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6456 states to 6456 states and 9189 transitions. [2022-10-17 10:33:25,200 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6456 [2022-10-17 10:33:25,207 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6456 [2022-10-17 10:33:25,207 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6456 states and 9189 transitions. [2022-10-17 10:33:25,217 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:33:25,217 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6456 states and 9189 transitions. [2022-10-17 10:33:25,225 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6456 states and 9189 transitions. [2022-10-17 10:33:25,295 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6456 to 4687. [2022-10-17 10:33:25,305 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4687 states, 4687 states have (on average 1.421804992532537) internal successors, (6664), 4686 states have internal predecessors, (6664), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:33:25,318 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4687 states to 4687 states and 6664 transitions. [2022-10-17 10:33:25,318 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4687 states and 6664 transitions. [2022-10-17 10:33:25,319 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:33:25,319 INFO L428 stractBuchiCegarLoop]: Abstraction has 4687 states and 6664 transitions. [2022-10-17 10:33:25,319 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-10-17 10:33:25,320 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4687 states and 6664 transitions. [2022-10-17 10:33:25,339 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4596 [2022-10-17 10:33:25,339 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:33:25,339 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:33:25,341 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:33:25,341 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:33:25,341 INFO L748 eck$LassoCheckResult]: Stem: 34431#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 34406#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 34290#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 34033#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34034#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 34087#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 34364#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 34039#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 34040#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 34162#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 34069#L514 assume !(0 == ~M_E~0); 34070#L514-2 assume !(0 == ~T1_E~0); 34383#L519-1 assume !(0 == ~T2_E~0); 34025#L524-1 assume !(0 == ~T3_E~0); 34026#L529-1 assume !(0 == ~T4_E~0); 34139#L534-1 assume !(0 == ~E_M~0); 34335#L539-1 assume !(0 == ~E_1~0); 34336#L544-1 assume !(0 == ~E_2~0); 34361#L549-1 assume !(0 == ~E_3~0); 34362#L554-1 assume !(0 == ~E_4~0); 34020#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 34021#L250 assume !(1 == ~m_pc~0); 34239#L250-2 is_master_triggered_~__retres1~0#1 := 0; 34367#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34202#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 34203#L637 assume !(0 != activate_threads_~tmp~1#1); 34027#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34028#L269 assume !(1 == ~t1_pc~0); 33964#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 34134#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34433#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 34384#L645 assume !(0 != activate_threads_~tmp___0~0#1); 34199#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34200#L288 assume !(1 == ~t2_pc~0); 34192#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 34193#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34214#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 34215#L653 assume !(0 != activate_threads_~tmp___1~0#1); 34329#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34228#L307 assume !(1 == ~t3_pc~0); 34152#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 34153#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34285#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 34372#L661 assume !(0 != activate_threads_~tmp___2~0#1); 34171#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 34172#L326 assume !(1 == ~t4_pc~0); 33977#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 33978#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 34227#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 34334#L669 assume !(0 != activate_threads_~tmp___3~0#1); 34331#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34332#L572 assume !(1 == ~M_E~0); 34368#L572-2 assume !(1 == ~T1_E~0); 34035#L577-1 assume !(1 == ~T2_E~0); 34036#L582-1 assume !(1 == ~T3_E~0); 34318#L587-1 assume !(1 == ~T4_E~0); 34324#L592-1 assume !(1 == ~E_M~0); 33971#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 33972#L602-1 assume !(1 == ~E_2~0); 34189#L607-1 assume !(1 == ~E_3~0); 34190#L612-1 assume !(1 == ~E_4~0); 34137#L617-1 assume { :end_inline_reset_delta_events } true; 34138#L803-2 [2022-10-17 10:33:25,342 INFO L750 eck$LassoCheckResult]: Loop: 34138#L803-2 assume !false; 36759#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 36758#L489 assume !false; 36757#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 36756#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 36751#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 36750#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 36747#L428 assume !(0 != eval_~tmp~0#1); 36746#L504 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 36745#L346-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 36744#L514-3 assume !(0 == ~M_E~0); 36743#L514-5 assume !(0 == ~T1_E~0); 36741#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 36740#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 36739#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 36735#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 36733#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 36731#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 36729#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 36726#L554-3 assume !(0 == ~E_4~0); 36724#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36721#L250-18 assume !(1 == ~m_pc~0); 36720#L250-20 is_master_triggered_~__retres1~0#1 := 0; 36717#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36715#L262-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 36713#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 36711#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36709#L269-18 assume !(1 == ~t1_pc~0); 36705#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 36702#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36700#L281-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 36698#L645-18 assume !(0 != activate_threads_~tmp___0~0#1); 36695#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36693#L288-18 assume !(1 == ~t2_pc~0); 36105#L288-20 is_transmit2_triggered_~__retres1~2#1 := 0; 36690#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36688#L300-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 36686#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 36684#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36682#L307-18 assume !(1 == ~t3_pc~0); 36679#L307-20 is_transmit3_triggered_~__retres1~3#1 := 0; 36678#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36676#L319-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 36674#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 36672#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36670#L326-18 assume !(1 == ~t4_pc~0); 36668#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 36666#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36664#L338-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 36662#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 36660#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36659#L572-3 assume !(1 == ~M_E~0); 36549#L572-5 assume !(1 == ~T1_E~0); 36657#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 36653#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 36649#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 36646#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 36643#L597-3 assume !(1 == ~E_1~0); 36640#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 36637#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 36633#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 36629#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 36620#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 36611#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 36602#L414-1 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 36139#L822 assume !(0 == start_simulation_~tmp~3#1); 36140#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 36857#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 36856#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 36851#L414-2 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 36849#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 36846#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 36844#L785 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 36841#L835 assume !(0 != start_simulation_~tmp___0~1#1); 34138#L803-2 [2022-10-17 10:33:25,342 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:33:25,342 INFO L85 PathProgramCache]: Analyzing trace with hash 1544561287, now seen corresponding path program 1 times [2022-10-17 10:33:25,342 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:33:25,343 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1334350527] [2022-10-17 10:33:25,343 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:33:25,343 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:33:25,351 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:33:25,392 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:33:25,393 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:33:25,393 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1334350527] [2022-10-17 10:33:25,393 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1334350527] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:33:25,393 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:33:25,394 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:33:25,394 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [435179923] [2022-10-17 10:33:25,394 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:33:25,394 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:33:25,395 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:33:25,395 INFO L85 PathProgramCache]: Analyzing trace with hash 689801394, now seen corresponding path program 1 times [2022-10-17 10:33:25,395 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:33:25,395 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1516433062] [2022-10-17 10:33:25,395 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:33:25,396 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:33:25,404 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:33:25,426 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:33:25,426 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:33:25,426 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1516433062] [2022-10-17 10:33:25,426 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1516433062] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:33:25,426 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:33:25,427 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:33:25,427 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1330806032] [2022-10-17 10:33:25,427 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:33:25,427 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:33:25,428 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:33:25,428 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-10-17 10:33:25,428 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-10-17 10:33:25,428 INFO L87 Difference]: Start difference. First operand 4687 states and 6664 transitions. cyclomatic complexity: 1981 Second operand has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:33:25,557 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:33:25,557 INFO L93 Difference]: Finished difference Result 6415 states and 8953 transitions. [2022-10-17 10:33:25,558 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6415 states and 8953 transitions. [2022-10-17 10:33:25,589 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 6230 [2022-10-17 10:33:25,639 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6415 states to 6415 states and 8953 transitions. [2022-10-17 10:33:25,639 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6415 [2022-10-17 10:33:25,646 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6415 [2022-10-17 10:33:25,646 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6415 states and 8953 transitions. [2022-10-17 10:33:25,655 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:33:25,655 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6415 states and 8953 transitions. [2022-10-17 10:33:25,663 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6415 states and 8953 transitions. [2022-10-17 10:33:25,747 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6415 to 5274. [2022-10-17 10:33:25,757 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5274 states, 5274 states have (on average 1.403109594235874) internal successors, (7400), 5273 states have internal predecessors, (7400), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:33:25,771 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5274 states to 5274 states and 7400 transitions. [2022-10-17 10:33:25,771 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5274 states and 7400 transitions. [2022-10-17 10:33:25,772 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-10-17 10:33:25,773 INFO L428 stractBuchiCegarLoop]: Abstraction has 5274 states and 7400 transitions. [2022-10-17 10:33:25,773 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-10-17 10:33:25,773 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5274 states and 7400 transitions. [2022-10-17 10:33:25,792 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5140 [2022-10-17 10:33:25,792 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:33:25,792 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:33:25,794 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:33:25,794 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:33:25,794 INFO L748 eck$LassoCheckResult]: Stem: 45557#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 45521#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 45406#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 45145#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 45146#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 45201#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 45478#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 45151#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 45152#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 45274#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 45184#L514 assume !(0 == ~M_E~0); 45185#L514-2 assume !(0 == ~T1_E~0); 45500#L519-1 assume !(0 == ~T2_E~0); 45135#L524-1 assume !(0 == ~T3_E~0); 45136#L529-1 assume !(0 == ~T4_E~0); 45252#L534-1 assume !(0 == ~E_M~0); 45448#L539-1 assume 0 == ~E_1~0;~E_1~0 := 1; 45449#L544-1 assume !(0 == ~E_2~0); 45598#L549-1 assume !(0 == ~E_3~0); 45597#L554-1 assume !(0 == ~E_4~0); 45596#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 45595#L250 assume !(1 == ~m_pc~0); 45594#L250-2 is_master_triggered_~__retres1~0#1 := 0; 45593#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 45592#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 45591#L637 assume !(0 != activate_threads_~tmp~1#1); 45590#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 45166#L269 assume !(1 == ~t1_pc~0); 45167#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 45600#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 45599#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 45586#L645 assume !(0 != activate_threads_~tmp___0~0#1); 45585#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 45584#L288 assume !(1 == ~t2_pc~0); 45583#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 45582#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 45581#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 45580#L653 assume !(0 != activate_threads_~tmp___1~0#1); 45579#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 45578#L307 assume !(1 == ~t3_pc~0); 45576#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 45575#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 45574#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 45573#L661 assume !(0 != activate_threads_~tmp___2~0#1); 45572#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 45571#L326 assume !(1 == ~t4_pc~0); 45570#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 45569#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 45568#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 45567#L669 assume !(0 != activate_threads_~tmp___3~0#1); 45566#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 45565#L572 assume !(1 == ~M_E~0); 45564#L572-2 assume !(1 == ~T1_E~0); 45563#L577-1 assume !(1 == ~T2_E~0); 45562#L582-1 assume !(1 == ~T3_E~0); 45561#L587-1 assume !(1 == ~T4_E~0); 45560#L592-1 assume !(1 == ~E_M~0); 45559#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 45082#L602-1 assume !(1 == ~E_2~0); 45300#L607-1 assume !(1 == ~E_3~0); 45301#L612-1 assume !(1 == ~E_4~0); 45250#L617-1 assume { :end_inline_reset_delta_events } true; 45251#L803-2 [2022-10-17 10:33:25,795 INFO L750 eck$LassoCheckResult]: Loop: 45251#L803-2 assume !false; 49616#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 49508#L489 assume !false; 49496#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 49490#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 49478#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 49475#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 49469#L428 assume !(0 != eval_~tmp~0#1); 49470#L504 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 50265#L346-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 50264#L514-3 assume !(0 == ~M_E~0); 50263#L514-5 assume !(0 == ~T1_E~0); 50262#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 50261#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 50260#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 50259#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 50257#L539-3 assume !(0 == ~E_1~0); 50258#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 50282#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 50281#L554-3 assume !(0 == ~E_4~0); 50280#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 50279#L250-18 assume !(1 == ~m_pc~0); 50278#L250-20 is_master_triggered_~__retres1~0#1 := 0; 50277#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50276#L262-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 50275#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 50274#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 50273#L269-18 assume !(1 == ~t1_pc~0); 50256#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 50271#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50270#L281-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 50269#L645-18 assume !(0 != activate_threads_~tmp___0~0#1); 50268#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 45256#L288-18 assume !(1 == ~t2_pc~0); 45257#L288-20 is_transmit2_triggered_~__retres1~2#1 := 0; 50212#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50211#L300-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 50210#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 50206#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 50203#L307-18 assume !(1 == ~t3_pc~0); 50199#L307-20 is_transmit3_triggered_~__retres1~3#1 := 0; 50198#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50195#L319-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 50192#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 50189#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 50186#L326-18 assume !(1 == ~t4_pc~0); 50183#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 50180#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 50177#L338-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 50174#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 50171#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50168#L572-3 assume !(1 == ~M_E~0); 49017#L572-5 assume !(1 == ~T1_E~0); 50162#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 50159#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 50156#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 50152#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 50124#L597-3 assume !(1 == ~E_1~0); 50122#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 50121#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 50120#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 50118#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 50113#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 50109#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 45526#L414-1 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 45527#L822 assume !(0 == start_simulation_~tmp~3#1); 47733#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 49636#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 49634#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 49632#L414-2 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 49630#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 49628#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 49625#L785 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 49623#L835 assume !(0 != start_simulation_~tmp___0~1#1); 45251#L803-2 [2022-10-17 10:33:25,797 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:33:25,797 INFO L85 PathProgramCache]: Analyzing trace with hash -383711415, now seen corresponding path program 1 times [2022-10-17 10:33:25,797 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:33:25,797 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [793433034] [2022-10-17 10:33:25,797 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:33:25,798 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:33:25,808 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:33:25,843 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:33:25,844 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:33:25,844 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [793433034] [2022-10-17 10:33:25,844 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [793433034] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:33:25,844 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:33:25,844 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:33:25,844 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1201635672] [2022-10-17 10:33:25,844 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:33:25,845 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:33:25,846 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:33:25,846 INFO L85 PathProgramCache]: Analyzing trace with hash 1123530480, now seen corresponding path program 1 times [2022-10-17 10:33:25,846 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:33:25,846 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2028372838] [2022-10-17 10:33:25,846 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:33:25,846 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:33:25,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:33:25,899 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:33:25,900 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:33:25,900 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2028372838] [2022-10-17 10:33:25,900 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2028372838] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:33:25,900 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:33:25,900 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-10-17 10:33:25,900 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [841502001] [2022-10-17 10:33:25,901 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:33:25,901 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:33:25,901 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:33:25,902 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-10-17 10:33:25,902 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-10-17 10:33:25,902 INFO L87 Difference]: Start difference. First operand 5274 states and 7400 transitions. cyclomatic complexity: 2130 Second operand has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:33:25,992 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:33:25,992 INFO L93 Difference]: Finished difference Result 5366 states and 7487 transitions. [2022-10-17 10:33:25,992 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5366 states and 7487 transitions. [2022-10-17 10:33:26,057 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 5262 [2022-10-17 10:33:26,073 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5366 states to 5366 states and 7487 transitions. [2022-10-17 10:33:26,073 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5366 [2022-10-17 10:33:26,078 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5366 [2022-10-17 10:33:26,078 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5366 states and 7487 transitions. [2022-10-17 10:33:26,085 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:33:26,085 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5366 states and 7487 transitions. [2022-10-17 10:33:26,091 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5366 states and 7487 transitions. [2022-10-17 10:33:26,143 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5366 to 4468. [2022-10-17 10:33:26,160 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4468 states, 4468 states have (on average 1.3986123545210385) internal successors, (6249), 4467 states have internal predecessors, (6249), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:33:26,179 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4468 states to 4468 states and 6249 transitions. [2022-10-17 10:33:26,179 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4468 states and 6249 transitions. [2022-10-17 10:33:26,180 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-10-17 10:33:26,181 INFO L428 stractBuchiCegarLoop]: Abstraction has 4468 states and 6249 transitions. [2022-10-17 10:33:26,181 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-10-17 10:33:26,181 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4468 states and 6249 transitions. [2022-10-17 10:33:26,200 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4380 [2022-10-17 10:33:26,201 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:33:26,201 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:33:26,202 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:33:26,202 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:33:26,202 INFO L748 eck$LassoCheckResult]: Stem: 56214#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 56187#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 56066#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 55795#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 55796#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 55849#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 56141#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 55801#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 55802#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 55928#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 55831#L514 assume !(0 == ~M_E~0); 55832#L514-2 assume !(0 == ~T1_E~0); 56167#L519-1 assume !(0 == ~T2_E~0); 55785#L524-1 assume !(0 == ~T3_E~0); 55786#L529-1 assume !(0 == ~T4_E~0); 55903#L534-1 assume !(0 == ~E_M~0); 56112#L539-1 assume !(0 == ~E_1~0); 56113#L544-1 assume !(0 == ~E_2~0); 56139#L549-1 assume !(0 == ~E_3~0); 56140#L554-1 assume !(0 == ~E_4~0); 55780#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 55781#L250 assume !(1 == ~m_pc~0); 56008#L250-2 is_master_triggered_~__retres1~0#1 := 0; 56145#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 55969#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 55970#L637 assume !(0 != activate_threads_~tmp~1#1); 55787#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 55788#L269 assume !(1 == ~t1_pc~0); 55727#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 55898#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 55925#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 55926#L645 assume !(0 != activate_threads_~tmp___0~0#1); 55966#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 55967#L288 assume !(1 == ~t2_pc~0); 55959#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 55960#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 55981#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 55982#L653 assume !(0 != activate_threads_~tmp___1~0#1); 56105#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 55995#L307 assume !(1 == ~t3_pc~0); 55918#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 55919#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 56053#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 56150#L661 assume !(0 != activate_threads_~tmp___2~0#1); 55937#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 55938#L326 assume !(1 == ~t4_pc~0); 55740#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 55741#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 55991#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 56111#L669 assume !(0 != activate_threads_~tmp___3~0#1); 56107#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 56108#L572 assume !(1 == ~M_E~0); 56146#L572-2 assume !(1 == ~T1_E~0); 55797#L577-1 assume !(1 == ~T2_E~0); 55798#L582-1 assume !(1 == ~T3_E~0); 56094#L587-1 assume !(1 == ~T4_E~0); 56101#L592-1 assume !(1 == ~E_M~0); 55732#L597-1 assume !(1 == ~E_1~0); 55733#L602-1 assume !(1 == ~E_2~0); 55956#L607-1 assume !(1 == ~E_3~0); 55957#L612-1 assume !(1 == ~E_4~0); 55901#L617-1 assume { :end_inline_reset_delta_events } true; 55902#L803-2 [2022-10-17 10:33:26,203 INFO L750 eck$LassoCheckResult]: Loop: 55902#L803-2 assume !false; 59296#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 59293#L489 assume !false; 59290#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 59287#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 59280#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 59277#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 59272#L428 assume !(0 != eval_~tmp~0#1); 59273#L504 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 60166#L346-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 60164#L514-3 assume !(0 == ~M_E~0); 60162#L514-5 assume !(0 == ~T1_E~0); 60160#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 60159#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 60158#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 60156#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 60154#L539-3 assume !(0 == ~E_1~0); 60152#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 60150#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 60148#L554-3 assume !(0 == ~E_4~0); 56033#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 56034#L250-18 assume !(1 == ~m_pc~0); 60146#L250-20 is_master_triggered_~__retres1~0#1 := 0; 60145#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 60142#L262-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 60140#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 60138#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 60119#L269-18 assume !(1 == ~t1_pc~0); 60116#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 60114#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 60111#L281-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 60109#L645-18 assume !(0 != activate_threads_~tmp___0~0#1); 60107#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 55909#L288-18 assume !(1 == ~t2_pc~0); 55910#L288-20 is_transmit2_triggered_~__retres1~2#1 := 0; 55730#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 55731#L300-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 55826#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 60039#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 60038#L307-18 assume !(1 == ~t3_pc~0); 60036#L307-20 is_transmit3_triggered_~__retres1~3#1 := 0; 60035#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 60034#L319-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 60033#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 60032#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 60031#L326-18 assume !(1 == ~t4_pc~0); 60030#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 60029#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 60028#L338-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 60027#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 60026#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 60025#L572-3 assume !(1 == ~M_E~0); 57060#L572-5 assume !(1 == ~T1_E~0); 60024#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 55778#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 55779#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 56031#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 56032#L597-3 assume !(1 == ~E_1~0); 55944#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 55945#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 55893#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 55894#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 55951#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 55914#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 55933#L414-1 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 56193#L822 assume !(0 == start_simulation_~tmp~3#1); 59199#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 59378#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 59374#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 59364#L414-2 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 59357#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 59348#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 59339#L785 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 59331#L835 assume !(0 != start_simulation_~tmp___0~1#1); 55902#L803-2 [2022-10-17 10:33:26,203 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:33:26,203 INFO L85 PathProgramCache]: Analyzing trace with hash 1546408329, now seen corresponding path program 1 times [2022-10-17 10:33:26,203 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:33:26,203 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1241342326] [2022-10-17 10:33:26,204 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:33:26,204 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:33:26,216 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:33:26,216 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:33:26,225 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:33:26,265 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:33:26,267 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:33:26,267 INFO L85 PathProgramCache]: Analyzing trace with hash 1123530480, now seen corresponding path program 2 times [2022-10-17 10:33:26,268 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:33:26,268 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [322655858] [2022-10-17 10:33:26,268 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:33:26,268 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:33:26,282 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:33:26,329 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:33:26,329 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:33:26,329 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [322655858] [2022-10-17 10:33:26,330 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [322655858] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:33:26,330 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:33:26,330 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-10-17 10:33:26,330 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1588758746] [2022-10-17 10:33:26,331 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:33:26,331 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:33:26,331 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:33:26,331 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-10-17 10:33:26,332 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-10-17 10:33:26,332 INFO L87 Difference]: Start difference. First operand 4468 states and 6249 transitions. cyclomatic complexity: 1785 Second operand has 5 states, 5 states have (on average 14.8) internal successors, (74), 5 states have internal predecessors, (74), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:33:26,436 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:33:26,437 INFO L93 Difference]: Finished difference Result 7888 states and 10869 transitions. [2022-10-17 10:33:26,437 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7888 states and 10869 transitions. [2022-10-17 10:33:26,468 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 7776 [2022-10-17 10:33:26,545 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7888 states to 7888 states and 10869 transitions. [2022-10-17 10:33:26,545 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7888 [2022-10-17 10:33:26,550 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7888 [2022-10-17 10:33:26,551 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7888 states and 10869 transitions. [2022-10-17 10:33:26,558 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:33:26,558 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7888 states and 10869 transitions. [2022-10-17 10:33:26,567 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7888 states and 10869 transitions. [2022-10-17 10:33:26,626 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7888 to 4516. [2022-10-17 10:33:26,633 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4516 states, 4516 states have (on average 1.3943755535872453) internal successors, (6297), 4515 states have internal predecessors, (6297), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:33:26,644 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4516 states to 4516 states and 6297 transitions. [2022-10-17 10:33:26,644 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4516 states and 6297 transitions. [2022-10-17 10:33:26,645 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-10-17 10:33:26,645 INFO L428 stractBuchiCegarLoop]: Abstraction has 4516 states and 6297 transitions. [2022-10-17 10:33:26,645 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-10-17 10:33:26,646 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4516 states and 6297 transitions. [2022-10-17 10:33:26,660 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4428 [2022-10-17 10:33:26,661 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:33:26,661 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:33:26,662 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:33:26,662 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:33:26,662 INFO L748 eck$LassoCheckResult]: Stem: 68581#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 68553#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 68434#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 68166#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 68167#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 68221#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 68505#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 68172#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 68173#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 68298#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 68202#L514 assume !(0 == ~M_E~0); 68203#L514-2 assume !(0 == ~T1_E~0); 68527#L519-1 assume !(0 == ~T2_E~0); 68158#L524-1 assume !(0 == ~T3_E~0); 68159#L529-1 assume !(0 == ~T4_E~0); 68275#L534-1 assume !(0 == ~E_M~0); 68476#L539-1 assume !(0 == ~E_1~0); 68477#L544-1 assume !(0 == ~E_2~0); 68501#L549-1 assume !(0 == ~E_3~0); 68502#L554-1 assume !(0 == ~E_4~0); 68153#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 68154#L250 assume !(1 == ~m_pc~0); 68373#L250-2 is_master_triggered_~__retres1~0#1 := 0; 68508#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 68336#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 68337#L637 assume !(0 != activate_threads_~tmp~1#1); 68160#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 68161#L269 assume !(1 == ~t1_pc~0); 68099#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 68270#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 68295#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 68296#L645 assume !(0 != activate_threads_~tmp___0~0#1); 68333#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 68334#L288 assume !(1 == ~t2_pc~0); 68325#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 68326#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 68347#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 68348#L653 assume !(0 != activate_threads_~tmp___1~0#1); 68470#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 68362#L307 assume !(1 == ~t3_pc~0); 68289#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 68290#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 68424#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 68513#L661 assume !(0 != activate_threads_~tmp___2~0#1); 68306#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 68307#L326 assume !(1 == ~t4_pc~0); 68112#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 68113#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 68360#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 68475#L669 assume !(0 != activate_threads_~tmp___3~0#1); 68472#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 68473#L572 assume !(1 == ~M_E~0); 68509#L572-2 assume !(1 == ~T1_E~0); 68168#L577-1 assume !(1 == ~T2_E~0); 68169#L582-1 assume !(1 == ~T3_E~0); 68459#L587-1 assume !(1 == ~T4_E~0); 68466#L592-1 assume !(1 == ~E_M~0); 68110#L597-1 assume !(1 == ~E_1~0); 68111#L602-1 assume !(1 == ~E_2~0); 68322#L607-1 assume !(1 == ~E_3~0); 68323#L612-1 assume !(1 == ~E_4~0); 68273#L617-1 assume { :end_inline_reset_delta_events } true; 68274#L803-2 [2022-10-17 10:33:26,663 INFO L750 eck$LassoCheckResult]: Loop: 68274#L803-2 assume !false; 69704#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 69703#L489 assume !false; 69702#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 69701#L386 assume !(0 == ~m_st~0); 69698#L390 assume !(0 == ~t1_st~0); 69699#L394 assume !(0 == ~t2_st~0); 69700#L398 assume !(0 == ~t3_st~0); 69697#L402 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5#1 := 0; 69695#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 69389#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 69390#L428 assume !(0 != eval_~tmp~0#1); 69694#L504 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 69693#L346-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 69692#L514-3 assume !(0 == ~M_E~0); 69691#L514-5 assume !(0 == ~T1_E~0); 69690#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 69689#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 69688#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 69687#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 69686#L539-3 assume !(0 == ~E_1~0); 69685#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 69684#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 69683#L554-3 assume !(0 == ~E_4~0); 69682#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 69681#L250-18 assume !(1 == ~m_pc~0); 69680#L250-20 is_master_triggered_~__retres1~0#1 := 0; 69679#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 69678#L262-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 69677#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 69676#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 69675#L269-18 assume !(1 == ~t1_pc~0); 69673#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 69672#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 69671#L281-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 69670#L645-18 assume !(0 != activate_threads_~tmp___0~0#1); 69669#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 69668#L288-18 assume !(1 == ~t2_pc~0); 69020#L288-20 is_transmit2_triggered_~__retres1~2#1 := 0; 69667#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 69666#L300-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 69665#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 69664#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 69663#L307-18 assume !(1 == ~t3_pc~0); 69661#L307-20 is_transmit3_triggered_~__retres1~3#1 := 0; 69660#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 69659#L319-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 69658#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 69657#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 69656#L326-18 assume !(1 == ~t4_pc~0); 69655#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 69654#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 69653#L338-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 69652#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 69651#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 69650#L572-3 assume !(1 == ~M_E~0); 69524#L572-5 assume !(1 == ~T1_E~0); 69649#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 69648#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 69647#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 69646#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 69645#L597-3 assume !(1 == ~E_1~0); 69644#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 69643#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 69642#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 69641#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 69639#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 69635#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 69634#L414-1 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 69632#L822 assume !(0 == start_simulation_~tmp~3#1); 69633#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 69725#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 69723#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 69721#L414-2 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 69719#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 69715#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 69713#L785 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 69711#L835 assume !(0 != start_simulation_~tmp___0~1#1); 68274#L803-2 [2022-10-17 10:33:26,663 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:33:26,664 INFO L85 PathProgramCache]: Analyzing trace with hash 1546408329, now seen corresponding path program 2 times [2022-10-17 10:33:26,664 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:33:26,664 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1021794754] [2022-10-17 10:33:26,664 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:33:26,664 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:33:26,673 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:33:26,673 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:33:26,683 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:33:26,710 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:33:26,710 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:33:26,711 INFO L85 PathProgramCache]: Analyzing trace with hash 11694820, now seen corresponding path program 1 times [2022-10-17 10:33:26,711 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:33:26,711 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [771933270] [2022-10-17 10:33:26,712 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:33:26,712 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:33:26,728 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:33:26,815 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:33:26,815 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:33:26,816 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [771933270] [2022-10-17 10:33:26,816 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [771933270] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:33:26,816 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:33:26,816 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-10-17 10:33:26,816 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [645886719] [2022-10-17 10:33:26,817 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:33:26,817 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:33:26,817 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:33:26,817 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-10-17 10:33:26,818 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-10-17 10:33:26,818 INFO L87 Difference]: Start difference. First operand 4516 states and 6297 transitions. cyclomatic complexity: 1785 Second operand has 5 states, 5 states have (on average 15.6) internal successors, (78), 5 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:33:27,042 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:33:27,042 INFO L93 Difference]: Finished difference Result 8960 states and 12392 transitions. [2022-10-17 10:33:27,043 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8960 states and 12392 transitions. [2022-10-17 10:33:27,090 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 8856 [2022-10-17 10:33:27,123 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8960 states to 8960 states and 12392 transitions. [2022-10-17 10:33:27,124 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8960 [2022-10-17 10:33:27,132 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8960 [2022-10-17 10:33:27,133 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8960 states and 12392 transitions. [2022-10-17 10:33:27,140 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:33:27,141 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8960 states and 12392 transitions. [2022-10-17 10:33:27,151 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8960 states and 12392 transitions. [2022-10-17 10:33:27,233 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8960 to 4648. [2022-10-17 10:33:27,241 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4648 states, 4648 states have (on average 1.3752151462994837) internal successors, (6392), 4647 states have internal predecessors, (6392), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:33:27,256 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4648 states to 4648 states and 6392 transitions. [2022-10-17 10:33:27,256 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4648 states and 6392 transitions. [2022-10-17 10:33:27,256 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-10-17 10:33:27,257 INFO L428 stractBuchiCegarLoop]: Abstraction has 4648 states and 6392 transitions. [2022-10-17 10:33:27,257 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-10-17 10:33:27,257 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4648 states and 6392 transitions. [2022-10-17 10:33:27,278 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4560 [2022-10-17 10:33:27,279 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:33:27,279 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:33:27,280 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:33:27,281 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:33:27,281 INFO L748 eck$LassoCheckResult]: Stem: 82089#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 82050#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 81930#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 81655#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 81656#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 81710#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 82001#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 81661#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 81662#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 81786#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 81692#L514 assume !(0 == ~M_E~0); 81693#L514-2 assume !(0 == ~T1_E~0); 82029#L519-1 assume !(0 == ~T2_E~0); 81647#L524-1 assume !(0 == ~T3_E~0); 81648#L529-1 assume !(0 == ~T4_E~0); 81763#L534-1 assume !(0 == ~E_M~0); 81975#L539-1 assume !(0 == ~E_1~0); 81976#L544-1 assume !(0 == ~E_2~0); 81999#L549-1 assume !(0 == ~E_3~0); 82000#L554-1 assume !(0 == ~E_4~0); 81642#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 81643#L250 assume !(1 == ~m_pc~0); 81866#L250-2 is_master_triggered_~__retres1~0#1 := 0; 82006#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 81826#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 81827#L637 assume !(0 != activate_threads_~tmp~1#1); 81649#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 81650#L269 assume !(1 == ~t1_pc~0); 81588#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 81758#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 81783#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 81784#L645 assume !(0 != activate_threads_~tmp___0~0#1); 81823#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 81824#L288 assume !(1 == ~t2_pc~0); 81817#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 81818#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 81840#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 81841#L653 assume !(0 != activate_threads_~tmp___1~0#1); 81969#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 81854#L307 assume !(1 == ~t3_pc~0); 81776#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 81777#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 81916#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 82011#L661 assume !(0 != activate_threads_~tmp___2~0#1); 81796#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 81797#L326 assume !(1 == ~t4_pc~0); 81601#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 81602#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 81850#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 81974#L669 assume !(0 != activate_threads_~tmp___3~0#1); 81971#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 81972#L572 assume !(1 == ~M_E~0); 82007#L572-2 assume !(1 == ~T1_E~0); 81657#L577-1 assume !(1 == ~T2_E~0); 81658#L582-1 assume !(1 == ~T3_E~0); 81958#L587-1 assume !(1 == ~T4_E~0); 81965#L592-1 assume !(1 == ~E_M~0); 81593#L597-1 assume !(1 == ~E_1~0); 81594#L602-1 assume !(1 == ~E_2~0); 81814#L607-1 assume !(1 == ~E_3~0); 81815#L612-1 assume !(1 == ~E_4~0); 81761#L617-1 assume { :end_inline_reset_delta_events } true; 81762#L803-2 [2022-10-17 10:33:27,282 INFO L750 eck$LassoCheckResult]: Loop: 81762#L803-2 assume !false; 83210#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 83209#L489 assume !false; 83208#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 83207#L386 assume !(0 == ~m_st~0); 83204#L390 assume !(0 == ~t1_st~0); 83205#L394 assume !(0 == ~t2_st~0); 83206#L398 assume !(0 == ~t3_st~0); 83203#L402 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5#1 := 0; 83202#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 82961#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 82962#L428 assume !(0 != eval_~tmp~0#1); 83201#L504 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 83200#L346-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 83199#L514-3 assume !(0 == ~M_E~0); 83198#L514-5 assume !(0 == ~T1_E~0); 83197#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 83196#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 83195#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 83194#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 83193#L539-3 assume !(0 == ~E_1~0); 83192#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 83191#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 83190#L554-3 assume !(0 == ~E_4~0); 83189#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 83188#L250-18 assume !(1 == ~m_pc~0); 83187#L250-20 is_master_triggered_~__retres1~0#1 := 0; 83186#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 83185#L262-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 83184#L637-18 assume !(0 != activate_threads_~tmp~1#1); 83183#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 83182#L269-18 assume !(1 == ~t1_pc~0); 83180#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 83179#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 83178#L281-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 83177#L645-18 assume !(0 != activate_threads_~tmp___0~0#1); 83176#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 83175#L288-18 assume !(1 == ~t2_pc~0); 82680#L288-20 is_transmit2_triggered_~__retres1~2#1 := 0; 83174#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 83173#L300-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 83172#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 83171#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 83170#L307-18 assume 1 == ~t3_pc~0; 83169#L308-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 83167#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 83166#L319-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 83165#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 83164#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 83163#L326-18 assume !(1 == ~t4_pc~0); 83162#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 83161#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 83160#L338-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 83159#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 83157#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 83155#L572-3 assume !(1 == ~M_E~0); 83055#L572-5 assume !(1 == ~T1_E~0); 83152#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 83150#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 83148#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 83146#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 83144#L597-3 assume !(1 == ~E_1~0); 83142#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 83140#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 83138#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 83136#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 83133#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 83128#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 83126#L414-1 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 83123#L822 assume !(0 == start_simulation_~tmp~3#1); 83124#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 83231#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 83229#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 83227#L414-2 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 83225#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 83221#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 83219#L785 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 83217#L835 assume !(0 != start_simulation_~tmp___0~1#1); 81762#L803-2 [2022-10-17 10:33:27,282 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:33:27,282 INFO L85 PathProgramCache]: Analyzing trace with hash 1546408329, now seen corresponding path program 3 times [2022-10-17 10:33:27,283 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:33:27,283 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [574037814] [2022-10-17 10:33:27,283 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:33:27,283 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:33:27,294 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:33:27,294 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:33:27,301 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:33:27,314 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:33:27,315 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:33:27,315 INFO L85 PathProgramCache]: Analyzing trace with hash -1055272987, now seen corresponding path program 1 times [2022-10-17 10:33:27,315 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:33:27,315 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [359729264] [2022-10-17 10:33:27,315 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:33:27,316 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:33:27,326 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:33:27,356 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:33:27,356 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:33:27,357 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [359729264] [2022-10-17 10:33:27,357 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [359729264] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:33:27,357 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:33:27,357 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:33:27,357 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [808022844] [2022-10-17 10:33:27,358 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:33:27,358 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:33:27,358 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:33:27,359 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:33:27,359 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:33:27,359 INFO L87 Difference]: Start difference. First operand 4648 states and 6392 transitions. cyclomatic complexity: 1748 Second operand has 3 states, 3 states have (on average 26.0) internal successors, (78), 3 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:33:27,423 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:33:27,424 INFO L93 Difference]: Finished difference Result 7304 states and 9896 transitions. [2022-10-17 10:33:27,424 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7304 states and 9896 transitions. [2022-10-17 10:33:27,465 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 7206 [2022-10-17 10:33:27,494 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7304 states to 7304 states and 9896 transitions. [2022-10-17 10:33:27,495 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7304 [2022-10-17 10:33:27,502 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7304 [2022-10-17 10:33:27,502 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7304 states and 9896 transitions. [2022-10-17 10:33:27,509 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:33:27,509 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7304 states and 9896 transitions. [2022-10-17 10:33:27,519 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7304 states and 9896 transitions. [2022-10-17 10:33:27,682 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7304 to 7048. [2022-10-17 10:33:27,692 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7048 states, 7048 states have (on average 1.3564131668558457) internal successors, (9560), 7047 states have internal predecessors, (9560), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:33:27,709 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7048 states to 7048 states and 9560 transitions. [2022-10-17 10:33:27,709 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7048 states and 9560 transitions. [2022-10-17 10:33:27,710 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:33:27,710 INFO L428 stractBuchiCegarLoop]: Abstraction has 7048 states and 9560 transitions. [2022-10-17 10:33:27,711 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-10-17 10:33:27,711 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7048 states and 9560 transitions. [2022-10-17 10:33:27,738 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 6950 [2022-10-17 10:33:27,738 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:33:27,738 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:33:27,739 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:33:27,739 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:33:27,740 INFO L748 eck$LassoCheckResult]: Stem: 94021#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 93991#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 93874#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 93613#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 93614#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 93669#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 93942#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 93619#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 93620#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 93743#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 93649#L514 assume !(0 == ~M_E~0); 93650#L514-2 assume !(0 == ~T1_E~0); 93967#L519-1 assume !(0 == ~T2_E~0); 93605#L524-1 assume !(0 == ~T3_E~0); 93606#L529-1 assume !(0 == ~T4_E~0); 93721#L534-1 assume !(0 == ~E_M~0); 93919#L539-1 assume !(0 == ~E_1~0); 93920#L544-1 assume !(0 == ~E_2~0); 93940#L549-1 assume !(0 == ~E_3~0); 93941#L554-1 assume !(0 == ~E_4~0); 93600#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 93601#L250 assume !(1 == ~m_pc~0); 93815#L250-2 is_master_triggered_~__retres1~0#1 := 0; 93947#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 93780#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 93781#L637 assume !(0 != activate_threads_~tmp~1#1); 93607#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 93608#L269 assume !(1 == ~t1_pc~0); 93546#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 93716#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 93740#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 93741#L645 assume !(0 != activate_threads_~tmp___0~0#1); 93777#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 93778#L288 assume !(1 == ~t2_pc~0); 93772#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 93773#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 93791#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 93792#L653 assume !(0 != activate_threads_~tmp___1~0#1); 93913#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 93804#L307 assume !(1 == ~t3_pc~0); 93734#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 93735#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 93861#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 93952#L661 assume !(0 != activate_threads_~tmp___2~0#1); 93752#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 93753#L326 assume !(1 == ~t4_pc~0); 93559#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 93560#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 93800#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 93918#L669 assume !(0 != activate_threads_~tmp___3~0#1); 93915#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 93916#L572 assume !(1 == ~M_E~0); 93948#L572-2 assume !(1 == ~T1_E~0); 93615#L577-1 assume !(1 == ~T2_E~0); 93616#L582-1 assume !(1 == ~T3_E~0); 93902#L587-1 assume !(1 == ~T4_E~0); 93909#L592-1 assume !(1 == ~E_M~0); 93551#L597-1 assume !(1 == ~E_1~0); 93552#L602-1 assume !(1 == ~E_2~0); 93769#L607-1 assume !(1 == ~E_3~0); 93770#L612-1 assume !(1 == ~E_4~0); 93719#L617-1 assume { :end_inline_reset_delta_events } true; 93720#L803-2 assume !false; 94856#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 94820#L489 [2022-10-17 10:33:27,740 INFO L750 eck$LassoCheckResult]: Loop: 94820#L489 assume !false; 94821#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 95009#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 95007#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 95005#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 94987#L428 assume 0 != eval_~tmp~0#1; 94980#L428-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 94973#L436 assume !(0 != eval_~tmp_ndt_1~0#1); 94897#L433 assume !(0 == ~t1_st~0); 94865#L447 assume !(0 == ~t2_st~0); 94855#L461 assume !(0 == ~t3_st~0); 94859#L475 assume !(0 == ~t4_st~0); 94820#L489 [2022-10-17 10:33:27,740 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:33:27,740 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 1 times [2022-10-17 10:33:27,741 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:33:27,741 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [698788788] [2022-10-17 10:33:27,741 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:33:27,741 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:33:27,750 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:33:27,750 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:33:27,756 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:33:27,768 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:33:27,768 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:33:27,768 INFO L85 PathProgramCache]: Analyzing trace with hash 1577382650, now seen corresponding path program 1 times [2022-10-17 10:33:27,769 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:33:27,769 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2053646227] [2022-10-17 10:33:27,769 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:33:27,769 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:33:27,772 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:33:27,772 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:33:27,774 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:33:27,776 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:33:27,777 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:33:27,777 INFO L85 PathProgramCache]: Analyzing trace with hash 189250340, now seen corresponding path program 1 times [2022-10-17 10:33:27,777 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:33:27,777 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2095414712] [2022-10-17 10:33:27,778 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:33:27,778 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:33:27,787 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:33:27,817 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:33:27,818 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:33:27,818 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2095414712] [2022-10-17 10:33:27,818 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2095414712] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:33:27,818 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:33:27,818 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:33:27,819 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [876934056] [2022-10-17 10:33:27,819 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:33:27,910 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:33:27,910 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:33:27,910 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:33:27,910 INFO L87 Difference]: Start difference. First operand 7048 states and 9560 transitions. cyclomatic complexity: 2518 Second operand has 3 states, 3 states have (on average 25.333333333333332) internal successors, (76), 3 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:33:27,972 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:33:27,972 INFO L93 Difference]: Finished difference Result 11326 states and 15229 transitions. [2022-10-17 10:33:27,972 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11326 states and 15229 transitions. [2022-10-17 10:33:28,018 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 11136 [2022-10-17 10:33:28,149 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11326 states to 11326 states and 15229 transitions. [2022-10-17 10:33:28,149 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11326 [2022-10-17 10:33:28,164 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11326 [2022-10-17 10:33:28,164 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11326 states and 15229 transitions. [2022-10-17 10:33:28,173 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:33:28,173 INFO L218 hiAutomatonCegarLoop]: Abstraction has 11326 states and 15229 transitions. [2022-10-17 10:33:28,184 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11326 states and 15229 transitions. [2022-10-17 10:33:28,292 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11326 to 11326. [2022-10-17 10:33:28,308 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11326 states, 11326 states have (on average 1.3446053328624403) internal successors, (15229), 11325 states have internal predecessors, (15229), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:33:28,336 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11326 states to 11326 states and 15229 transitions. [2022-10-17 10:33:28,336 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11326 states and 15229 transitions. [2022-10-17 10:33:28,336 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:33:28,337 INFO L428 stractBuchiCegarLoop]: Abstraction has 11326 states and 15229 transitions. [2022-10-17 10:33:28,337 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2022-10-17 10:33:28,337 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11326 states and 15229 transitions. [2022-10-17 10:33:28,371 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 11136 [2022-10-17 10:33:28,372 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:33:28,372 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:33:28,372 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:33:28,373 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:33:28,373 INFO L748 eck$LassoCheckResult]: Stem: 112459#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 112424#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 112275#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 111997#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 111998#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 112054#L353-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 112352#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 112003#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 112004#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 112133#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 112134#L514 assume !(0 == ~M_E~0); 112434#L514-2 assume !(0 == ~T1_E~0); 112435#L519-1 assume !(0 == ~T2_E~0); 111987#L524-1 assume !(0 == ~T3_E~0); 111988#L529-1 assume !(0 == ~T4_E~0); 112392#L534-1 assume !(0 == ~E_M~0); 112393#L539-1 assume !(0 == ~E_1~0); 112348#L544-1 assume !(0 == ~E_2~0); 112349#L549-1 assume !(0 == ~E_3~0); 112397#L554-1 assume !(0 == ~E_4~0); 112398#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 112213#L250 assume !(1 == ~m_pc~0); 112214#L250-2 is_master_triggered_~__retres1~0#1 := 0; 112388#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 112389#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 112356#L637 assume !(0 != activate_threads_~tmp~1#1); 112357#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 112018#L269 assume !(1 == ~t1_pc~0); 111928#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 112222#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 112223#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 112390#L645 assume !(0 != activate_threads_~tmp___0~0#1); 112391#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 112292#L288 assume !(1 == ~t2_pc~0); 112293#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 112307#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 112308#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 112316#L653 assume !(0 != activate_threads_~tmp___1~0#1); 112317#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 112199#L307 assume !(1 == ~t3_pc~0); 112200#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 112258#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 112259#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 112366#L661 assume !(0 != activate_threads_~tmp___2~0#1); 112367#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 112416#L326 assume !(1 == ~t4_pc~0); 112417#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 112194#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 112195#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 112368#L669 assume !(0 != activate_threads_~tmp___3~0#1); 112369#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 112362#L572 assume !(1 == ~M_E~0); 112363#L572-2 assume !(1 == ~T1_E~0); 112894#L577-1 assume !(1 == ~T2_E~0); 112893#L582-1 assume !(1 == ~T3_E~0); 112311#L587-1 assume !(1 == ~T4_E~0); 112312#L592-1 assume !(1 == ~E_M~0); 111933#L597-1 assume !(1 == ~E_1~0); 111934#L602-1 assume !(1 == ~E_2~0); 112870#L607-1 assume !(1 == ~E_3~0); 112453#L612-1 assume !(1 == ~E_4~0); 112454#L617-1 assume { :end_inline_reset_delta_events } true; 112855#L803-2 assume !false; 112847#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 112843#L489 [2022-10-17 10:33:28,373 INFO L750 eck$LassoCheckResult]: Loop: 112843#L489 assume !false; 112839#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 112834#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 112828#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 112825#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 112817#L428 assume 0 != eval_~tmp~0#1; 112810#L428-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 112804#L436 assume !(0 != eval_~tmp_ndt_1~0#1); 112798#L433 assume !(0 == ~t1_st~0); 112793#L447 assume !(0 == ~t2_st~0); 112788#L461 assume !(0 == ~t3_st~0); 112850#L475 assume !(0 == ~t4_st~0); 112843#L489 [2022-10-17 10:33:28,374 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:33:28,374 INFO L85 PathProgramCache]: Analyzing trace with hash 600428717, now seen corresponding path program 1 times [2022-10-17 10:33:28,374 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:33:28,374 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1106816685] [2022-10-17 10:33:28,374 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:33:28,375 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:33:28,385 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:33:28,402 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:33:28,402 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:33:28,402 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1106816685] [2022-10-17 10:33:28,402 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1106816685] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:33:28,402 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:33:28,403 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:33:28,403 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1798589483] [2022-10-17 10:33:28,403 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:33:28,404 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:33:28,404 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:33:28,404 INFO L85 PathProgramCache]: Analyzing trace with hash 1577382650, now seen corresponding path program 2 times [2022-10-17 10:33:28,404 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:33:28,404 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1034131544] [2022-10-17 10:33:28,405 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:33:28,405 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:33:28,409 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:33:28,410 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:33:28,412 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:33:28,415 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:33:28,496 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:33:28,496 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:33:28,496 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:33:28,497 INFO L87 Difference]: Start difference. First operand 11326 states and 15229 transitions. cyclomatic complexity: 3909 Second operand has 3 states, 3 states have (on average 21.333333333333332) internal successors, (64), 3 states have internal predecessors, (64), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:33:28,617 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:33:28,620 INFO L93 Difference]: Finished difference Result 11266 states and 15149 transitions. [2022-10-17 10:33:28,621 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11266 states and 15149 transitions. [2022-10-17 10:33:28,666 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 11136 [2022-10-17 10:33:28,701 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11266 states to 11266 states and 15149 transitions. [2022-10-17 10:33:28,702 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11266 [2022-10-17 10:33:28,708 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11266 [2022-10-17 10:33:28,708 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11266 states and 15149 transitions. [2022-10-17 10:33:28,715 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:33:28,716 INFO L218 hiAutomatonCegarLoop]: Abstraction has 11266 states and 15149 transitions. [2022-10-17 10:33:28,725 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11266 states and 15149 transitions. [2022-10-17 10:33:28,829 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11266 to 11266. [2022-10-17 10:33:28,845 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11266 states, 11266 states have (on average 1.3446653648144862) internal successors, (15149), 11265 states have internal predecessors, (15149), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:33:28,978 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11266 states to 11266 states and 15149 transitions. [2022-10-17 10:33:28,993 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11266 states and 15149 transitions. [2022-10-17 10:33:28,993 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:33:28,994 INFO L428 stractBuchiCegarLoop]: Abstraction has 11266 states and 15149 transitions. [2022-10-17 10:33:28,994 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2022-10-17 10:33:28,994 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11266 states and 15149 transitions. [2022-10-17 10:33:29,030 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 11136 [2022-10-17 10:33:29,030 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:33:29,030 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:33:29,031 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:33:29,031 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:33:29,032 INFO L748 eck$LassoCheckResult]: Stem: 135010#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 134980#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 134863#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 134593#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 134594#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 134648#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 134935#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 134599#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 134600#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 134727#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 134629#L514 assume !(0 == ~M_E~0); 134630#L514-2 assume !(0 == ~T1_E~0); 134954#L519-1 assume !(0 == ~T2_E~0); 134585#L524-1 assume !(0 == ~T3_E~0); 134586#L529-1 assume !(0 == ~T4_E~0); 134703#L534-1 assume !(0 == ~E_M~0); 134909#L539-1 assume !(0 == ~E_1~0); 134910#L544-1 assume !(0 == ~E_2~0); 134932#L549-1 assume !(0 == ~E_3~0); 134933#L554-1 assume !(0 == ~E_4~0); 134580#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 134581#L250 assume !(1 == ~m_pc~0); 134804#L250-2 is_master_triggered_~__retres1~0#1 := 0; 134938#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 134768#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 134769#L637 assume !(0 != activate_threads_~tmp~1#1); 134587#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 134588#L269 assume !(1 == ~t1_pc~0); 134526#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 134698#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 134724#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 134725#L645 assume !(0 != activate_threads_~tmp___0~0#1); 134765#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 134766#L288 assume !(1 == ~t2_pc~0); 134757#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 134758#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 134779#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 134780#L653 assume !(0 != activate_threads_~tmp___1~0#1); 134903#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 134792#L307 assume !(1 == ~t3_pc~0); 134717#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 134718#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 134855#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 134942#L661 assume !(0 != activate_threads_~tmp___2~0#1); 134736#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 134737#L326 assume !(1 == ~t4_pc~0); 134539#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 134540#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 134791#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 134908#L669 assume !(0 != activate_threads_~tmp___3~0#1); 134905#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 134906#L572 assume !(1 == ~M_E~0); 134939#L572-2 assume !(1 == ~T1_E~0); 134595#L577-1 assume !(1 == ~T2_E~0); 134596#L582-1 assume !(1 == ~T3_E~0); 134892#L587-1 assume !(1 == ~T4_E~0); 134899#L592-1 assume !(1 == ~E_M~0); 134537#L597-1 assume !(1 == ~E_1~0); 134538#L602-1 assume !(1 == ~E_2~0); 134754#L607-1 assume !(1 == ~E_3~0); 134755#L612-1 assume !(1 == ~E_4~0); 134701#L617-1 assume { :end_inline_reset_delta_events } true; 134702#L803-2 assume !false; 135395#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 135392#L489 [2022-10-17 10:33:29,032 INFO L750 eck$LassoCheckResult]: Loop: 135392#L489 assume !false; 135389#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 135383#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 135377#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 135373#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 135369#L428 assume 0 != eval_~tmp~0#1; 135363#L428-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 135356#L436 assume !(0 != eval_~tmp_ndt_1~0#1); 135348#L433 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 135334#L450 assume !(0 != eval_~tmp_ndt_2~0#1); 135336#L447 assume !(0 == ~t2_st~0); 135330#L461 assume !(0 == ~t3_st~0); 135398#L475 assume !(0 == ~t4_st~0); 135392#L489 [2022-10-17 10:33:29,032 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:33:29,032 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 2 times [2022-10-17 10:33:29,033 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:33:29,033 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [727679079] [2022-10-17 10:33:29,033 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:33:29,033 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:33:29,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:33:29,043 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:33:29,050 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:33:29,063 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:33:29,065 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:33:29,065 INFO L85 PathProgramCache]: Analyzing trace with hash 1507047706, now seen corresponding path program 1 times [2022-10-17 10:33:29,065 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:33:29,065 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1534101722] [2022-10-17 10:33:29,065 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:33:29,066 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:33:29,069 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:33:29,069 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:33:29,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:33:29,073 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:33:29,073 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:33:29,073 INFO L85 PathProgramCache]: Analyzing trace with hash 1424619056, now seen corresponding path program 1 times [2022-10-17 10:33:29,074 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:33:29,074 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [207151603] [2022-10-17 10:33:29,074 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:33:29,074 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:33:29,087 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:33:29,119 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:33:29,120 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:33:29,120 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [207151603] [2022-10-17 10:33:29,120 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [207151603] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:33:29,120 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:33:29,120 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:33:29,121 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1773286298] [2022-10-17 10:33:29,121 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:33:29,232 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:33:29,232 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:33:29,232 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:33:29,233 INFO L87 Difference]: Start difference. First operand 11266 states and 15149 transitions. cyclomatic complexity: 3889 Second operand has 3 states, 3 states have (on average 25.666666666666668) internal successors, (77), 3 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:33:29,343 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:33:29,343 INFO L93 Difference]: Finished difference Result 20858 states and 27889 transitions. [2022-10-17 10:33:29,343 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 20858 states and 27889 transitions. [2022-10-17 10:33:29,445 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 20664 [2022-10-17 10:33:29,672 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 20858 states to 20858 states and 27889 transitions. [2022-10-17 10:33:29,673 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 20858 [2022-10-17 10:33:29,682 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 20858 [2022-10-17 10:33:29,683 INFO L73 IsDeterministic]: Start isDeterministic. Operand 20858 states and 27889 transitions. [2022-10-17 10:33:29,694 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:33:29,694 INFO L218 hiAutomatonCegarLoop]: Abstraction has 20858 states and 27889 transitions. [2022-10-17 10:33:29,706 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20858 states and 27889 transitions. [2022-10-17 10:33:29,865 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20858 to 20368. [2022-10-17 10:33:29,884 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20368 states, 20368 states have (on average 1.3383248232521603) internal successors, (27259), 20367 states have internal predecessors, (27259), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:33:29,931 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20368 states to 20368 states and 27259 transitions. [2022-10-17 10:33:29,932 INFO L240 hiAutomatonCegarLoop]: Abstraction has 20368 states and 27259 transitions. [2022-10-17 10:33:29,932 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:33:29,933 INFO L428 stractBuchiCegarLoop]: Abstraction has 20368 states and 27259 transitions. [2022-10-17 10:33:29,933 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2022-10-17 10:33:29,933 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 20368 states and 27259 transitions. [2022-10-17 10:33:30,108 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 20174 [2022-10-17 10:33:30,108 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:33:30,108 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:33:30,109 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:33:30,109 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:33:30,110 INFO L748 eck$LassoCheckResult]: Stem: 167139#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 167114#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 166993#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 166725#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 166726#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 166781#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 167066#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 166731#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 166732#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 166859#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 166761#L514 assume !(0 == ~M_E~0); 166762#L514-2 assume !(0 == ~T1_E~0); 167089#L519-1 assume !(0 == ~T2_E~0); 166717#L524-1 assume !(0 == ~T3_E~0); 166718#L529-1 assume !(0 == ~T4_E~0); 166836#L534-1 assume !(0 == ~E_M~0); 167036#L539-1 assume !(0 == ~E_1~0); 167037#L544-1 assume !(0 == ~E_2~0); 167064#L549-1 assume !(0 == ~E_3~0); 167065#L554-1 assume !(0 == ~E_4~0); 166712#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 166713#L250 assume !(1 == ~m_pc~0); 166936#L250-2 is_master_triggered_~__retres1~0#1 := 0; 167070#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 166899#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 166900#L637 assume !(0 != activate_threads_~tmp~1#1); 166719#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 166720#L269 assume !(1 == ~t1_pc~0); 166658#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 166831#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 166856#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 166857#L645 assume !(0 != activate_threads_~tmp___0~0#1); 166896#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 166897#L288 assume !(1 == ~t2_pc~0); 166889#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 166890#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 166910#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 166911#L653 assume !(0 != activate_threads_~tmp___1~0#1); 167031#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 166923#L307 assume !(1 == ~t3_pc~0); 166849#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 166850#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 166980#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 167074#L661 assume !(0 != activate_threads_~tmp___2~0#1); 166869#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 166870#L326 assume !(1 == ~t4_pc~0); 166671#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 166672#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 166922#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 167035#L669 assume !(0 != activate_threads_~tmp___3~0#1); 167032#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 167033#L572 assume !(1 == ~M_E~0); 167071#L572-2 assume !(1 == ~T1_E~0); 166727#L577-1 assume !(1 == ~T2_E~0); 166728#L582-1 assume !(1 == ~T3_E~0); 167021#L587-1 assume !(1 == ~T4_E~0); 167027#L592-1 assume !(1 == ~E_M~0); 166663#L597-1 assume !(1 == ~E_1~0); 166664#L602-1 assume !(1 == ~E_2~0); 166886#L607-1 assume !(1 == ~E_3~0); 166887#L612-1 assume !(1 == ~E_4~0); 166834#L617-1 assume { :end_inline_reset_delta_events } true; 166835#L803-2 assume !false; 180150#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 178143#L489 [2022-10-17 10:33:30,110 INFO L750 eck$LassoCheckResult]: Loop: 178143#L489 assume !false; 180145#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 180142#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 180139#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 180137#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 180135#L428 assume 0 != eval_~tmp~0#1; 180132#L428-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 180129#L436 assume !(0 != eval_~tmp_ndt_1~0#1); 180126#L433 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 178097#L450 assume !(0 != eval_~tmp_ndt_2~0#1); 176013#L447 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 176009#L464 assume !(0 != eval_~tmp_ndt_3~0#1); 176011#L461 assume !(0 == ~t3_st~0); 178145#L475 assume !(0 == ~t4_st~0); 178143#L489 [2022-10-17 10:33:30,110 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:33:30,110 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 3 times [2022-10-17 10:33:30,111 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:33:30,111 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1744584339] [2022-10-17 10:33:30,111 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:33:30,111 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:33:30,122 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:33:30,122 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:33:30,129 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:33:30,148 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:33:30,149 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:33:30,149 INFO L85 PathProgramCache]: Analyzing trace with hash -530907670, now seen corresponding path program 1 times [2022-10-17 10:33:30,149 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:33:30,149 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [434629325] [2022-10-17 10:33:30,149 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:33:30,149 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:33:30,157 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:33:30,158 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:33:30,160 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:33:30,162 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:33:30,163 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:33:30,163 INFO L85 PathProgramCache]: Analyzing trace with hash 1208771476, now seen corresponding path program 1 times [2022-10-17 10:33:30,163 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:33:30,163 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1316345863] [2022-10-17 10:33:30,163 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:33:30,164 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:33:30,173 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:33:30,202 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:33:30,203 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:33:30,203 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1316345863] [2022-10-17 10:33:30,203 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1316345863] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:33:30,203 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:33:30,203 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:33:30,204 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1814382368] [2022-10-17 10:33:30,204 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:33:30,329 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:33:30,330 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:33:30,330 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:33:30,330 INFO L87 Difference]: Start difference. First operand 20368 states and 27259 transitions. cyclomatic complexity: 6897 Second operand has 3 states, 3 states have (on average 26.0) internal successors, (78), 3 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:33:30,459 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:33:30,459 INFO L93 Difference]: Finished difference Result 35922 states and 47917 transitions. [2022-10-17 10:33:30,460 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 35922 states and 47917 transitions. [2022-10-17 10:33:30,830 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 35600 [2022-10-17 10:33:31,039 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 35922 states to 35922 states and 47917 transitions. [2022-10-17 10:33:31,039 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 35922 [2022-10-17 10:33:31,060 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 35922 [2022-10-17 10:33:31,060 INFO L73 IsDeterministic]: Start isDeterministic. Operand 35922 states and 47917 transitions. [2022-10-17 10:33:31,085 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:33:31,085 INFO L218 hiAutomatonCegarLoop]: Abstraction has 35922 states and 47917 transitions. [2022-10-17 10:33:31,110 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 35922 states and 47917 transitions. [2022-10-17 10:33:31,469 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 35922 to 34746. [2022-10-17 10:33:31,501 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 34746 states, 34746 states have (on average 1.3387728083808208) internal successors, (46517), 34745 states have internal predecessors, (46517), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:33:31,760 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34746 states to 34746 states and 46517 transitions. [2022-10-17 10:33:31,760 INFO L240 hiAutomatonCegarLoop]: Abstraction has 34746 states and 46517 transitions. [2022-10-17 10:33:31,760 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:33:31,761 INFO L428 stractBuchiCegarLoop]: Abstraction has 34746 states and 46517 transitions. [2022-10-17 10:33:31,761 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2022-10-17 10:33:31,761 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 34746 states and 46517 transitions. [2022-10-17 10:33:31,907 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 34424 [2022-10-17 10:33:31,907 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:33:31,907 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:33:31,908 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:33:31,908 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:33:31,908 INFO L748 eck$LassoCheckResult]: Stem: 223467#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 223437#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 223299#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 223022#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 223023#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 223081#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 223383#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 223028#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 223029#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 223159#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 223060#L514 assume !(0 == ~M_E~0); 223061#L514-2 assume !(0 == ~T1_E~0); 223408#L519-1 assume !(0 == ~T2_E~0); 223014#L524-1 assume !(0 == ~T3_E~0); 223015#L529-1 assume !(0 == ~T4_E~0); 223136#L534-1 assume !(0 == ~E_M~0); 223353#L539-1 assume !(0 == ~E_1~0); 223354#L544-1 assume !(0 == ~E_2~0); 223379#L549-1 assume !(0 == ~E_3~0); 223380#L554-1 assume !(0 == ~E_4~0); 223009#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 223010#L250 assume !(1 == ~m_pc~0); 223240#L250-2 is_master_triggered_~__retres1~0#1 := 0; 223386#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 223197#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 223198#L637 assume !(0 != activate_threads_~tmp~1#1); 223016#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 223017#L269 assume !(1 == ~t1_pc~0); 222955#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 223131#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 223155#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 223156#L645 assume !(0 != activate_threads_~tmp___0~0#1); 223194#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 223195#L288 assume !(1 == ~t2_pc~0); 223189#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 223190#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 223209#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 223210#L653 assume !(0 != activate_threads_~tmp___1~0#1); 223346#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 223223#L307 assume !(1 == ~t3_pc~0); 223149#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 223150#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 223289#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 223391#L661 assume !(0 != activate_threads_~tmp___2~0#1); 223168#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 223169#L326 assume !(1 == ~t4_pc~0); 222968#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 222969#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 223221#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 223352#L669 assume !(0 != activate_threads_~tmp___3~0#1); 223348#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 223349#L572 assume !(1 == ~M_E~0); 223387#L572-2 assume !(1 == ~T1_E~0); 223024#L577-1 assume !(1 == ~T2_E~0); 223025#L582-1 assume !(1 == ~T3_E~0); 223335#L587-1 assume !(1 == ~T4_E~0); 223342#L592-1 assume !(1 == ~E_M~0); 222966#L597-1 assume !(1 == ~E_1~0); 222967#L602-1 assume !(1 == ~E_2~0); 223186#L607-1 assume !(1 == ~E_3~0); 223187#L612-1 assume !(1 == ~E_4~0); 223134#L617-1 assume { :end_inline_reset_delta_events } true; 223135#L803-2 assume !false; 230134#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 230132#L489 [2022-10-17 10:33:31,908 INFO L750 eck$LassoCheckResult]: Loop: 230132#L489 assume !false; 230130#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 230127#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 230125#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 230124#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 230120#L428 assume 0 != eval_~tmp~0#1; 230118#L428-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 230115#L436 assume !(0 != eval_~tmp_ndt_1~0#1); 230081#L433 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 230079#L450 assume !(0 != eval_~tmp_ndt_2~0#1); 229970#L447 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 229965#L464 assume !(0 != eval_~tmp_ndt_3~0#1); 229960#L461 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 229817#L478 assume !(0 != eval_~tmp_ndt_4~0#1); 229956#L475 assume !(0 == ~t4_st~0); 230132#L489 [2022-10-17 10:33:31,909 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:33:31,909 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 4 times [2022-10-17 10:33:31,910 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:33:31,910 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1211545470] [2022-10-17 10:33:31,910 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:33:31,910 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:33:31,934 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:33:31,939 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:33:31,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:33:31,975 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:33:31,975 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:33:31,975 INFO L85 PathProgramCache]: Analyzing trace with hash 721579562, now seen corresponding path program 1 times [2022-10-17 10:33:31,976 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:33:31,976 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [654197617] [2022-10-17 10:33:31,976 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:33:31,976 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:33:31,980 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:33:31,980 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:33:31,982 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:33:31,984 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:33:31,984 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:33:31,984 INFO L85 PathProgramCache]: Analyzing trace with hash -1182941760, now seen corresponding path program 1 times [2022-10-17 10:33:31,985 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:33:31,985 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [44827116] [2022-10-17 10:33:31,985 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:33:31,985 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:33:31,994 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:33:32,024 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:33:32,025 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:33:32,025 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [44827116] [2022-10-17 10:33:32,025 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [44827116] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:33:32,025 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:33:32,025 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-10-17 10:33:32,026 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1132266768] [2022-10-17 10:33:32,026 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:33:32,196 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:33:32,196 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:33:32,197 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:33:32,197 INFO L87 Difference]: Start difference. First operand 34746 states and 46517 transitions. cyclomatic complexity: 11777 Second operand has 3 states, 2 states have (on average 39.5) internal successors, (79), 3 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:33:32,415 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:33:32,415 INFO L93 Difference]: Finished difference Result 39504 states and 52667 transitions. [2022-10-17 10:33:32,415 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 39504 states and 52667 transitions. [2022-10-17 10:33:32,575 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 39262 [2022-10-17 10:33:32,861 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 39504 states to 39504 states and 52667 transitions. [2022-10-17 10:33:32,862 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 39504 [2022-10-17 10:33:32,882 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 39504 [2022-10-17 10:33:32,883 INFO L73 IsDeterministic]: Start isDeterministic. Operand 39504 states and 52667 transitions. [2022-10-17 10:33:32,927 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:33:32,927 INFO L218 hiAutomatonCegarLoop]: Abstraction has 39504 states and 52667 transitions. [2022-10-17 10:33:32,953 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39504 states and 52667 transitions. [2022-10-17 10:33:33,315 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39504 to 39056. [2022-10-17 10:33:33,348 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 39056 states, 39056 states have (on average 1.3370288816058993) internal successors, (52219), 39055 states have internal predecessors, (52219), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:33:33,692 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39056 states to 39056 states and 52219 transitions. [2022-10-17 10:33:33,692 INFO L240 hiAutomatonCegarLoop]: Abstraction has 39056 states and 52219 transitions. [2022-10-17 10:33:33,698 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:33:33,699 INFO L428 stractBuchiCegarLoop]: Abstraction has 39056 states and 52219 transitions. [2022-10-17 10:33:33,699 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2022-10-17 10:33:33,699 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 39056 states and 52219 transitions. [2022-10-17 10:33:33,790 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 38814 [2022-10-17 10:33:33,790 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:33:33,790 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:33:33,791 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:33:33,791 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:33:33,792 INFO L748 eck$LassoCheckResult]: Stem: 297766#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 297719#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 297562#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 297281#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 297282#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 297336#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 297657#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 297287#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 297288#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 297418#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 297317#L514 assume !(0 == ~M_E~0); 297318#L514-2 assume !(0 == ~T1_E~0); 297686#L519-1 assume !(0 == ~T2_E~0); 297273#L524-1 assume !(0 == ~T3_E~0); 297274#L529-1 assume !(0 == ~T4_E~0); 297392#L534-1 assume !(0 == ~E_M~0); 297624#L539-1 assume !(0 == ~E_1~0); 297625#L544-1 assume !(0 == ~E_2~0); 297654#L549-1 assume !(0 == ~E_3~0); 297655#L554-1 assume !(0 == ~E_4~0); 297268#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 297269#L250 assume !(1 == ~m_pc~0); 297504#L250-2 is_master_triggered_~__retres1~0#1 := 0; 297660#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 297459#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 297460#L637 assume !(0 != activate_threads_~tmp~1#1); 297275#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 297276#L269 assume !(1 == ~t1_pc~0); 297214#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 297387#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 297414#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 297415#L645 assume !(0 != activate_threads_~tmp___0~0#1); 297455#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 297456#L288 assume !(1 == ~t2_pc~0); 297448#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 297449#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 297472#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 297473#L653 assume !(0 != activate_threads_~tmp___1~0#1); 297615#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 297486#L307 assume !(1 == ~t3_pc~0); 297408#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 297409#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 297553#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 297666#L661 assume !(0 != activate_threads_~tmp___2~0#1); 297427#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 297428#L326 assume !(1 == ~t4_pc~0); 297227#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 297228#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 297484#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 297623#L669 assume !(0 != activate_threads_~tmp___3~0#1); 297620#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 297621#L572 assume !(1 == ~M_E~0); 297661#L572-2 assume !(1 == ~T1_E~0); 297283#L577-1 assume !(1 == ~T2_E~0); 297284#L582-1 assume !(1 == ~T3_E~0); 297601#L587-1 assume !(1 == ~T4_E~0); 297609#L592-1 assume !(1 == ~E_M~0); 297225#L597-1 assume !(1 == ~E_1~0); 297226#L602-1 assume !(1 == ~E_2~0); 297445#L607-1 assume !(1 == ~E_3~0); 297446#L612-1 assume !(1 == ~E_4~0); 297390#L617-1 assume { :end_inline_reset_delta_events } true; 297391#L803-2 assume !false; 311032#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 310672#L489 [2022-10-17 10:33:33,792 INFO L750 eck$LassoCheckResult]: Loop: 310672#L489 assume !false; 311028#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 311023#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 311020#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 311016#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 311012#L428 assume 0 != eval_~tmp~0#1; 311007#L428-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 311000#L436 assume !(0 != eval_~tmp_ndt_1~0#1); 305283#L433 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 305279#L450 assume !(0 != eval_~tmp_ndt_2~0#1); 305277#L447 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 304105#L464 assume !(0 != eval_~tmp_ndt_3~0#1); 305273#L461 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 305252#L478 assume !(0 != eval_~tmp_ndt_4~0#1); 305271#L475 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 310670#L492 assume !(0 != eval_~tmp_ndt_5~0#1); 310672#L489 [2022-10-17 10:33:33,792 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:33:33,793 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 5 times [2022-10-17 10:33:33,793 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:33:33,793 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1131940231] [2022-10-17 10:33:33,793 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:33:33,794 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:33:33,803 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:33:33,803 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:33:33,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:33:33,820 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:33:33,821 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:33:33,821 INFO L85 PathProgramCache]: Analyzing trace with hash 894126298, now seen corresponding path program 1 times [2022-10-17 10:33:33,821 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:33:33,821 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1676603276] [2022-10-17 10:33:33,821 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:33:33,822 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:33:33,825 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:33:33,825 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:33:33,827 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:33:33,829 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:33:33,830 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:33:33,830 INFO L85 PathProgramCache]: Analyzing trace with hash 1983507460, now seen corresponding path program 1 times [2022-10-17 10:33:33,830 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:33:33,830 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [147251304] [2022-10-17 10:33:33,830 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:33:33,831 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:33:33,840 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:33:33,840 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:33:33,846 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:33:33,861 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:33:35,693 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:33:35,693 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:33:35,712 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:33:35,861 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 17.10 10:33:35 BoogieIcfgContainer [2022-10-17 10:33:35,862 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2022-10-17 10:33:35,862 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-10-17 10:33:35,862 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-10-17 10:33:35,862 INFO L275 PluginConnector]: Witness Printer initialized [2022-10-17 10:33:35,863 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 17.10 10:33:21" (3/4) ... [2022-10-17 10:33:35,865 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2022-10-17 10:33:35,976 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0226a7e4-297f-426f-84a3-9f9bdc583d94/bin/uautomizer-J5u9QxTXDZ/witness.graphml [2022-10-17 10:33:35,977 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-10-17 10:33:35,978 INFO L158 Benchmark]: Toolchain (without parser) took 16215.57ms. Allocated memory was 98.6MB in the beginning and 4.7GB in the end (delta: 4.6GB). Free memory was 64.5MB in the beginning and 4.1GB in the end (delta: -4.1GB). Peak memory consumption was 534.0MB. Max. memory is 16.1GB. [2022-10-17 10:33:35,978 INFO L158 Benchmark]: CDTParser took 0.27ms. Allocated memory is still 98.6MB. Free memory is still 50.8MB. There was no memory consumed. Max. memory is 16.1GB. [2022-10-17 10:33:35,979 INFO L158 Benchmark]: CACSL2BoogieTranslator took 391.76ms. Allocated memory is still 98.6MB. Free memory was 64.3MB in the beginning and 66.5MB in the end (delta: -2.3MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. [2022-10-17 10:33:35,979 INFO L158 Benchmark]: Boogie Procedure Inliner took 77.47ms. Allocated memory is still 98.6MB. Free memory was 66.5MB in the beginning and 61.8MB in the end (delta: 4.7MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. [2022-10-17 10:33:35,979 INFO L158 Benchmark]: Boogie Preprocessor took 125.92ms. Allocated memory is still 98.6MB. Free memory was 61.8MB in the beginning and 57.6MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2022-10-17 10:33:35,980 INFO L158 Benchmark]: RCFGBuilder took 1119.42ms. Allocated memory was 98.6MB in the beginning and 121.6MB in the end (delta: 23.1MB). Free memory was 57.6MB in the beginning and 67.8MB in the end (delta: -10.2MB). Peak memory consumption was 27.3MB. Max. memory is 16.1GB. [2022-10-17 10:33:35,980 INFO L158 Benchmark]: BuchiAutomizer took 14380.24ms. Allocated memory was 121.6MB in the beginning and 4.7GB in the end (delta: 4.6GB). Free memory was 67.2MB in the beginning and 4.1GB in the end (delta: -4.1GB). Peak memory consumption was 505.4MB. Max. memory is 16.1GB. [2022-10-17 10:33:35,981 INFO L158 Benchmark]: Witness Printer took 114.61ms. Allocated memory is still 4.7GB. Free memory was 4.1GB in the beginning and 4.1GB in the end (delta: 9.4MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2022-10-17 10:33:35,983 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.27ms. Allocated memory is still 98.6MB. Free memory is still 50.8MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 391.76ms. Allocated memory is still 98.6MB. Free memory was 64.3MB in the beginning and 66.5MB in the end (delta: -2.3MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 77.47ms. Allocated memory is still 98.6MB. Free memory was 66.5MB in the beginning and 61.8MB in the end (delta: 4.7MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. * Boogie Preprocessor took 125.92ms. Allocated memory is still 98.6MB. Free memory was 61.8MB in the beginning and 57.6MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * RCFGBuilder took 1119.42ms. Allocated memory was 98.6MB in the beginning and 121.6MB in the end (delta: 23.1MB). Free memory was 57.6MB in the beginning and 67.8MB in the end (delta: -10.2MB). Peak memory consumption was 27.3MB. Max. memory is 16.1GB. * BuchiAutomizer took 14380.24ms. Allocated memory was 121.6MB in the beginning and 4.7GB in the end (delta: 4.6GB). Free memory was 67.2MB in the beginning and 4.1GB in the end (delta: -4.1GB). Peak memory consumption was 505.4MB. Max. memory is 16.1GB. * Witness Printer took 114.61ms. Allocated memory is still 4.7GB. Free memory was 4.1GB in the beginning and 4.1GB in the end (delta: 9.4MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 21 terminating modules (21 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.21 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 39056 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 14.2s and 22 iterations. TraceHistogramMax:1. Analysis of lassos took 5.2s. Construction of modules took 0.6s. Büchi inclusion checks took 7.4s. Highest rank in rank-based complementation 0. Minimization of det autom 21. Minimization of nondet autom 0. Automata minimization 3.2s AutomataMinimizationTime, 21 MinimizatonAttempts, 16627 StatesRemovedByMinimization, 14 NontrivialMinimizations. Non-live state removal took 2.4s Buchi closure took 0.1s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 17201 SdHoareTripleChecker+Valid, 0.9s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 17201 mSDsluCounter, 28224 SdHoareTripleChecker+Invalid, 0.7s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 13929 mSDsCounter, 250 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 660 IncrementalHoareTripleChecker+Invalid, 910 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 250 mSolverCounterUnsat, 14295 mSDtfsCounter, 660 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc4 concLT0 SILN1 SILU0 SILI13 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 423]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int t4_pc = 0; [L29] int m_st ; [L30] int t1_st ; [L31] int t2_st ; [L32] int t3_st ; [L33] int t4_st ; [L34] int m_i ; [L35] int t1_i ; [L36] int t2_i ; [L37] int t3_i ; [L38] int t4_i ; [L39] int M_E = 2; [L40] int T1_E = 2; [L41] int T2_E = 2; [L42] int T3_E = 2; [L43] int T4_E = 2; [L44] int E_M = 2; [L45] int E_1 = 2; [L46] int E_2 = 2; [L47] int E_3 = 2; [L48] int E_4 = 2; [L55] int token ; [L57] int local ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0, token=0] [L848] int __retres1 ; [L852] CALL init_model() [L760] m_i = 1 [L761] t1_i = 1 [L762] t2_i = 1 [L763] t3_i = 1 [L764] t4_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L852] RET init_model() [L853] CALL start_simulation() [L789] int kernel_st ; [L790] int tmp ; [L791] int tmp___0 ; [L795] kernel_st = 0 [L796] FCALL update_channels() [L797] CALL init_threads() [L353] COND TRUE m_i == 1 [L354] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L358] COND TRUE t1_i == 1 [L359] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L363] COND TRUE t2_i == 1 [L364] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L368] COND TRUE t3_i == 1 [L369] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L373] COND TRUE t4_i == 1 [L374] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L797] RET init_threads() [L798] CALL fire_delta_events() [L514] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L519] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L524] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L529] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L534] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L539] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L544] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L549] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L554] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L559] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L798] RET fire_delta_events() [L799] CALL activate_threads() [L627] int tmp ; [L628] int tmp___0 ; [L629] int tmp___1 ; [L630] int tmp___2 ; [L631] int tmp___3 ; [L635] CALL, EXPR is_master_triggered() [L247] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L250] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L260] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L262] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L635] RET, EXPR is_master_triggered() [L635] tmp = is_master_triggered() [L637] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, token=0] [L643] CALL, EXPR is_transmit1_triggered() [L266] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L269] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L279] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L281] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L643] RET, EXPR is_transmit1_triggered() [L643] tmp___0 = is_transmit1_triggered() [L645] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, token=0] [L651] CALL, EXPR is_transmit2_triggered() [L285] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L288] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L298] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L300] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L651] RET, EXPR is_transmit2_triggered() [L651] tmp___1 = is_transmit2_triggered() [L653] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, token=0] [L659] CALL, EXPR is_transmit3_triggered() [L304] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L307] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L317] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L319] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L659] RET, EXPR is_transmit3_triggered() [L659] tmp___2 = is_transmit3_triggered() [L661] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, token=0] [L667] CALL, EXPR is_transmit4_triggered() [L323] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L326] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L336] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L338] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L667] RET, EXPR is_transmit4_triggered() [L667] tmp___3 = is_transmit4_triggered() [L669] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, token=0] [L799] RET activate_threads() [L800] CALL reset_delta_events() [L572] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L577] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L582] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L587] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L592] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L597] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L602] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L607] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L612] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L617] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L800] RET reset_delta_events() [L803] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, kernel_st=0, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L806] kernel_st = 1 [L807] CALL eval() [L419] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] Loop: [L423] COND TRUE 1 [L426] CALL, EXPR exists_runnable_thread() [L383] int __retres1 ; [L386] COND TRUE m_st == 0 [L387] __retres1 = 1 [L414] return (__retres1); [L426] RET, EXPR exists_runnable_thread() [L426] tmp = exists_runnable_thread() [L428] COND TRUE \read(tmp) [L433] COND TRUE m_st == 0 [L434] int tmp_ndt_1; [L435] tmp_ndt_1 = __VERIFIER_nondet_int() [L436] COND FALSE !(\read(tmp_ndt_1)) [L447] COND TRUE t1_st == 0 [L448] int tmp_ndt_2; [L449] tmp_ndt_2 = __VERIFIER_nondet_int() [L450] COND FALSE !(\read(tmp_ndt_2)) [L461] COND TRUE t2_st == 0 [L462] int tmp_ndt_3; [L463] tmp_ndt_3 = __VERIFIER_nondet_int() [L464] COND FALSE !(\read(tmp_ndt_3)) [L475] COND TRUE t3_st == 0 [L476] int tmp_ndt_4; [L477] tmp_ndt_4 = __VERIFIER_nondet_int() [L478] COND FALSE !(\read(tmp_ndt_4)) [L489] COND TRUE t4_st == 0 [L490] int tmp_ndt_5; [L491] tmp_ndt_5 = __VERIFIER_nondet_int() [L492] COND FALSE !(\read(tmp_ndt_5)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 423]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int t4_pc = 0; [L29] int m_st ; [L30] int t1_st ; [L31] int t2_st ; [L32] int t3_st ; [L33] int t4_st ; [L34] int m_i ; [L35] int t1_i ; [L36] int t2_i ; [L37] int t3_i ; [L38] int t4_i ; [L39] int M_E = 2; [L40] int T1_E = 2; [L41] int T2_E = 2; [L42] int T3_E = 2; [L43] int T4_E = 2; [L44] int E_M = 2; [L45] int E_1 = 2; [L46] int E_2 = 2; [L47] int E_3 = 2; [L48] int E_4 = 2; [L55] int token ; [L57] int local ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0, token=0] [L848] int __retres1 ; [L852] CALL init_model() [L760] m_i = 1 [L761] t1_i = 1 [L762] t2_i = 1 [L763] t3_i = 1 [L764] t4_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L852] RET init_model() [L853] CALL start_simulation() [L789] int kernel_st ; [L790] int tmp ; [L791] int tmp___0 ; [L795] kernel_st = 0 [L796] FCALL update_channels() [L797] CALL init_threads() [L353] COND TRUE m_i == 1 [L354] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L358] COND TRUE t1_i == 1 [L359] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L363] COND TRUE t2_i == 1 [L364] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L368] COND TRUE t3_i == 1 [L369] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L373] COND TRUE t4_i == 1 [L374] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L797] RET init_threads() [L798] CALL fire_delta_events() [L514] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L519] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L524] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L529] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L534] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L539] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L544] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L549] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L554] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L559] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L798] RET fire_delta_events() [L799] CALL activate_threads() [L627] int tmp ; [L628] int tmp___0 ; [L629] int tmp___1 ; [L630] int tmp___2 ; [L631] int tmp___3 ; [L635] CALL, EXPR is_master_triggered() [L247] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L250] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L260] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L262] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L635] RET, EXPR is_master_triggered() [L635] tmp = is_master_triggered() [L637] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, token=0] [L643] CALL, EXPR is_transmit1_triggered() [L266] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L269] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L279] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L281] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L643] RET, EXPR is_transmit1_triggered() [L643] tmp___0 = is_transmit1_triggered() [L645] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, token=0] [L651] CALL, EXPR is_transmit2_triggered() [L285] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L288] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L298] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L300] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L651] RET, EXPR is_transmit2_triggered() [L651] tmp___1 = is_transmit2_triggered() [L653] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, token=0] [L659] CALL, EXPR is_transmit3_triggered() [L304] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L307] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L317] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L319] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L659] RET, EXPR is_transmit3_triggered() [L659] tmp___2 = is_transmit3_triggered() [L661] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, token=0] [L667] CALL, EXPR is_transmit4_triggered() [L323] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L326] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L336] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L338] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L667] RET, EXPR is_transmit4_triggered() [L667] tmp___3 = is_transmit4_triggered() [L669] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, token=0] [L799] RET activate_threads() [L800] CALL reset_delta_events() [L572] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L577] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L582] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L587] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L592] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L597] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L602] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L607] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L612] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L617] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L800] RET reset_delta_events() [L803] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, kernel_st=0, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L806] kernel_st = 1 [L807] CALL eval() [L419] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] Loop: [L423] COND TRUE 1 [L426] CALL, EXPR exists_runnable_thread() [L383] int __retres1 ; [L386] COND TRUE m_st == 0 [L387] __retres1 = 1 [L414] return (__retres1); [L426] RET, EXPR exists_runnable_thread() [L426] tmp = exists_runnable_thread() [L428] COND TRUE \read(tmp) [L433] COND TRUE m_st == 0 [L434] int tmp_ndt_1; [L435] tmp_ndt_1 = __VERIFIER_nondet_int() [L436] COND FALSE !(\read(tmp_ndt_1)) [L447] COND TRUE t1_st == 0 [L448] int tmp_ndt_2; [L449] tmp_ndt_2 = __VERIFIER_nondet_int() [L450] COND FALSE !(\read(tmp_ndt_2)) [L461] COND TRUE t2_st == 0 [L462] int tmp_ndt_3; [L463] tmp_ndt_3 = __VERIFIER_nondet_int() [L464] COND FALSE !(\read(tmp_ndt_3)) [L475] COND TRUE t3_st == 0 [L476] int tmp_ndt_4; [L477] tmp_ndt_4 = __VERIFIER_nondet_int() [L478] COND FALSE !(\read(tmp_ndt_4)) [L489] COND TRUE t4_st == 0 [L490] int tmp_ndt_5; [L491] tmp_ndt_5 = __VERIFIER_nondet_int() [L492] COND FALSE !(\read(tmp_ndt_5)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2022-10-17 10:33:36,131 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0226a7e4-297f-426f-84a3-9f9bdc583d94/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)