./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.04.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version dbf71c69 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0042236c-ae04-44fe-9ff8-d2ad69a89359/bin/uautomizer-J5u9QxTXDZ/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0042236c-ae04-44fe-9ff8-d2ad69a89359/bin/uautomizer-J5u9QxTXDZ/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0042236c-ae04-44fe-9ff8-d2ad69a89359/bin/uautomizer-J5u9QxTXDZ/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0042236c-ae04-44fe-9ff8-d2ad69a89359/bin/uautomizer-J5u9QxTXDZ/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.04.cil-2.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0042236c-ae04-44fe-9ff8-d2ad69a89359/bin/uautomizer-J5u9QxTXDZ/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0042236c-ae04-44fe-9ff8-d2ad69a89359/bin/uautomizer-J5u9QxTXDZ --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 05d3b7d21cc48825b4a0189c75f03d768acc6241312029d3e223c1b9b2a509ea --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-dbf71c6-m [2022-10-17 11:09:05,284 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-10-17 11:09:05,287 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-10-17 11:09:05,338 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-10-17 11:09:05,339 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-10-17 11:09:05,341 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-10-17 11:09:05,343 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-10-17 11:09:05,346 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-10-17 11:09:05,348 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-10-17 11:09:05,350 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-10-17 11:09:05,351 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-10-17 11:09:05,353 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-10-17 11:09:05,353 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-10-17 11:09:05,355 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-10-17 11:09:05,356 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-10-17 11:09:05,358 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-10-17 11:09:05,359 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-10-17 11:09:05,361 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-10-17 11:09:05,363 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-10-17 11:09:05,366 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-10-17 11:09:05,368 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-10-17 11:09:05,369 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-10-17 11:09:05,371 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-10-17 11:09:05,372 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-10-17 11:09:05,377 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-10-17 11:09:05,378 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-10-17 11:09:05,378 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-10-17 11:09:05,379 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-10-17 11:09:05,380 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-10-17 11:09:05,381 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-10-17 11:09:05,382 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-10-17 11:09:05,383 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-10-17 11:09:05,384 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-10-17 11:09:05,385 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-10-17 11:09:05,386 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-10-17 11:09:05,386 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-10-17 11:09:05,387 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-10-17 11:09:05,388 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-10-17 11:09:05,388 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-10-17 11:09:05,389 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-10-17 11:09:05,390 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-10-17 11:09:05,390 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0042236c-ae04-44fe-9ff8-d2ad69a89359/bin/uautomizer-J5u9QxTXDZ/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-10-17 11:09:05,421 INFO L113 SettingsManager]: Loading preferences was successful [2022-10-17 11:09:05,421 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-10-17 11:09:05,421 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-10-17 11:09:05,421 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-10-17 11:09:05,423 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-10-17 11:09:05,423 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-10-17 11:09:05,423 INFO L138 SettingsManager]: * Use SBE=true [2022-10-17 11:09:05,423 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-10-17 11:09:05,423 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-10-17 11:09:05,424 INFO L138 SettingsManager]: * Use old map elimination=false [2022-10-17 11:09:05,424 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-10-17 11:09:05,424 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-10-17 11:09:05,424 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-10-17 11:09:05,424 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-10-17 11:09:05,425 INFO L138 SettingsManager]: * sizeof long=4 [2022-10-17 11:09:05,425 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-10-17 11:09:05,425 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-10-17 11:09:05,425 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-10-17 11:09:05,425 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-10-17 11:09:05,426 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-10-17 11:09:05,426 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-10-17 11:09:05,426 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-10-17 11:09:05,426 INFO L138 SettingsManager]: * sizeof long double=12 [2022-10-17 11:09:05,426 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-10-17 11:09:05,427 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-10-17 11:09:05,427 INFO L138 SettingsManager]: * Use constant arrays=true [2022-10-17 11:09:05,427 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-10-17 11:09:05,427 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-10-17 11:09:05,427 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-10-17 11:09:05,428 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-10-17 11:09:05,428 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-10-17 11:09:05,429 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-10-17 11:09:05,429 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0042236c-ae04-44fe-9ff8-d2ad69a89359/bin/uautomizer-J5u9QxTXDZ/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0042236c-ae04-44fe-9ff8-d2ad69a89359/bin/uautomizer-J5u9QxTXDZ Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 05d3b7d21cc48825b4a0189c75f03d768acc6241312029d3e223c1b9b2a509ea [2022-10-17 11:09:05,719 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-10-17 11:09:05,748 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-10-17 11:09:05,751 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-10-17 11:09:05,752 INFO L271 PluginConnector]: Initializing CDTParser... [2022-10-17 11:09:05,753 INFO L275 PluginConnector]: CDTParser initialized [2022-10-17 11:09:05,754 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0042236c-ae04-44fe-9ff8-d2ad69a89359/bin/uautomizer-J5u9QxTXDZ/../../sv-benchmarks/c/systemc/token_ring.04.cil-2.c [2022-10-17 11:09:05,824 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0042236c-ae04-44fe-9ff8-d2ad69a89359/bin/uautomizer-J5u9QxTXDZ/data/441ceddb9/9d7d2ebd252541d3bd1d7ef959f8b82e/FLAG51e88bc01 [2022-10-17 11:09:06,346 INFO L306 CDTParser]: Found 1 translation units. [2022-10-17 11:09:06,346 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0042236c-ae04-44fe-9ff8-d2ad69a89359/sv-benchmarks/c/systemc/token_ring.04.cil-2.c [2022-10-17 11:09:06,360 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0042236c-ae04-44fe-9ff8-d2ad69a89359/bin/uautomizer-J5u9QxTXDZ/data/441ceddb9/9d7d2ebd252541d3bd1d7ef959f8b82e/FLAG51e88bc01 [2022-10-17 11:09:06,703 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0042236c-ae04-44fe-9ff8-d2ad69a89359/bin/uautomizer-J5u9QxTXDZ/data/441ceddb9/9d7d2ebd252541d3bd1d7ef959f8b82e [2022-10-17 11:09:06,705 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-10-17 11:09:06,707 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-10-17 11:09:06,711 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-10-17 11:09:06,712 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-10-17 11:09:06,716 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-10-17 11:09:06,717 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.10 11:09:06" (1/1) ... [2022-10-17 11:09:06,719 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@216e9a58 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 11:09:06, skipping insertion in model container [2022-10-17 11:09:06,721 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.10 11:09:06" (1/1) ... [2022-10-17 11:09:06,728 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-10-17 11:09:06,778 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-10-17 11:09:06,961 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0042236c-ae04-44fe-9ff8-d2ad69a89359/sv-benchmarks/c/systemc/token_ring.04.cil-2.c[671,684] [2022-10-17 11:09:07,031 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-10-17 11:09:07,041 INFO L203 MainTranslator]: Completed pre-run [2022-10-17 11:09:07,052 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0042236c-ae04-44fe-9ff8-d2ad69a89359/sv-benchmarks/c/systemc/token_ring.04.cil-2.c[671,684] [2022-10-17 11:09:07,092 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-10-17 11:09:07,108 INFO L208 MainTranslator]: Completed translation [2022-10-17 11:09:07,109 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 11:09:07 WrapperNode [2022-10-17 11:09:07,109 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-10-17 11:09:07,111 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-10-17 11:09:07,111 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-10-17 11:09:07,111 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-10-17 11:09:07,119 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 11:09:07" (1/1) ... [2022-10-17 11:09:07,129 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 11:09:07" (1/1) ... [2022-10-17 11:09:07,193 INFO L138 Inliner]: procedures = 36, calls = 44, calls flagged for inlining = 39, calls inlined = 78, statements flattened = 1074 [2022-10-17 11:09:07,194 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-10-17 11:09:07,195 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-10-17 11:09:07,195 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-10-17 11:09:07,195 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-10-17 11:09:07,204 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 11:09:07" (1/1) ... [2022-10-17 11:09:07,204 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 11:09:07" (1/1) ... [2022-10-17 11:09:07,209 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 11:09:07" (1/1) ... [2022-10-17 11:09:07,209 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 11:09:07" (1/1) ... [2022-10-17 11:09:07,225 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 11:09:07" (1/1) ... [2022-10-17 11:09:07,242 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 11:09:07" (1/1) ... [2022-10-17 11:09:07,246 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 11:09:07" (1/1) ... [2022-10-17 11:09:07,251 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 11:09:07" (1/1) ... [2022-10-17 11:09:07,260 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-10-17 11:09:07,261 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-10-17 11:09:07,261 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-10-17 11:09:07,261 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-10-17 11:09:07,262 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 11:09:07" (1/1) ... [2022-10-17 11:09:07,283 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 11:09:07,301 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0042236c-ae04-44fe-9ff8-d2ad69a89359/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 11:09:07,324 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0042236c-ae04-44fe-9ff8-d2ad69a89359/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 11:09:07,357 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0042236c-ae04-44fe-9ff8-d2ad69a89359/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-10-17 11:09:07,377 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-10-17 11:09:07,377 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-10-17 11:09:07,377 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-10-17 11:09:07,377 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-10-17 11:09:07,483 INFO L235 CfgBuilder]: Building ICFG [2022-10-17 11:09:07,484 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-10-17 11:09:08,530 INFO L276 CfgBuilder]: Performing block encoding [2022-10-17 11:09:08,547 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-10-17 11:09:08,551 INFO L300 CfgBuilder]: Removed 7 assume(true) statements. [2022-10-17 11:09:08,554 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 17.10 11:09:08 BoogieIcfgContainer [2022-10-17 11:09:08,555 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-10-17 11:09:08,556 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-10-17 11:09:08,556 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-10-17 11:09:08,561 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-10-17 11:09:08,562 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-10-17 11:09:08,562 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 17.10 11:09:06" (1/3) ... [2022-10-17 11:09:08,563 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@723936e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.10 11:09:08, skipping insertion in model container [2022-10-17 11:09:08,563 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-10-17 11:09:08,563 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 11:09:07" (2/3) ... [2022-10-17 11:09:08,564 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@723936e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.10 11:09:08, skipping insertion in model container [2022-10-17 11:09:08,564 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-10-17 11:09:08,564 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 17.10 11:09:08" (3/3) ... [2022-10-17 11:09:08,565 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.04.cil-2.c [2022-10-17 11:09:08,634 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-10-17 11:09:08,635 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-10-17 11:09:08,635 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-10-17 11:09:08,635 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-10-17 11:09:08,635 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-10-17 11:09:08,635 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-10-17 11:09:08,635 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-10-17 11:09:08,636 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-10-17 11:09:08,642 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 438 states, 437 states have (on average 1.5354691075514875) internal successors, (671), 437 states have internal predecessors, (671), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:09:08,687 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 367 [2022-10-17 11:09:08,688 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 11:09:08,688 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 11:09:08,705 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:09:08,705 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:09:08,706 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-10-17 11:09:08,708 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 438 states, 437 states have (on average 1.5354691075514875) internal successors, (671), 437 states have internal predecessors, (671), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:09:08,735 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 367 [2022-10-17 11:09:08,735 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 11:09:08,735 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 11:09:08,740 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:09:08,740 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:09:08,757 INFO L748 eck$LassoCheckResult]: Stem: 429#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 350#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 125#L778true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11#L358true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 49#L365true assume !(1 == ~m_i~0);~m_st~0 := 2; 324#L365-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 228#L370-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 181#L375-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 332#L380-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 210#L385-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 190#L526true assume !(0 == ~M_E~0); 413#L526-2true assume 0 == ~T1_E~0;~T1_E~0 := 1; 231#L531-1true assume !(0 == ~T2_E~0); 179#L536-1true assume !(0 == ~T3_E~0); 286#L541-1true assume !(0 == ~T4_E~0); 177#L546-1true assume !(0 == ~E_M~0); 239#L551-1true assume !(0 == ~E_1~0); 160#L556-1true assume !(0 == ~E_2~0); 188#L561-1true assume !(0 == ~E_3~0); 166#L566-1true assume 0 == ~E_4~0;~E_4~0 := 1; 362#L571-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 163#L262true assume 1 == ~m_pc~0; 436#L263true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 368#L273true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 75#L274true activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 365#L649true assume !(0 != activate_threads_~tmp~1#1); 432#L649-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 127#L281true assume !(1 == ~t1_pc~0); 385#L281-2true is_transmit1_triggered_~__retres1~1#1 := 0; 77#L292true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 209#L293true activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 111#L657true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 348#L657-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 168#L300true assume 1 == ~t2_pc~0; 296#L301true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 268#L311true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 107#L312true activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 186#L665true assume !(0 != activate_threads_~tmp___1~0#1); 38#L665-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 438#L319true assume !(1 == ~t3_pc~0); 18#L319-2true is_transmit3_triggered_~__retres1~3#1 := 0; 271#L330true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 122#L331true activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 140#L673true assume !(0 != activate_threads_~tmp___2~0#1); 28#L673-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 272#L338true assume 1 == ~t4_pc~0; 108#L339true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 72#L349true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 85#L350true activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 372#L681true assume !(0 != activate_threads_~tmp___3~0#1); 2#L681-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 359#L584true assume !(1 == ~M_E~0); 109#L584-2true assume !(1 == ~T1_E~0); 84#L589-1true assume !(1 == ~T2_E~0); 256#L594-1true assume !(1 == ~T3_E~0); 142#L599-1true assume !(1 == ~T4_E~0); 17#L604-1true assume !(1 == ~E_M~0); 9#L609-1true assume 1 == ~E_1~0;~E_1~0 := 2; 71#L614-1true assume !(1 == ~E_2~0); 121#L619-1true assume !(1 == ~E_3~0); 182#L624-1true assume !(1 == ~E_4~0); 392#L629-1true assume { :end_inline_reset_delta_events } true; 200#L815-2true [2022-10-17 11:09:08,769 INFO L750 eck$LassoCheckResult]: Loop: 200#L815-2true assume !false; 377#L816true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 353#L501true assume !true; 395#L516true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 355#L358-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 143#L526-3true assume 0 == ~M_E~0;~M_E~0 := 1; 262#L526-5true assume !(0 == ~T1_E~0); 73#L531-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 386#L536-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 14#L541-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 185#L546-3true assume 0 == ~E_M~0;~E_M~0 := 1; 433#L551-3true assume 0 == ~E_1~0;~E_1~0 := 1; 149#L556-3true assume 0 == ~E_2~0;~E_2~0 := 1; 234#L561-3true assume 0 == ~E_3~0;~E_3~0 := 1; 306#L566-3true assume !(0 == ~E_4~0); 79#L571-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 261#L262-18true assume 1 == ~m_pc~0; 278#L263-6true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 282#L273-6true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 70#L274-6true activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 358#L649-18true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 21#L649-20true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 158#L281-18true assume !(1 == ~t1_pc~0); 265#L281-20true is_transmit1_triggered_~__retres1~1#1 := 0; 170#L292-6true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 288#L293-6true activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 410#L657-18true assume !(0 != activate_threads_~tmp___0~0#1); 283#L657-20true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 323#L300-18true assume !(1 == ~t2_pc~0); 15#L300-20true is_transmit2_triggered_~__retres1~2#1 := 0; 46#L311-6true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 57#L312-6true activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 248#L665-18true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 307#L665-20true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 78#L319-18true assume !(1 == ~t3_pc~0); 238#L319-20true is_transmit3_triggered_~__retres1~3#1 := 0; 90#L330-6true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 113#L331-6true activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 216#L673-18true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 197#L673-20true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 126#L338-18true assume !(1 == ~t4_pc~0); 156#L338-20true is_transmit4_triggered_~__retres1~4#1 := 0; 101#L349-6true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 349#L350-6true activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 31#L681-18true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 172#L681-20true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 139#L584-3true assume 1 == ~M_E~0;~M_E~0 := 2; 280#L584-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 29#L589-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 134#L594-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 213#L599-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 151#L604-3true assume 1 == ~E_M~0;~E_M~0 := 2; 398#L609-3true assume !(1 == ~E_1~0); 196#L614-3true assume 1 == ~E_2~0;~E_2~0 := 2; 25#L619-3true assume 1 == ~E_3~0;~E_3~0 := 2; 211#L624-3true assume 1 == ~E_4~0;~E_4~0 := 2; 240#L629-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 250#L398-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 67#L425-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 293#L426-1true start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 95#L834true assume !(0 == start_simulation_~tmp~3#1); 219#L834-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 343#L398-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 215#L425-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 251#L426-2true stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 285#L789true assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 295#L796true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 183#L797true start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 198#L847true assume !(0 != start_simulation_~tmp___0~1#1); 200#L815-2true [2022-10-17 11:09:08,782 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:09:08,782 INFO L85 PathProgramCache]: Analyzing trace with hash 1553035642, now seen corresponding path program 1 times [2022-10-17 11:09:08,792 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:09:08,792 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [5785059] [2022-10-17 11:09:08,793 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:09:08,794 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:09:08,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:09:09,135 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:09:09,135 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:09:09,136 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [5785059] [2022-10-17 11:09:09,136 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [5785059] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:09:09,137 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:09:09,138 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:09:09,139 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [64131452] [2022-10-17 11:09:09,140 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:09:09,145 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 11:09:09,146 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:09:09,146 INFO L85 PathProgramCache]: Analyzing trace with hash -196327203, now seen corresponding path program 1 times [2022-10-17 11:09:09,147 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:09:09,148 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1828199796] [2022-10-17 11:09:09,148 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:09:09,148 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:09:09,185 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:09:09,230 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:09:09,230 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:09:09,231 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1828199796] [2022-10-17 11:09:09,231 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1828199796] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:09:09,231 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:09:09,231 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-10-17 11:09:09,231 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1610260883] [2022-10-17 11:09:09,232 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:09:09,233 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 11:09:09,234 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 11:09:09,265 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 11:09:09,266 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 11:09:09,269 INFO L87 Difference]: Start difference. First operand has 438 states, 437 states have (on average 1.5354691075514875) internal successors, (671), 437 states have internal predecessors, (671), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:09:09,333 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 11:09:09,333 INFO L93 Difference]: Finished difference Result 436 states and 652 transitions. [2022-10-17 11:09:09,335 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 436 states and 652 transitions. [2022-10-17 11:09:09,353 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 363 [2022-10-17 11:09:09,365 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 436 states to 430 states and 646 transitions. [2022-10-17 11:09:09,371 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 430 [2022-10-17 11:09:09,374 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 430 [2022-10-17 11:09:09,375 INFO L73 IsDeterministic]: Start isDeterministic. Operand 430 states and 646 transitions. [2022-10-17 11:09:09,378 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 11:09:09,379 INFO L218 hiAutomatonCegarLoop]: Abstraction has 430 states and 646 transitions. [2022-10-17 11:09:09,395 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 430 states and 646 transitions. [2022-10-17 11:09:09,427 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 430 to 430. [2022-10-17 11:09:09,429 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 430 states, 430 states have (on average 1.5023255813953489) internal successors, (646), 429 states have internal predecessors, (646), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:09:09,432 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 430 states to 430 states and 646 transitions. [2022-10-17 11:09:09,433 INFO L240 hiAutomatonCegarLoop]: Abstraction has 430 states and 646 transitions. [2022-10-17 11:09:09,435 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 11:09:09,443 INFO L428 stractBuchiCegarLoop]: Abstraction has 430 states and 646 transitions. [2022-10-17 11:09:09,444 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-10-17 11:09:09,444 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 430 states and 646 transitions. [2022-10-17 11:09:09,448 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 363 [2022-10-17 11:09:09,448 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 11:09:09,448 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 11:09:09,452 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:09:09,452 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:09:09,453 INFO L748 eck$LassoCheckResult]: Stem: 1312#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 1295#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 1107#L778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 905#L358 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 906#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 980#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1226#L370-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1184#L375-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1185#L380-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1212#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1194#L526 assume !(0 == ~M_E~0); 1195#L526-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1227#L531-1 assume !(0 == ~T2_E~0); 1180#L536-1 assume !(0 == ~T3_E~0); 1181#L541-1 assume !(0 == ~T4_E~0); 1176#L546-1 assume !(0 == ~E_M~0); 1177#L551-1 assume !(0 == ~E_1~0); 1153#L556-1 assume !(0 == ~E_2~0); 1154#L561-1 assume !(0 == ~E_3~0); 1164#L566-1 assume 0 == ~E_4~0;~E_4~0 := 1; 1165#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1158#L262 assume 1 == ~m_pc~0; 1159#L263 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1299#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1024#L274 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1025#L649 assume !(0 != activate_threads_~tmp~1#1); 1298#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1111#L281 assume !(1 == ~t1_pc~0); 1112#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1028#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1029#L293 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1087#L657 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1088#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1166#L300 assume 1 == ~t2_pc~0; 1167#L301 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1257#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1081#L312 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1082#L665 assume !(0 != activate_threads_~tmp___1~0#1); 960#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 961#L319 assume !(1 == ~t3_pc~0); 918#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 919#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1102#L331 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1103#L673 assume !(0 != activate_threads_~tmp___2~0#1); 939#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 940#L338 assume 1 == ~t4_pc~0; 1083#L339 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1004#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1018#L350 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1045#L681 assume !(0 != activate_threads_~tmp___3~0#1); 883#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 884#L584 assume !(1 == ~M_E~0); 1084#L584-2 assume !(1 == ~T1_E~0); 1043#L589-1 assume !(1 == ~T2_E~0); 1044#L594-1 assume !(1 == ~T3_E~0); 1132#L599-1 assume !(1 == ~T4_E~0); 917#L604-1 assume !(1 == ~E_M~0); 901#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 902#L614-1 assume !(1 == ~E_2~0); 1017#L619-1 assume !(1 == ~E_3~0); 1101#L624-1 assume !(1 == ~E_4~0); 1186#L629-1 assume { :end_inline_reset_delta_events } true; 1203#L815-2 [2022-10-17 11:09:09,453 INFO L750 eck$LassoCheckResult]: Loop: 1203#L815-2 assume !false; 1204#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1287#L501 assume !false; 1293#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1294#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1022#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1207#L426 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1208#L440 assume !(0 != eval_~tmp~0#1); 1306#L516 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1296#L358-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1133#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1134#L526-5 assume !(0 == ~T1_E~0); 1019#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1020#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 911#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 912#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1190#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1139#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1140#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1233#L566-3 assume !(0 == ~E_4~0); 1033#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1034#L262-18 assume 1 == ~m_pc~0; 1251#L263-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1124#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1015#L274-6 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1016#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 924#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 925#L281-18 assume !(1 == ~t1_pc~0); 1150#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 1169#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1170#L293-6 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1269#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 1265#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1266#L300-18 assume !(1 == ~t2_pc~0); 913#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 914#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 977#L312-6 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 994#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1241#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1030#L319-18 assume !(1 == ~t3_pc~0); 1031#L319-20 is_transmit3_triggered_~__retres1~3#1 := 0; 1037#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1053#L331-6 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1090#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1202#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1108#L338-18 assume 1 == ~t4_pc~0; 1109#L339-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1072#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1073#L350-6 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 945#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 946#L681-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1128#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1129#L584-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 941#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 942#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1121#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1142#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1143#L609-3 assume !(1 == ~E_1~0); 1201#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 933#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 934#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1213#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1236#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1011#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1012#L426-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 1059#L834 assume !(0 == start_simulation_~tmp~3#1); 1061#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1220#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1179#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1216#L426-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 1244#L789 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 1267#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1187#L797 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 1188#L847 assume !(0 != start_simulation_~tmp___0~1#1); 1203#L815-2 [2022-10-17 11:09:09,454 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:09:09,454 INFO L85 PathProgramCache]: Analyzing trace with hash 1119306556, now seen corresponding path program 1 times [2022-10-17 11:09:09,455 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:09:09,455 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [262459648] [2022-10-17 11:09:09,455 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:09:09,456 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:09:09,477 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:09:09,569 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:09:09,569 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:09:09,569 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [262459648] [2022-10-17 11:09:09,570 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [262459648] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:09:09,570 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:09:09,570 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:09:09,570 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [845816357] [2022-10-17 11:09:09,570 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:09:09,571 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 11:09:09,571 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:09:09,572 INFO L85 PathProgramCache]: Analyzing trace with hash 330425744, now seen corresponding path program 1 times [2022-10-17 11:09:09,572 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:09:09,572 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [121128996] [2022-10-17 11:09:09,572 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:09:09,572 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:09:09,603 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:09:09,670 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:09:09,670 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:09:09,670 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [121128996] [2022-10-17 11:09:09,671 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [121128996] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:09:09,671 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:09:09,671 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:09:09,671 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [975256319] [2022-10-17 11:09:09,671 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:09:09,672 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 11:09:09,672 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 11:09:09,673 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 11:09:09,673 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 11:09:09,673 INFO L87 Difference]: Start difference. First operand 430 states and 646 transitions. cyclomatic complexity: 217 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:09:09,703 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 11:09:09,704 INFO L93 Difference]: Finished difference Result 430 states and 645 transitions. [2022-10-17 11:09:09,704 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 430 states and 645 transitions. [2022-10-17 11:09:09,708 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 363 [2022-10-17 11:09:09,713 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 430 states to 430 states and 645 transitions. [2022-10-17 11:09:09,714 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 430 [2022-10-17 11:09:09,714 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 430 [2022-10-17 11:09:09,715 INFO L73 IsDeterministic]: Start isDeterministic. Operand 430 states and 645 transitions. [2022-10-17 11:09:09,716 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 11:09:09,718 INFO L218 hiAutomatonCegarLoop]: Abstraction has 430 states and 645 transitions. [2022-10-17 11:09:09,719 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 430 states and 645 transitions. [2022-10-17 11:09:09,735 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 430 to 430. [2022-10-17 11:09:09,737 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 430 states, 430 states have (on average 1.5) internal successors, (645), 429 states have internal predecessors, (645), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:09:09,739 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 430 states to 430 states and 645 transitions. [2022-10-17 11:09:09,739 INFO L240 hiAutomatonCegarLoop]: Abstraction has 430 states and 645 transitions. [2022-10-17 11:09:09,740 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 11:09:09,741 INFO L428 stractBuchiCegarLoop]: Abstraction has 430 states and 645 transitions. [2022-10-17 11:09:09,741 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-10-17 11:09:09,741 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 430 states and 645 transitions. [2022-10-17 11:09:09,745 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 363 [2022-10-17 11:09:09,753 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 11:09:09,753 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 11:09:09,756 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:09:09,756 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:09:09,756 INFO L748 eck$LassoCheckResult]: Stem: 2179#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 2162#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 1974#L778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1772#L358 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1773#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 1847#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2093#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2051#L375-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2052#L380-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2079#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2061#L526 assume !(0 == ~M_E~0); 2062#L526-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2094#L531-1 assume !(0 == ~T2_E~0); 2047#L536-1 assume !(0 == ~T3_E~0); 2048#L541-1 assume !(0 == ~T4_E~0); 2043#L546-1 assume !(0 == ~E_M~0); 2044#L551-1 assume !(0 == ~E_1~0); 2020#L556-1 assume !(0 == ~E_2~0); 2021#L561-1 assume !(0 == ~E_3~0); 2031#L566-1 assume 0 == ~E_4~0;~E_4~0 := 1; 2032#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2025#L262 assume 1 == ~m_pc~0; 2026#L263 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2166#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1891#L274 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1892#L649 assume !(0 != activate_threads_~tmp~1#1); 2165#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1978#L281 assume !(1 == ~t1_pc~0); 1979#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1895#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1896#L293 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1954#L657 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1955#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2033#L300 assume 1 == ~t2_pc~0; 2034#L301 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2124#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1948#L312 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1949#L665 assume !(0 != activate_threads_~tmp___1~0#1); 1827#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1828#L319 assume !(1 == ~t3_pc~0); 1785#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1786#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1969#L331 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1970#L673 assume !(0 != activate_threads_~tmp___2~0#1); 1806#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1807#L338 assume 1 == ~t4_pc~0; 1950#L339 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1871#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1885#L350 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1912#L681 assume !(0 != activate_threads_~tmp___3~0#1); 1750#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1751#L584 assume !(1 == ~M_E~0); 1951#L584-2 assume !(1 == ~T1_E~0); 1910#L589-1 assume !(1 == ~T2_E~0); 1911#L594-1 assume !(1 == ~T3_E~0); 1999#L599-1 assume !(1 == ~T4_E~0); 1784#L604-1 assume !(1 == ~E_M~0); 1768#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1769#L614-1 assume !(1 == ~E_2~0); 1884#L619-1 assume !(1 == ~E_3~0); 1968#L624-1 assume !(1 == ~E_4~0); 2053#L629-1 assume { :end_inline_reset_delta_events } true; 2070#L815-2 [2022-10-17 11:09:09,756 INFO L750 eck$LassoCheckResult]: Loop: 2070#L815-2 assume !false; 2071#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2154#L501 assume !false; 2160#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2161#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1889#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2074#L426 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2075#L440 assume !(0 != eval_~tmp~0#1); 2173#L516 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2163#L358-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2000#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2001#L526-5 assume !(0 == ~T1_E~0); 1886#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1887#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1778#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1779#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2057#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2006#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2007#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2100#L566-3 assume !(0 == ~E_4~0); 1900#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1901#L262-18 assume 1 == ~m_pc~0; 2118#L263-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1991#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1882#L274-6 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1883#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1791#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1792#L281-18 assume !(1 == ~t1_pc~0); 2017#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 2036#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2037#L293-6 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2136#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 2132#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2133#L300-18 assume !(1 == ~t2_pc~0); 1780#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 1781#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1844#L312-6 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1861#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2108#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1897#L319-18 assume !(1 == ~t3_pc~0); 1898#L319-20 is_transmit3_triggered_~__retres1~3#1 := 0; 1904#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1920#L331-6 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1957#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2069#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1975#L338-18 assume 1 == ~t4_pc~0; 1976#L339-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1939#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1940#L350-6 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1812#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1813#L681-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1995#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1996#L584-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1808#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1809#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1988#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2009#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2010#L609-3 assume !(1 == ~E_1~0); 2068#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1800#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1801#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2080#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2103#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1878#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1879#L426-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 1926#L834 assume !(0 == start_simulation_~tmp~3#1); 1928#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2087#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2046#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2083#L426-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 2111#L789 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 2134#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2054#L797 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 2055#L847 assume !(0 != start_simulation_~tmp___0~1#1); 2070#L815-2 [2022-10-17 11:09:09,757 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:09:09,757 INFO L85 PathProgramCache]: Analyzing trace with hash 1078631806, now seen corresponding path program 1 times [2022-10-17 11:09:09,757 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:09:09,758 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [563590459] [2022-10-17 11:09:09,758 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:09:09,758 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:09:09,783 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:09:09,822 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:09:09,823 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:09:09,823 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [563590459] [2022-10-17 11:09:09,823 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [563590459] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:09:09,823 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:09:09,824 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:09:09,824 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [862968665] [2022-10-17 11:09:09,824 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:09:09,825 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 11:09:09,825 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:09:09,825 INFO L85 PathProgramCache]: Analyzing trace with hash 330425744, now seen corresponding path program 2 times [2022-10-17 11:09:09,826 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:09:09,826 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [372346033] [2022-10-17 11:09:09,826 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:09:09,826 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:09:09,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:09:09,906 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:09:09,906 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:09:09,906 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [372346033] [2022-10-17 11:09:09,907 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [372346033] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:09:09,907 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:09:09,907 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:09:09,907 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1078755249] [2022-10-17 11:09:09,908 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:09:09,908 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 11:09:09,908 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 11:09:09,909 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 11:09:09,909 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 11:09:09,909 INFO L87 Difference]: Start difference. First operand 430 states and 645 transitions. cyclomatic complexity: 216 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:09:09,932 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 11:09:09,932 INFO L93 Difference]: Finished difference Result 430 states and 644 transitions. [2022-10-17 11:09:09,933 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 430 states and 644 transitions. [2022-10-17 11:09:09,937 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 363 [2022-10-17 11:09:09,941 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 430 states to 430 states and 644 transitions. [2022-10-17 11:09:09,942 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 430 [2022-10-17 11:09:09,942 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 430 [2022-10-17 11:09:09,942 INFO L73 IsDeterministic]: Start isDeterministic. Operand 430 states and 644 transitions. [2022-10-17 11:09:09,944 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 11:09:09,944 INFO L218 hiAutomatonCegarLoop]: Abstraction has 430 states and 644 transitions. [2022-10-17 11:09:09,945 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 430 states and 644 transitions. [2022-10-17 11:09:09,954 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 430 to 430. [2022-10-17 11:09:09,955 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 430 states, 430 states have (on average 1.4976744186046511) internal successors, (644), 429 states have internal predecessors, (644), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:09:09,957 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 430 states to 430 states and 644 transitions. [2022-10-17 11:09:09,958 INFO L240 hiAutomatonCegarLoop]: Abstraction has 430 states and 644 transitions. [2022-10-17 11:09:09,958 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 11:09:09,959 INFO L428 stractBuchiCegarLoop]: Abstraction has 430 states and 644 transitions. [2022-10-17 11:09:09,959 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-10-17 11:09:09,960 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 430 states and 644 transitions. [2022-10-17 11:09:09,963 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 363 [2022-10-17 11:09:09,963 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 11:09:09,963 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 11:09:09,965 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:09:09,965 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:09:09,966 INFO L748 eck$LassoCheckResult]: Stem: 3046#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 3029#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 2841#L778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2639#L358 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2640#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 2714#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2960#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2918#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2919#L380-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2946#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2928#L526 assume !(0 == ~M_E~0); 2929#L526-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2961#L531-1 assume !(0 == ~T2_E~0); 2914#L536-1 assume !(0 == ~T3_E~0); 2915#L541-1 assume !(0 == ~T4_E~0); 2910#L546-1 assume !(0 == ~E_M~0); 2911#L551-1 assume !(0 == ~E_1~0); 2887#L556-1 assume !(0 == ~E_2~0); 2888#L561-1 assume !(0 == ~E_3~0); 2898#L566-1 assume 0 == ~E_4~0;~E_4~0 := 1; 2899#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2892#L262 assume 1 == ~m_pc~0; 2893#L263 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3033#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2758#L274 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2759#L649 assume !(0 != activate_threads_~tmp~1#1); 3032#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2845#L281 assume !(1 == ~t1_pc~0); 2846#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2762#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2763#L293 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2821#L657 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2822#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2900#L300 assume 1 == ~t2_pc~0; 2901#L301 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2991#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2815#L312 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2816#L665 assume !(0 != activate_threads_~tmp___1~0#1); 2694#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2695#L319 assume !(1 == ~t3_pc~0); 2652#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2653#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2836#L331 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2837#L673 assume !(0 != activate_threads_~tmp___2~0#1); 2673#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2674#L338 assume 1 == ~t4_pc~0; 2817#L339 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2738#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2752#L350 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2779#L681 assume !(0 != activate_threads_~tmp___3~0#1); 2617#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2618#L584 assume !(1 == ~M_E~0); 2818#L584-2 assume !(1 == ~T1_E~0); 2777#L589-1 assume !(1 == ~T2_E~0); 2778#L594-1 assume !(1 == ~T3_E~0); 2866#L599-1 assume !(1 == ~T4_E~0); 2651#L604-1 assume !(1 == ~E_M~0); 2635#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2636#L614-1 assume !(1 == ~E_2~0); 2751#L619-1 assume !(1 == ~E_3~0); 2835#L624-1 assume !(1 == ~E_4~0); 2920#L629-1 assume { :end_inline_reset_delta_events } true; 2937#L815-2 [2022-10-17 11:09:09,966 INFO L750 eck$LassoCheckResult]: Loop: 2937#L815-2 assume !false; 2938#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3021#L501 assume !false; 3027#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3028#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2756#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2941#L426 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2942#L440 assume !(0 != eval_~tmp~0#1); 3040#L516 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3030#L358-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2867#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2868#L526-5 assume !(0 == ~T1_E~0); 2753#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2754#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2645#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2646#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2924#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2873#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2874#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2967#L566-3 assume !(0 == ~E_4~0); 2767#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2768#L262-18 assume 1 == ~m_pc~0; 2985#L263-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2858#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2749#L274-6 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2750#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2658#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2659#L281-18 assume !(1 == ~t1_pc~0); 2884#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 2903#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2904#L293-6 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3003#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 2999#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3000#L300-18 assume 1 == ~t2_pc~0; 2882#L301-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2648#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2711#L312-6 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2728#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2975#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2764#L319-18 assume !(1 == ~t3_pc~0); 2765#L319-20 is_transmit3_triggered_~__retres1~3#1 := 0; 2771#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2787#L331-6 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2824#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2936#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2842#L338-18 assume 1 == ~t4_pc~0; 2843#L339-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2806#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2807#L350-6 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2679#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2680#L681-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2862#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2863#L584-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2675#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2676#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2855#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2876#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2877#L609-3 assume !(1 == ~E_1~0); 2935#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2667#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2668#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2947#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2970#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2745#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2746#L426-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 2793#L834 assume !(0 == start_simulation_~tmp~3#1); 2795#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2954#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2913#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2950#L426-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 2978#L789 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 3001#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2921#L797 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 2922#L847 assume !(0 != start_simulation_~tmp___0~1#1); 2937#L815-2 [2022-10-17 11:09:09,967 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:09:09,967 INFO L85 PathProgramCache]: Analyzing trace with hash -308153604, now seen corresponding path program 1 times [2022-10-17 11:09:09,967 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:09:09,968 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [243715363] [2022-10-17 11:09:09,968 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:09:09,968 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:09:09,980 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:09:10,012 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:09:10,012 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:09:10,012 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [243715363] [2022-10-17 11:09:10,013 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [243715363] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:09:10,013 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:09:10,013 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:09:10,013 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [881709670] [2022-10-17 11:09:10,014 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:09:10,014 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 11:09:10,014 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:09:10,015 INFO L85 PathProgramCache]: Analyzing trace with hash 815600463, now seen corresponding path program 1 times [2022-10-17 11:09:10,015 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:09:10,015 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1430492440] [2022-10-17 11:09:10,015 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:09:10,016 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:09:10,029 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:09:10,079 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:09:10,080 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:09:10,080 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1430492440] [2022-10-17 11:09:10,080 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1430492440] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:09:10,080 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:09:10,081 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:09:10,081 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1625976612] [2022-10-17 11:09:10,081 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:09:10,082 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 11:09:10,082 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 11:09:10,082 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 11:09:10,083 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 11:09:10,083 INFO L87 Difference]: Start difference. First operand 430 states and 644 transitions. cyclomatic complexity: 215 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:09:10,097 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 11:09:10,098 INFO L93 Difference]: Finished difference Result 430 states and 643 transitions. [2022-10-17 11:09:10,098 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 430 states and 643 transitions. [2022-10-17 11:09:10,102 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 363 [2022-10-17 11:09:10,106 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 430 states to 430 states and 643 transitions. [2022-10-17 11:09:10,107 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 430 [2022-10-17 11:09:10,107 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 430 [2022-10-17 11:09:10,108 INFO L73 IsDeterministic]: Start isDeterministic. Operand 430 states and 643 transitions. [2022-10-17 11:09:10,108 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 11:09:10,109 INFO L218 hiAutomatonCegarLoop]: Abstraction has 430 states and 643 transitions. [2022-10-17 11:09:10,110 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 430 states and 643 transitions. [2022-10-17 11:09:10,116 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 430 to 430. [2022-10-17 11:09:10,117 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 430 states, 430 states have (on average 1.4953488372093022) internal successors, (643), 429 states have internal predecessors, (643), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:09:10,119 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 430 states to 430 states and 643 transitions. [2022-10-17 11:09:10,120 INFO L240 hiAutomatonCegarLoop]: Abstraction has 430 states and 643 transitions. [2022-10-17 11:09:10,120 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 11:09:10,121 INFO L428 stractBuchiCegarLoop]: Abstraction has 430 states and 643 transitions. [2022-10-17 11:09:10,121 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-10-17 11:09:10,121 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 430 states and 643 transitions. [2022-10-17 11:09:10,125 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 363 [2022-10-17 11:09:10,125 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 11:09:10,125 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 11:09:10,127 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:09:10,127 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:09:10,127 INFO L748 eck$LassoCheckResult]: Stem: 3913#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 3896#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 3711#L778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3506#L358 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3507#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 3581#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3827#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3786#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3787#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3814#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3796#L526 assume !(0 == ~M_E~0); 3797#L526-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3829#L531-1 assume !(0 == ~T2_E~0); 3781#L536-1 assume !(0 == ~T3_E~0); 3782#L541-1 assume !(0 == ~T4_E~0); 3777#L546-1 assume !(0 == ~E_M~0); 3778#L551-1 assume !(0 == ~E_1~0); 3754#L556-1 assume !(0 == ~E_2~0); 3755#L561-1 assume !(0 == ~E_3~0); 3765#L566-1 assume 0 == ~E_4~0;~E_4~0 := 1; 3766#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3759#L262 assume 1 == ~m_pc~0; 3760#L263 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3900#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3625#L274 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3626#L649 assume !(0 != activate_threads_~tmp~1#1); 3899#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3712#L281 assume !(1 == ~t1_pc~0); 3713#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3629#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3630#L293 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3688#L657 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3689#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3767#L300 assume 1 == ~t2_pc~0; 3768#L301 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3858#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3682#L312 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3683#L665 assume !(0 != activate_threads_~tmp___1~0#1); 3561#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3562#L319 assume !(1 == ~t3_pc~0); 3519#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3520#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3703#L331 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3704#L673 assume !(0 != activate_threads_~tmp___2~0#1); 3540#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3541#L338 assume 1 == ~t4_pc~0; 3684#L339 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3605#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3619#L350 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3646#L681 assume !(0 != activate_threads_~tmp___3~0#1); 3484#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3485#L584 assume !(1 == ~M_E~0); 3685#L584-2 assume !(1 == ~T1_E~0); 3644#L589-1 assume !(1 == ~T2_E~0); 3645#L594-1 assume !(1 == ~T3_E~0); 3733#L599-1 assume !(1 == ~T4_E~0); 3518#L604-1 assume !(1 == ~E_M~0); 3502#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 3503#L614-1 assume !(1 == ~E_2~0); 3618#L619-1 assume !(1 == ~E_3~0); 3702#L624-1 assume !(1 == ~E_4~0); 3785#L629-1 assume { :end_inline_reset_delta_events } true; 3804#L815-2 [2022-10-17 11:09:10,128 INFO L750 eck$LassoCheckResult]: Loop: 3804#L815-2 assume !false; 3805#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3888#L501 assume !false; 3894#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3895#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3623#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3808#L426 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3809#L440 assume !(0 != eval_~tmp~0#1); 3907#L516 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3897#L358-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3734#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3735#L526-5 assume !(0 == ~T1_E~0); 3620#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3621#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3512#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3513#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3791#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3740#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3741#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3834#L566-3 assume !(0 == ~E_4~0); 3634#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3635#L262-18 assume 1 == ~m_pc~0; 3852#L263-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3725#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3616#L274-6 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3617#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3525#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3526#L281-18 assume !(1 == ~t1_pc~0); 3751#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 3770#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3771#L293-6 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3870#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 3866#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3867#L300-18 assume 1 == ~t2_pc~0; 3749#L301-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3515#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3578#L312-6 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3595#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3842#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3631#L319-18 assume !(1 == ~t3_pc~0); 3632#L319-20 is_transmit3_triggered_~__retres1~3#1 := 0; 3638#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3654#L331-6 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3691#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3803#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3708#L338-18 assume 1 == ~t4_pc~0; 3709#L339-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3673#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3674#L350-6 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3546#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3547#L681-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3729#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3730#L584-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3542#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3543#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3722#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3743#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3744#L609-3 assume !(1 == ~E_1~0); 3802#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3534#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3535#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3813#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3837#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3612#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3613#L426-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 3660#L834 assume !(0 == start_simulation_~tmp~3#1); 3662#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3821#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3780#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3817#L426-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 3845#L789 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 3868#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3788#L797 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 3789#L847 assume !(0 != start_simulation_~tmp___0~1#1); 3804#L815-2 [2022-10-17 11:09:10,128 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:09:10,129 INFO L85 PathProgramCache]: Analyzing trace with hash -1184172610, now seen corresponding path program 1 times [2022-10-17 11:09:10,129 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:09:10,129 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [806555664] [2022-10-17 11:09:10,129 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:09:10,130 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:09:10,144 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:09:10,179 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:09:10,180 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:09:10,180 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [806555664] [2022-10-17 11:09:10,180 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [806555664] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:09:10,181 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:09:10,181 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-10-17 11:09:10,181 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1310556256] [2022-10-17 11:09:10,181 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:09:10,182 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 11:09:10,182 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:09:10,182 INFO L85 PathProgramCache]: Analyzing trace with hash 815600463, now seen corresponding path program 2 times [2022-10-17 11:09:10,183 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:09:10,183 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2141170665] [2022-10-17 11:09:10,183 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:09:10,183 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:09:10,195 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:09:10,231 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:09:10,231 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:09:10,231 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2141170665] [2022-10-17 11:09:10,232 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2141170665] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:09:10,232 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:09:10,232 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:09:10,232 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1140814385] [2022-10-17 11:09:10,233 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:09:10,233 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 11:09:10,233 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 11:09:10,234 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 11:09:10,234 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 11:09:10,234 INFO L87 Difference]: Start difference. First operand 430 states and 643 transitions. cyclomatic complexity: 214 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:09:10,262 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 11:09:10,262 INFO L93 Difference]: Finished difference Result 430 states and 638 transitions. [2022-10-17 11:09:10,262 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 430 states and 638 transitions. [2022-10-17 11:09:10,266 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 363 [2022-10-17 11:09:10,270 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 430 states to 430 states and 638 transitions. [2022-10-17 11:09:10,271 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 430 [2022-10-17 11:09:10,271 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 430 [2022-10-17 11:09:10,272 INFO L73 IsDeterministic]: Start isDeterministic. Operand 430 states and 638 transitions. [2022-10-17 11:09:10,272 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 11:09:10,273 INFO L218 hiAutomatonCegarLoop]: Abstraction has 430 states and 638 transitions. [2022-10-17 11:09:10,274 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 430 states and 638 transitions. [2022-10-17 11:09:10,309 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 430 to 430. [2022-10-17 11:09:10,310 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 430 states, 430 states have (on average 1.4837209302325582) internal successors, (638), 429 states have internal predecessors, (638), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:09:10,312 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 430 states to 430 states and 638 transitions. [2022-10-17 11:09:10,313 INFO L240 hiAutomatonCegarLoop]: Abstraction has 430 states and 638 transitions. [2022-10-17 11:09:10,313 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 11:09:10,314 INFO L428 stractBuchiCegarLoop]: Abstraction has 430 states and 638 transitions. [2022-10-17 11:09:10,314 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-10-17 11:09:10,314 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 430 states and 638 transitions. [2022-10-17 11:09:10,317 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 363 [2022-10-17 11:09:10,317 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 11:09:10,318 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 11:09:10,319 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:09:10,319 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:09:10,320 INFO L748 eck$LassoCheckResult]: Stem: 4780#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 4763#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 4578#L778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4373#L358 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4374#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 4448#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4694#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4652#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4653#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4681#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4662#L526 assume !(0 == ~M_E~0); 4663#L526-2 assume !(0 == ~T1_E~0); 4696#L531-1 assume !(0 == ~T2_E~0); 4648#L536-1 assume !(0 == ~T3_E~0); 4649#L541-1 assume !(0 == ~T4_E~0); 4644#L546-1 assume !(0 == ~E_M~0); 4645#L551-1 assume !(0 == ~E_1~0); 4621#L556-1 assume !(0 == ~E_2~0); 4622#L561-1 assume !(0 == ~E_3~0); 4632#L566-1 assume 0 == ~E_4~0;~E_4~0 := 1; 4633#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4626#L262 assume 1 == ~m_pc~0; 4627#L263 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4767#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4494#L274 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4495#L649 assume !(0 != activate_threads_~tmp~1#1); 4766#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4579#L281 assume !(1 == ~t1_pc~0); 4580#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4496#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4497#L293 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4555#L657 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4556#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4634#L300 assume 1 == ~t2_pc~0; 4635#L301 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4725#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4549#L312 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4550#L665 assume !(0 != activate_threads_~tmp___1~0#1); 4428#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4429#L319 assume !(1 == ~t3_pc~0); 4386#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4387#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4570#L331 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4571#L673 assume !(0 != activate_threads_~tmp___2~0#1); 4407#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4408#L338 assume 1 == ~t4_pc~0; 4551#L339 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4472#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4486#L350 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4513#L681 assume !(0 != activate_threads_~tmp___3~0#1); 4351#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4352#L584 assume !(1 == ~M_E~0); 4552#L584-2 assume !(1 == ~T1_E~0); 4511#L589-1 assume !(1 == ~T2_E~0); 4512#L594-1 assume !(1 == ~T3_E~0); 4600#L599-1 assume !(1 == ~T4_E~0); 4385#L604-1 assume !(1 == ~E_M~0); 4369#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 4370#L614-1 assume !(1 == ~E_2~0); 4485#L619-1 assume !(1 == ~E_3~0); 4569#L624-1 assume !(1 == ~E_4~0); 4654#L629-1 assume { :end_inline_reset_delta_events } true; 4671#L815-2 [2022-10-17 11:09:10,320 INFO L750 eck$LassoCheckResult]: Loop: 4671#L815-2 assume !false; 4672#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4755#L501 assume !false; 4761#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4762#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 4490#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4675#L426 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 4676#L440 assume !(0 != eval_~tmp~0#1); 4774#L516 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4764#L358-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4601#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4602#L526-5 assume !(0 == ~T1_E~0); 4487#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4488#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4381#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4382#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4658#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4607#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4608#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4701#L566-3 assume !(0 == ~E_4~0); 4501#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4502#L262-18 assume !(1 == ~m_pc~0); 4590#L262-20 is_master_triggered_~__retres1~0#1 := 0; 4591#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4483#L274-6 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4484#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4392#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4393#L281-18 assume !(1 == ~t1_pc~0); 4618#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 4637#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4638#L293-6 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4737#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 4733#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4734#L300-18 assume 1 == ~t2_pc~0; 4614#L301-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4380#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4445#L312-6 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4462#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4709#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4498#L319-18 assume !(1 == ~t3_pc~0); 4499#L319-20 is_transmit3_triggered_~__retres1~3#1 := 0; 4505#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4521#L331-6 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4558#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4670#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4575#L338-18 assume 1 == ~t4_pc~0; 4576#L339-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4540#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4541#L350-6 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4413#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4414#L681-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4594#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4595#L584-5 assume !(1 == ~T1_E~0); 4409#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4410#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4589#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4609#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4610#L609-3 assume !(1 == ~E_1~0); 4669#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4401#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4402#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4680#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4704#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 4479#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4480#L426-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 4527#L834 assume !(0 == start_simulation_~tmp~3#1); 4529#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4688#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 4647#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4684#L426-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 4712#L789 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 4735#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4655#L797 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 4656#L847 assume !(0 != start_simulation_~tmp___0~1#1); 4671#L815-2 [2022-10-17 11:09:10,321 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:09:10,321 INFO L85 PathProgramCache]: Analyzing trace with hash 1082208576, now seen corresponding path program 1 times [2022-10-17 11:09:10,321 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:09:10,321 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [562194153] [2022-10-17 11:09:10,322 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:09:10,322 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:09:10,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:09:10,386 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:09:10,387 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:09:10,387 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [562194153] [2022-10-17 11:09:10,387 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [562194153] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:09:10,388 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:09:10,388 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:09:10,388 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1680378951] [2022-10-17 11:09:10,388 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:09:10,389 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 11:09:10,389 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:09:10,389 INFO L85 PathProgramCache]: Analyzing trace with hash 760676686, now seen corresponding path program 1 times [2022-10-17 11:09:10,390 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:09:10,390 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1276982111] [2022-10-17 11:09:10,390 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:09:10,390 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:09:10,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:09:10,433 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:09:10,434 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:09:10,434 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1276982111] [2022-10-17 11:09:10,434 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1276982111] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:09:10,435 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:09:10,435 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:09:10,435 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1101681071] [2022-10-17 11:09:10,435 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:09:10,436 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 11:09:10,436 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 11:09:10,437 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-10-17 11:09:10,437 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-10-17 11:09:10,437 INFO L87 Difference]: Start difference. First operand 430 states and 638 transitions. cyclomatic complexity: 209 Second operand has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:09:10,548 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 11:09:10,549 INFO L93 Difference]: Finished difference Result 720 states and 1066 transitions. [2022-10-17 11:09:10,549 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 720 states and 1066 transitions. [2022-10-17 11:09:10,556 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 642 [2022-10-17 11:09:10,562 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 720 states to 720 states and 1066 transitions. [2022-10-17 11:09:10,562 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 720 [2022-10-17 11:09:10,563 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 720 [2022-10-17 11:09:10,564 INFO L73 IsDeterministic]: Start isDeterministic. Operand 720 states and 1066 transitions. [2022-10-17 11:09:10,565 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 11:09:10,565 INFO L218 hiAutomatonCegarLoop]: Abstraction has 720 states and 1066 transitions. [2022-10-17 11:09:10,567 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 720 states and 1066 transitions. [2022-10-17 11:09:10,579 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 720 to 719. [2022-10-17 11:09:10,581 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 719 states, 719 states have (on average 1.4812239221140473) internal successors, (1065), 718 states have internal predecessors, (1065), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:09:10,584 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 719 states to 719 states and 1065 transitions. [2022-10-17 11:09:10,585 INFO L240 hiAutomatonCegarLoop]: Abstraction has 719 states and 1065 transitions. [2022-10-17 11:09:10,585 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-10-17 11:09:10,586 INFO L428 stractBuchiCegarLoop]: Abstraction has 719 states and 1065 transitions. [2022-10-17 11:09:10,586 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-10-17 11:09:10,586 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 719 states and 1065 transitions. [2022-10-17 11:09:10,591 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 642 [2022-10-17 11:09:10,591 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 11:09:10,591 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 11:09:10,593 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:09:10,593 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:09:10,593 INFO L748 eck$LassoCheckResult]: Stem: 5956#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 5935#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 5738#L778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5533#L358 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5534#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 5608#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5859#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5816#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5817#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5845#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5826#L526 assume !(0 == ~M_E~0); 5827#L526-2 assume !(0 == ~T1_E~0); 5861#L531-1 assume !(0 == ~T2_E~0); 5812#L536-1 assume !(0 == ~T3_E~0); 5813#L541-1 assume !(0 == ~T4_E~0); 5808#L546-1 assume !(0 == ~E_M~0); 5809#L551-1 assume !(0 == ~E_1~0); 5785#L556-1 assume !(0 == ~E_2~0); 5786#L561-1 assume !(0 == ~E_3~0); 5796#L566-1 assume !(0 == ~E_4~0); 5797#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5790#L262 assume 1 == ~m_pc~0; 5791#L263 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5942#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5654#L274 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5655#L649 assume !(0 != activate_threads_~tmp~1#1); 5941#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5739#L281 assume !(1 == ~t1_pc~0); 5740#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5656#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5657#L293 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5715#L657 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5716#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5798#L300 assume 1 == ~t2_pc~0; 5799#L301 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5891#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5709#L312 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5710#L665 assume !(0 != activate_threads_~tmp___1~0#1); 5588#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5589#L319 assume !(1 == ~t3_pc~0); 5546#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5547#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5730#L331 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5731#L673 assume !(0 != activate_threads_~tmp___2~0#1); 5567#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5568#L338 assume 1 == ~t4_pc~0; 5711#L339 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5632#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5646#L350 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5673#L681 assume !(0 != activate_threads_~tmp___3~0#1); 5511#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5512#L584 assume 1 == ~M_E~0;~M_E~0 := 2; 5712#L584-2 assume !(1 == ~T1_E~0); 5671#L589-1 assume !(1 == ~T2_E~0); 5672#L594-1 assume !(1 == ~T3_E~0); 5763#L599-1 assume !(1 == ~T4_E~0); 5545#L604-1 assume !(1 == ~E_M~0); 5529#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 5530#L614-1 assume !(1 == ~E_2~0); 5645#L619-1 assume !(1 == ~E_3~0); 5729#L624-1 assume !(1 == ~E_4~0); 5818#L629-1 assume { :end_inline_reset_delta_events } true; 5835#L815-2 [2022-10-17 11:09:10,594 INFO L750 eck$LassoCheckResult]: Loop: 5835#L815-2 assume !false; 5836#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5926#L501 assume !false; 5933#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 5934#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 5650#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 5839#L426 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 5840#L440 assume !(0 != eval_~tmp~0#1); 5950#L516 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5937#L358-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5938#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5885#L526-5 assume !(0 == ~T1_E~0); 5647#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5648#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5541#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5542#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5822#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5770#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5771#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5866#L566-3 assume !(0 == ~E_4~0); 5661#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5662#L262-18 assume !(1 == ~m_pc~0); 5753#L262-20 is_master_triggered_~__retres1~0#1 := 0; 5754#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5643#L274-6 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5644#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5552#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5553#L281-18 assume !(1 == ~t1_pc~0); 5782#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 5801#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5802#L293-6 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5905#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 5901#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5902#L300-18 assume 1 == ~t2_pc~0; 5777#L301-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5540#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5605#L312-6 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5622#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5874#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5658#L319-18 assume !(1 == ~t3_pc~0); 5659#L319-20 is_transmit3_triggered_~__retres1~3#1 := 0; 5665#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5681#L331-6 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5718#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5834#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5735#L338-18 assume 1 == ~t4_pc~0; 5736#L339-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6081#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6079#L350-6 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6077#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6074#L681-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6072#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5757#L584-5 assume !(1 == ~T1_E~0); 6069#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5750#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5751#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5772#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5773#L609-3 assume !(1 == ~E_1~0); 5833#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5561#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5562#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5844#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 5869#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 5639#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 5640#L426-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 6032#L834 assume !(0 == start_simulation_~tmp~3#1); 5746#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 5852#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 5811#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 5848#L426-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 5877#L789 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 5903#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5819#L797 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 5820#L847 assume !(0 != start_simulation_~tmp___0~1#1); 5835#L815-2 [2022-10-17 11:09:10,594 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:09:10,595 INFO L85 PathProgramCache]: Analyzing trace with hash -516249280, now seen corresponding path program 1 times [2022-10-17 11:09:10,595 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:09:10,595 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [199721573] [2022-10-17 11:09:10,595 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:09:10,596 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:09:10,606 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:09:10,634 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:09:10,635 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:09:10,635 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [199721573] [2022-10-17 11:09:10,635 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [199721573] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:09:10,635 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:09:10,636 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-10-17 11:09:10,636 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1827578518] [2022-10-17 11:09:10,636 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:09:10,637 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 11:09:10,637 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:09:10,637 INFO L85 PathProgramCache]: Analyzing trace with hash 760676686, now seen corresponding path program 2 times [2022-10-17 11:09:10,637 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:09:10,638 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [273881630] [2022-10-17 11:09:10,638 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:09:10,638 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:09:10,649 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:09:10,676 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:09:10,677 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:09:10,677 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [273881630] [2022-10-17 11:09:10,677 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [273881630] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:09:10,678 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:09:10,678 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:09:10,678 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [776568385] [2022-10-17 11:09:10,678 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:09:10,679 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 11:09:10,679 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 11:09:10,679 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 11:09:10,680 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 11:09:10,680 INFO L87 Difference]: Start difference. First operand 719 states and 1065 transitions. cyclomatic complexity: 348 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:09:10,759 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 11:09:10,759 INFO L93 Difference]: Finished difference Result 1332 states and 1946 transitions. [2022-10-17 11:09:10,760 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1332 states and 1946 transitions. [2022-10-17 11:09:10,771 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1254 [2022-10-17 11:09:10,784 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1332 states to 1332 states and 1946 transitions. [2022-10-17 11:09:10,784 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1332 [2022-10-17 11:09:10,786 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1332 [2022-10-17 11:09:10,786 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1332 states and 1946 transitions. [2022-10-17 11:09:10,789 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 11:09:10,789 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1332 states and 1946 transitions. [2022-10-17 11:09:10,791 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1332 states and 1946 transitions. [2022-10-17 11:09:10,816 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1332 to 1264. [2022-10-17 11:09:10,819 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1264 states, 1264 states have (on average 1.4651898734177216) internal successors, (1852), 1263 states have internal predecessors, (1852), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:09:10,826 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1264 states to 1264 states and 1852 transitions. [2022-10-17 11:09:10,826 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1264 states and 1852 transitions. [2022-10-17 11:09:10,827 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 11:09:10,827 INFO L428 stractBuchiCegarLoop]: Abstraction has 1264 states and 1852 transitions. [2022-10-17 11:09:10,828 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-10-17 11:09:10,828 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1264 states and 1852 transitions. [2022-10-17 11:09:10,837 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1186 [2022-10-17 11:09:10,837 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 11:09:10,837 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 11:09:10,838 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:09:10,838 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:09:10,839 INFO L748 eck$LassoCheckResult]: Stem: 8132#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 8072#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 7804#L778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7591#L358 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7592#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 7669#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7947#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7891#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7892#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7926#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7903#L526 assume !(0 == ~M_E~0); 7904#L526-2 assume !(0 == ~T1_E~0); 7948#L531-1 assume !(0 == ~T2_E~0); 7887#L536-1 assume !(0 == ~T3_E~0); 7888#L541-1 assume !(0 == ~T4_E~0); 7883#L546-1 assume !(0 == ~E_M~0); 7884#L551-1 assume !(0 == ~E_1~0); 7859#L556-1 assume !(0 == ~E_2~0); 7860#L561-1 assume !(0 == ~E_3~0); 7869#L566-1 assume !(0 == ~E_4~0); 7870#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7864#L262 assume !(1 == ~m_pc~0); 7865#L262-2 is_master_triggered_~__retres1~0#1 := 0; 8088#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7712#L274 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7713#L649 assume !(0 != activate_threads_~tmp~1#1); 8085#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7808#L281 assume !(1 == ~t1_pc~0); 7809#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7716#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7717#L293 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7780#L657 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7781#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7871#L300 assume 1 == ~t2_pc~0; 7872#L301 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7987#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7774#L312 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7775#L665 assume !(0 != activate_threads_~tmp___1~0#1); 7647#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7648#L319 assume !(1 == ~t3_pc~0); 7604#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 7605#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7799#L331 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7800#L673 assume !(0 != activate_threads_~tmp___2~0#1); 7626#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7627#L338 assume 1 == ~t4_pc~0; 7776#L339 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7692#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7706#L350 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7733#L681 assume !(0 != activate_threads_~tmp___3~0#1); 7569#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7570#L584 assume 1 == ~M_E~0;~M_E~0 := 2; 7777#L584-2 assume !(1 == ~T1_E~0); 7731#L589-1 assume !(1 == ~T2_E~0); 7732#L594-1 assume !(1 == ~T3_E~0); 7831#L599-1 assume !(1 == ~T4_E~0); 7603#L604-1 assume !(1 == ~E_M~0); 7587#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 7588#L614-1 assume !(1 == ~E_2~0); 7705#L619-1 assume !(1 == ~E_3~0); 7798#L624-1 assume !(1 == ~E_4~0); 7893#L629-1 assume { :end_inline_reset_delta_events } true; 8673#L815-2 [2022-10-17 11:09:10,839 INFO L750 eck$LassoCheckResult]: Loop: 8673#L815-2 assume !false; 8094#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8054#L501 assume !false; 8069#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 8070#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 8122#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 8123#L426 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 8603#L440 assume !(0 != eval_~tmp~0#1); 8106#L516 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8107#L358-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8602#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7978#L526-5 assume !(0 == ~T1_E~0); 7707#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7708#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8101#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7898#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7899#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7844#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7845#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8027#L566-3 assume !(0 == ~E_4~0); 8028#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7976#L262-18 assume !(1 == ~m_pc~0); 7977#L262-20 is_master_triggered_~__retres1~0#1 := 0; 8800#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7703#L274-6 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7704#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8079#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8796#L281-18 assume 1 == ~t1_pc~0; 8093#L282-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7874#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7875#L293-6 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 8789#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 8003#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8004#L300-18 assume 1 == ~t2_pc~0; 8787#L301-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7665#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7666#L312-6 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7682#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7966#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7718#L319-18 assume !(1 == ~t3_pc~0); 7719#L319-20 is_transmit3_triggered_~__retres1~3#1 := 0; 7725#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7741#L331-6 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7934#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7913#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7805#L338-18 assume 1 == ~t4_pc~0; 7806#L339-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7761#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7762#L350-6 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8761#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8760#L681-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7827#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7828#L584-5 assume !(1 == ~T1_E~0); 7999#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8733#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8753#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8371#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8372#L609-3 assume !(1 == ~E_1~0); 8351#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8352#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8347#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8348#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 8343#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 8340#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 8016#L426-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 8017#L834 assume !(0 == start_simulation_~tmp~3#1); 7816#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 7938#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 7932#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 7933#L426-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 8005#L789 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 8006#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7894#L797 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 7895#L847 assume !(0 != start_simulation_~tmp___0~1#1); 8673#L815-2 [2022-10-17 11:09:10,840 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:09:10,840 INFO L85 PathProgramCache]: Analyzing trace with hash -1001423999, now seen corresponding path program 1 times [2022-10-17 11:09:10,840 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:09:10,841 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1416894831] [2022-10-17 11:09:10,841 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:09:10,841 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:09:10,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:09:10,899 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:09:10,900 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:09:10,900 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1416894831] [2022-10-17 11:09:10,900 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1416894831] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:09:10,900 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:09:10,900 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-10-17 11:09:10,901 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1918234935] [2022-10-17 11:09:10,901 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:09:10,901 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 11:09:10,902 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:09:10,902 INFO L85 PathProgramCache]: Analyzing trace with hash -1640848435, now seen corresponding path program 1 times [2022-10-17 11:09:10,902 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:09:10,902 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1690469624] [2022-10-17 11:09:10,902 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:09:10,903 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:09:10,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:09:10,941 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:09:10,941 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:09:10,942 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1690469624] [2022-10-17 11:09:10,942 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1690469624] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:09:10,942 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:09:10,942 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:09:10,942 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [385489318] [2022-10-17 11:09:10,943 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:09:10,943 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 11:09:10,943 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 11:09:10,944 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-10-17 11:09:10,944 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-10-17 11:09:10,944 INFO L87 Difference]: Start difference. First operand 1264 states and 1852 transitions. cyclomatic complexity: 592 Second operand has 5 states, 5 states have (on average 12.4) internal successors, (62), 5 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:09:11,146 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 11:09:11,146 INFO L93 Difference]: Finished difference Result 3385 states and 4947 transitions. [2022-10-17 11:09:11,146 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3385 states and 4947 transitions. [2022-10-17 11:09:11,180 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3214 [2022-10-17 11:09:11,250 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3385 states to 3385 states and 4947 transitions. [2022-10-17 11:09:11,250 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3385 [2022-10-17 11:09:11,254 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3385 [2022-10-17 11:09:11,255 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3385 states and 4947 transitions. [2022-10-17 11:09:11,260 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 11:09:11,261 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3385 states and 4947 transitions. [2022-10-17 11:09:11,265 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3385 states and 4947 transitions. [2022-10-17 11:09:11,306 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3385 to 1333. [2022-10-17 11:09:11,309 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1333 states, 1333 states have (on average 1.4411102775693923) internal successors, (1921), 1332 states have internal predecessors, (1921), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:09:11,316 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1333 states to 1333 states and 1921 transitions. [2022-10-17 11:09:11,317 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1333 states and 1921 transitions. [2022-10-17 11:09:11,317 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-10-17 11:09:11,321 INFO L428 stractBuchiCegarLoop]: Abstraction has 1333 states and 1921 transitions. [2022-10-17 11:09:11,321 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-10-17 11:09:11,322 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1333 states and 1921 transitions. [2022-10-17 11:09:11,331 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1252 [2022-10-17 11:09:11,332 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 11:09:11,332 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 11:09:11,333 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:09:11,333 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:09:11,334 INFO L748 eck$LassoCheckResult]: Stem: 12800#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 12725#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 12466#L778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12253#L358 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12254#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 12332#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12609#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12553#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12554#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12591#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12564#L526 assume !(0 == ~M_E~0); 12565#L526-2 assume !(0 == ~T1_E~0); 12610#L531-1 assume !(0 == ~T2_E~0); 12549#L536-1 assume !(0 == ~T3_E~0); 12550#L541-1 assume !(0 == ~T4_E~0); 12545#L546-1 assume !(0 == ~E_M~0); 12546#L551-1 assume !(0 == ~E_1~0); 12522#L556-1 assume !(0 == ~E_2~0); 12523#L561-1 assume !(0 == ~E_3~0); 12532#L566-1 assume !(0 == ~E_4~0); 12533#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12527#L262 assume !(1 == ~m_pc~0); 12528#L262-2 is_master_triggered_~__retres1~0#1 := 0; 12740#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12376#L274 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 12377#L649 assume !(0 != activate_threads_~tmp~1#1); 12736#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12470#L281 assume !(1 == ~t1_pc~0); 12471#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12380#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12381#L293 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 12441#L657 assume !(0 != activate_threads_~tmp___0~0#1); 12442#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12534#L300 assume 1 == ~t2_pc~0; 12535#L301 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12653#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12435#L312 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 12436#L665 assume !(0 != activate_threads_~tmp___1~0#1); 12309#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12310#L319 assume !(1 == ~t3_pc~0); 12266#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 12267#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12460#L331 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12461#L673 assume !(0 != activate_threads_~tmp___2~0#1); 12288#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12289#L338 assume 1 == ~t4_pc~0; 12437#L339 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12355#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12370#L350 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12397#L681 assume !(0 != activate_threads_~tmp___3~0#1); 12231#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12232#L584 assume 1 == ~M_E~0;~M_E~0 := 2; 12438#L584-2 assume !(1 == ~T1_E~0); 12395#L589-1 assume !(1 == ~T2_E~0); 12396#L594-1 assume !(1 == ~T3_E~0); 12496#L599-1 assume !(1 == ~T4_E~0); 12265#L604-1 assume !(1 == ~E_M~0); 12249#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 12250#L614-1 assume !(1 == ~E_2~0); 13405#L619-1 assume !(1 == ~E_3~0); 13404#L624-1 assume !(1 == ~E_4~0); 12555#L629-1 assume { :end_inline_reset_delta_events } true; 12575#L815-2 [2022-10-17 11:09:11,334 INFO L750 eck$LassoCheckResult]: Loop: 12575#L815-2 assume !false; 13390#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13389#L501 assume !false; 13388#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 12797#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 12374#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 12584#L426 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 12585#L440 assume !(0 != eval_~tmp~0#1); 12764#L516 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12728#L358-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12729#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13353#L526-5 assume !(0 == ~T1_E~0); 13549#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13548#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13547#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13546#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 13545#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13544#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13543#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13542#L566-3 assume !(0 == ~E_4~0); 13541#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12642#L262-18 assume !(1 == ~m_pc~0); 12643#L262-20 is_master_triggered_~__retres1~0#1 := 0; 12666#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12667#L274-6 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 12731#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12732#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12518#L281-18 assume !(1 == ~t1_pc~0); 12519#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 13540#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13538#L293-6 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 13535#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 13534#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13533#L300-18 assume 1 == ~t2_pc~0; 12515#L301-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12262#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12329#L312-6 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 12345#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12628#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12382#L319-18 assume 1 == ~t3_pc~0; 12384#L320-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12389#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12405#L331-6 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12444#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12574#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12467#L338-18 assume 1 == ~t4_pc~0; 12468#L339-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12516#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13497#L350-6 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13495#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13494#L681-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13493#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12492#L584-5 assume !(1 == ~T1_E~0); 13492#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13491#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13490#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 13489#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 13488#L609-3 assume !(1 == ~E_1~0); 13487#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13486#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13485#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12592#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 12631#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 12362#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 12363#L426-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 12677#L834 assume !(0 == start_simulation_~tmp~3#1); 12479#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 12601#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 12548#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 12597#L426-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 12632#L789 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 12670#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12557#L797 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 12558#L847 assume !(0 != start_simulation_~tmp___0~1#1); 12575#L815-2 [2022-10-17 11:09:11,335 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:09:11,335 INFO L85 PathProgramCache]: Analyzing trace with hash -299824125, now seen corresponding path program 1 times [2022-10-17 11:09:11,335 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:09:11,336 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [338632559] [2022-10-17 11:09:11,336 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:09:11,336 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:09:11,352 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:09:11,415 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:09:11,415 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:09:11,415 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [338632559] [2022-10-17 11:09:11,416 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [338632559] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:09:11,416 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:09:11,416 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:09:11,416 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1349464874] [2022-10-17 11:09:11,416 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:09:11,417 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 11:09:11,418 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:09:11,418 INFO L85 PathProgramCache]: Analyzing trace with hash -290772403, now seen corresponding path program 1 times [2022-10-17 11:09:11,418 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:09:11,419 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [102748702] [2022-10-17 11:09:11,419 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:09:11,419 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:09:11,432 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:09:11,498 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:09:11,499 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:09:11,499 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [102748702] [2022-10-17 11:09:11,499 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [102748702] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:09:11,499 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:09:11,499 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:09:11,500 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1867423918] [2022-10-17 11:09:11,500 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:09:11,500 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 11:09:11,501 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 11:09:11,501 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-10-17 11:09:11,501 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-10-17 11:09:11,502 INFO L87 Difference]: Start difference. First operand 1333 states and 1921 transitions. cyclomatic complexity: 592 Second operand has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:09:11,668 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 11:09:11,668 INFO L93 Difference]: Finished difference Result 3046 states and 4336 transitions. [2022-10-17 11:09:11,669 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3046 states and 4336 transitions. [2022-10-17 11:09:11,697 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 2876 [2022-10-17 11:09:11,725 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3046 states to 3046 states and 4336 transitions. [2022-10-17 11:09:11,725 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3046 [2022-10-17 11:09:11,729 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3046 [2022-10-17 11:09:11,729 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3046 states and 4336 transitions. [2022-10-17 11:09:11,734 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 11:09:11,734 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3046 states and 4336 transitions. [2022-10-17 11:09:11,739 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3046 states and 4336 transitions. [2022-10-17 11:09:11,788 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3046 to 2398. [2022-10-17 11:09:11,794 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2398 states, 2398 states have (on average 1.4336947456213511) internal successors, (3438), 2397 states have internal predecessors, (3438), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:09:11,851 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2398 states to 2398 states and 3438 transitions. [2022-10-17 11:09:11,852 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2398 states and 3438 transitions. [2022-10-17 11:09:11,852 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-10-17 11:09:11,853 INFO L428 stractBuchiCegarLoop]: Abstraction has 2398 states and 3438 transitions. [2022-10-17 11:09:11,854 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-10-17 11:09:11,854 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2398 states and 3438 transitions. [2022-10-17 11:09:11,871 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2316 [2022-10-17 11:09:11,871 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 11:09:11,871 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 11:09:11,873 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:09:11,873 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:09:11,873 INFO L748 eck$LassoCheckResult]: Stem: 17138#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 17099#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 16858#L778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16640#L358 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16641#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 16717#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16996#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16943#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16944#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16979#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16954#L526 assume !(0 == ~M_E~0); 16955#L526-2 assume !(0 == ~T1_E~0); 16997#L531-1 assume !(0 == ~T2_E~0); 16939#L536-1 assume !(0 == ~T3_E~0); 16940#L541-1 assume !(0 == ~T4_E~0); 16935#L546-1 assume !(0 == ~E_M~0); 16936#L551-1 assume !(0 == ~E_1~0); 16912#L556-1 assume !(0 == ~E_2~0); 16913#L561-1 assume !(0 == ~E_3~0); 16922#L566-1 assume !(0 == ~E_4~0); 16923#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16917#L262 assume !(1 == ~m_pc~0); 16918#L262-2 is_master_triggered_~__retres1~0#1 := 0; 17111#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16762#L274 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 16763#L649 assume !(0 != activate_threads_~tmp~1#1); 17107#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16862#L281 assume !(1 == ~t1_pc~0); 16863#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 17118#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16976#L293 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 16830#L657 assume !(0 != activate_threads_~tmp___0~0#1); 16831#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16924#L300 assume !(1 == ~t2_pc~0); 16925#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 17037#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16823#L312 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 16824#L665 assume !(0 != activate_threads_~tmp___1~0#1); 16696#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16697#L319 assume !(1 == ~t3_pc~0); 16654#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 16655#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16851#L331 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 16852#L673 assume !(0 != activate_threads_~tmp___2~0#1); 16675#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16676#L338 assume 1 == ~t4_pc~0; 16825#L339 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 16741#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16756#L350 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16783#L681 assume !(0 != activate_threads_~tmp___3~0#1); 16620#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16621#L584 assume 1 == ~M_E~0;~M_E~0 := 2; 16826#L584-2 assume !(1 == ~T1_E~0); 16827#L589-1 assume !(1 == ~T2_E~0); 17028#L594-1 assume !(1 == ~T3_E~0); 17029#L599-1 assume !(1 == ~T4_E~0); 16652#L604-1 assume !(1 == ~E_M~0); 16653#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 16754#L614-1 assume !(1 == ~E_2~0); 16755#L619-1 assume !(1 == ~E_3~0); 16945#L624-1 assume !(1 == ~E_4~0); 16946#L629-1 assume { :end_inline_reset_delta_events } true; 18741#L815-2 [2022-10-17 11:09:11,874 INFO L750 eck$LassoCheckResult]: Loop: 18741#L815-2 assume !false; 18730#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 18728#L501 assume !false; 18726#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 18724#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 18718#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 18717#L426 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 18715#L440 assume !(0 != eval_~tmp~0#1); 18716#L516 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19006#L358-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19004#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 19001#L526-5 assume !(0 == ~T1_E~0); 18999#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 18997#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18994#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18992#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 18990#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 18989#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 18987#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 18984#L566-3 assume !(0 == ~E_4~0); 18983#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18982#L262-18 assume !(1 == ~m_pc~0); 18981#L262-20 is_master_triggered_~__retres1~0#1 := 0; 18980#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18924#L274-6 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 18923#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18922#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18921#L281-18 assume !(1 == ~t1_pc~0); 18918#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 18917#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18916#L293-6 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 18914#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 18912#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18910#L300-18 assume !(1 == ~t2_pc~0); 17498#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 18907#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18904#L312-6 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 18902#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18900#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18899#L319-18 assume !(1 == ~t3_pc~0); 18896#L319-20 is_transmit3_triggered_~__retres1~3#1 := 0; 18893#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18891#L331-6 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 18889#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 18888#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18886#L338-18 assume 1 == ~t4_pc~0; 18883#L339-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 18881#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18879#L350-6 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 18877#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 16928#L681-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16929#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 16883#L584-5 assume !(1 == ~T1_E~0); 17052#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16874#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16875#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18804#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 18803#L609-3 assume !(1 == ~E_1~0); 18802#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 18801#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 18800#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16977#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 18798#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 18794#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 18793#L426-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 18792#L834 assume !(0 == start_simulation_~tmp~3#1); 16868#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 18787#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 18784#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 18781#L426-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 18780#L789 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 18778#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18776#L797 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 18743#L847 assume !(0 != start_simulation_~tmp___0~1#1); 18741#L815-2 [2022-10-17 11:09:11,876 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:09:11,876 INFO L85 PathProgramCache]: Analyzing trace with hash -1271498812, now seen corresponding path program 1 times [2022-10-17 11:09:11,877 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:09:11,877 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [69640220] [2022-10-17 11:09:11,877 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:09:11,877 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:09:11,889 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:09:11,934 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:09:11,935 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:09:11,935 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [69640220] [2022-10-17 11:09:11,937 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [69640220] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:09:11,940 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:09:11,940 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-10-17 11:09:11,941 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2005085194] [2022-10-17 11:09:11,941 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:09:11,942 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 11:09:11,943 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:09:11,943 INFO L85 PathProgramCache]: Analyzing trace with hash 275501967, now seen corresponding path program 1 times [2022-10-17 11:09:11,943 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:09:11,943 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [497092924] [2022-10-17 11:09:11,943 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:09:11,944 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:09:11,954 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:09:11,982 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:09:11,983 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:09:11,983 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [497092924] [2022-10-17 11:09:11,983 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [497092924] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:09:11,983 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:09:11,983 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:09:11,983 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [376801199] [2022-10-17 11:09:11,984 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:09:11,984 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 11:09:11,984 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 11:09:11,985 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 11:09:11,985 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 11:09:11,985 INFO L87 Difference]: Start difference. First operand 2398 states and 3438 transitions. cyclomatic complexity: 1044 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:09:12,077 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 11:09:12,077 INFO L93 Difference]: Finished difference Result 4365 states and 6231 transitions. [2022-10-17 11:09:12,077 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4365 states and 6231 transitions. [2022-10-17 11:09:12,115 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4264 [2022-10-17 11:09:12,157 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4365 states to 4365 states and 6231 transitions. [2022-10-17 11:09:12,157 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4365 [2022-10-17 11:09:12,163 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4365 [2022-10-17 11:09:12,163 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4365 states and 6231 transitions. [2022-10-17 11:09:12,170 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 11:09:12,170 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4365 states and 6231 transitions. [2022-10-17 11:09:12,176 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4365 states and 6231 transitions. [2022-10-17 11:09:12,263 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4365 to 4349. [2022-10-17 11:09:12,274 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4349 states, 4349 states have (on average 1.4290641526787766) internal successors, (6215), 4348 states have internal predecessors, (6215), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:09:12,292 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4349 states to 4349 states and 6215 transitions. [2022-10-17 11:09:12,292 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4349 states and 6215 transitions. [2022-10-17 11:09:12,292 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 11:09:12,293 INFO L428 stractBuchiCegarLoop]: Abstraction has 4349 states and 6215 transitions. [2022-10-17 11:09:12,293 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-10-17 11:09:12,294 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4349 states and 6215 transitions. [2022-10-17 11:09:12,314 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4248 [2022-10-17 11:09:12,314 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 11:09:12,314 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 11:09:12,316 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:09:12,316 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:09:12,316 INFO L748 eck$LassoCheckResult]: Stem: 23906#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 23856#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 23618#L778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 23410#L358 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 23411#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 23487#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 23758#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23702#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23703#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 23735#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 23713#L526 assume !(0 == ~M_E~0); 23714#L526-2 assume !(0 == ~T1_E~0); 23760#L531-1 assume !(0 == ~T2_E~0); 23698#L536-1 assume !(0 == ~T3_E~0); 23699#L541-1 assume !(0 == ~T4_E~0); 23694#L546-1 assume !(0 == ~E_M~0); 23695#L551-1 assume !(0 == ~E_1~0); 23672#L556-1 assume !(0 == ~E_2~0); 23673#L561-1 assume !(0 == ~E_3~0); 23682#L566-1 assume !(0 == ~E_4~0); 23683#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23677#L262 assume !(1 == ~m_pc~0); 23678#L262-2 is_master_triggered_~__retres1~0#1 := 0; 23866#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23532#L274 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 23533#L649 assume !(0 != activate_threads_~tmp~1#1); 23864#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23622#L281 assume !(1 == ~t1_pc~0); 23623#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 23879#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23734#L293 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 23597#L657 assume !(0 != activate_threads_~tmp___0~0#1); 23598#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23684#L300 assume !(1 == ~t2_pc~0); 23685#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 23799#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23592#L312 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 23593#L665 assume !(0 != activate_threads_~tmp___1~0#1); 23466#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 23467#L319 assume !(1 == ~t3_pc~0); 23423#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 23424#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23613#L331 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 23614#L673 assume !(0 != activate_threads_~tmp___2~0#1); 23445#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23446#L338 assume !(1 == ~t4_pc~0); 23511#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 23512#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23526#L350 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 23553#L681 assume !(0 != activate_threads_~tmp___3~0#1); 23390#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23391#L584 assume 1 == ~M_E~0;~M_E~0 := 2; 23862#L584-2 assume !(1 == ~T1_E~0); 25494#L589-1 assume !(1 == ~T2_E~0); 25488#L594-1 assume !(1 == ~T3_E~0); 25486#L599-1 assume !(1 == ~T4_E~0); 25484#L604-1 assume !(1 == ~E_M~0); 25482#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 25480#L614-1 assume !(1 == ~E_2~0); 25479#L619-1 assume !(1 == ~E_3~0); 23704#L624-1 assume !(1 == ~E_4~0); 23705#L629-1 assume { :end_inline_reset_delta_events } true; 25462#L815-2 [2022-10-17 11:09:12,316 INFO L750 eck$LassoCheckResult]: Loop: 25462#L815-2 assume !false; 25449#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 25448#L501 assume !false; 25447#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 25444#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 25436#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 25435#L426 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 25433#L440 assume !(0 != eval_~tmp~0#1); 25434#L516 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25619#L358-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25617#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 25616#L526-5 assume !(0 == ~T1_E~0); 25615#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25614#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25612#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 25610#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 25609#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 25608#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 25607#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 25606#L566-3 assume !(0 == ~E_4~0); 25605#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25604#L262-18 assume !(1 == ~m_pc~0); 25598#L262-20 is_master_triggered_~__retres1~0#1 := 0; 25596#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25594#L274-6 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 25591#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 25590#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25588#L281-18 assume 1 == ~t1_pc~0; 25585#L282-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 25583#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25581#L293-6 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 25579#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 25576#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25572#L300-18 assume !(1 == ~t2_pc~0); 25251#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 25569#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25567#L312-6 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 25564#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25562#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25560#L319-18 assume !(1 == ~t3_pc~0); 25558#L319-20 is_transmit3_triggered_~__retres1~3#1 := 0; 25556#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25554#L331-6 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 25552#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 25550#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25548#L338-18 assume !(1 == ~t4_pc~0); 25545#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 25543#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25541#L350-6 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 25539#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25537#L681-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25535#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 25531#L584-5 assume !(1 == ~T1_E~0); 25529#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 25527#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25525#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25523#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 25521#L609-3 assume !(1 == ~E_1~0); 25519#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 25517#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 25515#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 25511#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 25506#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 25501#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 25499#L426-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 25497#L834 assume !(0 == start_simulation_~tmp~3#1); 25495#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 25491#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 25487#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 25485#L426-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 25483#L789 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 25481#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 25472#L797 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 25467#L847 assume !(0 != start_simulation_~tmp___0~1#1); 25462#L815-2 [2022-10-17 11:09:12,317 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:09:12,317 INFO L85 PathProgramCache]: Analyzing trace with hash 843496709, now seen corresponding path program 1 times [2022-10-17 11:09:12,317 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:09:12,317 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [107294352] [2022-10-17 11:09:12,317 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:09:12,318 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:09:12,359 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:09:12,400 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:09:12,400 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:09:12,400 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [107294352] [2022-10-17 11:09:12,400 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [107294352] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:09:12,401 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:09:12,401 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-10-17 11:09:12,401 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1157988123] [2022-10-17 11:09:12,401 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:09:12,401 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 11:09:12,402 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:09:12,402 INFO L85 PathProgramCache]: Analyzing trace with hash 1197269455, now seen corresponding path program 1 times [2022-10-17 11:09:12,402 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:09:12,402 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [503983301] [2022-10-17 11:09:12,402 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:09:12,403 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:09:12,413 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:09:12,446 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:09:12,447 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:09:12,447 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [503983301] [2022-10-17 11:09:12,447 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [503983301] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:09:12,447 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:09:12,447 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:09:12,447 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1651116940] [2022-10-17 11:09:12,448 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:09:12,448 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 11:09:12,448 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 11:09:12,449 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 11:09:12,449 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 11:09:12,449 INFO L87 Difference]: Start difference. First operand 4349 states and 6215 transitions. cyclomatic complexity: 1874 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:09:12,513 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 11:09:12,513 INFO L93 Difference]: Finished difference Result 6516 states and 9297 transitions. [2022-10-17 11:09:12,514 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6516 states and 9297 transitions. [2022-10-17 11:09:12,551 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6412 [2022-10-17 11:09:12,597 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6516 states to 6516 states and 9297 transitions. [2022-10-17 11:09:12,597 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6516 [2022-10-17 11:09:12,605 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6516 [2022-10-17 11:09:12,605 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6516 states and 9297 transitions. [2022-10-17 11:09:12,616 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 11:09:12,616 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6516 states and 9297 transitions. [2022-10-17 11:09:12,624 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6516 states and 9297 transitions. [2022-10-17 11:09:12,705 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6516 to 4727. [2022-10-17 11:09:12,715 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4727 states, 4727 states have (on average 1.4250052887666596) internal successors, (6736), 4726 states have internal predecessors, (6736), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:09:12,786 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4727 states to 4727 states and 6736 transitions. [2022-10-17 11:09:12,786 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4727 states and 6736 transitions. [2022-10-17 11:09:12,787 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 11:09:12,788 INFO L428 stractBuchiCegarLoop]: Abstraction has 4727 states and 6736 transitions. [2022-10-17 11:09:12,788 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-10-17 11:09:12,788 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4727 states and 6736 transitions. [2022-10-17 11:09:12,810 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4636 [2022-10-17 11:09:12,811 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 11:09:12,811 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 11:09:12,812 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:09:12,812 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:09:12,813 INFO L748 eck$LassoCheckResult]: Stem: 34759#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 34724#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 34493#L778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 34282#L358 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34283#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 34356#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 34623#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 34574#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 34575#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 34606#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 34585#L526 assume !(0 == ~M_E~0); 34586#L526-2 assume !(0 == ~T1_E~0); 34626#L531-1 assume !(0 == ~T2_E~0); 34570#L536-1 assume !(0 == ~T3_E~0); 34571#L541-1 assume !(0 == ~T4_E~0); 34566#L546-1 assume !(0 == ~E_M~0); 34567#L551-1 assume !(0 == ~E_1~0); 34544#L556-1 assume !(0 == ~E_2~0); 34545#L561-1 assume !(0 == ~E_3~0); 34554#L566-1 assume !(0 == ~E_4~0); 34555#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 34549#L262 assume !(1 == ~m_pc~0); 34550#L262-2 is_master_triggered_~__retres1~0#1 := 0; 34728#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34402#L274 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 34403#L649 assume !(0 != activate_threads_~tmp~1#1); 34727#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34494#L281 assume !(1 == ~t1_pc~0); 34495#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 34404#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34405#L293 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 34465#L657 assume !(0 != activate_threads_~tmp___0~0#1); 34466#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34556#L300 assume !(1 == ~t2_pc~0); 34557#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 34663#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34460#L312 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 34461#L665 assume !(0 != activate_threads_~tmp___1~0#1); 34337#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34338#L319 assume !(1 == ~t3_pc~0); 34295#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 34296#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34485#L331 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 34486#L673 assume !(0 != activate_threads_~tmp___2~0#1); 34316#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 34317#L338 assume !(1 == ~t4_pc~0); 34379#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 34380#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 34396#L350 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 34421#L681 assume !(0 != activate_threads_~tmp___3~0#1); 34262#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34263#L584 assume !(1 == ~M_E~0); 34462#L584-2 assume !(1 == ~T1_E~0); 34419#L589-1 assume !(1 == ~T2_E~0); 34420#L594-1 assume !(1 == ~T3_E~0); 34519#L599-1 assume !(1 == ~T4_E~0); 34294#L604-1 assume !(1 == ~E_M~0); 34278#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 34279#L614-1 assume !(1 == ~E_2~0); 34393#L619-1 assume !(1 == ~E_3~0); 34484#L624-1 assume !(1 == ~E_4~0); 34576#L629-1 assume { :end_inline_reset_delta_events } true; 34743#L815-2 [2022-10-17 11:09:12,813 INFO L750 eck$LassoCheckResult]: Loop: 34743#L815-2 assume !false; 36257#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 36256#L501 assume !false; 36255#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 36251#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 36245#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 36243#L426 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 36240#L440 assume !(0 != eval_~tmp~0#1); 36238#L516 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 36236#L358-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 36233#L526-3 assume !(0 == ~M_E~0); 36231#L526-5 assume !(0 == ~T1_E~0); 36229#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 36227#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 36225#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 36221#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 36217#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 36214#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 36212#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 36210#L566-3 assume !(0 == ~E_4~0); 36207#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36206#L262-18 assume !(1 == ~m_pc~0); 36203#L262-20 is_master_triggered_~__retres1~0#1 := 0; 36201#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36199#L274-6 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 36198#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 36197#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36196#L281-18 assume 1 == ~t1_pc~0; 36195#L282-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 36181#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36177#L293-6 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 36175#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 35559#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 35064#L300-18 assume !(1 == ~t2_pc~0); 35061#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 35058#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35055#L312-6 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 35052#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 35049#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 35046#L319-18 assume !(1 == ~t3_pc~0); 35042#L319-20 is_transmit3_triggered_~__retres1~3#1 := 0; 35039#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 35036#L331-6 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 35033#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 35030#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 35026#L338-18 assume !(1 == ~t4_pc~0); 35021#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 35016#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 35007#L350-6 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 35003#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 35000#L681-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34980#L584-3 assume !(1 == ~M_E~0); 34973#L584-5 assume !(1 == ~T1_E~0); 34968#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 34963#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 34958#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 34953#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 34948#L609-3 assume !(1 == ~E_1~0); 34944#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 34940#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 34938#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 34937#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 34935#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 34909#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 34894#L426-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 34887#L834 assume !(0 == start_simulation_~tmp~3#1); 34500#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 34614#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 34569#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 34609#L426-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 34646#L789 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 34677#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 36282#L797 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 36281#L847 assume !(0 != start_simulation_~tmp___0~1#1); 34743#L815-2 [2022-10-17 11:09:12,813 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:09:12,813 INFO L85 PathProgramCache]: Analyzing trace with hash 1544561287, now seen corresponding path program 1 times [2022-10-17 11:09:12,814 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:09:12,814 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [891607706] [2022-10-17 11:09:12,814 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:09:12,814 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:09:12,824 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:09:12,870 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:09:12,870 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:09:12,871 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [891607706] [2022-10-17 11:09:12,871 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [891607706] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:09:12,871 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:09:12,871 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:09:12,871 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1400299998] [2022-10-17 11:09:12,871 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:09:12,872 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 11:09:12,872 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:09:12,872 INFO L85 PathProgramCache]: Analyzing trace with hash -662561777, now seen corresponding path program 1 times [2022-10-17 11:09:12,872 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:09:12,873 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [971852696] [2022-10-17 11:09:12,873 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:09:12,873 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:09:12,883 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:09:12,911 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:09:12,912 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:09:12,912 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [971852696] [2022-10-17 11:09:12,912 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [971852696] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:09:12,912 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:09:12,912 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:09:12,912 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1408724429] [2022-10-17 11:09:12,912 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:09:12,913 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 11:09:12,913 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 11:09:12,913 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-10-17 11:09:12,914 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-10-17 11:09:12,914 INFO L87 Difference]: Start difference. First operand 4727 states and 6736 transitions. cyclomatic complexity: 2013 Second operand has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:09:13,050 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 11:09:13,050 INFO L93 Difference]: Finished difference Result 6455 states and 9025 transitions. [2022-10-17 11:09:13,050 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6455 states and 9025 transitions. [2022-10-17 11:09:13,135 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 6270 [2022-10-17 11:09:13,178 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6455 states to 6455 states and 9025 transitions. [2022-10-17 11:09:13,178 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6455 [2022-10-17 11:09:13,184 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6455 [2022-10-17 11:09:13,185 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6455 states and 9025 transitions. [2022-10-17 11:09:13,196 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 11:09:13,196 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6455 states and 9025 transitions. [2022-10-17 11:09:13,206 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6455 states and 9025 transitions. [2022-10-17 11:09:13,309 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6455 to 5314. [2022-10-17 11:09:13,321 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5314 states, 5314 states have (on average 1.4060971019947308) internal successors, (7472), 5313 states have internal predecessors, (7472), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:09:13,339 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5314 states to 5314 states and 7472 transitions. [2022-10-17 11:09:13,339 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5314 states and 7472 transitions. [2022-10-17 11:09:13,340 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-10-17 11:09:13,340 INFO L428 stractBuchiCegarLoop]: Abstraction has 5314 states and 7472 transitions. [2022-10-17 11:09:13,341 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-10-17 11:09:13,341 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5314 states and 7472 transitions. [2022-10-17 11:09:13,366 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5180 [2022-10-17 11:09:13,366 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 11:09:13,366 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 11:09:13,368 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:09:13,368 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:09:13,369 INFO L748 eck$LassoCheckResult]: Stem: 45957#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 45913#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 45685#L778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 45474#L358 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 45475#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 45550#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 45813#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 45766#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 45767#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 45798#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 45776#L526 assume !(0 == ~M_E~0); 45777#L526-2 assume !(0 == ~T1_E~0); 45814#L531-1 assume !(0 == ~T2_E~0); 45762#L536-1 assume !(0 == ~T3_E~0); 45763#L541-1 assume !(0 == ~T4_E~0); 45758#L546-1 assume !(0 == ~E_M~0); 45759#L551-1 assume 0 == ~E_1~0;~E_1~0 := 1; 45826#L556-1 assume !(0 == ~E_2~0); 45999#L561-1 assume !(0 == ~E_3~0); 45998#L566-1 assume !(0 == ~E_4~0); 45997#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 45741#L262 assume !(1 == ~m_pc~0); 45742#L262-2 is_master_triggered_~__retres1~0#1 := 0; 45996#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 45595#L274 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 45596#L649 assume !(0 != activate_threads_~tmp~1#1); 45958#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 45688#L281 assume !(1 == ~t1_pc~0); 45689#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 45599#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 45600#L293 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 45991#L657 assume !(0 != activate_threads_~tmp___0~0#1); 45990#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 45989#L300 assume !(1 == ~t2_pc~0); 45988#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 45987#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 45986#L312 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 45985#L665 assume !(0 != activate_threads_~tmp___1~0#1); 45984#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 45983#L319 assume !(1 == ~t3_pc~0); 45981#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 45980#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 45979#L331 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 45978#L673 assume !(0 != activate_threads_~tmp___2~0#1); 45977#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 45976#L338 assume !(1 == ~t4_pc~0); 45975#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 45974#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 45973#L350 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 45972#L681 assume !(0 != activate_threads_~tmp___3~0#1); 45971#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 45970#L584 assume !(1 == ~M_E~0); 45969#L584-2 assume !(1 == ~T1_E~0); 45968#L589-1 assume !(1 == ~T2_E~0); 45967#L594-1 assume !(1 == ~T3_E~0); 45966#L599-1 assume !(1 == ~T4_E~0); 45965#L604-1 assume !(1 == ~E_M~0); 45964#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 45471#L614-1 assume !(1 == ~E_2~0); 45588#L619-1 assume !(1 == ~E_3~0); 45679#L624-1 assume !(1 == ~E_4~0); 45768#L629-1 assume { :end_inline_reset_delta_events } true; 45785#L815-2 [2022-10-17 11:09:13,369 INFO L750 eck$LassoCheckResult]: Loop: 45785#L815-2 assume !false; 45787#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 45906#L501 assume !false; 45911#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 45912#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 45593#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 45790#L426 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 45791#L440 assume !(0 != eval_~tmp~0#1); 45949#L516 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 50738#L358-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 50737#L526-3 assume !(0 == ~M_E~0); 50736#L526-5 assume !(0 == ~T1_E~0); 50735#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 50734#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 50733#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 50732#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 50731#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 50678#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 50679#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 50672#L566-3 assume !(0 == ~E_4~0); 50673#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 50666#L262-18 assume !(1 == ~m_pc~0); 50667#L262-20 is_master_triggered_~__retres1~0#1 := 0; 50659#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50660#L274-6 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 50653#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 50654#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 50646#L281-18 assume !(1 == ~t1_pc~0); 50647#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 50634#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50635#L293-6 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 50620#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 50621#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 45897#L300-18 assume !(1 == ~t2_pc~0); 45898#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 50705#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50704#L312-6 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 50703#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 50702#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 50701#L319-18 assume !(1 == ~t3_pc~0); 50699#L319-20 is_transmit3_triggered_~__retres1~3#1 := 0; 50698#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50697#L331-6 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 50696#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 50695#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 50694#L338-18 assume !(1 == ~t4_pc~0); 50693#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 50692#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 50691#L350-6 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 50690#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 50689#L681-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50688#L584-3 assume !(1 == ~M_E~0); 49820#L584-5 assume !(1 == ~T1_E~0); 50687#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 50686#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 50685#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 50684#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 50560#L609-3 assume !(1 == ~E_1~0); 50557#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 50556#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 50555#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 50554#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 45835#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 45580#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 45581#L426-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 45873#L834 assume !(0 == start_simulation_~tmp~3#1); 45696#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 45806#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 45761#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 45802#L426-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 45836#L789 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 45864#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 45769#L797 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 45770#L847 assume !(0 != start_simulation_~tmp___0~1#1); 45785#L815-2 [2022-10-17 11:09:13,370 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:09:13,370 INFO L85 PathProgramCache]: Analyzing trace with hash -383711415, now seen corresponding path program 1 times [2022-10-17 11:09:13,370 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:09:13,370 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1063504132] [2022-10-17 11:09:13,370 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:09:13,370 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:09:13,381 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:09:13,428 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:09:13,428 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:09:13,428 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1063504132] [2022-10-17 11:09:13,429 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1063504132] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:09:13,429 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:09:13,429 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:09:13,429 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [17718687] [2022-10-17 11:09:13,429 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:09:13,430 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 11:09:13,430 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:09:13,430 INFO L85 PathProgramCache]: Analyzing trace with hash 1738963344, now seen corresponding path program 1 times [2022-10-17 11:09:13,430 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:09:13,431 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1518872099] [2022-10-17 11:09:13,431 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:09:13,431 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:09:13,442 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:09:13,472 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:09:13,473 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:09:13,473 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1518872099] [2022-10-17 11:09:13,473 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1518872099] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:09:13,473 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:09:13,474 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:09:13,474 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1853541784] [2022-10-17 11:09:13,474 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:09:13,474 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 11:09:13,474 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 11:09:13,475 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-10-17 11:09:13,475 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-10-17 11:09:13,475 INFO L87 Difference]: Start difference. First operand 5314 states and 7472 transitions. cyclomatic complexity: 2162 Second operand has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:09:13,574 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 11:09:13,574 INFO L93 Difference]: Finished difference Result 5406 states and 7559 transitions. [2022-10-17 11:09:13,574 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5406 states and 7559 transitions. [2022-10-17 11:09:13,643 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 5302 [2022-10-17 11:09:13,662 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5406 states to 5406 states and 7559 transitions. [2022-10-17 11:09:13,662 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5406 [2022-10-17 11:09:13,668 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5406 [2022-10-17 11:09:13,668 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5406 states and 7559 transitions. [2022-10-17 11:09:13,675 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 11:09:13,676 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5406 states and 7559 transitions. [2022-10-17 11:09:13,683 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5406 states and 7559 transitions. [2022-10-17 11:09:13,749 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5406 to 4508. [2022-10-17 11:09:13,759 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4508 states, 4508 states have (on average 1.4021739130434783) internal successors, (6321), 4507 states have internal predecessors, (6321), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:09:13,773 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4508 states to 4508 states and 6321 transitions. [2022-10-17 11:09:13,773 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4508 states and 6321 transitions. [2022-10-17 11:09:13,774 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-10-17 11:09:13,774 INFO L428 stractBuchiCegarLoop]: Abstraction has 4508 states and 6321 transitions. [2022-10-17 11:09:13,774 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-10-17 11:09:13,775 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4508 states and 6321 transitions. [2022-10-17 11:09:13,793 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4420 [2022-10-17 11:09:13,793 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 11:09:13,793 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 11:09:13,795 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:09:13,795 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:09:13,795 INFO L748 eck$LassoCheckResult]: Stem: 56673#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 56637#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 56414#L778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 56204#L358 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 56205#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 56280#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 56538#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 56491#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 56492#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 56521#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 56501#L526 assume !(0 == ~M_E~0); 56502#L526-2 assume !(0 == ~T1_E~0); 56540#L531-1 assume !(0 == ~T2_E~0); 56487#L536-1 assume !(0 == ~T3_E~0); 56488#L541-1 assume !(0 == ~T4_E~0); 56483#L546-1 assume !(0 == ~E_M~0); 56484#L551-1 assume !(0 == ~E_1~0); 56462#L556-1 assume !(0 == ~E_2~0); 56463#L561-1 assume !(0 == ~E_3~0); 56472#L566-1 assume !(0 == ~E_4~0); 56473#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 56467#L262 assume !(1 == ~m_pc~0); 56468#L262-2 is_master_triggered_~__retres1~0#1 := 0; 56647#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 56325#L274 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 56326#L649 assume !(0 != activate_threads_~tmp~1#1); 56643#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 56417#L281 assume !(1 == ~t1_pc~0); 56418#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 56329#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 56330#L293 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 56389#L657 assume !(0 != activate_threads_~tmp___0~0#1); 56390#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 56474#L300 assume !(1 == ~t2_pc~0); 56475#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 56571#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 56384#L312 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 56385#L665 assume !(0 != activate_threads_~tmp___1~0#1); 56259#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 56260#L319 assume !(1 == ~t3_pc~0); 56217#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 56218#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 56409#L331 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 56410#L673 assume !(0 != activate_threads_~tmp___2~0#1); 56238#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 56239#L338 assume !(1 == ~t4_pc~0); 56302#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 56303#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 56319#L350 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 56346#L681 assume !(0 != activate_threads_~tmp___3~0#1); 56184#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 56185#L584 assume !(1 == ~M_E~0); 56386#L584-2 assume !(1 == ~T1_E~0); 56344#L589-1 assume !(1 == ~T2_E~0); 56345#L594-1 assume !(1 == ~T3_E~0); 56440#L599-1 assume !(1 == ~T4_E~0); 56216#L604-1 assume !(1 == ~E_M~0); 56200#L609-1 assume !(1 == ~E_1~0); 56201#L614-1 assume !(1 == ~E_2~0); 56318#L619-1 assume !(1 == ~E_3~0); 56408#L624-1 assume !(1 == ~E_4~0); 56493#L629-1 assume { :end_inline_reset_delta_events } true; 56510#L815-2 [2022-10-17 11:09:13,795 INFO L750 eck$LassoCheckResult]: Loop: 56510#L815-2 assume !false; 56512#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 56626#L501 assume !false; 60604#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 60573#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 60568#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 60567#L426 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 56666#L440 assume !(0 != eval_~tmp~0#1); 56658#L516 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 56640#L358-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 56441#L526-3 assume !(0 == ~M_E~0); 56442#L526-5 assume !(0 == ~T1_E~0); 56320#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 56321#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 56210#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 56211#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 56497#L551-3 assume !(0 == ~E_1~0); 56448#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 56449#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 56546#L566-3 assume !(0 == ~E_4~0); 56334#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 56335#L262-18 assume !(1 == ~m_pc~0); 56431#L262-20 is_master_triggered_~__retres1~0#1 := 0; 56432#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 56316#L274-6 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 56317#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 56223#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 56224#L281-18 assume !(1 == ~t1_pc~0); 56459#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 56476#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 56477#L293-6 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 56591#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 56587#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 56588#L300-18 assume !(1 == ~t2_pc~0); 59921#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 59919#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 59917#L312-6 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 59916#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 59915#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 59909#L319-18 assume !(1 == ~t3_pc~0); 59906#L319-20 is_transmit3_triggered_~__retres1~3#1 := 0; 59903#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 59902#L331-6 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 59901#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 59900#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 59898#L338-18 assume !(1 == ~t4_pc~0); 59894#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 59891#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 59888#L350-6 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 59885#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 59882#L681-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 59879#L584-3 assume !(1 == ~M_E~0); 57866#L584-5 assume !(1 == ~T1_E~0); 59874#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 59871#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 59868#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 59866#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 59864#L609-3 assume !(1 == ~E_1~0); 59863#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 59862#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 59861#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 59860#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 59857#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 58010#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 57985#L426-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 56829#L834 assume !(0 == start_simulation_~tmp~3#1); 56426#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 56531#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 56486#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 56526#L426-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 56559#L789 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 56589#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 56494#L797 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 56495#L847 assume !(0 != start_simulation_~tmp___0~1#1); 56510#L815-2 [2022-10-17 11:09:13,796 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:09:13,796 INFO L85 PathProgramCache]: Analyzing trace with hash 1546408329, now seen corresponding path program 1 times [2022-10-17 11:09:13,796 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:09:13,796 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [355861089] [2022-10-17 11:09:13,796 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:09:13,797 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:09:13,807 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 11:09:13,807 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 11:09:13,814 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 11:09:13,847 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 11:09:13,848 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:09:13,848 INFO L85 PathProgramCache]: Analyzing trace with hash -2122274866, now seen corresponding path program 1 times [2022-10-17 11:09:13,848 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:09:13,848 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1341616309] [2022-10-17 11:09:13,849 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:09:13,849 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:09:13,860 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:09:13,908 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:09:13,908 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:09:13,908 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1341616309] [2022-10-17 11:09:13,908 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1341616309] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:09:13,908 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:09:13,909 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-10-17 11:09:13,909 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1245545256] [2022-10-17 11:09:13,909 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:09:13,909 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 11:09:13,910 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 11:09:13,910 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-10-17 11:09:13,910 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-10-17 11:09:13,910 INFO L87 Difference]: Start difference. First operand 4508 states and 6321 transitions. cyclomatic complexity: 1817 Second operand has 5 states, 5 states have (on average 14.8) internal successors, (74), 5 states have internal predecessors, (74), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:09:14,042 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 11:09:14,042 INFO L93 Difference]: Finished difference Result 7968 states and 11013 transitions. [2022-10-17 11:09:14,042 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7968 states and 11013 transitions. [2022-10-17 11:09:14,083 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 7856 [2022-10-17 11:09:14,117 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7968 states to 7968 states and 11013 transitions. [2022-10-17 11:09:14,117 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7968 [2022-10-17 11:09:14,127 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7968 [2022-10-17 11:09:14,127 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7968 states and 11013 transitions. [2022-10-17 11:09:14,139 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 11:09:14,139 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7968 states and 11013 transitions. [2022-10-17 11:09:14,152 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7968 states and 11013 transitions. [2022-10-17 11:09:14,320 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7968 to 4556. [2022-10-17 11:09:14,328 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4556 states, 4556 states have (on average 1.3979367866549606) internal successors, (6369), 4555 states have internal predecessors, (6369), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:09:14,341 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4556 states to 4556 states and 6369 transitions. [2022-10-17 11:09:14,342 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4556 states and 6369 transitions. [2022-10-17 11:09:14,342 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-10-17 11:09:14,342 INFO L428 stractBuchiCegarLoop]: Abstraction has 4556 states and 6369 transitions. [2022-10-17 11:09:14,343 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-10-17 11:09:14,343 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4556 states and 6369 transitions. [2022-10-17 11:09:14,359 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4468 [2022-10-17 11:09:14,359 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 11:09:14,359 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 11:09:14,361 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:09:14,361 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:09:14,361 INFO L748 eck$LassoCheckResult]: Stem: 69201#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 69155#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 68906#L778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 68696#L358 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 68697#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 68771#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 69046#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 68990#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 68991#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 69027#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 69003#L526 assume !(0 == ~M_E~0); 69004#L526-2 assume !(0 == ~T1_E~0); 69048#L531-1 assume !(0 == ~T2_E~0); 68986#L536-1 assume !(0 == ~T3_E~0); 68987#L541-1 assume !(0 == ~T4_E~0); 68982#L546-1 assume !(0 == ~E_M~0); 68983#L551-1 assume !(0 == ~E_1~0); 68960#L556-1 assume !(0 == ~E_2~0); 68961#L561-1 assume !(0 == ~E_3~0); 68970#L566-1 assume !(0 == ~E_4~0); 68971#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 68965#L262 assume !(1 == ~m_pc~0); 68966#L262-2 is_master_triggered_~__retres1~0#1 := 0; 69167#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 68816#L274 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 68817#L649 assume !(0 != activate_threads_~tmp~1#1); 69166#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 68907#L281 assume !(1 == ~t1_pc~0); 68908#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 68818#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 68819#L293 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 68878#L657 assume !(0 != activate_threads_~tmp___0~0#1); 68879#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 68972#L300 assume !(1 == ~t2_pc~0); 68973#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 69085#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 68873#L312 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 68874#L665 assume !(0 != activate_threads_~tmp___1~0#1); 68751#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 68752#L319 assume !(1 == ~t3_pc~0); 68709#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 68710#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 68899#L331 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 68900#L673 assume !(0 != activate_threads_~tmp___2~0#1); 68730#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 68731#L338 assume !(1 == ~t4_pc~0); 68793#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 68794#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 68810#L350 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 68835#L681 assume !(0 != activate_threads_~tmp___3~0#1); 68676#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 68677#L584 assume !(1 == ~M_E~0); 68875#L584-2 assume !(1 == ~T1_E~0); 68833#L589-1 assume !(1 == ~T2_E~0); 68834#L594-1 assume !(1 == ~T3_E~0); 68934#L599-1 assume !(1 == ~T4_E~0); 68708#L604-1 assume !(1 == ~E_M~0); 68692#L609-1 assume !(1 == ~E_1~0); 68693#L614-1 assume !(1 == ~E_2~0); 68807#L619-1 assume !(1 == ~E_3~0); 68898#L624-1 assume !(1 == ~E_4~0); 68992#L629-1 assume { :end_inline_reset_delta_events } true; 69181#L815-2 [2022-10-17 11:09:14,361 INFO L750 eck$LassoCheckResult]: Loop: 69181#L815-2 assume !false; 73117#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 72870#L501 assume !false; 72865#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 69199#L398 assume !(0 == ~m_st~0); 68811#L402 assume !(0 == ~t1_st~0); 68813#L406 assume !(0 == ~t2_st~0); 68935#L410 assume !(0 == ~t3_st~0); 69118#L414 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5#1 := 0; 69202#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 70652#L426 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 70653#L440 assume !(0 != eval_~tmp~0#1); 72622#L516 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 72735#L358-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 72733#L526-3 assume !(0 == ~M_E~0); 72728#L526-5 assume !(0 == ~T1_E~0); 72729#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 72724#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 72725#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 72716#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 72717#L551-3 assume !(0 == ~E_1~0); 72711#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 72712#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 72704#L566-3 assume !(0 == ~E_4~0); 72705#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 72700#L262-18 assume !(1 == ~m_pc~0); 72701#L262-20 is_master_triggered_~__retres1~0#1 := 0; 72696#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 72697#L274-6 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 72692#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 72693#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 72689#L281-18 assume !(1 == ~t1_pc~0); 72688#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 72683#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 72684#L293-6 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 72678#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 72679#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 72675#L300-18 assume !(1 == ~t2_pc~0); 71500#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 72672#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 72673#L312-6 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 72666#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 72667#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 72659#L319-18 assume 1 == ~t3_pc~0; 72661#L320-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 72648#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 72649#L331-6 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 72620#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 72621#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 68904#L338-18 assume !(1 == ~t4_pc~0); 68905#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 68863#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 68864#L350-6 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 69154#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 73121#L681-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 68928#L584-3 assume !(1 == ~M_E~0); 68929#L584-5 assume !(1 == ~T1_E~0); 69099#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 68919#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 68920#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 68944#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 68945#L609-3 assume !(1 == ~E_1~0); 69010#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 69011#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 69025#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 69026#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 69067#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 68801#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 68802#L426-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 69112#L834 assume !(0 == start_simulation_~tmp~3#1); 73143#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 73140#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 73136#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 73134#L426-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 73133#L789 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 73130#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 73128#L797 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 73118#L847 assume !(0 != start_simulation_~tmp___0~1#1); 69181#L815-2 [2022-10-17 11:09:14,362 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:09:14,362 INFO L85 PathProgramCache]: Analyzing trace with hash 1546408329, now seen corresponding path program 2 times [2022-10-17 11:09:14,362 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:09:14,362 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1802867089] [2022-10-17 11:09:14,363 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:09:14,363 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:09:14,373 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 11:09:14,373 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 11:09:14,380 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 11:09:14,396 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 11:09:14,396 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:09:14,396 INFO L85 PathProgramCache]: Analyzing trace with hash 9407681, now seen corresponding path program 1 times [2022-10-17 11:09:14,396 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:09:14,397 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2141990747] [2022-10-17 11:09:14,397 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:09:14,397 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:09:14,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:09:14,453 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:09:14,453 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:09:14,453 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2141990747] [2022-10-17 11:09:14,454 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2141990747] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:09:14,454 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:09:14,454 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-10-17 11:09:14,454 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1249083402] [2022-10-17 11:09:14,454 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:09:14,454 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 11:09:14,455 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 11:09:14,455 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-10-17 11:09:14,455 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-10-17 11:09:14,456 INFO L87 Difference]: Start difference. First operand 4556 states and 6369 transitions. cyclomatic complexity: 1817 Second operand has 5 states, 5 states have (on average 15.6) internal successors, (78), 5 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:09:14,642 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 11:09:14,642 INFO L93 Difference]: Finished difference Result 15184 states and 20965 transitions. [2022-10-17 11:09:14,642 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 15184 states and 20965 transitions. [2022-10-17 11:09:14,796 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 15024 [2022-10-17 11:09:14,856 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 15184 states to 15184 states and 20965 transitions. [2022-10-17 11:09:14,856 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15184 [2022-10-17 11:09:14,872 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15184 [2022-10-17 11:09:14,872 INFO L73 IsDeterministic]: Start isDeterministic. Operand 15184 states and 20965 transitions. [2022-10-17 11:09:14,888 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 11:09:14,888 INFO L218 hiAutomatonCegarLoop]: Abstraction has 15184 states and 20965 transitions. [2022-10-17 11:09:14,909 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15184 states and 20965 transitions. [2022-10-17 11:09:15,003 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15184 to 4604. [2022-10-17 11:09:15,010 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4604 states, 4604 states have (on average 1.3937880104257168) internal successors, (6417), 4603 states have internal predecessors, (6417), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:09:15,023 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4604 states to 4604 states and 6417 transitions. [2022-10-17 11:09:15,024 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4604 states and 6417 transitions. [2022-10-17 11:09:15,024 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-10-17 11:09:15,025 INFO L428 stractBuchiCegarLoop]: Abstraction has 4604 states and 6417 transitions. [2022-10-17 11:09:15,025 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-10-17 11:09:15,025 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4604 states and 6417 transitions. [2022-10-17 11:09:15,040 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4516 [2022-10-17 11:09:15,041 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 11:09:15,041 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 11:09:15,042 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:09:15,042 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:09:15,043 INFO L748 eck$LassoCheckResult]: Stem: 88926#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 88887#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 88663#L778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 88453#L358 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 88454#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 88530#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 88791#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 88744#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 88745#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 88774#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 88754#L526 assume !(0 == ~M_E~0); 88755#L526-2 assume !(0 == ~T1_E~0); 88792#L531-1 assume !(0 == ~T2_E~0); 88740#L536-1 assume !(0 == ~T3_E~0); 88741#L541-1 assume !(0 == ~T4_E~0); 88735#L546-1 assume !(0 == ~E_M~0); 88736#L551-1 assume !(0 == ~E_1~0); 88714#L556-1 assume !(0 == ~E_2~0); 88715#L561-1 assume !(0 == ~E_3~0); 88724#L566-1 assume !(0 == ~E_4~0); 88725#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 88719#L262 assume !(1 == ~m_pc~0); 88720#L262-2 is_master_triggered_~__retres1~0#1 := 0; 88899#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 88575#L274 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 88576#L649 assume !(0 != activate_threads_~tmp~1#1); 88894#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 88666#L281 assume !(1 == ~t1_pc~0); 88667#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 88579#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 88580#L293 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 88638#L657 assume !(0 != activate_threads_~tmp___0~0#1); 88639#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 88726#L300 assume !(1 == ~t2_pc~0); 88727#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 88828#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 88633#L312 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 88634#L665 assume !(0 != activate_threads_~tmp___1~0#1); 88508#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 88509#L319 assume !(1 == ~t3_pc~0); 88466#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 88467#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 88658#L331 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 88659#L673 assume !(0 != activate_threads_~tmp___2~0#1); 88487#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 88488#L338 assume !(1 == ~t4_pc~0); 88552#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 88553#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 88569#L350 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 88596#L681 assume !(0 != activate_threads_~tmp___3~0#1); 88433#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 88434#L584 assume !(1 == ~M_E~0); 88635#L584-2 assume !(1 == ~T1_E~0); 88594#L589-1 assume !(1 == ~T2_E~0); 88595#L594-1 assume !(1 == ~T3_E~0); 88690#L599-1 assume !(1 == ~T4_E~0); 88465#L604-1 assume !(1 == ~E_M~0); 88449#L609-1 assume !(1 == ~E_1~0); 88450#L614-1 assume !(1 == ~E_2~0); 88568#L619-1 assume !(1 == ~E_3~0); 88657#L624-1 assume !(1 == ~E_4~0); 88746#L629-1 assume { :end_inline_reset_delta_events } true; 88909#L815-2 [2022-10-17 11:09:15,043 INFO L750 eck$LassoCheckResult]: Loop: 88909#L815-2 assume !false; 91552#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 91551#L501 assume !false; 91550#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 91549#L398 assume !(0 == ~m_st~0); 91546#L402 assume !(0 == ~t1_st~0); 91547#L406 assume !(0 == ~t2_st~0); 91548#L410 assume !(0 == ~t3_st~0); 91544#L414 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5#1 := 0; 91545#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 91539#L426 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 91540#L440 assume !(0 != eval_~tmp~0#1); 91796#L516 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 91794#L358-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 91792#L526-3 assume !(0 == ~M_E~0); 91790#L526-5 assume !(0 == ~T1_E~0); 91788#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 91786#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 91784#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 91782#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 91780#L551-3 assume !(0 == ~E_1~0); 91778#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 91776#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 91774#L566-3 assume !(0 == ~E_4~0); 91772#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 91770#L262-18 assume !(1 == ~m_pc~0); 91768#L262-20 is_master_triggered_~__retres1~0#1 := 0; 91766#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 91764#L274-6 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 91762#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 91760#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 91757#L281-18 assume !(1 == ~t1_pc~0); 91754#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 91752#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 91750#L293-6 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 91748#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 91746#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 91744#L300-18 assume !(1 == ~t2_pc~0); 91743#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 91742#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 91741#L312-6 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 91740#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 91739#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 91738#L319-18 assume 1 == ~t3_pc~0; 91737#L320-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 91735#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 91734#L331-6 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 91733#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 91732#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 91731#L338-18 assume !(1 == ~t4_pc~0); 91730#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 91729#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 91728#L350-6 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 91727#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 91726#L681-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 91725#L584-3 assume !(1 == ~M_E~0); 91016#L584-5 assume !(1 == ~T1_E~0); 91724#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 91723#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 91722#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 91721#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 91720#L609-3 assume !(1 == ~E_1~0); 91719#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 91718#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 91717#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 91716#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 91714#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 91707#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 91703#L426-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 91698#L834 assume !(0 == start_simulation_~tmp~3#1); 91570#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 91567#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 91564#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 91562#L426-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 91560#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 91558#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 91557#L797 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 91556#L847 assume !(0 != start_simulation_~tmp___0~1#1); 88909#L815-2 [2022-10-17 11:09:15,044 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:09:15,044 INFO L85 PathProgramCache]: Analyzing trace with hash 1546408329, now seen corresponding path program 3 times [2022-10-17 11:09:15,044 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:09:15,044 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1463379898] [2022-10-17 11:09:15,044 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:09:15,045 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:09:15,056 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 11:09:15,056 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 11:09:15,063 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 11:09:15,147 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 11:09:15,147 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:09:15,148 INFO L85 PathProgramCache]: Analyzing trace with hash 9348099, now seen corresponding path program 1 times [2022-10-17 11:09:15,148 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:09:15,148 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [521366582] [2022-10-17 11:09:15,148 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:09:15,148 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:09:15,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:09:15,267 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:09:15,268 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:09:15,268 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [521366582] [2022-10-17 11:09:15,268 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [521366582] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:09:15,268 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:09:15,268 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-10-17 11:09:15,269 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2000845660] [2022-10-17 11:09:15,269 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:09:15,269 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 11:09:15,269 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 11:09:15,270 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-10-17 11:09:15,270 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-10-17 11:09:15,271 INFO L87 Difference]: Start difference. First operand 4604 states and 6417 transitions. cyclomatic complexity: 1817 Second operand has 5 states, 5 states have (on average 15.6) internal successors, (78), 5 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:09:15,484 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 11:09:15,484 INFO L93 Difference]: Finished difference Result 9176 states and 12704 transitions. [2022-10-17 11:09:15,484 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9176 states and 12704 transitions. [2022-10-17 11:09:15,536 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 9072 [2022-10-17 11:09:15,576 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9176 states to 9176 states and 12704 transitions. [2022-10-17 11:09:15,576 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9176 [2022-10-17 11:09:15,589 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9176 [2022-10-17 11:09:15,589 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9176 states and 12704 transitions. [2022-10-17 11:09:15,597 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 11:09:15,597 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9176 states and 12704 transitions. [2022-10-17 11:09:15,607 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9176 states and 12704 transitions. [2022-10-17 11:09:15,686 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9176 to 4736. [2022-10-17 11:09:15,693 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4736 states, 4736 states have (on average 1.375) internal successors, (6512), 4735 states have internal predecessors, (6512), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:09:15,708 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4736 states to 4736 states and 6512 transitions. [2022-10-17 11:09:15,708 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4736 states and 6512 transitions. [2022-10-17 11:09:15,708 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-10-17 11:09:15,709 INFO L428 stractBuchiCegarLoop]: Abstraction has 4736 states and 6512 transitions. [2022-10-17 11:09:15,709 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-10-17 11:09:15,709 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4736 states and 6512 transitions. [2022-10-17 11:09:15,727 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4648 [2022-10-17 11:09:15,727 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 11:09:15,727 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 11:09:15,729 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:09:15,729 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:09:15,729 INFO L748 eck$LassoCheckResult]: Stem: 102724#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 102688#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 102455#L778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 102246#L358 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 102247#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 102321#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 102593#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 102538#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 102539#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 102574#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 102549#L526 assume !(0 == ~M_E~0); 102550#L526-2 assume !(0 == ~T1_E~0); 102596#L531-1 assume !(0 == ~T2_E~0); 102534#L536-1 assume !(0 == ~T3_E~0); 102535#L541-1 assume !(0 == ~T4_E~0); 102529#L546-1 assume !(0 == ~E_M~0); 102530#L551-1 assume !(0 == ~E_1~0); 102503#L556-1 assume !(0 == ~E_2~0); 102504#L561-1 assume !(0 == ~E_3~0); 102514#L566-1 assume !(0 == ~E_4~0); 102515#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 102508#L262 assume !(1 == ~m_pc~0); 102509#L262-2 is_master_triggered_~__retres1~0#1 := 0; 102696#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 102367#L274 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 102368#L649 assume !(0 != activate_threads_~tmp~1#1); 102695#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 102456#L281 assume !(1 == ~t1_pc~0); 102457#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 102369#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 102370#L293 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 102429#L657 assume !(0 != activate_threads_~tmp___0~0#1); 102430#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 102516#L300 assume !(1 == ~t2_pc~0); 102517#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 102628#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 102424#L312 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 102425#L665 assume !(0 != activate_threads_~tmp___1~0#1); 102301#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 102302#L319 assume !(1 == ~t3_pc~0); 102259#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 102260#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 102447#L331 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 102448#L673 assume !(0 != activate_threads_~tmp___2~0#1); 102280#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 102281#L338 assume !(1 == ~t4_pc~0); 102344#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 102345#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 102361#L350 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 102386#L681 assume !(0 != activate_threads_~tmp___3~0#1); 102226#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 102227#L584 assume !(1 == ~M_E~0); 102426#L584-2 assume !(1 == ~T1_E~0); 102384#L589-1 assume !(1 == ~T2_E~0); 102385#L594-1 assume !(1 == ~T3_E~0); 102480#L599-1 assume !(1 == ~T4_E~0); 102258#L604-1 assume !(1 == ~E_M~0); 102242#L609-1 assume !(1 == ~E_1~0); 102243#L614-1 assume !(1 == ~E_2~0); 102358#L619-1 assume !(1 == ~E_3~0); 102446#L624-1 assume !(1 == ~E_4~0); 102540#L629-1 assume { :end_inline_reset_delta_events } true; 102707#L815-2 [2022-10-17 11:09:15,729 INFO L750 eck$LassoCheckResult]: Loop: 102707#L815-2 assume !false; 103855#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 103853#L501 assume !false; 103851#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 103849#L398 assume !(0 == ~m_st~0); 103847#L402 assume !(0 == ~t1_st~0); 103845#L406 assume !(0 == ~t2_st~0); 103843#L410 assume !(0 == ~t3_st~0); 103839#L414 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5#1 := 0; 103837#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 103835#L426 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 103832#L440 assume !(0 != eval_~tmp~0#1); 103830#L516 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 103828#L358-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 103826#L526-3 assume !(0 == ~M_E~0); 103823#L526-5 assume !(0 == ~T1_E~0); 103821#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 103819#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 103817#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 103815#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 103813#L551-3 assume !(0 == ~E_1~0); 103810#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 103808#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 103806#L566-3 assume !(0 == ~E_4~0); 103804#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 103802#L262-18 assume !(1 == ~m_pc~0); 103800#L262-20 is_master_triggered_~__retres1~0#1 := 0; 103798#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 103796#L274-6 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 103794#L649-18 assume !(0 != activate_threads_~tmp~1#1); 103792#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 102939#L281-18 assume !(1 == ~t1_pc~0); 102932#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 102927#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 102923#L293-6 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 102919#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 102915#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 102911#L300-18 assume !(1 == ~t2_pc~0); 102910#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 102909#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 102908#L312-6 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 102907#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 102906#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 102905#L319-18 assume !(1 == ~t3_pc~0); 102903#L319-20 is_transmit3_triggered_~__retres1~3#1 := 0; 102902#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 102901#L331-6 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 102900#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 102899#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 102898#L338-18 assume !(1 == ~t4_pc~0); 102868#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 102846#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 102844#L350-6 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 102842#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 102839#L681-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 102837#L584-3 assume !(1 == ~M_E~0); 102834#L584-5 assume !(1 == ~T1_E~0); 102832#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 102833#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 102828#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 102829#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 104136#L609-3 assume !(1 == ~E_1~0); 104134#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 104132#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 104131#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 104130#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 103560#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 103556#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 103554#L426-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 102811#L834 assume !(0 == start_simulation_~tmp~3#1); 102812#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 103945#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 103941#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 103939#L426-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 103938#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 103936#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 103935#L797 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 103934#L847 assume !(0 != start_simulation_~tmp___0~1#1); 102707#L815-2 [2022-10-17 11:09:15,730 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:09:15,730 INFO L85 PathProgramCache]: Analyzing trace with hash 1546408329, now seen corresponding path program 4 times [2022-10-17 11:09:15,730 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:09:15,731 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1143736547] [2022-10-17 11:09:15,734 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:09:15,734 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:09:15,756 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 11:09:15,756 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 11:09:15,764 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 11:09:15,779 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 11:09:15,780 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:09:15,780 INFO L85 PathProgramCache]: Analyzing trace with hash 1045278470, now seen corresponding path program 1 times [2022-10-17 11:09:15,780 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:09:15,780 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1147743719] [2022-10-17 11:09:15,780 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:09:15,781 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:09:15,795 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:09:15,828 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:09:15,828 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:09:15,828 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1147743719] [2022-10-17 11:09:15,828 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1147743719] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:09:15,828 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:09:15,829 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:09:15,829 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1910253802] [2022-10-17 11:09:15,829 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:09:15,829 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 11:09:15,830 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 11:09:15,830 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 11:09:15,831 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 11:09:15,831 INFO L87 Difference]: Start difference. First operand 4736 states and 6512 transitions. cyclomatic complexity: 1780 Second operand has 3 states, 3 states have (on average 26.0) internal successors, (78), 3 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:09:15,897 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 11:09:15,898 INFO L93 Difference]: Finished difference Result 7392 states and 10008 transitions. [2022-10-17 11:09:15,898 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7392 states and 10008 transitions. [2022-10-17 11:09:15,981 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 7294 [2022-10-17 11:09:16,007 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7392 states to 7392 states and 10008 transitions. [2022-10-17 11:09:16,008 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7392 [2022-10-17 11:09:16,012 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7392 [2022-10-17 11:09:16,012 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7392 states and 10008 transitions. [2022-10-17 11:09:16,018 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 11:09:16,018 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7392 states and 10008 transitions. [2022-10-17 11:09:16,025 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7392 states and 10008 transitions. [2022-10-17 11:09:16,103 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7392 to 7136. [2022-10-17 11:09:16,115 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7136 states, 7136 states have (on average 1.3553811659192825) internal successors, (9672), 7135 states have internal predecessors, (9672), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:09:16,138 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7136 states to 7136 states and 9672 transitions. [2022-10-17 11:09:16,138 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7136 states and 9672 transitions. [2022-10-17 11:09:16,138 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 11:09:16,139 INFO L428 stractBuchiCegarLoop]: Abstraction has 7136 states and 9672 transitions. [2022-10-17 11:09:16,139 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2022-10-17 11:09:16,139 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7136 states and 9672 transitions. [2022-10-17 11:09:16,165 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 7038 [2022-10-17 11:09:16,165 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 11:09:16,165 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 11:09:16,166 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:09:16,166 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:09:16,167 INFO L748 eck$LassoCheckResult]: Stem: 114890#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 114842#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 114591#L778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 114380#L358 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 114381#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 114456#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 114731#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 114679#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 114680#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 114714#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 114690#L526 assume !(0 == ~M_E~0); 114691#L526-2 assume !(0 == ~T1_E~0); 114733#L531-1 assume !(0 == ~T2_E~0); 114675#L536-1 assume !(0 == ~T3_E~0); 114676#L541-1 assume !(0 == ~T4_E~0); 114670#L546-1 assume !(0 == ~E_M~0); 114671#L551-1 assume !(0 == ~E_1~0); 114645#L556-1 assume !(0 == ~E_2~0); 114646#L561-1 assume !(0 == ~E_3~0); 114655#L566-1 assume !(0 == ~E_4~0); 114656#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 114650#L262 assume !(1 == ~m_pc~0); 114651#L262-2 is_master_triggered_~__retres1~0#1 := 0; 114851#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 114500#L274 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 114501#L649 assume !(0 != activate_threads_~tmp~1#1); 114849#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 114595#L281 assume !(1 == ~t1_pc~0); 114596#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 114504#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 114505#L293 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 114566#L657 assume !(0 != activate_threads_~tmp___0~0#1); 114567#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 114658#L300 assume !(1 == ~t2_pc~0); 114659#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 114774#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 114561#L312 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 114562#L665 assume !(0 != activate_threads_~tmp___1~0#1); 114435#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 114436#L319 assume !(1 == ~t3_pc~0); 114393#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 114394#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 114586#L331 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 114587#L673 assume !(0 != activate_threads_~tmp___2~0#1); 114414#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 114415#L338 assume !(1 == ~t4_pc~0); 114479#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 114480#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 114494#L350 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 114521#L681 assume !(0 != activate_threads_~tmp___3~0#1); 114360#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 114361#L584 assume !(1 == ~M_E~0); 114563#L584-2 assume !(1 == ~T1_E~0); 114519#L589-1 assume !(1 == ~T2_E~0); 114520#L594-1 assume !(1 == ~T3_E~0); 114617#L599-1 assume !(1 == ~T4_E~0); 114392#L604-1 assume !(1 == ~E_M~0); 114376#L609-1 assume !(1 == ~E_1~0); 114377#L614-1 assume !(1 == ~E_2~0); 114493#L619-1 assume !(1 == ~E_3~0); 114585#L624-1 assume !(1 == ~E_4~0); 114681#L629-1 assume { :end_inline_reset_delta_events } true; 114866#L815-2 assume !false; 115700#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 115701#L501 [2022-10-17 11:09:16,167 INFO L750 eck$LassoCheckResult]: Loop: 115701#L501 assume !false; 115677#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 115678#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 115985#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 115984#L426 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 115975#L440 assume 0 != eval_~tmp~0#1; 115968#L440-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 115964#L448 assume !(0 != eval_~tmp_ndt_1~0#1); 115956#L445 assume !(0 == ~t1_st~0); 115952#L459 assume !(0 == ~t2_st~0); 115949#L473 assume !(0 == ~t3_st~0); 115704#L487 assume !(0 == ~t4_st~0); 115701#L501 [2022-10-17 11:09:16,168 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:09:16,168 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 1 times [2022-10-17 11:09:16,168 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:09:16,169 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [575389659] [2022-10-17 11:09:16,169 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:09:16,169 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:09:16,180 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 11:09:16,180 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 11:09:16,187 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 11:09:16,200 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 11:09:16,201 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:09:16,201 INFO L85 PathProgramCache]: Analyzing trace with hash 1608874715, now seen corresponding path program 1 times [2022-10-17 11:09:16,201 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:09:16,201 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1025301905] [2022-10-17 11:09:16,202 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:09:16,202 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:09:16,206 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 11:09:16,206 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 11:09:16,208 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 11:09:16,210 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 11:09:16,211 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:09:16,211 INFO L85 PathProgramCache]: Analyzing trace with hash 220742405, now seen corresponding path program 1 times [2022-10-17 11:09:16,211 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:09:16,212 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1185908422] [2022-10-17 11:09:16,212 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:09:16,212 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:09:16,223 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:09:16,254 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:09:16,255 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:09:16,255 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1185908422] [2022-10-17 11:09:16,255 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1185908422] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:09:16,255 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:09:16,255 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:09:16,256 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [588420077] [2022-10-17 11:09:16,256 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:09:16,356 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 11:09:16,356 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 11:09:16,356 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 11:09:16,357 INFO L87 Difference]: Start difference. First operand 7136 states and 9672 transitions. cyclomatic complexity: 2542 Second operand has 3 states, 3 states have (on average 25.333333333333332) internal successors, (76), 3 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:09:16,428 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 11:09:16,428 INFO L93 Difference]: Finished difference Result 11454 states and 15389 transitions. [2022-10-17 11:09:16,428 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11454 states and 15389 transitions. [2022-10-17 11:09:16,477 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 11264 [2022-10-17 11:09:16,518 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11454 states to 11454 states and 15389 transitions. [2022-10-17 11:09:16,518 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11454 [2022-10-17 11:09:16,525 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11454 [2022-10-17 11:09:16,525 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11454 states and 15389 transitions. [2022-10-17 11:09:16,533 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 11:09:16,533 INFO L218 hiAutomatonCegarLoop]: Abstraction has 11454 states and 15389 transitions. [2022-10-17 11:09:16,542 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11454 states and 15389 transitions. [2022-10-17 11:09:16,663 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11454 to 11454. [2022-10-17 11:09:16,788 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11454 states, 11454 states have (on average 1.3435481054653395) internal successors, (15389), 11453 states have internal predecessors, (15389), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:09:16,817 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11454 states to 11454 states and 15389 transitions. [2022-10-17 11:09:16,817 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11454 states and 15389 transitions. [2022-10-17 11:09:16,817 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 11:09:16,818 INFO L428 stractBuchiCegarLoop]: Abstraction has 11454 states and 15389 transitions. [2022-10-17 11:09:16,818 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2022-10-17 11:09:16,818 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11454 states and 15389 transitions. [2022-10-17 11:09:16,854 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 11264 [2022-10-17 11:09:16,854 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 11:09:16,854 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 11:09:16,855 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:09:16,855 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:09:16,856 INFO L748 eck$LassoCheckResult]: Stem: 133493#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 133446#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 133196#L778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 132978#L358 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 132979#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 133055#L365-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 133331#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 133278#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 133279#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 133313#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 133291#L526 assume !(0 == ~M_E~0); 133292#L526-2 assume !(0 == ~T1_E~0); 133334#L531-1 assume !(0 == ~T2_E~0); 133274#L536-1 assume !(0 == ~T3_E~0); 133275#L541-1 assume !(0 == ~T4_E~0); 133269#L546-1 assume !(0 == ~E_M~0); 133270#L551-1 assume !(0 == ~E_1~0); 133246#L556-1 assume !(0 == ~E_2~0); 133247#L561-1 assume !(0 == ~E_3~0); 133256#L566-1 assume !(0 == ~E_4~0); 133257#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 133251#L262 assume !(1 == ~m_pc~0); 133252#L262-2 is_master_triggered_~__retres1~0#1 := 0; 133456#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 133102#L274 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 133103#L649 assume !(0 != activate_threads_~tmp~1#1); 133455#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 133197#L281 assume !(1 == ~t1_pc~0); 133198#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 133104#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 133105#L293 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 133168#L657 assume !(0 != activate_threads_~tmp___0~0#1); 133169#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 133949#L300 assume !(1 == ~t2_pc~0); 133947#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 133945#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 133163#L312 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 133164#L665 assume !(0 != activate_threads_~tmp___1~0#1); 133033#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 133034#L319 assume !(1 == ~t3_pc~0); 132991#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 132992#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 133188#L331 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 133189#L673 assume !(0 != activate_threads_~tmp___2~0#1); 133012#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 133013#L338 assume !(1 == ~t4_pc~0); 133077#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 133078#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 133095#L350 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 133121#L681 assume !(0 != activate_threads_~tmp___3~0#1); 132958#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 132959#L584 assume !(1 == ~M_E~0); 133165#L584-2 assume !(1 == ~T1_E~0); 133119#L589-1 assume !(1 == ~T2_E~0); 133120#L594-1 assume !(1 == ~T3_E~0); 133220#L599-1 assume !(1 == ~T4_E~0); 132990#L604-1 assume !(1 == ~E_M~0); 132974#L609-1 assume !(1 == ~E_1~0); 132975#L614-1 assume !(1 == ~E_2~0); 133914#L619-1 assume !(1 == ~E_3~0); 133913#L624-1 assume !(1 == ~E_4~0); 133910#L629-1 assume { :end_inline_reset_delta_events } true; 133908#L815-2 assume !false; 133896#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 133889#L501 [2022-10-17 11:09:16,856 INFO L750 eck$LassoCheckResult]: Loop: 133889#L501 assume !false; 133885#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 133879#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 133874#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 133869#L426 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 133865#L440 assume 0 != eval_~tmp~0#1; 133860#L440-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 133854#L448 assume !(0 != eval_~tmp_ndt_1~0#1); 133839#L445 assume !(0 == ~t1_st~0); 133837#L459 assume !(0 == ~t2_st~0); 133790#L473 assume !(0 == ~t3_st~0); 133899#L487 assume !(0 == ~t4_st~0); 133889#L501 [2022-10-17 11:09:16,856 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:09:16,856 INFO L85 PathProgramCache]: Analyzing trace with hash 600428717, now seen corresponding path program 1 times [2022-10-17 11:09:16,856 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:09:16,857 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [720090714] [2022-10-17 11:09:16,857 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:09:16,857 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:09:16,865 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:09:16,883 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:09:16,883 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:09:16,883 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [720090714] [2022-10-17 11:09:16,883 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [720090714] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:09:16,883 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:09:16,883 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:09:16,884 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [897756374] [2022-10-17 11:09:16,884 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:09:16,884 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 11:09:16,884 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:09:16,885 INFO L85 PathProgramCache]: Analyzing trace with hash 1608874715, now seen corresponding path program 2 times [2022-10-17 11:09:16,885 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:09:16,885 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1414377504] [2022-10-17 11:09:16,885 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:09:16,885 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:09:16,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 11:09:16,889 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 11:09:16,891 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 11:09:16,892 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 11:09:16,968 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 11:09:16,968 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 11:09:16,968 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 11:09:16,969 INFO L87 Difference]: Start difference. First operand 11454 states and 15389 transitions. cyclomatic complexity: 3941 Second operand has 3 states, 3 states have (on average 21.333333333333332) internal successors, (64), 3 states have internal predecessors, (64), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:09:17,012 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 11:09:17,013 INFO L93 Difference]: Finished difference Result 11394 states and 15309 transitions. [2022-10-17 11:09:17,013 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11394 states and 15309 transitions. [2022-10-17 11:09:17,066 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 11264 [2022-10-17 11:09:17,109 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11394 states to 11394 states and 15309 transitions. [2022-10-17 11:09:17,110 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11394 [2022-10-17 11:09:17,117 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11394 [2022-10-17 11:09:17,117 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11394 states and 15309 transitions. [2022-10-17 11:09:17,125 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 11:09:17,126 INFO L218 hiAutomatonCegarLoop]: Abstraction has 11394 states and 15309 transitions. [2022-10-17 11:09:17,134 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11394 states and 15309 transitions. [2022-10-17 11:09:17,348 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11394 to 11394. [2022-10-17 11:09:17,360 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11394 states, 11394 states have (on average 1.3436018957345972) internal successors, (15309), 11393 states have internal predecessors, (15309), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:09:17,386 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11394 states to 11394 states and 15309 transitions. [2022-10-17 11:09:17,386 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11394 states and 15309 transitions. [2022-10-17 11:09:17,387 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 11:09:17,387 INFO L428 stractBuchiCegarLoop]: Abstraction has 11394 states and 15309 transitions. [2022-10-17 11:09:17,387 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2022-10-17 11:09:17,388 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11394 states and 15309 transitions. [2022-10-17 11:09:17,426 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 11264 [2022-10-17 11:09:17,427 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 11:09:17,427 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 11:09:17,428 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:09:17,428 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:09:17,428 INFO L748 eck$LassoCheckResult]: Stem: 156343#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 156294#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 156048#L778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 155832#L358 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 155833#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 155909#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 156190#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 156133#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 156134#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 156168#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 156145#L526 assume !(0 == ~M_E~0); 156146#L526-2 assume !(0 == ~T1_E~0); 156193#L531-1 assume !(0 == ~T2_E~0); 156129#L536-1 assume !(0 == ~T3_E~0); 156130#L541-1 assume !(0 == ~T4_E~0); 156124#L546-1 assume !(0 == ~E_M~0); 156125#L551-1 assume !(0 == ~E_1~0); 156099#L556-1 assume !(0 == ~E_2~0); 156100#L561-1 assume !(0 == ~E_3~0); 156109#L566-1 assume !(0 == ~E_4~0); 156110#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 156104#L262 assume !(1 == ~m_pc~0); 156105#L262-2 is_master_triggered_~__retres1~0#1 := 0; 156309#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 155955#L274 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 155956#L649 assume !(0 != activate_threads_~tmp~1#1); 156308#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 156049#L281 assume !(1 == ~t1_pc~0); 156050#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 155957#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 155958#L293 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 156020#L657 assume !(0 != activate_threads_~tmp___0~0#1); 156021#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 156112#L300 assume !(1 == ~t2_pc~0); 156113#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 156226#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 156015#L312 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 156016#L665 assume !(0 != activate_threads_~tmp___1~0#1); 155887#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 155888#L319 assume !(1 == ~t3_pc~0); 155845#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 155846#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 156041#L331 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 156042#L673 assume !(0 != activate_threads_~tmp___2~0#1); 155866#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 155867#L338 assume !(1 == ~t4_pc~0); 155931#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 155932#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 155950#L350 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 155974#L681 assume !(0 != activate_threads_~tmp___3~0#1); 155812#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 155813#L584 assume !(1 == ~M_E~0); 156017#L584-2 assume !(1 == ~T1_E~0); 155972#L589-1 assume !(1 == ~T2_E~0); 155973#L594-1 assume !(1 == ~T3_E~0); 156075#L599-1 assume !(1 == ~T4_E~0); 155844#L604-1 assume !(1 == ~E_M~0); 155828#L609-1 assume !(1 == ~E_1~0); 155829#L614-1 assume !(1 == ~E_2~0); 155947#L619-1 assume !(1 == ~E_3~0); 156040#L624-1 assume !(1 == ~E_4~0); 156135#L629-1 assume { :end_inline_reset_delta_events } true; 156325#L815-2 assume !false; 164202#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 160017#L501 [2022-10-17 11:09:17,428 INFO L750 eck$LassoCheckResult]: Loop: 160017#L501 assume !false; 164198#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 164195#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 164193#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 164191#L426 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 164189#L440 assume 0 != eval_~tmp~0#1; 164187#L440-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 156010#L448 assume !(0 != eval_~tmp_ndt_1~0#1); 156011#L445 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 158480#L462 assume !(0 != eval_~tmp_ndt_2~0#1); 158473#L459 assume !(0 == ~t2_st~0); 158469#L473 assume !(0 == ~t3_st~0); 160025#L487 assume !(0 == ~t4_st~0); 160017#L501 [2022-10-17 11:09:17,429 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:09:17,429 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 2 times [2022-10-17 11:09:17,429 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:09:17,429 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [933684873] [2022-10-17 11:09:17,429 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:09:17,430 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:09:17,440 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 11:09:17,440 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 11:09:17,447 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 11:09:17,458 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 11:09:17,458 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:09:17,459 INFO L85 PathProgramCache]: Analyzing trace with hash -1811665542, now seen corresponding path program 1 times [2022-10-17 11:09:17,459 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:09:17,459 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1005327341] [2022-10-17 11:09:17,459 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:09:17,459 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:09:17,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 11:09:17,463 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 11:09:17,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 11:09:17,468 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 11:09:17,468 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:09:17,468 INFO L85 PathProgramCache]: Analyzing trace with hash -1894094192, now seen corresponding path program 1 times [2022-10-17 11:09:17,468 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:09:17,469 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1341306658] [2022-10-17 11:09:17,469 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:09:17,469 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:09:17,481 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:09:17,515 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:09:17,515 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:09:17,515 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1341306658] [2022-10-17 11:09:17,516 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1341306658] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:09:17,518 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:09:17,518 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:09:17,519 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [927419576] [2022-10-17 11:09:17,519 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:09:17,771 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 11:09:17,771 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 11:09:17,771 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 11:09:17,772 INFO L87 Difference]: Start difference. First operand 11394 states and 15309 transitions. cyclomatic complexity: 3921 Second operand has 3 states, 3 states have (on average 25.666666666666668) internal successors, (77), 3 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:09:17,916 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 11:09:17,916 INFO L93 Difference]: Finished difference Result 21066 states and 28145 transitions. [2022-10-17 11:09:17,916 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21066 states and 28145 transitions. [2022-10-17 11:09:18,035 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 20872 [2022-10-17 11:09:18,129 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21066 states to 21066 states and 28145 transitions. [2022-10-17 11:09:18,130 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21066 [2022-10-17 11:09:18,144 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21066 [2022-10-17 11:09:18,145 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21066 states and 28145 transitions. [2022-10-17 11:09:18,163 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 11:09:18,163 INFO L218 hiAutomatonCegarLoop]: Abstraction has 21066 states and 28145 transitions. [2022-10-17 11:09:18,180 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21066 states and 28145 transitions. [2022-10-17 11:09:18,521 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21066 to 20576. [2022-10-17 11:09:18,541 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20576 states, 20576 states have (on average 1.3372375583203733) internal successors, (27515), 20575 states have internal predecessors, (27515), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:09:18,586 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20576 states to 20576 states and 27515 transitions. [2022-10-17 11:09:18,587 INFO L240 hiAutomatonCegarLoop]: Abstraction has 20576 states and 27515 transitions. [2022-10-17 11:09:18,587 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 11:09:18,588 INFO L428 stractBuchiCegarLoop]: Abstraction has 20576 states and 27515 transitions. [2022-10-17 11:09:18,588 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2022-10-17 11:09:18,588 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 20576 states and 27515 transitions. [2022-10-17 11:09:18,780 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 20382 [2022-10-17 11:09:18,780 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 11:09:18,780 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 11:09:18,781 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:09:18,781 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:09:18,782 INFO L748 eck$LassoCheckResult]: Stem: 188813#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 188769#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 188514#L778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 188300#L358 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 188301#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 188376#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 188655#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 188601#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 188602#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 188634#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 188613#L526 assume !(0 == ~M_E~0); 188614#L526-2 assume !(0 == ~T1_E~0); 188657#L531-1 assume !(0 == ~T2_E~0); 188597#L536-1 assume !(0 == ~T3_E~0); 188598#L541-1 assume !(0 == ~T4_E~0); 188592#L546-1 assume !(0 == ~E_M~0); 188593#L551-1 assume !(0 == ~E_1~0); 188569#L556-1 assume !(0 == ~E_2~0); 188570#L561-1 assume !(0 == ~E_3~0); 188580#L566-1 assume !(0 == ~E_4~0); 188581#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 188574#L262 assume !(1 == ~m_pc~0); 188575#L262-2 is_master_triggered_~__retres1~0#1 := 0; 188780#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 188420#L274 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 188421#L649 assume !(0 != activate_threads_~tmp~1#1); 188778#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 188518#L281 assume !(1 == ~t1_pc~0); 188519#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 188424#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 188425#L293 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 188484#L657 assume !(0 != activate_threads_~tmp___0~0#1); 188485#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 188582#L300 assume !(1 == ~t2_pc~0); 188583#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 188695#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 188479#L312 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 188480#L665 assume !(0 != activate_threads_~tmp___1~0#1); 188355#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 188356#L319 assume !(1 == ~t3_pc~0); 188313#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 188314#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 188507#L331 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 188508#L673 assume !(0 != activate_threads_~tmp___2~0#1); 188334#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 188335#L338 assume !(1 == ~t4_pc~0); 188399#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 188400#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 188415#L350 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 188441#L681 assume !(0 != activate_threads_~tmp___3~0#1); 188280#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 188281#L584 assume !(1 == ~M_E~0); 188481#L584-2 assume !(1 == ~T1_E~0); 188439#L589-1 assume !(1 == ~T2_E~0); 188440#L594-1 assume !(1 == ~T3_E~0); 188541#L599-1 assume !(1 == ~T4_E~0); 188312#L604-1 assume !(1 == ~E_M~0); 188296#L609-1 assume !(1 == ~E_1~0); 188297#L614-1 assume !(1 == ~E_2~0); 188414#L619-1 assume !(1 == ~E_3~0); 188506#L624-1 assume !(1 == ~E_4~0); 188603#L629-1 assume { :end_inline_reset_delta_events } true; 188792#L815-2 assume !false; 193461#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 193458#L501 [2022-10-17 11:09:18,782 INFO L750 eck$LassoCheckResult]: Loop: 193458#L501 assume !false; 193459#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 193452#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 193454#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 193445#L426 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 193446#L440 assume 0 != eval_~tmp~0#1; 193362#L440-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 193363#L448 assume !(0 != eval_~tmp_ndt_1~0#1); 193353#L445 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 193354#L462 assume !(0 != eval_~tmp_ndt_2~0#1); 193241#L459 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 193034#L476 assume !(0 != eval_~tmp_ndt_3~0#1); 193036#L473 assume !(0 == ~t3_st~0); 193521#L487 assume !(0 == ~t4_st~0); 193458#L501 [2022-10-17 11:09:18,782 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:09:18,782 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 3 times [2022-10-17 11:09:18,782 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:09:18,783 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1337765005] [2022-10-17 11:09:18,783 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:09:18,784 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:09:18,795 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 11:09:18,796 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 11:09:18,802 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 11:09:18,824 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 11:09:18,824 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:09:18,825 INFO L85 PathProgramCache]: Analyzing trace with hash -331803221, now seen corresponding path program 1 times [2022-10-17 11:09:18,825 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:09:18,825 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [858585029] [2022-10-17 11:09:18,825 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:09:18,825 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:09:18,830 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 11:09:18,830 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 11:09:18,834 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 11:09:18,836 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 11:09:18,836 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:09:18,836 INFO L85 PathProgramCache]: Analyzing trace with hash 1407875925, now seen corresponding path program 1 times [2022-10-17 11:09:18,837 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:09:18,837 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1335063875] [2022-10-17 11:09:18,837 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:09:18,837 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:09:18,849 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:09:18,882 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:09:18,883 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:09:18,883 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1335063875] [2022-10-17 11:09:18,883 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1335063875] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:09:18,883 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:09:18,883 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:09:18,883 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2114510320] [2022-10-17 11:09:18,884 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:09:19,007 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 11:09:19,008 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 11:09:19,008 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 11:09:19,008 INFO L87 Difference]: Start difference. First operand 20576 states and 27515 transitions. cyclomatic complexity: 6945 Second operand has 3 states, 3 states have (on average 26.0) internal successors, (78), 3 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:09:19,177 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 11:09:19,177 INFO L93 Difference]: Finished difference Result 36290 states and 48365 transitions. [2022-10-17 11:09:19,177 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 36290 states and 48365 transitions. [2022-10-17 11:09:19,482 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 35968 [2022-10-17 11:09:19,602 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 36290 states to 36290 states and 48365 transitions. [2022-10-17 11:09:19,602 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 36290 [2022-10-17 11:09:19,623 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 36290 [2022-10-17 11:09:19,623 INFO L73 IsDeterministic]: Start isDeterministic. Operand 36290 states and 48365 transitions. [2022-10-17 11:09:19,646 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 11:09:19,646 INFO L218 hiAutomatonCegarLoop]: Abstraction has 36290 states and 48365 transitions. [2022-10-17 11:09:19,665 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36290 states and 48365 transitions. [2022-10-17 11:09:20,171 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36290 to 35114. [2022-10-17 11:09:20,206 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 35114 states, 35114 states have (on average 1.3375007119667368) internal successors, (46965), 35113 states have internal predecessors, (46965), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:09:20,431 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35114 states to 35114 states and 46965 transitions. [2022-10-17 11:09:20,432 INFO L240 hiAutomatonCegarLoop]: Abstraction has 35114 states and 46965 transitions. [2022-10-17 11:09:20,432 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 11:09:20,433 INFO L428 stractBuchiCegarLoop]: Abstraction has 35114 states and 46965 transitions. [2022-10-17 11:09:20,433 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2022-10-17 11:09:20,433 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 35114 states and 46965 transitions. [2022-10-17 11:09:20,558 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 34792 [2022-10-17 11:09:20,559 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 11:09:20,559 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 11:09:20,561 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:09:20,561 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:09:20,561 INFO L748 eck$LassoCheckResult]: Stem: 245695#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 245643#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 245385#L778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 245174#L358 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 245175#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 245252#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 245522#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 245467#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 245468#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 245498#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 245478#L526 assume !(0 == ~M_E~0); 245479#L526-2 assume !(0 == ~T1_E~0); 245524#L531-1 assume !(0 == ~T2_E~0); 245463#L536-1 assume !(0 == ~T3_E~0); 245464#L541-1 assume !(0 == ~T4_E~0); 245458#L546-1 assume !(0 == ~E_M~0); 245459#L551-1 assume !(0 == ~E_1~0); 245436#L556-1 assume !(0 == ~E_2~0); 245437#L561-1 assume !(0 == ~E_3~0); 245446#L566-1 assume !(0 == ~E_4~0); 245447#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 245441#L262 assume !(1 == ~m_pc~0); 245442#L262-2 is_master_triggered_~__retres1~0#1 := 0; 245656#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 245297#L274 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 245298#L649 assume !(0 != activate_threads_~tmp~1#1); 245653#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 245388#L281 assume !(1 == ~t1_pc~0); 245389#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 245301#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 245302#L293 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 245361#L657 assume !(0 != activate_threads_~tmp___0~0#1); 245362#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 245449#L300 assume !(1 == ~t2_pc~0); 245450#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 245564#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 245356#L312 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 245357#L665 assume !(0 != activate_threads_~tmp___1~0#1); 245229#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 245230#L319 assume !(1 == ~t3_pc~0); 245187#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 245188#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 245380#L331 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 245381#L673 assume !(0 != activate_threads_~tmp___2~0#1); 245208#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 245209#L338 assume !(1 == ~t4_pc~0); 245275#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 245276#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 245292#L350 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 245318#L681 assume !(0 != activate_threads_~tmp___3~0#1); 245154#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 245155#L584 assume !(1 == ~M_E~0); 245358#L584-2 assume !(1 == ~T1_E~0); 245316#L589-1 assume !(1 == ~T2_E~0); 245317#L594-1 assume !(1 == ~T3_E~0); 245410#L599-1 assume !(1 == ~T4_E~0); 245186#L604-1 assume !(1 == ~E_M~0); 245170#L609-1 assume !(1 == ~E_1~0); 245171#L614-1 assume !(1 == ~E_2~0); 245291#L619-1 assume !(1 == ~E_3~0); 245379#L624-1 assume !(1 == ~E_4~0); 245469#L629-1 assume { :end_inline_reset_delta_events } true; 245667#L815-2 assume !false; 254997#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 254994#L501 [2022-10-17 11:09:20,561 INFO L750 eck$LassoCheckResult]: Loop: 254994#L501 assume !false; 254992#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 254989#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 254986#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 254987#L426 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 255664#L440 assume 0 != eval_~tmp~0#1; 255662#L440-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 255659#L448 assume !(0 != eval_~tmp_ndt_1~0#1); 255655#L445 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 254941#L462 assume !(0 != eval_~tmp_ndt_2~0#1); 254972#L459 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 256347#L476 assume !(0 != eval_~tmp_ndt_3~0#1); 255005#L473 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 255006#L490 assume !(0 != eval_~tmp_ndt_4~0#1); 255000#L487 assume !(0 == ~t4_st~0); 254994#L501 [2022-10-17 11:09:20,562 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:09:20,562 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 4 times [2022-10-17 11:09:20,562 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:09:20,563 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1373064648] [2022-10-17 11:09:20,563 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:09:20,563 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:09:20,574 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 11:09:20,575 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 11:09:20,582 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 11:09:20,596 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 11:09:20,596 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:09:20,596 INFO L85 PathProgramCache]: Analyzing trace with hash -1696117078, now seen corresponding path program 1 times [2022-10-17 11:09:20,597 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:09:20,597 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019433523] [2022-10-17 11:09:20,597 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:09:20,597 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:09:20,601 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 11:09:20,601 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 11:09:20,604 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 11:09:20,606 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 11:09:20,607 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:09:20,607 INFO L85 PathProgramCache]: Analyzing trace with hash 694328896, now seen corresponding path program 1 times [2022-10-17 11:09:20,607 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:09:20,607 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [996202996] [2022-10-17 11:09:20,607 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:09:20,607 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:09:20,620 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:09:20,660 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:09:20,660 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:09:20,660 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [996202996] [2022-10-17 11:09:20,661 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [996202996] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:09:20,661 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:09:20,662 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-10-17 11:09:20,663 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [490151188] [2022-10-17 11:09:20,663 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:09:20,834 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 11:09:20,834 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 11:09:20,834 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 11:09:20,835 INFO L87 Difference]: Start difference. First operand 35114 states and 46965 transitions. cyclomatic complexity: 11857 Second operand has 3 states, 2 states have (on average 39.5) internal successors, (79), 3 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:09:21,215 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 11:09:21,215 INFO L93 Difference]: Finished difference Result 39904 states and 53203 transitions. [2022-10-17 11:09:21,216 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 39904 states and 53203 transitions. [2022-10-17 11:09:21,406 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 39662 [2022-10-17 11:09:21,550 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 39904 states to 39904 states and 53203 transitions. [2022-10-17 11:09:21,551 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 39904 [2022-10-17 11:09:21,571 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 39904 [2022-10-17 11:09:21,571 INFO L73 IsDeterministic]: Start isDeterministic. Operand 39904 states and 53203 transitions. [2022-10-17 11:09:21,595 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 11:09:21,595 INFO L218 hiAutomatonCegarLoop]: Abstraction has 39904 states and 53203 transitions. [2022-10-17 11:09:21,616 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39904 states and 53203 transitions. [2022-10-17 11:09:22,296 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39904 to 39456. [2022-10-17 11:09:22,332 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 39456 states, 39456 states have (on average 1.33705900243309) internal successors, (52755), 39455 states have internal predecessors, (52755), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:09:22,440 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39456 states to 39456 states and 52755 transitions. [2022-10-17 11:09:22,440 INFO L240 hiAutomatonCegarLoop]: Abstraction has 39456 states and 52755 transitions. [2022-10-17 11:09:22,441 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 11:09:22,442 INFO L428 stractBuchiCegarLoop]: Abstraction has 39456 states and 52755 transitions. [2022-10-17 11:09:22,442 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2022-10-17 11:09:22,443 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 39456 states and 52755 transitions. [2022-10-17 11:09:22,606 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 39214 [2022-10-17 11:09:22,606 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 11:09:22,607 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 11:09:22,608 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:09:22,608 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:09:22,608 INFO L748 eck$LassoCheckResult]: Stem: 320749#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 320685#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 320414#L778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 320200#L358 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 320201#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 320280#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 320556#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 320501#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 320502#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 320535#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 320513#L526 assume !(0 == ~M_E~0); 320514#L526-2 assume !(0 == ~T1_E~0); 320559#L531-1 assume !(0 == ~T2_E~0); 320497#L536-1 assume !(0 == ~T3_E~0); 320498#L541-1 assume !(0 == ~T4_E~0); 320493#L546-1 assume !(0 == ~E_M~0); 320494#L551-1 assume !(0 == ~E_1~0); 320467#L556-1 assume !(0 == ~E_2~0); 320468#L561-1 assume !(0 == ~E_3~0); 320478#L566-1 assume !(0 == ~E_4~0); 320479#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 320472#L262 assume !(1 == ~m_pc~0); 320473#L262-2 is_master_triggered_~__retres1~0#1 := 0; 320698#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 320324#L274 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 320325#L649 assume !(0 != activate_threads_~tmp~1#1); 320696#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 320418#L281 assume !(1 == ~t1_pc~0); 320419#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 320328#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 320329#L293 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 320388#L657 assume !(0 != activate_threads_~tmp___0~0#1); 320389#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 320481#L300 assume !(1 == ~t2_pc~0); 320482#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 320607#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 320383#L312 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 320384#L665 assume !(0 != activate_threads_~tmp___1~0#1); 320257#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 320258#L319 assume !(1 == ~t3_pc~0); 320213#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 320214#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 320409#L331 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 320410#L673 assume !(0 != activate_threads_~tmp___2~0#1); 320235#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 320236#L338 assume !(1 == ~t4_pc~0); 320303#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 320304#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 320319#L350 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 320345#L681 assume !(0 != activate_threads_~tmp___3~0#1); 320180#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 320181#L584 assume !(1 == ~M_E~0); 320385#L584-2 assume !(1 == ~T1_E~0); 320343#L589-1 assume !(1 == ~T2_E~0); 320344#L594-1 assume !(1 == ~T3_E~0); 320440#L599-1 assume !(1 == ~T4_E~0); 320212#L604-1 assume !(1 == ~E_M~0); 320196#L609-1 assume !(1 == ~E_1~0); 320197#L614-1 assume !(1 == ~E_2~0); 320318#L619-1 assume !(1 == ~E_3~0); 320408#L624-1 assume !(1 == ~E_4~0); 320503#L629-1 assume { :end_inline_reset_delta_events } true; 320716#L815-2 assume !false; 330247#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 330244#L501 [2022-10-17 11:09:22,608 INFO L750 eck$LassoCheckResult]: Loop: 330244#L501 assume !false; 330242#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 330239#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 330235#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 330231#L426 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 330228#L440 assume 0 != eval_~tmp~0#1; 330224#L440-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 330220#L448 assume !(0 != eval_~tmp_ndt_1~0#1); 330217#L445 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 329439#L462 assume !(0 != eval_~tmp_ndt_2~0#1); 330212#L459 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 327002#L476 assume !(0 != eval_~tmp_ndt_3~0#1); 330207#L473 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 330189#L490 assume !(0 != eval_~tmp_ndt_4~0#1); 330203#L487 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 330248#L504 assume !(0 != eval_~tmp_ndt_5~0#1); 330244#L501 [2022-10-17 11:09:22,610 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:09:22,610 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 5 times [2022-10-17 11:09:22,610 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:09:22,610 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [56248695] [2022-10-17 11:09:22,610 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:09:22,611 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:09:22,623 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 11:09:22,624 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 11:09:22,632 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 11:09:22,646 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 11:09:22,646 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:09:22,647 INFO L85 PathProgramCache]: Analyzing trace with hash -1040025477, now seen corresponding path program 1 times [2022-10-17 11:09:22,647 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:09:22,647 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1008152500] [2022-10-17 11:09:22,647 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:09:22,647 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:09:22,654 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 11:09:22,654 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 11:09:22,665 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 11:09:22,668 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 11:09:22,671 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:09:22,671 INFO L85 PathProgramCache]: Analyzing trace with hash 49355685, now seen corresponding path program 1 times [2022-10-17 11:09:22,671 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:09:22,673 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1154626261] [2022-10-17 11:09:22,673 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:09:22,673 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:09:22,688 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 11:09:22,689 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 11:09:22,697 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 11:09:22,716 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 11:09:24,451 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 11:09:24,452 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 11:09:24,477 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 11:09:24,701 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 17.10 11:09:24 BoogieIcfgContainer [2022-10-17 11:09:24,701 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2022-10-17 11:09:24,702 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-10-17 11:09:24,702 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-10-17 11:09:24,702 INFO L275 PluginConnector]: Witness Printer initialized [2022-10-17 11:09:24,703 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 17.10 11:09:08" (3/4) ... [2022-10-17 11:09:24,706 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2022-10-17 11:09:24,809 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0042236c-ae04-44fe-9ff8-d2ad69a89359/bin/uautomizer-J5u9QxTXDZ/witness.graphml [2022-10-17 11:09:24,809 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-10-17 11:09:24,810 INFO L158 Benchmark]: Toolchain (without parser) took 18103.30ms. Allocated memory was 100.7MB in the beginning and 7.8GB in the end (delta: 7.7GB). Free memory was 62.2MB in the beginning and 7.0GB in the end (delta: -6.9GB). Peak memory consumption was 810.2MB. Max. memory is 16.1GB. [2022-10-17 11:09:24,811 INFO L158 Benchmark]: CDTParser took 0.28ms. Allocated memory is still 100.7MB. Free memory is still 78.8MB. There was no memory consumed. Max. memory is 16.1GB. [2022-10-17 11:09:24,811 INFO L158 Benchmark]: CACSL2BoogieTranslator took 398.37ms. Allocated memory is still 100.7MB. Free memory was 62.0MB in the beginning and 71.1MB in the end (delta: -9.0MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. [2022-10-17 11:09:24,812 INFO L158 Benchmark]: Boogie Procedure Inliner took 83.53ms. Allocated memory is still 100.7MB. Free memory was 71.1MB in the beginning and 66.9MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2022-10-17 11:09:24,812 INFO L158 Benchmark]: Boogie Preprocessor took 65.72ms. Allocated memory is still 100.7MB. Free memory was 66.9MB in the beginning and 63.0MB in the end (delta: 3.9MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-10-17 11:09:24,812 INFO L158 Benchmark]: RCFGBuilder took 1293.68ms. Allocated memory is still 100.7MB. Free memory was 62.7MB in the beginning and 50.1MB in the end (delta: 12.5MB). Peak memory consumption was 32.1MB. Max. memory is 16.1GB. [2022-10-17 11:09:24,813 INFO L158 Benchmark]: BuchiAutomizer took 16145.71ms. Allocated memory was 100.7MB in the beginning and 7.8GB in the end (delta: 7.7GB). Free memory was 50.1MB in the beginning and 7.0GB in the end (delta: -6.9GB). Peak memory consumption was 788.6MB. Max. memory is 16.1GB. [2022-10-17 11:09:24,813 INFO L158 Benchmark]: Witness Printer took 107.57ms. Allocated memory is still 7.8GB. Free memory was 7.0GB in the beginning and 7.0GB in the end (delta: 9.6MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. [2022-10-17 11:09:24,815 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.28ms. Allocated memory is still 100.7MB. Free memory is still 78.8MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 398.37ms. Allocated memory is still 100.7MB. Free memory was 62.0MB in the beginning and 71.1MB in the end (delta: -9.0MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 83.53ms. Allocated memory is still 100.7MB. Free memory was 71.1MB in the beginning and 66.9MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 65.72ms. Allocated memory is still 100.7MB. Free memory was 66.9MB in the beginning and 63.0MB in the end (delta: 3.9MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 1293.68ms. Allocated memory is still 100.7MB. Free memory was 62.7MB in the beginning and 50.1MB in the end (delta: 12.5MB). Peak memory consumption was 32.1MB. Max. memory is 16.1GB. * BuchiAutomizer took 16145.71ms. Allocated memory was 100.7MB in the beginning and 7.8GB in the end (delta: 7.7GB). Free memory was 50.1MB in the beginning and 7.0GB in the end (delta: -6.9GB). Peak memory consumption was 788.6MB. Max. memory is 16.1GB. * Witness Printer took 107.57ms. Allocated memory is still 7.8GB. Free memory was 7.0GB in the beginning and 7.0GB in the end (delta: 9.6MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 22 terminating modules (22 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.22 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 39456 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 15.9s and 23 iterations. TraceHistogramMax:1. Analysis of lassos took 5.5s. Construction of modules took 0.7s. Büchi inclusion checks took 8.5s. Highest rank in rank-based complementation 0. Minimization of det autom 22. Minimization of nondet autom 0. Automata minimization 4.1s AutomataMinimizationTime, 22 MinimizatonAttempts, 27415 StatesRemovedByMinimization, 15 NontrivialMinimizations. Non-live state removal took 2.3s Buchi closure took 0.1s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 19147 SdHoareTripleChecker+Valid, 1.0s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 19147 mSDsluCounter, 32259 SdHoareTripleChecker+Invalid, 0.8s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 16630 mSDsCounter, 266 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 715 IncrementalHoareTripleChecker+Invalid, 981 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 266 mSolverCounterUnsat, 15629 mSDtfsCounter, 715 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc4 concLT0 SILN1 SILU0 SILI13 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 435]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int t4_pc = 0; [L29] int m_st ; [L30] int t1_st ; [L31] int t2_st ; [L32] int t3_st ; [L33] int t4_st ; [L34] int m_i ; [L35] int t1_i ; [L36] int t2_i ; [L37] int t3_i ; [L38] int t4_i ; [L39] int M_E = 2; [L40] int T1_E = 2; [L41] int T2_E = 2; [L42] int T3_E = 2; [L43] int T4_E = 2; [L44] int E_M = 2; [L45] int E_1 = 2; [L46] int E_2 = 2; [L47] int E_3 = 2; [L48] int E_4 = 2; [L55] int token ; [L57] int local ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0, token=0] [L860] int __retres1 ; [L864] CALL init_model() [L772] m_i = 1 [L773] t1_i = 1 [L774] t2_i = 1 [L775] t3_i = 1 [L776] t4_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L864] RET init_model() [L865] CALL start_simulation() [L801] int kernel_st ; [L802] int tmp ; [L803] int tmp___0 ; [L807] kernel_st = 0 [L808] FCALL update_channels() [L809] CALL init_threads() [L365] COND TRUE m_i == 1 [L366] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L370] COND TRUE t1_i == 1 [L371] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L375] COND TRUE t2_i == 1 [L376] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L380] COND TRUE t3_i == 1 [L381] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L385] COND TRUE t4_i == 1 [L386] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L809] RET init_threads() [L810] CALL fire_delta_events() [L526] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L531] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L536] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L541] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L546] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L551] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L556] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L561] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L566] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L571] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L810] RET fire_delta_events() [L811] CALL activate_threads() [L639] int tmp ; [L640] int tmp___0 ; [L641] int tmp___1 ; [L642] int tmp___2 ; [L643] int tmp___3 ; [L647] CALL, EXPR is_master_triggered() [L259] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L262] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L272] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L274] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L647] RET, EXPR is_master_triggered() [L647] tmp = is_master_triggered() [L649] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, token=0] [L655] CALL, EXPR is_transmit1_triggered() [L278] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L281] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L291] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L293] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L655] RET, EXPR is_transmit1_triggered() [L655] tmp___0 = is_transmit1_triggered() [L657] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, token=0] [L663] CALL, EXPR is_transmit2_triggered() [L297] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L300] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L310] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L312] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L663] RET, EXPR is_transmit2_triggered() [L663] tmp___1 = is_transmit2_triggered() [L665] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, token=0] [L671] CALL, EXPR is_transmit3_triggered() [L316] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L319] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L329] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L331] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L671] RET, EXPR is_transmit3_triggered() [L671] tmp___2 = is_transmit3_triggered() [L673] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, token=0] [L679] CALL, EXPR is_transmit4_triggered() [L335] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L338] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L348] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L350] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L679] RET, EXPR is_transmit4_triggered() [L679] tmp___3 = is_transmit4_triggered() [L681] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, token=0] [L811] RET activate_threads() [L812] CALL reset_delta_events() [L584] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L589] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L594] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L599] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L604] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L609] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L614] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L619] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L624] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L629] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L812] RET reset_delta_events() [L815] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, kernel_st=0, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L818] kernel_st = 1 [L819] CALL eval() [L431] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] Loop: [L435] COND TRUE 1 [L438] CALL, EXPR exists_runnable_thread() [L395] int __retres1 ; [L398] COND TRUE m_st == 0 [L399] __retres1 = 1 [L426] return (__retres1); [L438] RET, EXPR exists_runnable_thread() [L438] tmp = exists_runnable_thread() [L440] COND TRUE \read(tmp) [L445] COND TRUE m_st == 0 [L446] int tmp_ndt_1; [L447] tmp_ndt_1 = __VERIFIER_nondet_int() [L448] COND FALSE !(\read(tmp_ndt_1)) [L459] COND TRUE t1_st == 0 [L460] int tmp_ndt_2; [L461] tmp_ndt_2 = __VERIFIER_nondet_int() [L462] COND FALSE !(\read(tmp_ndt_2)) [L473] COND TRUE t2_st == 0 [L474] int tmp_ndt_3; [L475] tmp_ndt_3 = __VERIFIER_nondet_int() [L476] COND FALSE !(\read(tmp_ndt_3)) [L487] COND TRUE t3_st == 0 [L488] int tmp_ndt_4; [L489] tmp_ndt_4 = __VERIFIER_nondet_int() [L490] COND FALSE !(\read(tmp_ndt_4)) [L501] COND TRUE t4_st == 0 [L502] int tmp_ndt_5; [L503] tmp_ndt_5 = __VERIFIER_nondet_int() [L504] COND FALSE !(\read(tmp_ndt_5)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 435]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int t4_pc = 0; [L29] int m_st ; [L30] int t1_st ; [L31] int t2_st ; [L32] int t3_st ; [L33] int t4_st ; [L34] int m_i ; [L35] int t1_i ; [L36] int t2_i ; [L37] int t3_i ; [L38] int t4_i ; [L39] int M_E = 2; [L40] int T1_E = 2; [L41] int T2_E = 2; [L42] int T3_E = 2; [L43] int T4_E = 2; [L44] int E_M = 2; [L45] int E_1 = 2; [L46] int E_2 = 2; [L47] int E_3 = 2; [L48] int E_4 = 2; [L55] int token ; [L57] int local ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0, token=0] [L860] int __retres1 ; [L864] CALL init_model() [L772] m_i = 1 [L773] t1_i = 1 [L774] t2_i = 1 [L775] t3_i = 1 [L776] t4_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L864] RET init_model() [L865] CALL start_simulation() [L801] int kernel_st ; [L802] int tmp ; [L803] int tmp___0 ; [L807] kernel_st = 0 [L808] FCALL update_channels() [L809] CALL init_threads() [L365] COND TRUE m_i == 1 [L366] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L370] COND TRUE t1_i == 1 [L371] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L375] COND TRUE t2_i == 1 [L376] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L380] COND TRUE t3_i == 1 [L381] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L385] COND TRUE t4_i == 1 [L386] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L809] RET init_threads() [L810] CALL fire_delta_events() [L526] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L531] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L536] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L541] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L546] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L551] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L556] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L561] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L566] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L571] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L810] RET fire_delta_events() [L811] CALL activate_threads() [L639] int tmp ; [L640] int tmp___0 ; [L641] int tmp___1 ; [L642] int tmp___2 ; [L643] int tmp___3 ; [L647] CALL, EXPR is_master_triggered() [L259] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L262] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L272] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L274] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L647] RET, EXPR is_master_triggered() [L647] tmp = is_master_triggered() [L649] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, token=0] [L655] CALL, EXPR is_transmit1_triggered() [L278] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L281] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L291] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L293] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L655] RET, EXPR is_transmit1_triggered() [L655] tmp___0 = is_transmit1_triggered() [L657] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, token=0] [L663] CALL, EXPR is_transmit2_triggered() [L297] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L300] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L310] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L312] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L663] RET, EXPR is_transmit2_triggered() [L663] tmp___1 = is_transmit2_triggered() [L665] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, token=0] [L671] CALL, EXPR is_transmit3_triggered() [L316] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L319] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L329] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L331] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L671] RET, EXPR is_transmit3_triggered() [L671] tmp___2 = is_transmit3_triggered() [L673] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, token=0] [L679] CALL, EXPR is_transmit4_triggered() [L335] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L338] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L348] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L350] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L679] RET, EXPR is_transmit4_triggered() [L679] tmp___3 = is_transmit4_triggered() [L681] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, token=0] [L811] RET activate_threads() [L812] CALL reset_delta_events() [L584] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L589] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L594] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L599] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L604] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L609] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L614] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L619] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L624] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L629] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L812] RET reset_delta_events() [L815] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, kernel_st=0, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L818] kernel_st = 1 [L819] CALL eval() [L431] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] Loop: [L435] COND TRUE 1 [L438] CALL, EXPR exists_runnable_thread() [L395] int __retres1 ; [L398] COND TRUE m_st == 0 [L399] __retres1 = 1 [L426] return (__retres1); [L438] RET, EXPR exists_runnable_thread() [L438] tmp = exists_runnable_thread() [L440] COND TRUE \read(tmp) [L445] COND TRUE m_st == 0 [L446] int tmp_ndt_1; [L447] tmp_ndt_1 = __VERIFIER_nondet_int() [L448] COND FALSE !(\read(tmp_ndt_1)) [L459] COND TRUE t1_st == 0 [L460] int tmp_ndt_2; [L461] tmp_ndt_2 = __VERIFIER_nondet_int() [L462] COND FALSE !(\read(tmp_ndt_2)) [L473] COND TRUE t2_st == 0 [L474] int tmp_ndt_3; [L475] tmp_ndt_3 = __VERIFIER_nondet_int() [L476] COND FALSE !(\read(tmp_ndt_3)) [L487] COND TRUE t3_st == 0 [L488] int tmp_ndt_4; [L489] tmp_ndt_4 = __VERIFIER_nondet_int() [L490] COND FALSE !(\read(tmp_ndt_4)) [L501] COND TRUE t4_st == 0 [L502] int tmp_ndt_5; [L503] tmp_ndt_5 = __VERIFIER_nondet_int() [L504] COND FALSE !(\read(tmp_ndt_5)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2022-10-17 11:09:24,976 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0042236c-ae04-44fe-9ff8-d2ad69a89359/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)