./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.06.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version dbf71c69 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_347855b0-ff3a-4f68-a6b0-dbc63c69658f/bin/uautomizer-J5u9QxTXDZ/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_347855b0-ff3a-4f68-a6b0-dbc63c69658f/bin/uautomizer-J5u9QxTXDZ/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_347855b0-ff3a-4f68-a6b0-dbc63c69658f/bin/uautomizer-J5u9QxTXDZ/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_347855b0-ff3a-4f68-a6b0-dbc63c69658f/bin/uautomizer-J5u9QxTXDZ/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.06.cil-2.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_347855b0-ff3a-4f68-a6b0-dbc63c69658f/bin/uautomizer-J5u9QxTXDZ/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_347855b0-ff3a-4f68-a6b0-dbc63c69658f/bin/uautomizer-J5u9QxTXDZ --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 4d0fbec14d1477738cb6d25ea9b61fc7005f787f2c8a0ac2c555d7e4fa1dbf47 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-dbf71c6-m [2022-10-17 11:04:25,297 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-10-17 11:04:25,303 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-10-17 11:04:25,354 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-10-17 11:04:25,354 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-10-17 11:04:25,358 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-10-17 11:04:25,360 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-10-17 11:04:25,366 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-10-17 11:04:25,368 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-10-17 11:04:25,374 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-10-17 11:04:25,375 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-10-17 11:04:25,378 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-10-17 11:04:25,378 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-10-17 11:04:25,381 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-10-17 11:04:25,383 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-10-17 11:04:25,385 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-10-17 11:04:25,387 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-10-17 11:04:25,388 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-10-17 11:04:25,390 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-10-17 11:04:25,396 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-10-17 11:04:25,398 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-10-17 11:04:25,400 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-10-17 11:04:25,403 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-10-17 11:04:25,404 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-10-17 11:04:25,414 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-10-17 11:04:25,415 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-10-17 11:04:25,415 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-10-17 11:04:25,418 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-10-17 11:04:25,418 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-10-17 11:04:25,420 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-10-17 11:04:25,420 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-10-17 11:04:25,421 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-10-17 11:04:25,424 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-10-17 11:04:25,425 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-10-17 11:04:25,426 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-10-17 11:04:25,427 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-10-17 11:04:25,428 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-10-17 11:04:25,429 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-10-17 11:04:25,429 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-10-17 11:04:25,430 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-10-17 11:04:25,431 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-10-17 11:04:25,431 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_347855b0-ff3a-4f68-a6b0-dbc63c69658f/bin/uautomizer-J5u9QxTXDZ/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-10-17 11:04:25,473 INFO L113 SettingsManager]: Loading preferences was successful [2022-10-17 11:04:25,474 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-10-17 11:04:25,474 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-10-17 11:04:25,474 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-10-17 11:04:25,476 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-10-17 11:04:25,476 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-10-17 11:04:25,476 INFO L138 SettingsManager]: * Use SBE=true [2022-10-17 11:04:25,477 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-10-17 11:04:25,477 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-10-17 11:04:25,477 INFO L138 SettingsManager]: * Use old map elimination=false [2022-10-17 11:04:25,478 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-10-17 11:04:25,478 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-10-17 11:04:25,479 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-10-17 11:04:25,479 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-10-17 11:04:25,479 INFO L138 SettingsManager]: * sizeof long=4 [2022-10-17 11:04:25,479 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-10-17 11:04:25,480 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-10-17 11:04:25,480 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-10-17 11:04:25,480 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-10-17 11:04:25,480 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-10-17 11:04:25,481 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-10-17 11:04:25,481 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-10-17 11:04:25,481 INFO L138 SettingsManager]: * sizeof long double=12 [2022-10-17 11:04:25,482 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-10-17 11:04:25,483 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-10-17 11:04:25,483 INFO L138 SettingsManager]: * Use constant arrays=true [2022-10-17 11:04:25,483 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-10-17 11:04:25,484 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-10-17 11:04:25,484 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-10-17 11:04:25,484 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-10-17 11:04:25,484 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-10-17 11:04:25,486 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-10-17 11:04:25,486 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_347855b0-ff3a-4f68-a6b0-dbc63c69658f/bin/uautomizer-J5u9QxTXDZ/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_347855b0-ff3a-4f68-a6b0-dbc63c69658f/bin/uautomizer-J5u9QxTXDZ Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 4d0fbec14d1477738cb6d25ea9b61fc7005f787f2c8a0ac2c555d7e4fa1dbf47 [2022-10-17 11:04:25,737 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-10-17 11:04:25,756 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-10-17 11:04:25,759 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-10-17 11:04:25,760 INFO L271 PluginConnector]: Initializing CDTParser... [2022-10-17 11:04:25,765 INFO L275 PluginConnector]: CDTParser initialized [2022-10-17 11:04:25,767 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_347855b0-ff3a-4f68-a6b0-dbc63c69658f/bin/uautomizer-J5u9QxTXDZ/../../sv-benchmarks/c/systemc/token_ring.06.cil-2.c [2022-10-17 11:04:25,826 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_347855b0-ff3a-4f68-a6b0-dbc63c69658f/bin/uautomizer-J5u9QxTXDZ/data/4a0469b1a/a39768c3accb4e599bcdc15d71853064/FLAG60aa26ce3 [2022-10-17 11:04:26,328 INFO L306 CDTParser]: Found 1 translation units. [2022-10-17 11:04:26,333 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_347855b0-ff3a-4f68-a6b0-dbc63c69658f/sv-benchmarks/c/systemc/token_ring.06.cil-2.c [2022-10-17 11:04:26,345 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_347855b0-ff3a-4f68-a6b0-dbc63c69658f/bin/uautomizer-J5u9QxTXDZ/data/4a0469b1a/a39768c3accb4e599bcdc15d71853064/FLAG60aa26ce3 [2022-10-17 11:04:26,682 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_347855b0-ff3a-4f68-a6b0-dbc63c69658f/bin/uautomizer-J5u9QxTXDZ/data/4a0469b1a/a39768c3accb4e599bcdc15d71853064 [2022-10-17 11:04:26,684 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-10-17 11:04:26,685 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-10-17 11:04:26,688 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-10-17 11:04:26,688 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-10-17 11:04:26,691 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-10-17 11:04:26,692 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.10 11:04:26" (1/1) ... [2022-10-17 11:04:26,693 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@27005a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 11:04:26, skipping insertion in model container [2022-10-17 11:04:26,693 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.10 11:04:26" (1/1) ... [2022-10-17 11:04:26,705 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-10-17 11:04:26,752 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-10-17 11:04:26,928 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_347855b0-ff3a-4f68-a6b0-dbc63c69658f/sv-benchmarks/c/systemc/token_ring.06.cil-2.c[671,684] [2022-10-17 11:04:27,012 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-10-17 11:04:27,022 INFO L203 MainTranslator]: Completed pre-run [2022-10-17 11:04:27,033 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_347855b0-ff3a-4f68-a6b0-dbc63c69658f/sv-benchmarks/c/systemc/token_ring.06.cil-2.c[671,684] [2022-10-17 11:04:27,090 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-10-17 11:04:27,109 INFO L208 MainTranslator]: Completed translation [2022-10-17 11:04:27,110 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 11:04:27 WrapperNode [2022-10-17 11:04:27,110 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-10-17 11:04:27,111 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-10-17 11:04:27,111 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-10-17 11:04:27,111 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-10-17 11:04:27,126 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 11:04:27" (1/1) ... [2022-10-17 11:04:27,138 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 11:04:27" (1/1) ... [2022-10-17 11:04:27,210 INFO L138 Inliner]: procedures = 40, calls = 49, calls flagged for inlining = 44, calls inlined = 113, statements flattened = 1650 [2022-10-17 11:04:27,210 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-10-17 11:04:27,211 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-10-17 11:04:27,211 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-10-17 11:04:27,211 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-10-17 11:04:27,222 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 11:04:27" (1/1) ... [2022-10-17 11:04:27,222 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 11:04:27" (1/1) ... [2022-10-17 11:04:27,232 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 11:04:27" (1/1) ... [2022-10-17 11:04:27,232 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 11:04:27" (1/1) ... [2022-10-17 11:04:27,260 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 11:04:27" (1/1) ... [2022-10-17 11:04:27,284 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 11:04:27" (1/1) ... [2022-10-17 11:04:27,307 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 11:04:27" (1/1) ... [2022-10-17 11:04:27,313 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 11:04:27" (1/1) ... [2022-10-17 11:04:27,343 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-10-17 11:04:27,344 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-10-17 11:04:27,344 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-10-17 11:04:27,344 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-10-17 11:04:27,345 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 11:04:27" (1/1) ... [2022-10-17 11:04:27,357 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 11:04:27,372 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_347855b0-ff3a-4f68-a6b0-dbc63c69658f/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 11:04:27,392 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_347855b0-ff3a-4f68-a6b0-dbc63c69658f/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 11:04:27,420 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_347855b0-ff3a-4f68-a6b0-dbc63c69658f/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-10-17 11:04:27,442 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-10-17 11:04:27,442 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-10-17 11:04:27,442 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-10-17 11:04:27,443 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-10-17 11:04:27,569 INFO L235 CfgBuilder]: Building ICFG [2022-10-17 11:04:27,571 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-10-17 11:04:29,143 INFO L276 CfgBuilder]: Performing block encoding [2022-10-17 11:04:29,158 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-10-17 11:04:29,158 INFO L300 CfgBuilder]: Removed 9 assume(true) statements. [2022-10-17 11:04:29,161 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 17.10 11:04:29 BoogieIcfgContainer [2022-10-17 11:04:29,161 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-10-17 11:04:29,162 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-10-17 11:04:29,162 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-10-17 11:04:29,166 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-10-17 11:04:29,167 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-10-17 11:04:29,167 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 17.10 11:04:26" (1/3) ... [2022-10-17 11:04:29,168 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7fcb57f7 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.10 11:04:29, skipping insertion in model container [2022-10-17 11:04:29,168 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-10-17 11:04:29,168 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 11:04:27" (2/3) ... [2022-10-17 11:04:29,169 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7fcb57f7 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.10 11:04:29, skipping insertion in model container [2022-10-17 11:04:29,169 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-10-17 11:04:29,169 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 17.10 11:04:29" (3/3) ... [2022-10-17 11:04:29,170 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.06.cil-2.c [2022-10-17 11:04:29,234 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-10-17 11:04:29,235 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-10-17 11:04:29,235 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-10-17 11:04:29,235 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-10-17 11:04:29,235 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-10-17 11:04:29,235 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-10-17 11:04:29,235 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-10-17 11:04:29,235 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-10-17 11:04:29,275 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 687 states, 686 states have (on average 1.5233236151603498) internal successors, (1045), 686 states have internal predecessors, (1045), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:04:29,350 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 592 [2022-10-17 11:04:29,350 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 11:04:29,350 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 11:04:29,376 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:04:29,376 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:04:29,377 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-10-17 11:04:29,379 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 687 states, 686 states have (on average 1.5233236151603498) internal successors, (1045), 686 states have internal predecessors, (1045), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:04:29,392 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 592 [2022-10-17 11:04:29,392 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 11:04:29,392 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 11:04:29,398 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:04:29,399 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:04:29,416 INFO L748 eck$LassoCheckResult]: Stem: 670#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 564#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 532#L1016true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 494#L468true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 91#L475true assume !(1 == ~m_i~0);~m_st~0 := 2; 551#L475-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 309#L480-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 614#L485-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 251#L490-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 120#L495-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 452#L500-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 80#L505-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 521#L684true assume !(0 == ~M_E~0); 436#L684-2true assume !(0 == ~T1_E~0); 278#L689-1true assume !(0 == ~T2_E~0); 662#L694-1true assume !(0 == ~T3_E~0); 277#L699-1true assume !(0 == ~T4_E~0); 430#L704-1true assume !(0 == ~T5_E~0); 239#L709-1true assume !(0 == ~T6_E~0); 198#L714-1true assume 0 == ~E_M~0;~E_M~0 := 1; 398#L719-1true assume !(0 == ~E_1~0); 579#L724-1true assume !(0 == ~E_2~0); 65#L729-1true assume !(0 == ~E_3~0); 559#L734-1true assume !(0 == ~E_4~0); 486#L739-1true assume !(0 == ~E_5~0); 171#L744-1true assume !(0 == ~E_6~0); 400#L749-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 46#L334true assume !(1 == ~m_pc~0); 233#L334-2true is_master_triggered_~__retres1~0#1 := 0; 497#L345true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 62#L346true activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 155#L849true assume !(0 != activate_threads_~tmp~1#1); 362#L849-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 118#L353true assume 1 == ~t1_pc~0; 587#L354true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 312#L364true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 70#L365true activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 287#L857true assume !(0 != activate_threads_~tmp___0~0#1); 93#L857-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 557#L372true assume !(1 == ~t2_pc~0); 161#L372-2true is_transmit2_triggered_~__retres1~2#1 := 0; 229#L383true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 511#L384true activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 472#L865true assume !(0 != activate_threads_~tmp___1~0#1); 40#L865-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 448#L391true assume 1 == ~t3_pc~0; 571#L392true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 111#L402true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 231#L403true activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 391#L873true assume !(0 != activate_threads_~tmp___2~0#1); 158#L873-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 468#L410true assume 1 == ~t4_pc~0; 586#L411true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 367#L421true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 539#L422true activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 474#L881true assume !(0 != activate_threads_~tmp___3~0#1); 163#L881-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 271#L429true assume !(1 == ~t5_pc~0); 67#L429-2true is_transmit5_triggered_~__retres1~5#1 := 0; 649#L440true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 32#L441true activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 335#L889true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 358#L889-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 151#L448true assume 1 == ~t6_pc~0; 89#L449true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 330#L459true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 415#L460true activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 526#L897true assume !(0 != activate_threads_~tmp___5~0#1); 636#L897-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 629#L762true assume !(1 == ~M_E~0); 185#L762-2true assume !(1 == ~T1_E~0); 584#L767-1true assume !(1 == ~T2_E~0); 536#L772-1true assume 1 == ~T3_E~0;~T3_E~0 := 2; 359#L777-1true assume !(1 == ~T4_E~0); 262#L782-1true assume !(1 == ~T5_E~0); 84#L787-1true assume !(1 == ~T6_E~0); 82#L792-1true assume !(1 == ~E_M~0); 104#L797-1true assume !(1 == ~E_1~0); 417#L802-1true assume !(1 == ~E_2~0); 236#L807-1true assume !(1 == ~E_3~0); 481#L812-1true assume 1 == ~E_4~0;~E_4~0 := 2; 605#L817-1true assume !(1 == ~E_5~0); 279#L822-1true assume !(1 == ~E_6~0); 495#L827-1true assume { :end_inline_reset_delta_events } true; 156#L1053-2true [2022-10-17 11:04:29,421 INFO L750 eck$LassoCheckResult]: Loop: 156#L1053-2true assume !false; 471#L1054true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 548#L659true assume !true; 350#L674true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 313#L468-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 253#L684-3true assume 0 == ~M_E~0;~M_E~0 := 1; 423#L684-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 2#L689-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 183#L694-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 28#L699-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 344#L704-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 477#L709-3true assume !(0 == ~T6_E~0); 322#L714-3true assume 0 == ~E_M~0;~E_M~0 := 1; 178#L719-3true assume 0 == ~E_1~0;~E_1~0 := 1; 25#L724-3true assume 0 == ~E_2~0;~E_2~0 := 1; 303#L729-3true assume 0 == ~E_3~0;~E_3~0 := 1; 369#L734-3true assume 0 == ~E_4~0;~E_4~0 := 1; 348#L739-3true assume 0 == ~E_5~0;~E_5~0 := 1; 527#L744-3true assume 0 == ~E_6~0;~E_6~0 := 1; 478#L749-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31#L334-24true assume !(1 == ~m_pc~0); 103#L334-26true is_master_triggered_~__retres1~0#1 := 0; 317#L345-8true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 655#L346-8true activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 18#L849-24true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 612#L849-26true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 346#L353-24true assume !(1 == ~t1_pc~0); 623#L353-26true is_transmit1_triggered_~__retres1~1#1 := 0; 545#L364-8true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 646#L365-8true activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 573#L857-24true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 42#L857-26true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 72#L372-24true assume 1 == ~t2_pc~0; 22#L373-8true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 221#L383-8true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 94#L384-8true activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 520#L865-24true assume !(0 != activate_threads_~tmp___1~0#1); 651#L865-26true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 200#L391-24true assume 1 == ~t3_pc~0; 463#L392-8true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 401#L402-8true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 483#L403-8true activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 264#L873-24true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 245#L873-26true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 134#L410-24true assume !(1 == ~t4_pc~0); 63#L410-26true is_transmit4_triggered_~__retres1~4#1 := 0; 373#L421-8true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 399#L422-8true activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 162#L881-24true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 81#L881-26true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 131#L429-24true assume 1 == ~t5_pc~0; 269#L430-8true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 372#L440-8true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 157#L441-8true activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 107#L889-24true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 214#L889-26true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 79#L448-24true assume 1 == ~t6_pc~0; 109#L449-8true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 74#L459-8true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 382#L460-8true activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 502#L897-24true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 273#L897-26true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 493#L762-3true assume 1 == ~M_E~0;~M_E~0 := 2; 242#L762-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 566#L767-3true assume !(1 == ~T2_E~0); 659#L772-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 530#L777-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 68#L782-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 635#L787-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 383#L792-3true assume 1 == ~E_M~0;~E_M~0 := 2; 199#L797-3true assume 1 == ~E_1~0;~E_1~0 := 2; 438#L802-3true assume 1 == ~E_2~0;~E_2~0 := 2; 653#L807-3true assume !(1 == ~E_3~0); 299#L812-3true assume 1 == ~E_4~0;~E_4~0 := 2; 489#L817-3true assume 1 == ~E_5~0;~E_5~0 := 2; 393#L822-3true assume 1 == ~E_6~0;~E_6~0 := 2; 375#L827-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 212#L518-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 376#L555-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 237#L556-1true start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 607#L1072true assume !(0 == start_simulation_~tmp~3#1); 143#L1072-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 485#L518-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 75#L555-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 35#L556-2true stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 36#L1027true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 589#L1034true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 385#L1035true start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 396#L1085true assume !(0 != start_simulation_~tmp___0~1#1); 156#L1053-2true [2022-10-17 11:04:29,443 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:04:29,443 INFO L85 PathProgramCache]: Analyzing trace with hash -376834623, now seen corresponding path program 1 times [2022-10-17 11:04:29,452 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:04:29,453 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [753517258] [2022-10-17 11:04:29,453 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:04:29,454 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:04:29,581 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:04:29,731 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:04:29,732 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:04:29,733 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [753517258] [2022-10-17 11:04:29,734 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [753517258] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:04:29,735 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:04:29,736 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:04:29,737 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1022516256] [2022-10-17 11:04:29,738 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:04:29,742 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 11:04:29,744 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:04:29,744 INFO L85 PathProgramCache]: Analyzing trace with hash 1474708463, now seen corresponding path program 1 times [2022-10-17 11:04:29,745 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:04:29,745 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [469606725] [2022-10-17 11:04:29,745 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:04:29,745 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:04:29,759 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:04:29,796 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:04:29,796 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:04:29,796 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [469606725] [2022-10-17 11:04:29,796 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [469606725] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:04:29,797 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:04:29,797 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-10-17 11:04:29,797 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [639659750] [2022-10-17 11:04:29,797 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:04:29,799 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 11:04:29,800 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 11:04:29,837 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 11:04:29,838 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 11:04:29,841 INFO L87 Difference]: Start difference. First operand has 687 states, 686 states have (on average 1.5233236151603498) internal successors, (1045), 686 states have internal predecessors, (1045), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:04:29,912 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 11:04:29,912 INFO L93 Difference]: Finished difference Result 686 states and 1024 transitions. [2022-10-17 11:04:29,913 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 686 states and 1024 transitions. [2022-10-17 11:04:29,921 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 590 [2022-10-17 11:04:29,934 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 686 states to 681 states and 1019 transitions. [2022-10-17 11:04:29,935 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 681 [2022-10-17 11:04:29,936 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 681 [2022-10-17 11:04:29,937 INFO L73 IsDeterministic]: Start isDeterministic. Operand 681 states and 1019 transitions. [2022-10-17 11:04:29,942 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 11:04:29,943 INFO L218 hiAutomatonCegarLoop]: Abstraction has 681 states and 1019 transitions. [2022-10-17 11:04:29,967 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 681 states and 1019 transitions. [2022-10-17 11:04:30,015 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 681 to 681. [2022-10-17 11:04:30,023 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 681 states, 681 states have (on average 1.4963289280469898) internal successors, (1019), 680 states have internal predecessors, (1019), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:04:30,026 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 681 states to 681 states and 1019 transitions. [2022-10-17 11:04:30,027 INFO L240 hiAutomatonCegarLoop]: Abstraction has 681 states and 1019 transitions. [2022-10-17 11:04:30,028 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 11:04:30,032 INFO L428 stractBuchiCegarLoop]: Abstraction has 681 states and 1019 transitions. [2022-10-17 11:04:30,032 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-10-17 11:04:30,032 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 681 states and 1019 transitions. [2022-10-17 11:04:30,037 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 590 [2022-10-17 11:04:30,037 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 11:04:30,038 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 11:04:30,039 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:04:30,040 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:04:30,040 INFO L748 eck$LassoCheckResult]: Stem: 2061#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 2041#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 2033#L1016 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2016#L468 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1566#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 1567#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1882#L480-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1883#L485-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1811#L490-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1615#L495-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1616#L500-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1547#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1548#L684 assume !(0 == ~M_E~0); 1984#L684-2 assume !(0 == ~T1_E~0); 1841#L689-1 assume !(0 == ~T2_E~0); 1842#L694-1 assume !(0 == ~T3_E~0); 1839#L699-1 assume !(0 == ~T4_E~0); 1840#L704-1 assume !(0 == ~T5_E~0); 1797#L709-1 assume !(0 == ~T6_E~0); 1742#L714-1 assume 0 == ~E_M~0;~E_M~0 := 1; 1743#L719-1 assume !(0 == ~E_1~0); 1961#L724-1 assume !(0 == ~E_2~0); 1519#L729-1 assume !(0 == ~E_3~0); 1520#L734-1 assume !(0 == ~E_4~0); 2013#L739-1 assume !(0 == ~E_5~0); 1702#L744-1 assume !(0 == ~E_6~0); 1703#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1480#L334 assume !(1 == ~m_pc~0); 1481#L334-2 is_master_triggered_~__retres1~0#1 := 0; 1788#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1513#L346 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1514#L849 assume !(0 != activate_threads_~tmp~1#1); 1676#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1610#L353 assume 1 == ~t1_pc~0; 1611#L354 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1886#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1529#L365 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1530#L857 assume !(0 != activate_threads_~tmp___0~0#1); 1568#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1569#L372 assume !(1 == ~t2_pc~0); 1663#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1662#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1782#L384 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2004#L865 assume !(0 != activate_threads_~tmp___1~0#1); 1467#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1468#L391 assume 1 == ~t3_pc~0; 1995#L392 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1389#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1596#L403 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1787#L873 assume !(0 != activate_threads_~tmp___2~0#1); 1680#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1681#L410 assume 1 == ~t4_pc~0; 2003#L411 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1903#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1935#L422 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2005#L881 assume !(0 != activate_threads_~tmp___3~0#1); 1690#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1691#L429 assume !(1 == ~t5_pc~0); 1523#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1524#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1454#L441 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1455#L889 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1909#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1671#L448 assume 1 == ~t6_pc~0; 1559#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1560#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1906#L460 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1971#L897 assume !(0 != activate_threads_~tmp___5~0#1); 2030#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2058#L762 assume !(1 == ~M_E~0); 1722#L762-2 assume !(1 == ~T1_E~0); 1723#L767-1 assume !(1 == ~T2_E~0); 2035#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1929#L777-1 assume !(1 == ~T4_E~0); 1824#L782-1 assume !(1 == ~T5_E~0); 1551#L787-1 assume !(1 == ~T6_E~0); 1549#L792-1 assume !(1 == ~E_M~0); 1550#L797-1 assume !(1 == ~E_1~0); 1587#L802-1 assume !(1 == ~E_2~0); 1793#L807-1 assume !(1 == ~E_3~0); 1794#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 2009#L817-1 assume !(1 == ~E_5~0); 1845#L822-1 assume !(1 == ~E_6~0); 1846#L827-1 assume { :end_inline_reset_delta_events } true; 1678#L1053-2 [2022-10-17 11:04:30,041 INFO L750 eck$LassoCheckResult]: Loop: 1678#L1053-2 assume !false; 1679#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1391#L659 assume !false; 1641#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1642#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1644#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 2062#L556 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1953#L570 assume !(0 != eval_~tmp~0#1); 1921#L674 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1887#L468-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1816#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1817#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1382#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1383#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1442#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1443#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1914#L709-3 assume !(0 == ~T6_E~0); 1899#L714-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1714#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1435#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1436#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1874#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1919#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1920#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2007#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1449#L334-24 assume 1 == ~m_pc~0; 1450#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1585#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1892#L346-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1423#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1424#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1916#L353-24 assume 1 == ~t1_pc~0; 1917#L354-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1946#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2036#L365-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2046#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1471#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1472#L372-24 assume 1 == ~t2_pc~0; 1428#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1429#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1570#L384-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1571#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 2024#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1747#L391-24 assume 1 == ~t3_pc~0; 1748#L392-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1962#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1963#L403-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1825#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1803#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1640#L410-24 assume 1 == ~t4_pc~0; 1586#L411-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1516#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1937#L422-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1686#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1545#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1546#L429-24 assume 1 == ~t5_pc~0; 1635#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1831#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1677#L441-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1590#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1591#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1540#L448-24 assume !(1 == ~t6_pc~0); 1541#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 1534#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1535#L460-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1945#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1835#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1836#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1801#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1802#L767-3 assume !(1 == ~T2_E~0); 2042#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2032#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1525#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1526#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1947#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1744#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1745#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1986#L807-3 assume !(1 == ~E_3~0); 1868#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1869#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1956#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1941#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1765#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1426#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1791#L556-1 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 1792#L1072 assume !(0 == start_simulation_~tmp~3#1); 1654#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1655#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1536#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1456#L556-2 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 1457#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1458#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1949#L1035 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 1950#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 1678#L1053-2 [2022-10-17 11:04:30,042 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:04:30,042 INFO L85 PathProgramCache]: Analyzing trace with hash 765667843, now seen corresponding path program 1 times [2022-10-17 11:04:30,042 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:04:30,042 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1163441866] [2022-10-17 11:04:30,042 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:04:30,043 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:04:30,061 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:04:30,178 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:04:30,178 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:04:30,179 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1163441866] [2022-10-17 11:04:30,179 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1163441866] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:04:30,179 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:04:30,179 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:04:30,180 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [256021244] [2022-10-17 11:04:30,180 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:04:30,180 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 11:04:30,181 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:04:30,181 INFO L85 PathProgramCache]: Analyzing trace with hash 1464043290, now seen corresponding path program 1 times [2022-10-17 11:04:30,182 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:04:30,182 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1598294439] [2022-10-17 11:04:30,182 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:04:30,183 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:04:30,207 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:04:30,281 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:04:30,282 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:04:30,282 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1598294439] [2022-10-17 11:04:30,282 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1598294439] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:04:30,283 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:04:30,283 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:04:30,283 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1148531663] [2022-10-17 11:04:30,283 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:04:30,284 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 11:04:30,284 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 11:04:30,284 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 11:04:30,285 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 11:04:30,285 INFO L87 Difference]: Start difference. First operand 681 states and 1019 transitions. cyclomatic complexity: 339 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:04:30,315 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 11:04:30,317 INFO L93 Difference]: Finished difference Result 681 states and 1018 transitions. [2022-10-17 11:04:30,317 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 681 states and 1018 transitions. [2022-10-17 11:04:30,325 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 590 [2022-10-17 11:04:30,331 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 681 states to 681 states and 1018 transitions. [2022-10-17 11:04:30,331 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 681 [2022-10-17 11:04:30,333 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 681 [2022-10-17 11:04:30,333 INFO L73 IsDeterministic]: Start isDeterministic. Operand 681 states and 1018 transitions. [2022-10-17 11:04:30,335 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 11:04:30,335 INFO L218 hiAutomatonCegarLoop]: Abstraction has 681 states and 1018 transitions. [2022-10-17 11:04:30,338 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 681 states and 1018 transitions. [2022-10-17 11:04:30,349 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 681 to 681. [2022-10-17 11:04:30,351 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 681 states, 681 states have (on average 1.4948604992657857) internal successors, (1018), 680 states have internal predecessors, (1018), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:04:30,355 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 681 states to 681 states and 1018 transitions. [2022-10-17 11:04:30,355 INFO L240 hiAutomatonCegarLoop]: Abstraction has 681 states and 1018 transitions. [2022-10-17 11:04:30,355 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 11:04:30,356 INFO L428 stractBuchiCegarLoop]: Abstraction has 681 states and 1018 transitions. [2022-10-17 11:04:30,357 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-10-17 11:04:30,357 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 681 states and 1018 transitions. [2022-10-17 11:04:30,362 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 590 [2022-10-17 11:04:30,362 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 11:04:30,362 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 11:04:30,364 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:04:30,368 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:04:30,369 INFO L748 eck$LassoCheckResult]: Stem: 3430#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 3410#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 3402#L1016 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3385#L468 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2933#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 2934#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3251#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3252#L485-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3180#L490-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2984#L495-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2985#L500-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 2914#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2915#L684 assume !(0 == ~M_E~0); 3353#L684-2 assume !(0 == ~T1_E~0); 3210#L689-1 assume !(0 == ~T2_E~0); 3211#L694-1 assume !(0 == ~T3_E~0); 3208#L699-1 assume !(0 == ~T4_E~0); 3209#L704-1 assume !(0 == ~T5_E~0); 3166#L709-1 assume !(0 == ~T6_E~0); 3111#L714-1 assume 0 == ~E_M~0;~E_M~0 := 1; 3112#L719-1 assume !(0 == ~E_1~0); 3330#L724-1 assume !(0 == ~E_2~0); 2888#L729-1 assume !(0 == ~E_3~0); 2889#L734-1 assume !(0 == ~E_4~0); 3382#L739-1 assume !(0 == ~E_5~0); 3071#L744-1 assume !(0 == ~E_6~0); 3072#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2849#L334 assume !(1 == ~m_pc~0); 2850#L334-2 is_master_triggered_~__retres1~0#1 := 0; 3157#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2882#L346 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2883#L849 assume !(0 != activate_threads_~tmp~1#1); 3045#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2979#L353 assume 1 == ~t1_pc~0; 2980#L354 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3255#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2898#L365 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2899#L857 assume !(0 != activate_threads_~tmp___0~0#1); 2937#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2938#L372 assume !(1 == ~t2_pc~0); 3032#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3031#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3151#L384 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3373#L865 assume !(0 != activate_threads_~tmp___1~0#1); 2836#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2837#L391 assume 1 == ~t3_pc~0; 3363#L392 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2756#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2965#L403 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3155#L873 assume !(0 != activate_threads_~tmp___2~0#1); 3049#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3050#L410 assume 1 == ~t4_pc~0; 3371#L411 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3271#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3304#L422 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3374#L881 assume !(0 != activate_threads_~tmp___3~0#1); 3056#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3057#L429 assume !(1 == ~t5_pc~0); 2892#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2893#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2821#L441 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2822#L889 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3278#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3040#L448 assume 1 == ~t6_pc~0; 2928#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2929#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3275#L460 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3340#L897 assume !(0 != activate_threads_~tmp___5~0#1); 3399#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3427#L762 assume !(1 == ~M_E~0); 3091#L762-2 assume !(1 == ~T1_E~0); 3092#L767-1 assume !(1 == ~T2_E~0); 3404#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3298#L777-1 assume !(1 == ~T4_E~0); 3193#L782-1 assume !(1 == ~T5_E~0); 2920#L787-1 assume !(1 == ~T6_E~0); 2918#L792-1 assume !(1 == ~E_M~0); 2919#L797-1 assume !(1 == ~E_1~0); 2955#L802-1 assume !(1 == ~E_2~0); 3160#L807-1 assume !(1 == ~E_3~0); 3161#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 3378#L817-1 assume !(1 == ~E_5~0); 3212#L822-1 assume !(1 == ~E_6~0); 3213#L827-1 assume { :end_inline_reset_delta_events } true; 3046#L1053-2 [2022-10-17 11:04:30,372 INFO L750 eck$LassoCheckResult]: Loop: 3046#L1053-2 assume !false; 3047#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2760#L659 assume !false; 3010#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 3011#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 3013#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 3431#L556 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3322#L570 assume !(0 != eval_~tmp~0#1); 3290#L674 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3256#L468-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3183#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3184#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2751#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2752#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2811#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2812#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3283#L709-3 assume !(0 == ~T6_E~0); 3266#L714-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3080#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2804#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2805#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3243#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3288#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3289#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3376#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2818#L334-24 assume 1 == ~m_pc~0; 2819#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2954#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3261#L346-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2790#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2791#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3285#L353-24 assume 1 == ~t1_pc~0; 3286#L354-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3313#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3405#L365-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3415#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2840#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2841#L372-24 assume 1 == ~t2_pc~0; 2797#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2798#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2939#L384-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2940#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 3394#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3116#L391-24 assume 1 == ~t3_pc~0; 3117#L392-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3331#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3332#L403-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3195#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3174#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3009#L410-24 assume !(1 == ~t4_pc~0); 2884#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 2885#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3306#L422-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3055#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2916#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2917#L429-24 assume 1 == ~t5_pc~0; 3004#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3200#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3048#L441-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2959#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2960#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2911#L448-24 assume !(1 == ~t6_pc~0); 2912#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 2903#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2904#L460-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3315#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3204#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3205#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3170#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3171#L767-3 assume !(1 == ~T2_E~0); 3411#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3401#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2894#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2895#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3316#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3113#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3114#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3355#L807-3 assume !(1 == ~E_3~0); 3237#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3238#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3325#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3310#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 3134#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2795#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 3162#L556-1 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 3163#L1072 assume !(0 == start_simulation_~tmp~3#1); 3023#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 3024#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2905#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 2827#L556-2 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 2828#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2829#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3318#L1035 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 3319#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 3046#L1053-2 [2022-10-17 11:04:30,373 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:04:30,373 INFO L85 PathProgramCache]: Analyzing trace with hash -73365819, now seen corresponding path program 1 times [2022-10-17 11:04:30,373 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:04:30,374 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [522472062] [2022-10-17 11:04:30,374 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:04:30,374 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:04:30,391 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:04:30,428 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:04:30,429 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:04:30,429 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [522472062] [2022-10-17 11:04:30,429 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [522472062] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:04:30,429 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:04:30,429 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:04:30,430 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1878115691] [2022-10-17 11:04:30,430 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:04:30,430 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 11:04:30,431 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:04:30,431 INFO L85 PathProgramCache]: Analyzing trace with hash 590565595, now seen corresponding path program 1 times [2022-10-17 11:04:30,431 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:04:30,431 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1525113004] [2022-10-17 11:04:30,431 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:04:30,432 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:04:30,450 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:04:30,500 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:04:30,500 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:04:30,501 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1525113004] [2022-10-17 11:04:30,501 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1525113004] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:04:30,501 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:04:30,501 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:04:30,502 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1803216062] [2022-10-17 11:04:30,502 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:04:30,502 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 11:04:30,502 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 11:04:30,503 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 11:04:30,503 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 11:04:30,503 INFO L87 Difference]: Start difference. First operand 681 states and 1018 transitions. cyclomatic complexity: 338 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:04:30,523 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 11:04:30,523 INFO L93 Difference]: Finished difference Result 681 states and 1017 transitions. [2022-10-17 11:04:30,523 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 681 states and 1017 transitions. [2022-10-17 11:04:30,530 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 590 [2022-10-17 11:04:30,536 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 681 states to 681 states and 1017 transitions. [2022-10-17 11:04:30,536 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 681 [2022-10-17 11:04:30,537 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 681 [2022-10-17 11:04:30,538 INFO L73 IsDeterministic]: Start isDeterministic. Operand 681 states and 1017 transitions. [2022-10-17 11:04:30,539 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 11:04:30,539 INFO L218 hiAutomatonCegarLoop]: Abstraction has 681 states and 1017 transitions. [2022-10-17 11:04:30,540 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 681 states and 1017 transitions. [2022-10-17 11:04:30,551 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 681 to 681. [2022-10-17 11:04:30,552 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 681 states, 681 states have (on average 1.4933920704845816) internal successors, (1017), 680 states have internal predecessors, (1017), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:04:30,556 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 681 states to 681 states and 1017 transitions. [2022-10-17 11:04:30,556 INFO L240 hiAutomatonCegarLoop]: Abstraction has 681 states and 1017 transitions. [2022-10-17 11:04:30,556 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 11:04:30,557 INFO L428 stractBuchiCegarLoop]: Abstraction has 681 states and 1017 transitions. [2022-10-17 11:04:30,557 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-10-17 11:04:30,557 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 681 states and 1017 transitions. [2022-10-17 11:04:30,562 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 590 [2022-10-17 11:04:30,563 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 11:04:30,563 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 11:04:30,565 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:04:30,565 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:04:30,565 INFO L748 eck$LassoCheckResult]: Stem: 4799#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 4779#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 4771#L1016 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4754#L468 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4302#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 4303#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4620#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4621#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4549#L490-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4353#L495-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4354#L500-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4283#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4284#L684 assume !(0 == ~M_E~0); 4722#L684-2 assume !(0 == ~T1_E~0); 4579#L689-1 assume !(0 == ~T2_E~0); 4580#L694-1 assume !(0 == ~T3_E~0); 4577#L699-1 assume !(0 == ~T4_E~0); 4578#L704-1 assume !(0 == ~T5_E~0); 4535#L709-1 assume !(0 == ~T6_E~0); 4480#L714-1 assume 0 == ~E_M~0;~E_M~0 := 1; 4481#L719-1 assume !(0 == ~E_1~0); 4699#L724-1 assume !(0 == ~E_2~0); 4257#L729-1 assume !(0 == ~E_3~0); 4258#L734-1 assume !(0 == ~E_4~0); 4751#L739-1 assume !(0 == ~E_5~0); 4440#L744-1 assume !(0 == ~E_6~0); 4441#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4218#L334 assume !(1 == ~m_pc~0); 4219#L334-2 is_master_triggered_~__retres1~0#1 := 0; 4526#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4251#L346 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4252#L849 assume !(0 != activate_threads_~tmp~1#1); 4414#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4348#L353 assume 1 == ~t1_pc~0; 4349#L354 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4624#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4267#L365 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4268#L857 assume !(0 != activate_threads_~tmp___0~0#1); 4306#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4307#L372 assume !(1 == ~t2_pc~0); 4401#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4400#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4520#L384 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4742#L865 assume !(0 != activate_threads_~tmp___1~0#1); 4205#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4206#L391 assume 1 == ~t3_pc~0; 4732#L392 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4125#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4334#L403 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4524#L873 assume !(0 != activate_threads_~tmp___2~0#1); 4418#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4419#L410 assume 1 == ~t4_pc~0; 4741#L411 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4640#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4673#L422 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4743#L881 assume !(0 != activate_threads_~tmp___3~0#1); 4425#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4426#L429 assume !(1 == ~t5_pc~0); 4261#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4262#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4190#L441 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4191#L889 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4647#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4409#L448 assume 1 == ~t6_pc~0; 4297#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4298#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4644#L460 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4709#L897 assume !(0 != activate_threads_~tmp___5~0#1); 4768#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4796#L762 assume !(1 == ~M_E~0); 4460#L762-2 assume !(1 == ~T1_E~0); 4461#L767-1 assume !(1 == ~T2_E~0); 4773#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4667#L777-1 assume !(1 == ~T4_E~0); 4562#L782-1 assume !(1 == ~T5_E~0); 4289#L787-1 assume !(1 == ~T6_E~0); 4287#L792-1 assume !(1 == ~E_M~0); 4288#L797-1 assume !(1 == ~E_1~0); 4324#L802-1 assume !(1 == ~E_2~0); 4529#L807-1 assume !(1 == ~E_3~0); 4530#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 4747#L817-1 assume !(1 == ~E_5~0); 4583#L822-1 assume !(1 == ~E_6~0); 4584#L827-1 assume { :end_inline_reset_delta_events } true; 4415#L1053-2 [2022-10-17 11:04:30,566 INFO L750 eck$LassoCheckResult]: Loop: 4415#L1053-2 assume !false; 4416#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4129#L659 assume !false; 4379#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4380#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 4382#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4800#L556 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 4691#L570 assume !(0 != eval_~tmp~0#1); 4659#L674 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4625#L468-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4553#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4554#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4120#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4121#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4180#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4181#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4652#L709-3 assume !(0 == ~T6_E~0); 4635#L714-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4449#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4173#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4174#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4612#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4657#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4658#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4745#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4187#L334-24 assume 1 == ~m_pc~0; 4188#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4323#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4630#L346-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4159#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4160#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4654#L353-24 assume !(1 == ~t1_pc~0); 4656#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 4682#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4774#L365-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4784#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4209#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4210#L372-24 assume 1 == ~t2_pc~0; 4166#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4167#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4308#L384-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4309#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 4763#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4485#L391-24 assume 1 == ~t3_pc~0; 4486#L392-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4700#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4701#L403-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4564#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4543#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4378#L410-24 assume 1 == ~t4_pc~0; 4325#L411-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4254#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4675#L422-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4424#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4285#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4286#L429-24 assume 1 == ~t5_pc~0; 4373#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4569#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4417#L441-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4328#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4329#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4280#L448-24 assume !(1 == ~t6_pc~0); 4281#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 4272#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4273#L460-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4684#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4573#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4574#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4539#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4540#L767-3 assume !(1 == ~T2_E~0); 4780#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4770#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4263#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4264#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4685#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4482#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4483#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4724#L807-3 assume !(1 == ~E_3~0); 4606#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4607#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4694#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4679#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4503#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 4164#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4531#L556-1 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 4532#L1072 assume !(0 == start_simulation_~tmp~3#1); 4392#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4393#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 4274#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4196#L556-2 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 4197#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4198#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4687#L1035 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 4688#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 4415#L1053-2 [2022-10-17 11:04:30,566 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:04:30,566 INFO L85 PathProgramCache]: Analyzing trace with hash -100431421, now seen corresponding path program 1 times [2022-10-17 11:04:30,567 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:04:30,567 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [429620914] [2022-10-17 11:04:30,567 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:04:30,567 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:04:30,582 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:04:30,629 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:04:30,630 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:04:30,630 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [429620914] [2022-10-17 11:04:30,630 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [429620914] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:04:30,630 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:04:30,631 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:04:30,631 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1747806497] [2022-10-17 11:04:30,631 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:04:30,632 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 11:04:30,632 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:04:30,632 INFO L85 PathProgramCache]: Analyzing trace with hash 2040971931, now seen corresponding path program 1 times [2022-10-17 11:04:30,632 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:04:30,633 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1294997776] [2022-10-17 11:04:30,633 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:04:30,633 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:04:30,651 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:04:30,699 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:04:30,700 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:04:30,700 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1294997776] [2022-10-17 11:04:30,700 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1294997776] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:04:30,700 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:04:30,701 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:04:30,701 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [369268912] [2022-10-17 11:04:30,701 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:04:30,701 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 11:04:30,702 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 11:04:30,702 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 11:04:30,702 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 11:04:30,703 INFO L87 Difference]: Start difference. First operand 681 states and 1017 transitions. cyclomatic complexity: 337 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:04:30,723 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 11:04:30,723 INFO L93 Difference]: Finished difference Result 681 states and 1016 transitions. [2022-10-17 11:04:30,724 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 681 states and 1016 transitions. [2022-10-17 11:04:30,731 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 590 [2022-10-17 11:04:30,737 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 681 states to 681 states and 1016 transitions. [2022-10-17 11:04:30,738 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 681 [2022-10-17 11:04:30,738 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 681 [2022-10-17 11:04:30,739 INFO L73 IsDeterministic]: Start isDeterministic. Operand 681 states and 1016 transitions. [2022-10-17 11:04:30,740 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 11:04:30,740 INFO L218 hiAutomatonCegarLoop]: Abstraction has 681 states and 1016 transitions. [2022-10-17 11:04:30,742 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 681 states and 1016 transitions. [2022-10-17 11:04:30,754 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 681 to 681. [2022-10-17 11:04:30,755 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 681 states, 681 states have (on average 1.4919236417033774) internal successors, (1016), 680 states have internal predecessors, (1016), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:04:30,757 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 681 states to 681 states and 1016 transitions. [2022-10-17 11:04:30,758 INFO L240 hiAutomatonCegarLoop]: Abstraction has 681 states and 1016 transitions. [2022-10-17 11:04:30,762 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 11:04:30,763 INFO L428 stractBuchiCegarLoop]: Abstraction has 681 states and 1016 transitions. [2022-10-17 11:04:30,764 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-10-17 11:04:30,764 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 681 states and 1016 transitions. [2022-10-17 11:04:30,769 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 590 [2022-10-17 11:04:30,769 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 11:04:30,770 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 11:04:30,771 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:04:30,772 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:04:30,772 INFO L748 eck$LassoCheckResult]: Stem: 6168#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 6148#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 6140#L1016 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6123#L468 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5673#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 5674#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5989#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5990#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5918#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5722#L495-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5723#L500-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5654#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5655#L684 assume !(0 == ~M_E~0); 6091#L684-2 assume !(0 == ~T1_E~0); 5948#L689-1 assume !(0 == ~T2_E~0); 5949#L694-1 assume !(0 == ~T3_E~0); 5946#L699-1 assume !(0 == ~T4_E~0); 5947#L704-1 assume !(0 == ~T5_E~0); 5904#L709-1 assume !(0 == ~T6_E~0); 5849#L714-1 assume 0 == ~E_M~0;~E_M~0 := 1; 5850#L719-1 assume !(0 == ~E_1~0); 6068#L724-1 assume !(0 == ~E_2~0); 5626#L729-1 assume !(0 == ~E_3~0); 5627#L734-1 assume !(0 == ~E_4~0); 6120#L739-1 assume !(0 == ~E_5~0); 5809#L744-1 assume !(0 == ~E_6~0); 5810#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5587#L334 assume !(1 == ~m_pc~0); 5588#L334-2 is_master_triggered_~__retres1~0#1 := 0; 5895#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5620#L346 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5621#L849 assume !(0 != activate_threads_~tmp~1#1); 5783#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5717#L353 assume 1 == ~t1_pc~0; 5718#L354 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5993#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5636#L365 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5637#L857 assume !(0 != activate_threads_~tmp___0~0#1); 5675#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5676#L372 assume !(1 == ~t2_pc~0); 5770#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5769#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5889#L384 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6111#L865 assume !(0 != activate_threads_~tmp___1~0#1); 5574#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5575#L391 assume 1 == ~t3_pc~0; 6102#L392 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5496#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5703#L403 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5894#L873 assume !(0 != activate_threads_~tmp___2~0#1); 5787#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5788#L410 assume 1 == ~t4_pc~0; 6110#L411 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6010#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6042#L422 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6112#L881 assume !(0 != activate_threads_~tmp___3~0#1); 5797#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5798#L429 assume !(1 == ~t5_pc~0); 5630#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 5631#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5561#L441 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5562#L889 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6016#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5778#L448 assume 1 == ~t6_pc~0; 5666#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5667#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6013#L460 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6078#L897 assume !(0 != activate_threads_~tmp___5~0#1); 6137#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6165#L762 assume !(1 == ~M_E~0); 5829#L762-2 assume !(1 == ~T1_E~0); 5830#L767-1 assume !(1 == ~T2_E~0); 6142#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6036#L777-1 assume !(1 == ~T4_E~0); 5931#L782-1 assume !(1 == ~T5_E~0); 5658#L787-1 assume !(1 == ~T6_E~0); 5656#L792-1 assume !(1 == ~E_M~0); 5657#L797-1 assume !(1 == ~E_1~0); 5694#L802-1 assume !(1 == ~E_2~0); 5900#L807-1 assume !(1 == ~E_3~0); 5901#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 6116#L817-1 assume !(1 == ~E_5~0); 5952#L822-1 assume !(1 == ~E_6~0); 5953#L827-1 assume { :end_inline_reset_delta_events } true; 5785#L1053-2 [2022-10-17 11:04:30,773 INFO L750 eck$LassoCheckResult]: Loop: 5785#L1053-2 assume !false; 5786#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5498#L659 assume !false; 5748#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 5749#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 5751#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 6169#L556 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 6060#L570 assume !(0 != eval_~tmp~0#1); 6028#L674 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5994#L468-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5923#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5924#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5489#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5490#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5549#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5550#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6021#L709-3 assume !(0 == ~T6_E~0); 6006#L714-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5821#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5542#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5543#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5981#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6026#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6027#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6114#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5556#L334-24 assume 1 == ~m_pc~0; 5557#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5692#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5999#L346-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5530#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5531#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6022#L353-24 assume 1 == ~t1_pc~0; 6023#L354-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6051#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6143#L365-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6153#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5578#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5579#L372-24 assume !(1 == ~t2_pc~0); 5537#L372-26 is_transmit2_triggered_~__retres1~2#1 := 0; 5536#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5677#L384-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5678#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 6131#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5854#L391-24 assume !(1 == ~t3_pc~0); 5856#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 6069#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6070#L403-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5932#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5910#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5747#L410-24 assume !(1 == ~t4_pc~0); 5622#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 5623#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6044#L422-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5793#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5652#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5653#L429-24 assume 1 == ~t5_pc~0; 5742#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5938#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5784#L441-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5697#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5698#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5647#L448-24 assume !(1 == ~t6_pc~0); 5648#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 5641#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5642#L460-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6053#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5942#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5943#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5908#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5909#L767-3 assume !(1 == ~T2_E~0); 6149#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6139#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5632#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5633#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6054#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5851#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5852#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6093#L807-3 assume !(1 == ~E_3~0); 5975#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5976#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6063#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6048#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 5872#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 5533#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 5898#L556-1 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 5899#L1072 assume !(0 == start_simulation_~tmp~3#1); 5761#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 5762#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 5643#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 5563#L556-2 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 5564#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5565#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6056#L1035 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 6057#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 5785#L1053-2 [2022-10-17 11:04:30,774 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:04:30,774 INFO L85 PathProgramCache]: Analyzing trace with hash 1976905477, now seen corresponding path program 1 times [2022-10-17 11:04:30,775 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:04:30,776 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [74622895] [2022-10-17 11:04:30,776 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:04:30,776 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:04:30,810 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:04:30,841 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:04:30,841 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:04:30,841 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [74622895] [2022-10-17 11:04:30,842 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [74622895] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:04:30,842 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:04:30,842 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:04:30,842 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1643048795] [2022-10-17 11:04:30,843 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:04:30,843 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 11:04:30,844 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:04:30,844 INFO L85 PathProgramCache]: Analyzing trace with hash -1270008291, now seen corresponding path program 1 times [2022-10-17 11:04:30,844 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:04:30,844 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1588088188] [2022-10-17 11:04:30,845 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:04:30,845 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:04:30,859 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:04:30,899 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:04:30,899 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:04:30,900 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1588088188] [2022-10-17 11:04:30,906 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1588088188] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:04:30,906 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:04:30,907 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:04:30,907 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1677260905] [2022-10-17 11:04:30,907 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:04:30,908 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 11:04:30,908 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 11:04:30,908 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 11:04:30,909 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 11:04:30,909 INFO L87 Difference]: Start difference. First operand 681 states and 1016 transitions. cyclomatic complexity: 336 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:04:30,930 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 11:04:30,930 INFO L93 Difference]: Finished difference Result 681 states and 1015 transitions. [2022-10-17 11:04:30,931 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 681 states and 1015 transitions. [2022-10-17 11:04:30,937 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 590 [2022-10-17 11:04:30,943 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 681 states to 681 states and 1015 transitions. [2022-10-17 11:04:30,943 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 681 [2022-10-17 11:04:30,945 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 681 [2022-10-17 11:04:30,945 INFO L73 IsDeterministic]: Start isDeterministic. Operand 681 states and 1015 transitions. [2022-10-17 11:04:30,946 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 11:04:30,946 INFO L218 hiAutomatonCegarLoop]: Abstraction has 681 states and 1015 transitions. [2022-10-17 11:04:30,948 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 681 states and 1015 transitions. [2022-10-17 11:04:30,957 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 681 to 681. [2022-10-17 11:04:30,959 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 681 states, 681 states have (on average 1.4904552129221733) internal successors, (1015), 680 states have internal predecessors, (1015), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:04:30,962 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 681 states to 681 states and 1015 transitions. [2022-10-17 11:04:30,962 INFO L240 hiAutomatonCegarLoop]: Abstraction has 681 states and 1015 transitions. [2022-10-17 11:04:30,963 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 11:04:30,965 INFO L428 stractBuchiCegarLoop]: Abstraction has 681 states and 1015 transitions. [2022-10-17 11:04:30,966 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-10-17 11:04:30,966 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 681 states and 1015 transitions. [2022-10-17 11:04:30,970 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 590 [2022-10-17 11:04:30,971 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 11:04:30,971 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 11:04:30,973 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:04:30,973 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:04:30,973 INFO L748 eck$LassoCheckResult]: Stem: 7537#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 7517#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 7509#L1016 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7492#L468 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7040#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 7041#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7358#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7359#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7287#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7091#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 7092#L500-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7021#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7022#L684 assume !(0 == ~M_E~0); 7460#L684-2 assume !(0 == ~T1_E~0); 7317#L689-1 assume !(0 == ~T2_E~0); 7318#L694-1 assume !(0 == ~T3_E~0); 7315#L699-1 assume !(0 == ~T4_E~0); 7316#L704-1 assume !(0 == ~T5_E~0); 7273#L709-1 assume !(0 == ~T6_E~0); 7218#L714-1 assume 0 == ~E_M~0;~E_M~0 := 1; 7219#L719-1 assume !(0 == ~E_1~0); 7437#L724-1 assume !(0 == ~E_2~0); 6995#L729-1 assume !(0 == ~E_3~0); 6996#L734-1 assume !(0 == ~E_4~0); 7489#L739-1 assume !(0 == ~E_5~0); 7178#L744-1 assume !(0 == ~E_6~0); 7179#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6956#L334 assume !(1 == ~m_pc~0); 6957#L334-2 is_master_triggered_~__retres1~0#1 := 0; 7264#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6989#L346 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6990#L849 assume !(0 != activate_threads_~tmp~1#1); 7152#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7086#L353 assume 1 == ~t1_pc~0; 7087#L354 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7362#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7005#L365 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7006#L857 assume !(0 != activate_threads_~tmp___0~0#1); 7044#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7045#L372 assume !(1 == ~t2_pc~0); 7139#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7138#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7258#L384 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7480#L865 assume !(0 != activate_threads_~tmp___1~0#1); 6943#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6944#L391 assume 1 == ~t3_pc~0; 7470#L392 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6863#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7072#L403 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7262#L873 assume !(0 != activate_threads_~tmp___2~0#1); 7156#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7157#L410 assume 1 == ~t4_pc~0; 7478#L411 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7378#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7411#L422 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7481#L881 assume !(0 != activate_threads_~tmp___3~0#1); 7163#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7164#L429 assume !(1 == ~t5_pc~0); 6999#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 7000#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6928#L441 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6929#L889 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7385#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7147#L448 assume 1 == ~t6_pc~0; 7035#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7036#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7382#L460 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7447#L897 assume !(0 != activate_threads_~tmp___5~0#1); 7506#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7534#L762 assume !(1 == ~M_E~0); 7198#L762-2 assume !(1 == ~T1_E~0); 7199#L767-1 assume !(1 == ~T2_E~0); 7511#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7405#L777-1 assume !(1 == ~T4_E~0); 7300#L782-1 assume !(1 == ~T5_E~0); 7027#L787-1 assume !(1 == ~T6_E~0); 7025#L792-1 assume !(1 == ~E_M~0); 7026#L797-1 assume !(1 == ~E_1~0); 7062#L802-1 assume !(1 == ~E_2~0); 7267#L807-1 assume !(1 == ~E_3~0); 7268#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 7485#L817-1 assume !(1 == ~E_5~0); 7319#L822-1 assume !(1 == ~E_6~0); 7320#L827-1 assume { :end_inline_reset_delta_events } true; 7153#L1053-2 [2022-10-17 11:04:30,973 INFO L750 eck$LassoCheckResult]: Loop: 7153#L1053-2 assume !false; 7154#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6867#L659 assume !false; 7117#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 7118#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 7120#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 7538#L556 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 7429#L570 assume !(0 != eval_~tmp~0#1); 7397#L674 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7363#L468-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7290#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7291#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6858#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6859#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6918#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6919#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7390#L709-3 assume !(0 == ~T6_E~0); 7373#L714-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7187#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6911#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6912#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7350#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7395#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7396#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7483#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6925#L334-24 assume 1 == ~m_pc~0; 6926#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7061#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7368#L346-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6897#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6898#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7392#L353-24 assume 1 == ~t1_pc~0; 7393#L354-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7420#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7512#L365-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7522#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6947#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6948#L372-24 assume 1 == ~t2_pc~0; 6904#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6905#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7046#L384-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7047#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 7501#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7223#L391-24 assume 1 == ~t3_pc~0; 7224#L392-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7438#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7439#L403-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7302#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7281#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7116#L410-24 assume 1 == ~t4_pc~0; 7063#L411-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6992#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7413#L422-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7162#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7023#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7024#L429-24 assume 1 == ~t5_pc~0; 7111#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7307#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7155#L441-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7066#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7067#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7018#L448-24 assume !(1 == ~t6_pc~0); 7019#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 7010#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7011#L460-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7422#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7311#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7312#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7277#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7278#L767-3 assume !(1 == ~T2_E~0); 7518#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7508#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7001#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7002#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7423#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7220#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7221#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7462#L807-3 assume !(1 == ~E_3~0); 7344#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7345#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7432#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 7417#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 7241#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 6902#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 7269#L556-1 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 7270#L1072 assume !(0 == start_simulation_~tmp~3#1); 7130#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 7131#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 7012#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 6934#L556-2 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 6935#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6936#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7425#L1035 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 7426#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 7153#L1053-2 [2022-10-17 11:04:30,974 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:04:30,975 INFO L85 PathProgramCache]: Analyzing trace with hash 242801027, now seen corresponding path program 1 times [2022-10-17 11:04:30,976 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:04:30,977 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [662387671] [2022-10-17 11:04:30,977 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:04:30,977 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:04:30,998 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:04:31,037 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:04:31,037 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:04:31,038 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [662387671] [2022-10-17 11:04:31,038 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [662387671] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:04:31,039 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:04:31,039 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:04:31,044 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1171315942] [2022-10-17 11:04:31,045 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:04:31,046 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 11:04:31,047 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:04:31,049 INFO L85 PathProgramCache]: Analyzing trace with hash 1464043290, now seen corresponding path program 2 times [2022-10-17 11:04:31,050 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:04:31,050 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2005901936] [2022-10-17 11:04:31,051 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:04:31,051 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:04:31,069 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:04:31,113 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:04:31,114 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:04:31,114 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2005901936] [2022-10-17 11:04:31,120 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2005901936] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:04:31,120 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:04:31,120 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:04:31,120 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [975526293] [2022-10-17 11:04:31,120 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:04:31,121 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 11:04:31,122 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 11:04:31,122 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 11:04:31,123 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 11:04:31,123 INFO L87 Difference]: Start difference. First operand 681 states and 1015 transitions. cyclomatic complexity: 335 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:04:31,140 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 11:04:31,140 INFO L93 Difference]: Finished difference Result 681 states and 1014 transitions. [2022-10-17 11:04:31,140 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 681 states and 1014 transitions. [2022-10-17 11:04:31,147 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 590 [2022-10-17 11:04:31,152 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 681 states to 681 states and 1014 transitions. [2022-10-17 11:04:31,153 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 681 [2022-10-17 11:04:31,154 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 681 [2022-10-17 11:04:31,154 INFO L73 IsDeterministic]: Start isDeterministic. Operand 681 states and 1014 transitions. [2022-10-17 11:04:31,155 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 11:04:31,155 INFO L218 hiAutomatonCegarLoop]: Abstraction has 681 states and 1014 transitions. [2022-10-17 11:04:31,157 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 681 states and 1014 transitions. [2022-10-17 11:04:31,167 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 681 to 681. [2022-10-17 11:04:31,169 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 681 states, 681 states have (on average 1.4889867841409692) internal successors, (1014), 680 states have internal predecessors, (1014), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:04:31,172 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 681 states to 681 states and 1014 transitions. [2022-10-17 11:04:31,172 INFO L240 hiAutomatonCegarLoop]: Abstraction has 681 states and 1014 transitions. [2022-10-17 11:04:31,173 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 11:04:31,176 INFO L428 stractBuchiCegarLoop]: Abstraction has 681 states and 1014 transitions. [2022-10-17 11:04:31,176 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-10-17 11:04:31,176 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 681 states and 1014 transitions. [2022-10-17 11:04:31,181 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 590 [2022-10-17 11:04:31,181 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 11:04:31,181 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 11:04:31,182 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:04:31,183 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:04:31,183 INFO L748 eck$LassoCheckResult]: Stem: 8906#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 8886#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 8878#L1016 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8861#L468 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8409#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 8410#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8727#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8728#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8656#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8460#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 8461#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 8390#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8391#L684 assume !(0 == ~M_E~0); 8829#L684-2 assume !(0 == ~T1_E~0); 8686#L689-1 assume !(0 == ~T2_E~0); 8687#L694-1 assume !(0 == ~T3_E~0); 8684#L699-1 assume !(0 == ~T4_E~0); 8685#L704-1 assume !(0 == ~T5_E~0); 8642#L709-1 assume !(0 == ~T6_E~0); 8587#L714-1 assume 0 == ~E_M~0;~E_M~0 := 1; 8588#L719-1 assume !(0 == ~E_1~0); 8806#L724-1 assume !(0 == ~E_2~0); 8364#L729-1 assume !(0 == ~E_3~0); 8365#L734-1 assume !(0 == ~E_4~0); 8858#L739-1 assume !(0 == ~E_5~0); 8547#L744-1 assume !(0 == ~E_6~0); 8548#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8325#L334 assume !(1 == ~m_pc~0); 8326#L334-2 is_master_triggered_~__retres1~0#1 := 0; 8633#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8358#L346 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 8359#L849 assume !(0 != activate_threads_~tmp~1#1); 8521#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8455#L353 assume 1 == ~t1_pc~0; 8456#L354 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8731#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8374#L365 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8375#L857 assume !(0 != activate_threads_~tmp___0~0#1); 8413#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8414#L372 assume !(1 == ~t2_pc~0); 8508#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 8507#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8627#L384 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8849#L865 assume !(0 != activate_threads_~tmp___1~0#1); 8312#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8313#L391 assume 1 == ~t3_pc~0; 8839#L392 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8232#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8441#L403 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8631#L873 assume !(0 != activate_threads_~tmp___2~0#1); 8525#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8526#L410 assume 1 == ~t4_pc~0; 8848#L411 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8747#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8780#L422 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8850#L881 assume !(0 != activate_threads_~tmp___3~0#1); 8532#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8533#L429 assume !(1 == ~t5_pc~0); 8368#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 8369#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8297#L441 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8298#L889 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8754#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8516#L448 assume 1 == ~t6_pc~0; 8404#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8405#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8751#L460 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8816#L897 assume !(0 != activate_threads_~tmp___5~0#1); 8875#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8903#L762 assume !(1 == ~M_E~0); 8567#L762-2 assume !(1 == ~T1_E~0); 8568#L767-1 assume !(1 == ~T2_E~0); 8880#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8774#L777-1 assume !(1 == ~T4_E~0); 8669#L782-1 assume !(1 == ~T5_E~0); 8396#L787-1 assume !(1 == ~T6_E~0); 8394#L792-1 assume !(1 == ~E_M~0); 8395#L797-1 assume !(1 == ~E_1~0); 8431#L802-1 assume !(1 == ~E_2~0); 8636#L807-1 assume !(1 == ~E_3~0); 8637#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 8854#L817-1 assume !(1 == ~E_5~0); 8690#L822-1 assume !(1 == ~E_6~0); 8691#L827-1 assume { :end_inline_reset_delta_events } true; 8522#L1053-2 [2022-10-17 11:04:31,183 INFO L750 eck$LassoCheckResult]: Loop: 8522#L1053-2 assume !false; 8523#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8236#L659 assume !false; 8486#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 8487#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 8489#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 8907#L556 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 8798#L570 assume !(0 != eval_~tmp~0#1); 8766#L674 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8732#L468-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8660#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8661#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8227#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8228#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8287#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8288#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8759#L709-3 assume !(0 == ~T6_E~0); 8742#L714-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8556#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8280#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8281#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8719#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8764#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8765#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8852#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8294#L334-24 assume 1 == ~m_pc~0; 8295#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 8430#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8737#L346-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 8266#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8267#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8761#L353-24 assume 1 == ~t1_pc~0; 8762#L354-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8789#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8881#L365-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8891#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8316#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8317#L372-24 assume 1 == ~t2_pc~0; 8273#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8274#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8415#L384-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8416#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 8870#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8592#L391-24 assume 1 == ~t3_pc~0; 8593#L392-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8807#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8808#L403-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8671#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8650#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8485#L410-24 assume 1 == ~t4_pc~0; 8432#L411-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8361#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8782#L422-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8531#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8392#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8393#L429-24 assume 1 == ~t5_pc~0; 8480#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8676#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8524#L441-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8435#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8436#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8387#L448-24 assume !(1 == ~t6_pc~0); 8388#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 8379#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8380#L460-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8791#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8680#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8681#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8646#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8647#L767-3 assume !(1 == ~T2_E~0); 8887#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8877#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8370#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8371#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8792#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8589#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8590#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8831#L807-3 assume !(1 == ~E_3~0); 8713#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8714#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8801#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8786#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 8610#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 8271#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 8638#L556-1 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 8639#L1072 assume !(0 == start_simulation_~tmp~3#1); 8499#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 8500#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 8381#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 8303#L556-2 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 8304#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8305#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8794#L1035 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 8795#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 8522#L1053-2 [2022-10-17 11:04:31,184 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:04:31,185 INFO L85 PathProgramCache]: Analyzing trace with hash -644421819, now seen corresponding path program 1 times [2022-10-17 11:04:31,185 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:04:31,185 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [893148489] [2022-10-17 11:04:31,185 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:04:31,185 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:04:31,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:04:31,294 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:04:31,294 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:04:31,294 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [893148489] [2022-10-17 11:04:31,295 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [893148489] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:04:31,295 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:04:31,295 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:04:31,295 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [785591558] [2022-10-17 11:04:31,295 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:04:31,296 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 11:04:31,296 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:04:31,296 INFO L85 PathProgramCache]: Analyzing trace with hash 1464043290, now seen corresponding path program 3 times [2022-10-17 11:04:31,296 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:04:31,297 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [932256640] [2022-10-17 11:04:31,297 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:04:31,297 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:04:31,311 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:04:31,343 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:04:31,343 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:04:31,343 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [932256640] [2022-10-17 11:04:31,343 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [932256640] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:04:31,344 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:04:31,345 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:04:31,345 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [487900567] [2022-10-17 11:04:31,346 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:04:31,346 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 11:04:31,346 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 11:04:31,347 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-10-17 11:04:31,347 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-10-17 11:04:31,347 INFO L87 Difference]: Start difference. First operand 681 states and 1014 transitions. cyclomatic complexity: 334 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:04:31,519 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 11:04:31,519 INFO L93 Difference]: Finished difference Result 1170 states and 1738 transitions. [2022-10-17 11:04:31,519 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1170 states and 1738 transitions. [2022-10-17 11:04:31,530 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1064 [2022-10-17 11:04:31,540 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1170 states to 1170 states and 1738 transitions. [2022-10-17 11:04:31,540 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1170 [2022-10-17 11:04:31,541 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1170 [2022-10-17 11:04:31,542 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1170 states and 1738 transitions. [2022-10-17 11:04:31,544 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 11:04:31,544 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1170 states and 1738 transitions. [2022-10-17 11:04:31,547 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1170 states and 1738 transitions. [2022-10-17 11:04:31,569 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1170 to 1169. [2022-10-17 11:04:31,571 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1169 states, 1169 states have (on average 1.485885372112917) internal successors, (1737), 1168 states have internal predecessors, (1737), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:04:31,577 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1169 states to 1169 states and 1737 transitions. [2022-10-17 11:04:31,577 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1169 states and 1737 transitions. [2022-10-17 11:04:31,577 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-10-17 11:04:31,580 INFO L428 stractBuchiCegarLoop]: Abstraction has 1169 states and 1737 transitions. [2022-10-17 11:04:31,580 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-10-17 11:04:31,580 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1169 states and 1737 transitions. [2022-10-17 11:04:31,588 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1064 [2022-10-17 11:04:31,588 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 11:04:31,588 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 11:04:31,590 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:04:31,590 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:04:31,590 INFO L748 eck$LassoCheckResult]: Stem: 10804#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 10780#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 10771#L1016 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10752#L468 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10270#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 10271#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10594#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10595#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10521#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10321#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 10322#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 10251#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10252#L684 assume !(0 == ~M_E~0); 10711#L684-2 assume !(0 == ~T1_E~0); 10552#L689-1 assume !(0 == ~T2_E~0); 10553#L694-1 assume !(0 == ~T3_E~0); 10550#L699-1 assume !(0 == ~T4_E~0); 10551#L704-1 assume !(0 == ~T5_E~0); 10506#L709-1 assume !(0 == ~T6_E~0); 10450#L714-1 assume !(0 == ~E_M~0); 10451#L719-1 assume !(0 == ~E_1~0); 10683#L724-1 assume !(0 == ~E_2~0); 10225#L729-1 assume !(0 == ~E_3~0); 10226#L734-1 assume !(0 == ~E_4~0); 10748#L739-1 assume !(0 == ~E_5~0); 10409#L744-1 assume !(0 == ~E_6~0); 10410#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10186#L334 assume !(1 == ~m_pc~0); 10187#L334-2 is_master_triggered_~__retres1~0#1 := 0; 10497#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10219#L346 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 10220#L849 assume !(0 != activate_threads_~tmp~1#1); 10382#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10316#L353 assume 1 == ~t1_pc~0; 10317#L354 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10600#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10235#L365 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 10236#L857 assume !(0 != activate_threads_~tmp___0~0#1); 10274#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10275#L372 assume !(1 == ~t2_pc~0); 10369#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 10368#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10491#L384 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10738#L865 assume !(0 != activate_threads_~tmp___1~0#1); 10173#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10174#L391 assume 1 == ~t3_pc~0; 10724#L392 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10093#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10302#L403 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10495#L873 assume !(0 != activate_threads_~tmp___2~0#1); 10387#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10388#L410 assume 1 == ~t4_pc~0; 10735#L411 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10618#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10652#L422 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10739#L881 assume !(0 != activate_threads_~tmp___3~0#1); 10394#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10395#L429 assume !(1 == ~t5_pc~0); 10229#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 10230#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10158#L441 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10159#L889 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10625#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10377#L448 assume 1 == ~t6_pc~0; 10265#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10266#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10622#L460 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10694#L897 assume !(0 != activate_threads_~tmp___5~0#1); 10767#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10798#L762 assume 1 == ~M_E~0;~M_E~0 := 2; 10429#L762-2 assume !(1 == ~T1_E~0); 10430#L767-1 assume !(1 == ~T2_E~0); 10773#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10646#L777-1 assume !(1 == ~T4_E~0); 10534#L782-1 assume !(1 == ~T5_E~0); 10257#L787-1 assume !(1 == ~T6_E~0); 10255#L792-1 assume !(1 == ~E_M~0); 10256#L797-1 assume !(1 == ~E_1~0); 10292#L802-1 assume !(1 == ~E_2~0); 10500#L807-1 assume !(1 == ~E_3~0); 10501#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 10744#L817-1 assume !(1 == ~E_5~0); 10795#L822-1 assume !(1 == ~E_6~0); 10753#L827-1 assume { :end_inline_reset_delta_events } true; 10383#L1053-2 [2022-10-17 11:04:31,590 INFO L750 eck$LassoCheckResult]: Loop: 10383#L1053-2 assume !false; 10384#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10824#L659 assume !false; 10823#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 10821#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 10815#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 10814#L556 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 10812#L570 assume !(0 != eval_~tmp~0#1); 10811#L674 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10810#L468-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10808#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10809#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11168#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11167#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11166#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11165#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11164#L709-3 assume !(0 == ~T6_E~0); 11163#L714-3 assume !(0 == ~E_M~0); 11162#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11161#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10585#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10586#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10653#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 11155#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 10742#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10155#L334-24 assume 1 == ~m_pc~0; 10156#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 10291#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11125#L346-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 11124#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11123#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11122#L353-24 assume !(1 == ~t1_pc~0); 11120#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 11119#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11118#L365-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11117#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11116#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11114#L372-24 assume 1 == ~t2_pc~0; 11110#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11108#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11106#L384-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11097#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 10802#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10455#L391-24 assume 1 == ~t3_pc~0; 10456#L392-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10684#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10685#L403-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10536#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10514#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10346#L410-24 assume 1 == ~t4_pc~0; 10293#L411-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10222#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10656#L422-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10393#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10253#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10254#L429-24 assume 1 == ~t5_pc~0; 10341#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10542#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10655#L441-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10296#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10297#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10248#L448-24 assume !(1 == ~t6_pc~0); 10249#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 10240#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10241#L460-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10666#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10546#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10547#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10751#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11059#L767-3 assume !(1 == ~T2_E~0); 11057#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11055#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11053#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11051#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 11048#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10668#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11045#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11043#L807-3 assume !(1 == ~E_3~0); 11041#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 11039#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 11035#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11022#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 10473#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 10132#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 10502#L556-1 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 10503#L1072 assume !(0 == start_simulation_~tmp~3#1); 10360#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 10361#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 10242#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 10164#L556-2 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 10165#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10166#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10670#L1035 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 10671#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 10383#L1053-2 [2022-10-17 11:04:31,591 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:04:31,591 INFO L85 PathProgramCache]: Analyzing trace with hash -1050737979, now seen corresponding path program 1 times [2022-10-17 11:04:31,591 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:04:31,591 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [652989595] [2022-10-17 11:04:31,592 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:04:31,593 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:04:31,607 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:04:31,665 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:04:31,665 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:04:31,665 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [652989595] [2022-10-17 11:04:31,670 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [652989595] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:04:31,670 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:04:31,670 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:04:31,670 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1355657904] [2022-10-17 11:04:31,672 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:04:31,673 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 11:04:31,673 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:04:31,673 INFO L85 PathProgramCache]: Analyzing trace with hash 2068037533, now seen corresponding path program 1 times [2022-10-17 11:04:31,673 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:04:31,674 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [714476665] [2022-10-17 11:04:31,676 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:04:31,677 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:04:31,689 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:04:31,742 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:04:31,742 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:04:31,743 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [714476665] [2022-10-17 11:04:31,743 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [714476665] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:04:31,743 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:04:31,743 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:04:31,743 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1090245335] [2022-10-17 11:04:31,743 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:04:31,744 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 11:04:31,744 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 11:04:31,744 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-10-17 11:04:31,745 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-10-17 11:04:31,745 INFO L87 Difference]: Start difference. First operand 1169 states and 1737 transitions. cyclomatic complexity: 570 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:04:31,955 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 11:04:31,956 INFO L93 Difference]: Finished difference Result 3123 states and 4559 transitions. [2022-10-17 11:04:31,956 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3123 states and 4559 transitions. [2022-10-17 11:04:32,025 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2908 [2022-10-17 11:04:32,051 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3123 states to 3123 states and 4559 transitions. [2022-10-17 11:04:32,052 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3123 [2022-10-17 11:04:32,055 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3123 [2022-10-17 11:04:32,056 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3123 states and 4559 transitions. [2022-10-17 11:04:32,060 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 11:04:32,061 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3123 states and 4559 transitions. [2022-10-17 11:04:32,065 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3123 states and 4559 transitions. [2022-10-17 11:04:32,122 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3123 to 2935. [2022-10-17 11:04:32,128 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2935 states, 2935 states have (on average 1.466098807495741) internal successors, (4303), 2934 states have internal predecessors, (4303), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:04:32,141 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2935 states to 2935 states and 4303 transitions. [2022-10-17 11:04:32,141 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2935 states and 4303 transitions. [2022-10-17 11:04:32,141 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-10-17 11:04:32,144 INFO L428 stractBuchiCegarLoop]: Abstraction has 2935 states and 4303 transitions. [2022-10-17 11:04:32,144 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-10-17 11:04:32,144 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2935 states and 4303 transitions. [2022-10-17 11:04:32,164 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2822 [2022-10-17 11:04:32,165 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 11:04:32,165 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 11:04:32,168 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:04:32,168 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:04:32,169 INFO L748 eck$LassoCheckResult]: Stem: 15215#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 15155#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 15132#L1016 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15106#L468 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14573#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 14574#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14924#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14925#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14843#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14624#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14625#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 14553#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14554#L684 assume !(0 == ~M_E~0); 15058#L684-2 assume !(0 == ~T1_E~0); 14877#L689-1 assume !(0 == ~T2_E~0); 14878#L694-1 assume !(0 == ~T3_E~0); 14875#L699-1 assume !(0 == ~T4_E~0); 14876#L704-1 assume !(0 == ~T5_E~0); 14827#L709-1 assume !(0 == ~T6_E~0); 14767#L714-1 assume !(0 == ~E_M~0); 14768#L719-1 assume !(0 == ~E_1~0); 15025#L724-1 assume !(0 == ~E_2~0); 14527#L729-1 assume !(0 == ~E_3~0); 14528#L734-1 assume !(0 == ~E_4~0); 15100#L739-1 assume !(0 == ~E_5~0); 14721#L744-1 assume !(0 == ~E_6~0); 14722#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14487#L334 assume !(1 == ~m_pc~0); 14488#L334-2 is_master_triggered_~__retres1~0#1 := 0; 14816#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14521#L346 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 14522#L849 assume !(0 != activate_threads_~tmp~1#1); 14694#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14620#L353 assume !(1 == ~t1_pc~0); 14621#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 14928#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14537#L365 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 14538#L857 assume !(0 != activate_threads_~tmp___0~0#1); 14577#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14578#L372 assume !(1 == ~t2_pc~0); 14679#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 14678#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14809#L384 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 15087#L865 assume !(0 != activate_threads_~tmp___1~0#1); 14474#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14475#L391 assume 1 == ~t3_pc~0; 15072#L392 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14395#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14606#L403 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14813#L873 assume !(0 != activate_threads_~tmp___2~0#1); 14698#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14699#L410 assume 1 == ~t4_pc~0; 15085#L411 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14950#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14993#L422 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15088#L881 assume !(0 != activate_threads_~tmp___3~0#1); 14706#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14707#L429 assume !(1 == ~t5_pc~0); 14531#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 14532#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14459#L441 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14460#L889 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14960#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14687#L448 assume 1 == ~t6_pc~0; 14568#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 14569#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14955#L460 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15037#L897 assume !(0 != activate_threads_~tmp___5~0#1); 15127#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15196#L762 assume 1 == ~M_E~0;~M_E~0 := 2; 15197#L762-2 assume !(1 == ~T1_E~0); 16732#L767-1 assume !(1 == ~T2_E~0); 16731#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16730#L777-1 assume !(1 == ~T4_E~0); 16729#L782-1 assume !(1 == ~T5_E~0); 16728#L787-1 assume !(1 == ~T6_E~0); 16727#L792-1 assume !(1 == ~E_M~0); 14558#L797-1 assume !(1 == ~E_1~0); 16726#L802-1 assume !(1 == ~E_2~0); 16725#L807-1 assume !(1 == ~E_3~0); 16724#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 16723#L817-1 assume !(1 == ~E_5~0); 16722#L822-1 assume !(1 == ~E_6~0); 16622#L827-1 assume { :end_inline_reset_delta_events } true; 16621#L1053-2 [2022-10-17 11:04:32,169 INFO L750 eck$LassoCheckResult]: Loop: 16621#L1053-2 assume !false; 16618#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16616#L659 assume !false; 14654#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 14655#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 15223#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 15224#L556 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 15016#L570 assume !(0 != eval_~tmp~0#1); 14974#L674 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14975#L468-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17293#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 15044#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15045#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14744#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14745#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17302#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17301#L709-3 assume !(0 == ~T6_E~0); 17300#L714-3 assume !(0 == ~E_M~0); 17299#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 17298#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17297#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17296#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 17295#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 17294#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 15092#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15093#L334-24 assume !(1 == ~m_pc~0); 16556#L334-26 is_master_triggered_~__retres1~0#1 := 0; 16555#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16554#L346-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 16553#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 15185#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14970#L353-24 assume !(1 == ~t1_pc~0); 14971#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 15141#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15142#L365-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 15161#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14478#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14479#L372-24 assume 1 == ~t2_pc~0; 14435#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14436#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14579#L384-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 14580#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 15122#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14772#L391-24 assume 1 == ~t3_pc~0; 14773#L392-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15026#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15027#L403-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14860#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14835#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14651#L410-24 assume !(1 == ~t4_pc~0); 14652#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 16676#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16675#L422-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16674#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 16673#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16672#L429-24 assume 1 == ~t5_pc~0; 16670#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16669#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16668#L441-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16667#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 16666#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16665#L448-24 assume !(1 == ~t6_pc~0); 16663#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 16662#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16661#L460-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16660#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 16659#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16658#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 16097#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16657#L767-3 assume !(1 == ~T2_E~0); 16656#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16655#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16654#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16653#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16652#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 15010#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16651#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16650#L807-3 assume !(1 == ~E_3~0); 16649#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16648#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16647#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16646#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 16644#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 16638#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 16637#L556-1 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 16636#L1072 assume !(0 == start_simulation_~tmp~3#1); 15138#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 16629#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 16628#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 16627#L556-2 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 16626#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16625#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16624#L1035 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 16623#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 16621#L1053-2 [2022-10-17 11:04:32,170 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:04:32,170 INFO L85 PathProgramCache]: Analyzing trace with hash 1143388102, now seen corresponding path program 1 times [2022-10-17 11:04:32,170 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:04:32,170 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1889258650] [2022-10-17 11:04:32,171 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:04:32,171 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:04:32,184 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:04:32,237 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:04:32,237 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:04:32,237 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1889258650] [2022-10-17 11:04:32,238 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1889258650] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:04:32,238 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:04:32,238 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:04:32,238 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [480581779] [2022-10-17 11:04:32,238 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:04:32,239 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 11:04:32,239 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:04:32,239 INFO L85 PathProgramCache]: Analyzing trace with hash -1962778593, now seen corresponding path program 1 times [2022-10-17 11:04:32,240 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:04:32,240 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [587635867] [2022-10-17 11:04:32,240 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:04:32,241 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:04:32,254 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:04:32,289 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:04:32,290 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:04:32,290 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [587635867] [2022-10-17 11:04:32,290 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [587635867] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:04:32,290 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:04:32,290 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:04:32,291 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1899425986] [2022-10-17 11:04:32,291 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:04:32,291 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 11:04:32,291 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 11:04:32,292 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-10-17 11:04:32,292 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-10-17 11:04:32,292 INFO L87 Difference]: Start difference. First operand 2935 states and 4303 transitions. cyclomatic complexity: 1372 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:04:32,523 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 11:04:32,523 INFO L93 Difference]: Finished difference Result 8042 states and 11650 transitions. [2022-10-17 11:04:32,523 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8042 states and 11650 transitions. [2022-10-17 11:04:32,631 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7680 [2022-10-17 11:04:32,697 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8042 states to 8042 states and 11650 transitions. [2022-10-17 11:04:32,698 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8042 [2022-10-17 11:04:32,709 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8042 [2022-10-17 11:04:32,709 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8042 states and 11650 transitions. [2022-10-17 11:04:32,722 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 11:04:32,723 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8042 states and 11650 transitions. [2022-10-17 11:04:32,732 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8042 states and 11650 transitions. [2022-10-17 11:04:32,876 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8042 to 7638. [2022-10-17 11:04:32,893 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7638 states, 7638 states have (on average 1.4548311076197957) internal successors, (11112), 7637 states have internal predecessors, (11112), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:04:32,924 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7638 states to 7638 states and 11112 transitions. [2022-10-17 11:04:32,925 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7638 states and 11112 transitions. [2022-10-17 11:04:32,925 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-10-17 11:04:32,926 INFO L428 stractBuchiCegarLoop]: Abstraction has 7638 states and 11112 transitions. [2022-10-17 11:04:32,926 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-10-17 11:04:32,926 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7638 states and 11112 transitions. [2022-10-17 11:04:32,963 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7506 [2022-10-17 11:04:32,964 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 11:04:32,964 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 11:04:32,965 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:04:32,966 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:04:32,966 INFO L748 eck$LassoCheckResult]: Stem: 26154#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 26107#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 26091#L1016 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26066#L468 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 25559#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 25560#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25891#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25892#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25811#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25609#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 25610#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 25538#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 25539#L684 assume !(0 == ~M_E~0); 26017#L684-2 assume !(0 == ~T1_E~0); 25845#L689-1 assume !(0 == ~T2_E~0); 25846#L694-1 assume !(0 == ~T3_E~0); 25843#L699-1 assume !(0 == ~T4_E~0); 25844#L704-1 assume !(0 == ~T5_E~0); 25797#L709-1 assume !(0 == ~T6_E~0); 25743#L714-1 assume !(0 == ~E_M~0); 25744#L719-1 assume !(0 == ~E_1~0); 25986#L724-1 assume !(0 == ~E_2~0); 25512#L729-1 assume !(0 == ~E_3~0); 25513#L734-1 assume !(0 == ~E_4~0); 26063#L739-1 assume !(0 == ~E_5~0); 25702#L744-1 assume !(0 == ~E_6~0); 25703#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25473#L334 assume !(1 == ~m_pc~0); 25474#L334-2 is_master_triggered_~__retres1~0#1 := 0; 25787#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25506#L346 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 25507#L849 assume !(0 != activate_threads_~tmp~1#1); 25675#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25605#L353 assume !(1 == ~t1_pc~0); 25606#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 25896#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25522#L365 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 25523#L857 assume !(0 != activate_threads_~tmp___0~0#1); 25563#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25564#L372 assume !(1 == ~t2_pc~0); 25661#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 25660#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25781#L384 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 26050#L865 assume !(0 != activate_threads_~tmp___1~0#1); 25460#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25461#L391 assume !(1 == ~t3_pc~0); 25381#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 25382#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25591#L403 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 25785#L873 assume !(0 != activate_threads_~tmp___2~0#1); 25679#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25680#L410 assume 1 == ~t4_pc~0; 26048#L411 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25911#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25951#L422 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 26051#L881 assume !(0 != activate_threads_~tmp___3~0#1); 25687#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25688#L429 assume !(1 == ~t5_pc~0); 25516#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 25517#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25445#L441 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 25446#L889 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 25918#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25668#L448 assume 1 == ~t6_pc~0; 25554#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 25555#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25915#L460 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 25999#L897 assume !(0 != activate_threads_~tmp___5~0#1); 26087#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26140#L762 assume 1 == ~M_E~0;~M_E~0 := 2; 26141#L762-2 assume !(1 == ~T1_E~0); 26118#L767-1 assume !(1 == ~T2_E~0); 26119#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25943#L777-1 assume !(1 == ~T4_E~0); 25944#L782-1 assume !(1 == ~T5_E~0); 25545#L787-1 assume !(1 == ~T6_E~0); 25546#L792-1 assume !(1 == ~E_M~0); 25543#L797-1 assume !(1 == ~E_1~0); 25581#L802-1 assume !(1 == ~E_2~0); 26001#L807-1 assume !(1 == ~E_3~0); 31707#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 31704#L817-1 assume !(1 == ~E_5~0); 31700#L822-1 assume !(1 == ~E_6~0); 26067#L827-1 assume { :end_inline_reset_delta_events } true; 26068#L1053-2 [2022-10-17 11:04:32,967 INFO L750 eck$LassoCheckResult]: Loop: 26068#L1053-2 assume !false; 31726#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 31725#L659 assume !false; 31717#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 31718#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 31671#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 31672#L556 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 31379#L570 assume !(0 != eval_~tmp~0#1); 31381#L674 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 32734#L468-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 32733#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 32732#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 32731#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 32730#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 32729#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 32728#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 32727#L709-3 assume !(0 == ~T6_E~0); 32726#L714-3 assume !(0 == ~E_M~0); 32725#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 32724#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 32723#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 32722#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 32721#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 32720#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 32719#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32718#L334-24 assume !(1 == ~m_pc~0); 32717#L334-26 is_master_triggered_~__retres1~0#1 := 0; 32716#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 32715#L346-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 32714#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 32713#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32712#L353-24 assume !(1 == ~t1_pc~0); 32711#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 32710#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32709#L365-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 32708#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 32707#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 32706#L372-24 assume 1 == ~t2_pc~0; 32704#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 32703#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32702#L384-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 32701#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 32700#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 32699#L391-24 assume !(1 == ~t3_pc~0); 32698#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 32697#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32696#L403-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 32695#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 32694#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32693#L410-24 assume !(1 == ~t4_pc~0); 32691#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 32690#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32689#L422-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 32688#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 32687#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 32686#L429-24 assume 1 == ~t5_pc~0; 32684#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 32683#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 32682#L441-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 32681#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 32680#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 32679#L448-24 assume !(1 == ~t6_pc~0); 32677#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 32676#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 32675#L460-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 32674#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 32673#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32672#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 32531#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 32671#L767-3 assume !(1 == ~T2_E~0); 32670#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 32669#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 32668#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 32667#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 32666#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 32523#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 32665#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 32664#L807-3 assume !(1 == ~E_3~0); 32663#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 32662#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 32661#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 32660#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 32658#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 32652#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 32651#L556-1 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 32650#L1072 assume !(0 == start_simulation_~tmp~3#1); 32648#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 32641#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 32640#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 32639#L556-2 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 32638#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 32637#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 32636#L1035 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 32635#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 26068#L1053-2 [2022-10-17 11:04:32,967 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:04:32,968 INFO L85 PathProgramCache]: Analyzing trace with hash 186459719, now seen corresponding path program 1 times [2022-10-17 11:04:32,968 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:04:32,968 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1525000425] [2022-10-17 11:04:32,968 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:04:32,968 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:04:32,980 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:04:33,021 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:04:33,022 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:04:33,022 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1525000425] [2022-10-17 11:04:33,022 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1525000425] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:04:33,022 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:04:33,026 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-10-17 11:04:33,026 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [739860045] [2022-10-17 11:04:33,027 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:04:33,028 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 11:04:33,028 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:04:33,029 INFO L85 PathProgramCache]: Analyzing trace with hash 231347488, now seen corresponding path program 1 times [2022-10-17 11:04:33,029 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:04:33,029 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [614291390] [2022-10-17 11:04:33,029 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:04:33,029 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:04:33,041 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:04:33,135 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:04:33,135 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:04:33,136 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [614291390] [2022-10-17 11:04:33,136 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [614291390] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:04:33,136 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:04:33,136 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:04:33,136 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1823546470] [2022-10-17 11:04:33,137 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:04:33,137 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 11:04:33,137 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 11:04:33,138 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 11:04:33,138 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 11:04:33,138 INFO L87 Difference]: Start difference. First operand 7638 states and 11112 transitions. cyclomatic complexity: 3482 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 2 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:04:33,276 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 11:04:33,276 INFO L93 Difference]: Finished difference Result 14179 states and 20558 transitions. [2022-10-17 11:04:33,276 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14179 states and 20558 transitions. [2022-10-17 11:04:33,374 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 13982 [2022-10-17 11:04:33,465 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14179 states to 14179 states and 20558 transitions. [2022-10-17 11:04:33,465 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14179 [2022-10-17 11:04:33,481 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14179 [2022-10-17 11:04:33,481 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14179 states and 20558 transitions. [2022-10-17 11:04:33,505 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 11:04:33,505 INFO L218 hiAutomatonCegarLoop]: Abstraction has 14179 states and 20558 transitions. [2022-10-17 11:04:33,523 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14179 states and 20558 transitions. [2022-10-17 11:04:33,831 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14179 to 14143. [2022-10-17 11:04:33,864 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14143 states, 14143 states have (on average 1.4510358481227463) internal successors, (20522), 14142 states have internal predecessors, (20522), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:04:33,914 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14143 states to 14143 states and 20522 transitions. [2022-10-17 11:04:33,914 INFO L240 hiAutomatonCegarLoop]: Abstraction has 14143 states and 20522 transitions. [2022-10-17 11:04:33,915 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 11:04:33,916 INFO L428 stractBuchiCegarLoop]: Abstraction has 14143 states and 20522 transitions. [2022-10-17 11:04:33,916 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-10-17 11:04:33,916 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14143 states and 20522 transitions. [2022-10-17 11:04:33,986 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 13946 [2022-10-17 11:04:33,986 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 11:04:33,986 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 11:04:33,988 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:04:33,988 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:04:33,988 INFO L748 eck$LassoCheckResult]: Stem: 48011#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 47952#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 47934#L1016 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 47905#L468 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 47382#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 47383#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 47724#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 47725#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 47644#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 47435#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 47436#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 47362#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 47363#L684 assume !(0 == ~M_E~0); 47854#L684-2 assume !(0 == ~T1_E~0); 47680#L689-1 assume !(0 == ~T2_E~0); 47681#L694-1 assume !(0 == ~T3_E~0); 47678#L699-1 assume !(0 == ~T4_E~0); 47679#L704-1 assume !(0 == ~T5_E~0); 47629#L709-1 assume !(0 == ~T6_E~0); 47569#L714-1 assume !(0 == ~E_M~0); 47570#L719-1 assume !(0 == ~E_1~0); 47826#L724-1 assume !(0 == ~E_2~0); 47336#L729-1 assume !(0 == ~E_3~0); 47337#L734-1 assume !(0 == ~E_4~0); 47899#L739-1 assume !(0 == ~E_5~0); 47524#L744-1 assume !(0 == ~E_6~0); 47525#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47298#L334 assume !(1 == ~m_pc~0); 47299#L334-2 is_master_triggered_~__retres1~0#1 := 0; 47620#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47330#L346 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 47331#L849 assume !(0 != activate_threads_~tmp~1#1); 47499#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 47431#L353 assume !(1 == ~t1_pc~0); 47432#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 47728#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47346#L365 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 47347#L857 assume !(0 != activate_threads_~tmp___0~0#1); 47386#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47387#L372 assume !(1 == ~t2_pc~0); 47485#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 47484#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47613#L384 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 47885#L865 assume !(0 != activate_threads_~tmp___1~0#1); 47285#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47286#L391 assume !(1 == ~t3_pc~0); 47205#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 47206#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 47417#L403 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 47617#L873 assume !(0 != activate_threads_~tmp___2~0#1); 47503#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 47504#L410 assume !(1 == ~t4_pc~0); 47744#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 47745#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47791#L422 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 47886#L881 assume !(0 != activate_threads_~tmp___3~0#1); 47510#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47511#L429 assume !(1 == ~t5_pc~0); 47340#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 47341#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47270#L441 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 47271#L889 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 47754#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 47492#L448 assume 1 == ~t6_pc~0; 47377#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 47378#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 47750#L460 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 47837#L897 assume !(0 != activate_threads_~tmp___5~0#1); 47928#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 47994#L762 assume 1 == ~M_E~0;~M_E~0 := 2; 47547#L762-2 assume !(1 == ~T1_E~0); 47548#L767-1 assume !(1 == ~T2_E~0); 47936#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 47937#L777-1 assume !(1 == ~T4_E~0); 47660#L782-1 assume !(1 == ~T5_E~0); 47661#L787-1 assume !(1 == ~T6_E~0); 47366#L792-1 assume !(1 == ~E_M~0); 47367#L797-1 assume !(1 == ~E_1~0); 47839#L802-1 assume !(1 == ~E_2~0); 47840#L807-1 assume !(1 == ~E_3~0); 47894#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 47895#L817-1 assume !(1 == ~E_5~0); 47682#L822-1 assume !(1 == ~E_6~0); 47683#L827-1 assume { :end_inline_reset_delta_events } true; 53466#L1053-2 [2022-10-17 11:04:33,989 INFO L750 eck$LassoCheckResult]: Loop: 53466#L1053-2 assume !false; 53444#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 53442#L659 assume !false; 53441#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 53439#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 53432#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 53433#L556 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 59322#L570 assume !(0 != eval_~tmp~0#1); 59323#L674 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 60866#L468-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 60864#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 60862#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 60860#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 60858#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 60342#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 60341#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 60340#L709-3 assume !(0 == ~T6_E~0); 60339#L714-3 assume !(0 == ~E_M~0); 60338#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 60337#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 60336#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 60334#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 60332#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 60330#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 60328#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 60327#L334-24 assume !(1 == ~m_pc~0); 60326#L334-26 is_master_triggered_~__retres1~0#1 := 0; 60325#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 60262#L346-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 60261#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 60260#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 60259#L353-24 assume !(1 == ~t1_pc~0); 60258#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 60257#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 60256#L365-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 60255#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 60254#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 60253#L372-24 assume 1 == ~t2_pc~0; 60251#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 60249#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 60247#L384-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 60245#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 60243#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 60240#L391-24 assume !(1 == ~t3_pc~0); 60238#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 60236#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 60234#L403-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 60232#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 60230#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 60228#L410-24 assume !(1 == ~t4_pc~0); 60226#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 60224#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 60222#L422-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 60220#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 60218#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 60216#L429-24 assume 1 == ~t5_pc~0; 60198#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 60196#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 60194#L441-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 60192#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 60190#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 60188#L448-24 assume !(1 == ~t6_pc~0); 60185#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 60183#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 60181#L460-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 60179#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 60177#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 60175#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 57582#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 60172#L767-3 assume !(1 == ~T2_E~0); 60170#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 60168#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 60165#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 60163#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 60161#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 57574#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 60158#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 60156#L807-3 assume !(1 == ~E_3~0); 60153#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 60151#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 60149#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 60147#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 60095#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 60082#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 60076#L556-1 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 60069#L1072 assume !(0 == start_simulation_~tmp~3#1); 59916#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 54475#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 54474#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 54470#L556-2 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 54468#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 54466#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 54465#L1035 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 53469#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 53466#L1053-2 [2022-10-17 11:04:33,989 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:04:33,990 INFO L85 PathProgramCache]: Analyzing trace with hash -1390098040, now seen corresponding path program 1 times [2022-10-17 11:04:33,990 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:04:33,990 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1122804473] [2022-10-17 11:04:33,990 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:04:33,990 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:04:34,004 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:04:34,177 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:04:34,177 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:04:34,178 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1122804473] [2022-10-17 11:04:34,178 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1122804473] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:04:34,178 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:04:34,178 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-10-17 11:04:34,178 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [654099583] [2022-10-17 11:04:34,178 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:04:34,179 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 11:04:34,179 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:04:34,179 INFO L85 PathProgramCache]: Analyzing trace with hash 231347488, now seen corresponding path program 2 times [2022-10-17 11:04:34,180 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:04:34,180 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1328104651] [2022-10-17 11:04:34,180 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:04:34,180 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:04:34,193 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:04:34,223 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:04:34,224 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:04:34,224 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1328104651] [2022-10-17 11:04:34,224 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1328104651] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:04:34,224 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:04:34,224 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:04:34,225 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [281808820] [2022-10-17 11:04:34,225 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:04:34,225 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 11:04:34,225 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 11:04:34,226 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-10-17 11:04:34,226 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-10-17 11:04:34,227 INFO L87 Difference]: Start difference. First operand 14143 states and 20522 transitions. cyclomatic complexity: 6395 Second operand has 5 states, 5 states have (on average 16.8) internal successors, (84), 5 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:04:34,622 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 11:04:34,622 INFO L93 Difference]: Finished difference Result 33842 states and 49567 transitions. [2022-10-17 11:04:34,623 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 33842 states and 49567 transitions. [2022-10-17 11:04:35,103 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 33388 [2022-10-17 11:04:35,312 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 33842 states to 33842 states and 49567 transitions. [2022-10-17 11:04:35,313 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 33842 [2022-10-17 11:04:35,353 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 33842 [2022-10-17 11:04:35,353 INFO L73 IsDeterministic]: Start isDeterministic. Operand 33842 states and 49567 transitions. [2022-10-17 11:04:35,456 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 11:04:35,457 INFO L218 hiAutomatonCegarLoop]: Abstraction has 33842 states and 49567 transitions. [2022-10-17 11:04:35,494 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33842 states and 49567 transitions. [2022-10-17 11:04:35,756 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33842 to 14752. [2022-10-17 11:04:35,779 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14752 states, 14752 states have (on average 1.4324159436008677) internal successors, (21131), 14751 states have internal predecessors, (21131), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:04:35,829 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14752 states to 14752 states and 21131 transitions. [2022-10-17 11:04:35,830 INFO L240 hiAutomatonCegarLoop]: Abstraction has 14752 states and 21131 transitions. [2022-10-17 11:04:35,830 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-10-17 11:04:35,831 INFO L428 stractBuchiCegarLoop]: Abstraction has 14752 states and 21131 transitions. [2022-10-17 11:04:35,831 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-10-17 11:04:35,831 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14752 states and 21131 transitions. [2022-10-17 11:04:35,900 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 14552 [2022-10-17 11:04:35,901 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 11:04:35,901 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 11:04:35,903 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:04:35,903 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:04:35,903 INFO L748 eck$LassoCheckResult]: Stem: 96024#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 95961#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 95945#L1016 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 95916#L468 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 95383#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 95384#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 95727#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 95728#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 95648#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 95431#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 95432#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 95364#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 95365#L684 assume !(0 == ~M_E~0); 95864#L684-2 assume !(0 == ~T1_E~0); 95680#L689-1 assume !(0 == ~T2_E~0); 95681#L694-1 assume !(0 == ~T3_E~0); 95678#L699-1 assume !(0 == ~T4_E~0); 95679#L704-1 assume !(0 == ~T5_E~0); 95631#L709-1 assume !(0 == ~T6_E~0); 95569#L714-1 assume !(0 == ~E_M~0); 95570#L719-1 assume !(0 == ~E_1~0); 95834#L724-1 assume !(0 == ~E_2~0); 95335#L729-1 assume !(0 == ~E_3~0); 95336#L734-1 assume !(0 == ~E_4~0); 95911#L739-1 assume !(0 == ~E_5~0); 95526#L744-1 assume !(0 == ~E_6~0); 95527#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 95296#L334 assume !(1 == ~m_pc~0); 95297#L334-2 is_master_triggered_~__retres1~0#1 := 0; 95620#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 95329#L346 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 95330#L849 assume !(0 != activate_threads_~tmp~1#1); 95499#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 95427#L353 assume !(1 == ~t1_pc~0); 95428#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 95731#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 95345#L365 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 95346#L857 assume !(0 != activate_threads_~tmp___0~0#1); 95385#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 95386#L372 assume !(1 == ~t2_pc~0); 95485#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 95484#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 95614#L384 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 95896#L865 assume !(0 != activate_threads_~tmp___1~0#1); 95285#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 95286#L391 assume !(1 == ~t3_pc~0); 95205#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 95206#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 95413#L403 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 95619#L873 assume !(0 != activate_threads_~tmp___2~0#1); 95503#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 95504#L410 assume !(1 == ~t4_pc~0); 95749#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 95750#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 95792#L422 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 95900#L881 assume !(0 != activate_threads_~tmp___3~0#1); 95514#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 95515#L429 assume !(1 == ~t5_pc~0); 95339#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 95340#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 96019#L441 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 95758#L889 assume !(0 != activate_threads_~tmp___4~0#1); 95759#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 95494#L448 assume 1 == ~t6_pc~0; 95376#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 95377#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 95754#L460 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 95848#L897 assume !(0 != activate_threads_~tmp___5~0#1); 95942#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 96004#L762 assume 1 == ~M_E~0;~M_E~0 := 2; 95550#L762-2 assume !(1 == ~T1_E~0); 95551#L767-1 assume !(1 == ~T2_E~0); 95947#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 95788#L777-1 assume !(1 == ~T4_E~0); 95661#L782-1 assume !(1 == ~T5_E~0); 95368#L787-1 assume !(1 == ~T6_E~0); 95366#L792-1 assume !(1 == ~E_M~0); 95367#L797-1 assume !(1 == ~E_1~0); 95404#L802-1 assume !(1 == ~E_2~0); 95625#L807-1 assume !(1 == ~E_3~0); 95626#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 95908#L817-1 assume !(1 == ~E_5~0); 95684#L822-1 assume !(1 == ~E_6~0); 95685#L827-1 assume { :end_inline_reset_delta_events } true; 95501#L1053-2 [2022-10-17 11:04:35,904 INFO L750 eck$LassoCheckResult]: Loop: 95501#L1053-2 assume !false; 95502#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 95210#L659 assume !false; 95463#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 95464#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 108473#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 108471#L556 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 108468#L570 assume !(0 != eval_~tmp~0#1); 108469#L674 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 109556#L468-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 109553#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 109550#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 109547#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 109544#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 109541#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 109538#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 109535#L709-3 assume !(0 == ~T6_E~0); 109492#L714-3 assume !(0 == ~E_M~0); 109489#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 109486#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 109482#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 109479#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 109476#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 109473#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 109430#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 109429#L334-24 assume !(1 == ~m_pc~0); 109428#L334-26 is_master_triggered_~__retres1~0#1 := 0; 109427#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 109426#L346-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 109425#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 109424#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 109423#L353-24 assume !(1 == ~t1_pc~0); 109422#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 109421#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 109420#L365-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 109419#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 109418#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 109417#L372-24 assume 1 == ~t2_pc~0; 109415#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 109414#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 109413#L384-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 109412#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 109411#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 109410#L391-24 assume !(1 == ~t3_pc~0); 109409#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 109408#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 109407#L403-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 109406#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 109405#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 109404#L410-24 assume !(1 == ~t4_pc~0); 109403#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 109402#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 109401#L422-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 109400#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 109399#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 109398#L429-24 assume !(1 == ~t5_pc~0); 109397#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 109395#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 109393#L441-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 109391#L889-24 assume !(0 != activate_threads_~tmp___4~0#1); 109388#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 109385#L448-24 assume 1 == ~t6_pc~0; 109381#L449-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 109377#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 109374#L460-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 109371#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 109368#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 109363#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 108142#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 109358#L767-3 assume !(1 == ~T2_E~0); 109355#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 109352#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 109349#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 109346#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 109342#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 108131#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 109339#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 109337#L807-3 assume !(1 == ~E_3~0); 109335#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 109333#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 109331#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 109328#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 95592#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 95242#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 95623#L556-1 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 95624#L1072 assume !(0 == start_simulation_~tmp~3#1); 95948#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 109832#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 109831#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 95273#L556-2 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 95274#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 109770#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 109769#L1035 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 109766#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 95501#L1053-2 [2022-10-17 11:04:35,904 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:04:35,905 INFO L85 PathProgramCache]: Analyzing trace with hash 1099430922, now seen corresponding path program 1 times [2022-10-17 11:04:35,905 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:04:35,905 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [673785536] [2022-10-17 11:04:35,905 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:04:35,905 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:04:35,919 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:04:36,106 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:04:36,106 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:04:36,107 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [673785536] [2022-10-17 11:04:36,107 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [673785536] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:04:36,107 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:04:36,107 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:04:36,107 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [926610234] [2022-10-17 11:04:36,107 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:04:36,108 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 11:04:36,108 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:04:36,108 INFO L85 PathProgramCache]: Analyzing trace with hash 6971362, now seen corresponding path program 1 times [2022-10-17 11:04:36,109 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:04:36,109 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1837884222] [2022-10-17 11:04:36,109 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:04:36,109 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:04:36,120 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:04:36,151 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:04:36,151 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:04:36,151 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1837884222] [2022-10-17 11:04:36,152 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1837884222] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:04:36,152 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:04:36,152 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:04:36,152 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [7781585] [2022-10-17 11:04:36,152 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:04:36,153 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 11:04:36,153 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 11:04:36,153 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-10-17 11:04:36,153 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-10-17 11:04:36,153 INFO L87 Difference]: Start difference. First operand 14752 states and 21131 transitions. cyclomatic complexity: 6395 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:04:36,515 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 11:04:36,515 INFO L93 Difference]: Finished difference Result 41693 states and 59140 transitions. [2022-10-17 11:04:36,515 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 41693 states and 59140 transitions. [2022-10-17 11:04:36,948 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 40302 [2022-10-17 11:04:37,194 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 41693 states to 41693 states and 59140 transitions. [2022-10-17 11:04:37,195 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 41693 [2022-10-17 11:04:37,222 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 41693 [2022-10-17 11:04:37,222 INFO L73 IsDeterministic]: Start isDeterministic. Operand 41693 states and 59140 transitions. [2022-10-17 11:04:37,258 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 11:04:37,258 INFO L218 hiAutomatonCegarLoop]: Abstraction has 41693 states and 59140 transitions. [2022-10-17 11:04:37,303 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41693 states and 59140 transitions. [2022-10-17 11:04:37,837 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41693 to 40509. [2022-10-17 11:04:37,897 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 40509 states, 40509 states have (on average 1.4232392801599645) internal successors, (57654), 40508 states have internal predecessors, (57654), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:04:38,205 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40509 states to 40509 states and 57654 transitions. [2022-10-17 11:04:38,205 INFO L240 hiAutomatonCegarLoop]: Abstraction has 40509 states and 57654 transitions. [2022-10-17 11:04:38,206 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-10-17 11:04:38,207 INFO L428 stractBuchiCegarLoop]: Abstraction has 40509 states and 57654 transitions. [2022-10-17 11:04:38,207 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-10-17 11:04:38,207 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 40509 states and 57654 transitions. [2022-10-17 11:04:38,447 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 40158 [2022-10-17 11:04:38,447 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 11:04:38,447 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 11:04:38,449 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:04:38,449 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:04:38,449 INFO L748 eck$LassoCheckResult]: Stem: 152499#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 152439#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 152418#L1016 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 152389#L468 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 151834#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 151835#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 152190#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 152191#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 152105#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 151888#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 151889#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 151816#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 151817#L684 assume !(0 == ~M_E~0); 152337#L684-2 assume !(0 == ~T1_E~0); 152143#L689-1 assume !(0 == ~T2_E~0); 152144#L694-1 assume !(0 == ~T3_E~0); 152141#L699-1 assume !(0 == ~T4_E~0); 152142#L704-1 assume !(0 == ~T5_E~0); 152090#L709-1 assume !(0 == ~T6_E~0); 152027#L714-1 assume !(0 == ~E_M~0); 152028#L719-1 assume !(0 == ~E_1~0); 152302#L724-1 assume !(0 == ~E_2~0); 151787#L729-1 assume !(0 == ~E_3~0); 151788#L734-1 assume !(0 == ~E_4~0); 152382#L739-1 assume !(0 == ~E_5~0); 151977#L744-1 assume !(0 == ~E_6~0); 151978#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 151749#L334 assume !(1 == ~m_pc~0); 151750#L334-2 is_master_triggered_~__retres1~0#1 := 0; 152080#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 151781#L346 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 151782#L849 assume !(0 != activate_threads_~tmp~1#1); 151952#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 151884#L353 assume !(1 == ~t1_pc~0); 151885#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 152195#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 151797#L365 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 151798#L857 assume !(0 != activate_threads_~tmp___0~0#1); 151836#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 151837#L372 assume !(1 == ~t2_pc~0); 151938#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 151937#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 152073#L384 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 152363#L865 assume !(0 != activate_threads_~tmp___1~0#1); 151738#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 151739#L391 assume !(1 == ~t3_pc~0); 151660#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 151661#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 151868#L403 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 152077#L873 assume !(0 != activate_threads_~tmp___2~0#1); 151956#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 151957#L410 assume !(1 == ~t4_pc~0); 152216#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 152217#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 152263#L422 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 152367#L881 assume !(0 != activate_threads_~tmp___3~0#1); 151965#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 151966#L429 assume !(1 == ~t5_pc~0); 151791#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 151792#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 151723#L441 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 151724#L889 assume !(0 != activate_threads_~tmp___4~0#1); 152225#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 151947#L448 assume !(1 == ~t6_pc~0); 151869#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 151870#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 152223#L460 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 152314#L897 assume !(0 != activate_threads_~tmp___5~0#1); 152412#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 152482#L762 assume 1 == ~M_E~0;~M_E~0 := 2; 152483#L762-2 assume !(1 == ~T1_E~0); 152453#L767-1 assume !(1 == ~T2_E~0); 152454#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 152256#L777-1 assume !(1 == ~T4_E~0); 152257#L782-1 assume !(1 == ~T5_E~0); 151821#L787-1 assume !(1 == ~T6_E~0); 151822#L792-1 assume !(1 == ~E_M~0); 151819#L797-1 assume !(1 == ~E_1~0); 151856#L802-1 assume !(1 == ~E_2~0); 152085#L807-1 assume !(1 == ~E_3~0); 152086#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 152469#L817-1 assume !(1 == ~E_5~0); 152470#L822-1 assume !(1 == ~E_6~0); 152390#L827-1 assume { :end_inline_reset_delta_events } true; 152391#L1053-2 [2022-10-17 11:04:38,449 INFO L750 eck$LassoCheckResult]: Loop: 152391#L1053-2 assume !false; 185799#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 185798#L659 assume !false; 185797#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 185795#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 185789#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 185788#L556 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 185786#L570 assume !(0 != eval_~tmp~0#1); 185787#L674 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 185958#L468-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 185957#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 185956#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 185955#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 185954#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 185953#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 185952#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 185951#L709-3 assume !(0 == ~T6_E~0); 185950#L714-3 assume !(0 == ~E_M~0); 185949#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 185948#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 185947#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 185946#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 185945#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 185944#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 185943#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 185942#L334-24 assume !(1 == ~m_pc~0); 185941#L334-26 is_master_triggered_~__retres1~0#1 := 0; 185940#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 185939#L346-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 185938#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 185937#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 185936#L353-24 assume !(1 == ~t1_pc~0); 185935#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 185934#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 185933#L365-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 185932#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 185931#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 185930#L372-24 assume 1 == ~t2_pc~0; 185928#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 185927#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 185926#L384-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 185925#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 185924#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 185923#L391-24 assume !(1 == ~t3_pc~0); 185922#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 185921#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 185920#L403-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 185919#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 185918#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 185917#L410-24 assume !(1 == ~t4_pc~0); 185916#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 185915#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 185914#L422-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 185913#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 185912#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 185911#L429-24 assume !(1 == ~t5_pc~0); 185908#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 185907#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 185906#L441-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 185905#L889-24 assume !(0 != activate_threads_~tmp___4~0#1); 185903#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 185902#L448-24 assume !(1 == ~t6_pc~0); 185901#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 185900#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 185899#L460-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 185898#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 185897#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 185896#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 170428#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 185895#L767-3 assume !(1 == ~T2_E~0); 185894#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 185893#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 185892#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 185891#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 185890#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 170420#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 185889#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 185888#L807-3 assume !(1 == ~E_3~0); 185887#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 185886#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 185885#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 185884#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 185882#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 185876#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 185875#L556-1 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 185874#L1072 assume !(0 == start_simulation_~tmp~3#1); 185872#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 185865#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 185864#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 185863#L556-2 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 185862#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 185861#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 185860#L1035 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 185859#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 152391#L1053-2 [2022-10-17 11:04:38,450 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:04:38,450 INFO L85 PathProgramCache]: Analyzing trace with hash 125941963, now seen corresponding path program 1 times [2022-10-17 11:04:38,450 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:04:38,450 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1259441721] [2022-10-17 11:04:38,450 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:04:38,450 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:04:38,481 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:04:38,528 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:04:38,528 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:04:38,528 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1259441721] [2022-10-17 11:04:38,529 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1259441721] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:04:38,529 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:04:38,529 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-10-17 11:04:38,529 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [97220193] [2022-10-17 11:04:38,529 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:04:38,530 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 11:04:38,531 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:04:38,531 INFO L85 PathProgramCache]: Analyzing trace with hash -1569586397, now seen corresponding path program 1 times [2022-10-17 11:04:38,531 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:04:38,531 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1564863440] [2022-10-17 11:04:38,531 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:04:38,532 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:04:38,547 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:04:38,579 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:04:38,579 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:04:38,580 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1564863440] [2022-10-17 11:04:38,580 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1564863440] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:04:38,580 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:04:38,580 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:04:38,580 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1115409374] [2022-10-17 11:04:38,580 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:04:38,581 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 11:04:38,581 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 11:04:38,582 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 11:04:38,582 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 11:04:38,582 INFO L87 Difference]: Start difference. First operand 40509 states and 57654 transitions. cyclomatic complexity: 17177 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 2 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:04:38,881 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 11:04:38,881 INFO L93 Difference]: Finished difference Result 60176 states and 85801 transitions. [2022-10-17 11:04:38,882 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 60176 states and 85801 transitions. [2022-10-17 11:04:39,441 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 59708 [2022-10-17 11:04:39,811 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 60176 states to 60176 states and 85801 transitions. [2022-10-17 11:04:39,812 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 60176 [2022-10-17 11:04:39,844 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 60176 [2022-10-17 11:04:39,844 INFO L73 IsDeterministic]: Start isDeterministic. Operand 60176 states and 85801 transitions. [2022-10-17 11:04:39,876 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 11:04:39,876 INFO L218 hiAutomatonCegarLoop]: Abstraction has 60176 states and 85801 transitions. [2022-10-17 11:04:39,923 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60176 states and 85801 transitions. [2022-10-17 11:04:40,477 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60176 to 42180. [2022-10-17 11:04:40,525 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 42180 states, 42180 states have (on average 1.4284257942152678) internal successors, (60251), 42179 states have internal predecessors, (60251), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:04:40,815 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42180 states to 42180 states and 60251 transitions. [2022-10-17 11:04:40,816 INFO L240 hiAutomatonCegarLoop]: Abstraction has 42180 states and 60251 transitions. [2022-10-17 11:04:40,816 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 11:04:40,817 INFO L428 stractBuchiCegarLoop]: Abstraction has 42180 states and 60251 transitions. [2022-10-17 11:04:40,817 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-10-17 11:04:40,817 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 42180 states and 60251 transitions. [2022-10-17 11:04:40,941 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 41843 [2022-10-17 11:04:40,941 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 11:04:40,942 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 11:04:40,943 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:04:40,943 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:04:40,944 INFO L748 eck$LassoCheckResult]: Stem: 253181#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 253113#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 253094#L1016 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 253070#L468 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 252526#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 252527#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 252875#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 252876#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 252793#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 252580#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 252581#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 252509#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 252510#L684 assume !(0 == ~M_E~0); 253020#L684-2 assume !(0 == ~T1_E~0); 252826#L689-1 assume !(0 == ~T2_E~0); 252827#L694-1 assume !(0 == ~T3_E~0); 252824#L699-1 assume !(0 == ~T4_E~0); 252825#L704-1 assume !(0 == ~T5_E~0); 252779#L709-1 assume !(0 == ~T6_E~0); 252717#L714-1 assume !(0 == ~E_M~0); 252718#L719-1 assume !(0 == ~E_1~0); 252984#L724-1 assume !(0 == ~E_2~0); 252482#L729-1 assume !(0 == ~E_3~0); 252483#L734-1 assume !(0 == ~E_4~0); 253062#L739-1 assume !(0 == ~E_5~0); 252672#L744-1 assume !(0 == ~E_6~0); 252673#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 252442#L334 assume !(1 == ~m_pc~0); 252443#L334-2 is_master_triggered_~__retres1~0#1 := 0; 252770#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 252476#L346 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 252477#L849 assume !(0 != activate_threads_~tmp~1#1); 252646#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 252576#L353 assume !(1 == ~t1_pc~0); 252577#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 252879#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 252492#L365 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 252493#L857 assume !(0 != activate_threads_~tmp___0~0#1); 252530#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 252531#L372 assume !(1 == ~t2_pc~0); 252632#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 252631#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 252763#L384 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 253049#L865 assume !(0 != activate_threads_~tmp___1~0#1); 252428#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 252429#L391 assume !(1 == ~t3_pc~0); 252350#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 252351#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 252560#L403 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 252767#L873 assume !(0 != activate_threads_~tmp___2~0#1); 252650#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 252651#L410 assume !(1 == ~t4_pc~0); 252899#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 252900#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 252942#L422 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 253050#L881 assume !(0 != activate_threads_~tmp___3~0#1); 252657#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 252658#L429 assume !(1 == ~t5_pc~0); 252486#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 252487#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 252413#L441 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 252414#L889 assume !(0 != activate_threads_~tmp___4~0#1); 252908#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 252639#L448 assume !(1 == ~t6_pc~0); 252561#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 252562#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 252904#L460 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 252997#L897 assume !(0 != activate_threads_~tmp___5~0#1); 253089#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 253161#L762 assume !(1 == ~M_E~0); 252696#L762-2 assume !(1 == ~T1_E~0); 252697#L767-1 assume !(1 == ~T2_E~0); 253096#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 252935#L777-1 assume !(1 == ~T4_E~0); 252808#L782-1 assume !(1 == ~T5_E~0); 252515#L787-1 assume !(1 == ~T6_E~0); 252513#L792-1 assume !(1 == ~E_M~0); 252514#L797-1 assume !(1 == ~E_1~0); 252548#L802-1 assume !(1 == ~E_2~0); 252773#L807-1 assume !(1 == ~E_3~0); 252774#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 253057#L817-1 assume !(1 == ~E_5~0); 252828#L822-1 assume !(1 == ~E_6~0); 252829#L827-1 assume { :end_inline_reset_delta_events } true; 253071#L1053-2 [2022-10-17 11:04:40,944 INFO L750 eck$LassoCheckResult]: Loop: 253071#L1053-2 assume !false; 259775#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 259770#L659 assume !false; 259771#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 259666#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 259661#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 267206#L556 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 267207#L570 assume !(0 != eval_~tmp~0#1); 283072#L674 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 290368#L468-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 290367#L684-3 assume !(0 == ~M_E~0); 290366#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 290365#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 290364#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 290363#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 290362#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 290361#L709-3 assume !(0 == ~T6_E~0); 290360#L714-3 assume !(0 == ~E_M~0); 290359#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 290358#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 290357#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 290356#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 290355#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 290354#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 290353#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 290352#L334-24 assume !(1 == ~m_pc~0); 290351#L334-26 is_master_triggered_~__retres1~0#1 := 0; 290350#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 290349#L346-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 290348#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 290347#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 290346#L353-24 assume !(1 == ~t1_pc~0); 290345#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 290344#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 290343#L365-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 290342#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 290341#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 290340#L372-24 assume 1 == ~t2_pc~0; 290338#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 290337#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 290336#L384-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 290335#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 290334#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 290333#L391-24 assume !(1 == ~t3_pc~0); 290332#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 290331#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 290330#L403-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 290329#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 290328#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 290327#L410-24 assume !(1 == ~t4_pc~0); 290326#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 290325#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 290324#L422-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 290323#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 290322#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 290321#L429-24 assume !(1 == ~t5_pc~0); 290318#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 290317#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 290316#L441-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 290315#L889-24 assume !(0 != activate_threads_~tmp___4~0#1); 290313#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 290312#L448-24 assume !(1 == ~t6_pc~0); 290311#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 290310#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 290309#L460-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 290308#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 290307#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 290306#L762-3 assume !(1 == ~M_E~0); 274721#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 290305#L767-3 assume !(1 == ~T2_E~0); 290304#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 290303#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 290302#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 290301#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 290300#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 290299#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 290298#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 290297#L807-3 assume !(1 == ~E_3~0); 290296#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 290295#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 290294#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 290293#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 290291#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 290285#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 290284#L556-1 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 274845#L1072 assume !(0 == start_simulation_~tmp~3#1); 259806#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 259807#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 283199#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 259786#L556-2 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 259787#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 283146#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 283126#L1035 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 283125#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 253071#L1053-2 [2022-10-17 11:04:40,945 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:04:40,945 INFO L85 PathProgramCache]: Analyzing trace with hash -1153921715, now seen corresponding path program 1 times [2022-10-17 11:04:40,945 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:04:40,946 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [236186214] [2022-10-17 11:04:40,946 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:04:40,946 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:04:40,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:04:41,022 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:04:41,022 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:04:41,022 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [236186214] [2022-10-17 11:04:41,022 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [236186214] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:04:41,022 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:04:41,023 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:04:41,023 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1920181850] [2022-10-17 11:04:41,024 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:04:41,026 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 11:04:41,026 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:04:41,027 INFO L85 PathProgramCache]: Analyzing trace with hash -1525489309, now seen corresponding path program 1 times [2022-10-17 11:04:41,027 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:04:41,027 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1338015462] [2022-10-17 11:04:41,027 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:04:41,027 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:04:41,047 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:04:41,076 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:04:41,077 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:04:41,077 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1338015462] [2022-10-17 11:04:41,077 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1338015462] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:04:41,077 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:04:41,077 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:04:41,078 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2077536300] [2022-10-17 11:04:41,078 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:04:41,078 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 11:04:41,079 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 11:04:41,079 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-10-17 11:04:41,080 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-10-17 11:04:41,080 INFO L87 Difference]: Start difference. First operand 42180 states and 60251 transitions. cyclomatic complexity: 18087 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:04:41,564 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 11:04:41,564 INFO L93 Difference]: Finished difference Result 68061 states and 96660 transitions. [2022-10-17 11:04:41,565 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 68061 states and 96660 transitions. [2022-10-17 11:04:41,876 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 67527 [2022-10-17 11:04:42,140 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 68061 states to 68061 states and 96660 transitions. [2022-10-17 11:04:42,140 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 68061 [2022-10-17 11:04:42,187 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 68061 [2022-10-17 11:04:42,187 INFO L73 IsDeterministic]: Start isDeterministic. Operand 68061 states and 96660 transitions. [2022-10-17 11:04:42,236 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 11:04:42,237 INFO L218 hiAutomatonCegarLoop]: Abstraction has 68061 states and 96660 transitions. [2022-10-17 11:04:42,288 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 68061 states and 96660 transitions. [2022-10-17 11:04:43,194 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 68061 to 49132. [2022-10-17 11:04:43,240 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 49132 states, 49132 states have (on average 1.4234104046242775) internal successors, (69935), 49131 states have internal predecessors, (69935), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:04:43,366 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49132 states to 49132 states and 69935 transitions. [2022-10-17 11:04:43,366 INFO L240 hiAutomatonCegarLoop]: Abstraction has 49132 states and 69935 transitions. [2022-10-17 11:04:43,367 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-10-17 11:04:43,367 INFO L428 stractBuchiCegarLoop]: Abstraction has 49132 states and 69935 transitions. [2022-10-17 11:04:43,367 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-10-17 11:04:43,368 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 49132 states and 69935 transitions. [2022-10-17 11:04:43,524 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 48733 [2022-10-17 11:04:43,525 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 11:04:43,525 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 11:04:43,526 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:04:43,527 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:04:43,527 INFO L748 eck$LassoCheckResult]: Stem: 363435#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 363377#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 363354#L1016 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 363327#L468 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 362772#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 362773#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 363131#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 363132#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 363046#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 362827#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 362828#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 362756#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 362757#L684 assume !(0 == ~M_E~0); 363274#L684-2 assume !(0 == ~T1_E~0); 363081#L689-1 assume !(0 == ~T2_E~0); 363082#L694-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 363433#L699-1 assume !(0 == ~T4_E~0); 363474#L704-1 assume !(0 == ~T5_E~0); 363473#L709-1 assume !(0 == ~T6_E~0); 362968#L714-1 assume !(0 == ~E_M~0); 362969#L719-1 assume !(0 == ~E_1~0); 363240#L724-1 assume !(0 == ~E_2~0); 362729#L729-1 assume !(0 == ~E_3~0); 362730#L734-1 assume !(0 == ~E_4~0); 363471#L739-1 assume !(0 == ~E_5~0); 362919#L744-1 assume !(0 == ~E_6~0); 362920#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 363242#L334 assume !(1 == ~m_pc~0); 363469#L334-2 is_master_triggered_~__retres1~0#1 := 0; 363468#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 363467#L346 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 362892#L849 assume !(0 != activate_threads_~tmp~1#1); 362893#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 363466#L353 assume !(1 == ~t1_pc~0); 363465#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 363136#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 363137#L365 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 363099#L857 assume !(0 != activate_threads_~tmp___0~0#1); 363100#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 363372#L372 assume !(1 == ~t2_pc~0); 363373#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 363464#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 363463#L384 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 363462#L865 assume !(0 != activate_threads_~tmp___1~0#1); 362678#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 362679#L391 assume !(1 == ~t3_pc~0); 363289#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 363460#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 363459#L403 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 363458#L873 assume !(0 != activate_threads_~tmp___2~0#1); 362897#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 362898#L410 assume !(1 == ~t4_pc~0); 363302#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 363200#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 363201#L422 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 363456#L881 assume !(0 != activate_threads_~tmp___3~0#1); 362904#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 362905#L429 assume !(1 == ~t5_pc~0); 363359#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 363455#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 363452#L441 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 363449#L889 assume !(0 != activate_threads_~tmp___4~0#1); 363190#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 363191#L448 assume !(1 == ~t6_pc~0); 363448#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 363160#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 363161#L460 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 363256#L897 assume !(0 != activate_threads_~tmp___5~0#1); 363422#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 363423#L762 assume !(1 == ~M_E~0); 363446#L762-2 assume !(1 == ~T1_E~0); 363395#L767-1 assume !(1 == ~T2_E~0); 363396#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 363192#L777-1 assume !(1 == ~T4_E~0); 363060#L782-1 assume !(1 == ~T5_E~0); 362762#L787-1 assume !(1 == ~T6_E~0); 362760#L792-1 assume !(1 == ~E_M~0); 362761#L797-1 assume !(1 == ~E_1~0); 362794#L802-1 assume !(1 == ~E_2~0); 363023#L807-1 assume !(1 == ~E_3~0); 363024#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 363315#L817-1 assume !(1 == ~E_5~0); 363083#L822-1 assume !(1 == ~E_6~0); 363084#L827-1 assume { :end_inline_reset_delta_events } true; 363328#L1053-2 [2022-10-17 11:04:43,527 INFO L750 eck$LassoCheckResult]: Loop: 363328#L1053-2 assume !false; 385744#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 385742#L659 assume !false; 385740#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 385737#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 385724#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 385722#L556 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 385719#L570 assume !(0 != eval_~tmp~0#1); 385716#L674 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 385714#L468-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 385712#L684-3 assume !(0 == ~M_E~0); 385710#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 385709#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 385708#L694-3 assume !(0 == ~T3_E~0); 371442#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 371441#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 371440#L709-3 assume !(0 == ~T6_E~0); 371439#L714-3 assume !(0 == ~E_M~0); 371438#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 371437#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 371436#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 371435#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 371434#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 371433#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 371432#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 371431#L334-24 assume !(1 == ~m_pc~0); 371430#L334-26 is_master_triggered_~__retres1~0#1 := 0; 371429#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 371428#L346-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 371427#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 371426#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 371425#L353-24 assume !(1 == ~t1_pc~0); 371424#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 371423#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 371422#L365-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 371420#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 371421#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 391503#L372-24 assume 1 == ~t2_pc~0; 391501#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 391500#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 391499#L384-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 391498#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 391497#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 391496#L391-24 assume !(1 == ~t3_pc~0); 391495#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 391493#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 391491#L403-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 391489#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 391487#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 391486#L410-24 assume !(1 == ~t4_pc~0); 391485#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 391483#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 391482#L422-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 391481#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 391480#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 391478#L429-24 assume 1 == ~t5_pc~0; 391476#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 391477#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 391484#L441-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 391467#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 391465#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 391464#L448-24 assume !(1 == ~t6_pc~0); 391463#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 391462#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 391461#L460-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 391459#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 391457#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 391455#L762-3 assume !(1 == ~M_E~0); 380501#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 385739#L767-3 assume !(1 == ~T2_E~0); 385647#L772-3 assume !(1 == ~T3_E~0); 385645#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 385643#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 385642#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 385641#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 385640#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 385639#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 385638#L807-3 assume !(1 == ~E_3~0); 385637#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 385636#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 385635#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 385634#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 385632#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 385569#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 371203#L556-1 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 371204#L1072 assume !(0 == start_simulation_~tmp~3#1); 380645#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 385775#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 385773#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 385771#L556-2 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 385769#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 385767#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 385765#L1035 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 385763#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 363328#L1053-2 [2022-10-17 11:04:43,528 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:04:43,528 INFO L85 PathProgramCache]: Analyzing trace with hash -661295541, now seen corresponding path program 1 times [2022-10-17 11:04:43,528 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:04:43,529 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [915548875] [2022-10-17 11:04:43,529 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:04:43,529 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:04:43,540 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:04:43,926 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:04:43,926 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:04:43,926 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [915548875] [2022-10-17 11:04:43,926 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [915548875] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:04:43,927 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:04:43,927 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:04:43,927 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1197143701] [2022-10-17 11:04:43,927 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:04:43,927 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 11:04:43,928 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:04:43,928 INFO L85 PathProgramCache]: Analyzing trace with hash -916407008, now seen corresponding path program 1 times [2022-10-17 11:04:43,928 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:04:43,928 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [884700555] [2022-10-17 11:04:43,929 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:04:43,929 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:04:43,957 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:04:43,984 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:04:43,984 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:04:43,984 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [884700555] [2022-10-17 11:04:43,985 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [884700555] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:04:43,985 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:04:43,985 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:04:43,985 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [767799487] [2022-10-17 11:04:43,985 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:04:43,986 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 11:04:43,986 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 11:04:43,986 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-10-17 11:04:43,986 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-10-17 11:04:43,986 INFO L87 Difference]: Start difference. First operand 49132 states and 69935 transitions. cyclomatic complexity: 20819 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:04:44,224 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 11:04:44,224 INFO L93 Difference]: Finished difference Result 61098 states and 86575 transitions. [2022-10-17 11:04:44,225 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 61098 states and 86575 transitions. [2022-10-17 11:04:44,492 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 60637 [2022-10-17 11:04:44,676 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 61098 states to 61098 states and 86575 transitions. [2022-10-17 11:04:44,676 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 61098 [2022-10-17 11:04:44,715 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 61098 [2022-10-17 11:04:44,715 INFO L73 IsDeterministic]: Start isDeterministic. Operand 61098 states and 86575 transitions. [2022-10-17 11:04:44,777 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 11:04:44,777 INFO L218 hiAutomatonCegarLoop]: Abstraction has 61098 states and 86575 transitions. [2022-10-17 11:04:44,813 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61098 states and 86575 transitions. [2022-10-17 11:04:45,644 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61098 to 42180. [2022-10-17 11:04:45,675 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 42180 states, 42180 states have (on average 1.420697012802276) internal successors, (59925), 42179 states have internal predecessors, (59925), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:04:45,771 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42180 states to 42180 states and 59925 transitions. [2022-10-17 11:04:45,771 INFO L240 hiAutomatonCegarLoop]: Abstraction has 42180 states and 59925 transitions. [2022-10-17 11:04:45,772 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-10-17 11:04:45,772 INFO L428 stractBuchiCegarLoop]: Abstraction has 42180 states and 59925 transitions. [2022-10-17 11:04:45,772 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-10-17 11:04:45,772 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 42180 states and 59925 transitions. [2022-10-17 11:04:45,910 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 41843 [2022-10-17 11:04:45,910 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 11:04:45,910 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 11:04:45,912 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:04:45,913 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:04:45,913 INFO L748 eck$LassoCheckResult]: Stem: 473657#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 473598#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 473579#L1016 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 473556#L468 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 473015#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 473016#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 473370#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 473371#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 473291#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 473072#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 473073#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 472999#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 473000#L684 assume !(0 == ~M_E~0); 473499#L684-2 assume !(0 == ~T1_E~0); 473325#L689-1 assume !(0 == ~T2_E~0); 473326#L694-1 assume !(0 == ~T3_E~0); 473323#L699-1 assume !(0 == ~T4_E~0); 473324#L704-1 assume !(0 == ~T5_E~0); 473274#L709-1 assume !(0 == ~T6_E~0); 473212#L714-1 assume !(0 == ~E_M~0); 473213#L719-1 assume !(0 == ~E_1~0); 473471#L724-1 assume !(0 == ~E_2~0); 472971#L729-1 assume !(0 == ~E_3~0); 472972#L734-1 assume !(0 == ~E_4~0); 473545#L739-1 assume !(0 == ~E_5~0); 473166#L744-1 assume !(0 == ~E_6~0); 473167#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 472932#L334 assume !(1 == ~m_pc~0); 472933#L334-2 is_master_triggered_~__retres1~0#1 := 0; 473264#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 472965#L346 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 472966#L849 assume !(0 != activate_threads_~tmp~1#1); 473139#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 473068#L353 assume !(1 == ~t1_pc~0); 473069#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 473375#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 472981#L365 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 472982#L857 assume !(0 != activate_threads_~tmp___0~0#1); 473019#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 473020#L372 assume !(1 == ~t2_pc~0); 473124#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 473123#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 473257#L384 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 473529#L865 assume !(0 != activate_threads_~tmp___1~0#1); 472919#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 472920#L391 assume !(1 == ~t3_pc~0); 472841#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 472842#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 473052#L403 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 473261#L873 assume !(0 != activate_threads_~tmp___2~0#1); 473143#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 473144#L410 assume !(1 == ~t4_pc~0); 473391#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 473392#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 473432#L422 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 473530#L881 assume !(0 != activate_threads_~tmp___3~0#1); 473150#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 473151#L429 assume !(1 == ~t5_pc~0); 472975#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 472976#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 472904#L441 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 472905#L889 assume !(0 != activate_threads_~tmp___4~0#1); 473399#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 473132#L448 assume !(1 == ~t6_pc~0); 473053#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 473054#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 473396#L460 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 473482#L897 assume !(0 != activate_threads_~tmp___5~0#1); 473574#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 473639#L762 assume !(1 == ~M_E~0); 473191#L762-2 assume !(1 == ~T1_E~0); 473192#L767-1 assume !(1 == ~T2_E~0); 473583#L772-1 assume !(1 == ~T3_E~0); 473425#L777-1 assume !(1 == ~T4_E~0); 473305#L782-1 assume !(1 == ~T5_E~0); 473005#L787-1 assume !(1 == ~T6_E~0); 473003#L792-1 assume !(1 == ~E_M~0); 473004#L797-1 assume !(1 == ~E_1~0); 473037#L802-1 assume !(1 == ~E_2~0); 473267#L807-1 assume !(1 == ~E_3~0); 473268#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 473539#L817-1 assume !(1 == ~E_5~0); 473327#L822-1 assume !(1 == ~E_6~0); 473328#L827-1 assume { :end_inline_reset_delta_events } true; 473557#L1053-2 [2022-10-17 11:04:45,914 INFO L750 eck$LassoCheckResult]: Loop: 473557#L1053-2 assume !false; 504233#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 504231#L659 assume !false; 504229#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 504224#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 504215#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 504213#L556 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 504210#L570 assume !(0 != eval_~tmp~0#1); 504211#L674 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 507011#L468-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 507009#L684-3 assume !(0 == ~M_E~0); 507007#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 507005#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 507003#L694-3 assume !(0 == ~T3_E~0); 506999#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 506997#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 506995#L709-3 assume !(0 == ~T6_E~0); 506990#L714-3 assume !(0 == ~E_M~0); 506985#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 506983#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 506981#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 506980#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 506979#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 506971#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 506969#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 506967#L334-24 assume !(1 == ~m_pc~0); 506964#L334-26 is_master_triggered_~__retres1~0#1 := 0; 506962#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 506960#L346-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 506958#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 506956#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 506954#L353-24 assume !(1 == ~t1_pc~0); 506952#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 506950#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 506948#L365-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 506946#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 506944#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 506942#L372-24 assume !(1 == ~t2_pc~0); 506940#L372-26 is_transmit2_triggered_~__retres1~2#1 := 0; 506937#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 506935#L384-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 506933#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 506931#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 506929#L391-24 assume !(1 == ~t3_pc~0); 506927#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 506925#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 506923#L403-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 506921#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 506919#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 506917#L410-24 assume !(1 == ~t4_pc~0); 506914#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 506912#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 479951#L422-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 479947#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 479945#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 479942#L429-24 assume !(1 == ~t5_pc~0); 479938#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 479939#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 505687#L441-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 505686#L889-24 assume !(0 != activate_threads_~tmp___4~0#1); 505684#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 505682#L448-24 assume !(1 == ~t6_pc~0); 505680#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 505678#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 505676#L460-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 505674#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 505672#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 505670#L762-3 assume !(1 == ~M_E~0); 477734#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 505667#L767-3 assume !(1 == ~T2_E~0); 505666#L772-3 assume !(1 == ~T3_E~0); 505664#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 505662#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 505660#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 505658#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 505656#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 505654#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 505652#L807-3 assume !(1 == ~E_3~0); 505650#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 505648#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 505646#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 505644#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 504414#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 504408#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 504406#L556-1 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 477823#L1072 assume !(0 == start_simulation_~tmp~3#1); 477824#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 504395#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 504393#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 504391#L556-2 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 504389#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 504387#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 504385#L1035 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 504383#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 473557#L1053-2 [2022-10-17 11:04:45,914 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:04:45,914 INFO L85 PathProgramCache]: Analyzing trace with hash -895756277, now seen corresponding path program 1 times [2022-10-17 11:04:45,914 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:04:45,915 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [36587625] [2022-10-17 11:04:45,915 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:04:45,915 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:04:45,933 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:04:46,013 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:04:46,014 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:04:46,014 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [36587625] [2022-10-17 11:04:46,014 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [36587625] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:04:46,014 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:04:46,015 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:04:46,015 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [844422763] [2022-10-17 11:04:46,015 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:04:46,015 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 11:04:46,016 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:04:46,016 INFO L85 PathProgramCache]: Analyzing trace with hash 1817893732, now seen corresponding path program 1 times [2022-10-17 11:04:46,016 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:04:46,016 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [658499310] [2022-10-17 11:04:46,016 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:04:46,017 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:04:46,299 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:04:46,366 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:04:46,366 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:04:46,366 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [658499310] [2022-10-17 11:04:46,366 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [658499310] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:04:46,366 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:04:46,367 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:04:46,367 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [631044022] [2022-10-17 11:04:46,367 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:04:46,367 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 11:04:46,368 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 11:04:46,368 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-10-17 11:04:46,368 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-10-17 11:04:46,369 INFO L87 Difference]: Start difference. First operand 42180 states and 59925 transitions. cyclomatic complexity: 17761 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:04:46,719 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 11:04:46,720 INFO L93 Difference]: Finished difference Result 67544 states and 95082 transitions. [2022-10-17 11:04:46,720 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 67544 states and 95082 transitions. [2022-10-17 11:04:47,009 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 67000 [2022-10-17 11:04:47,184 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 67544 states to 67544 states and 95082 transitions. [2022-10-17 11:04:47,184 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 67544 [2022-10-17 11:04:47,225 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 67544 [2022-10-17 11:04:47,226 INFO L73 IsDeterministic]: Start isDeterministic. Operand 67544 states and 95082 transitions. [2022-10-17 11:04:47,262 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 11:04:47,262 INFO L218 hiAutomatonCegarLoop]: Abstraction has 67544 states and 95082 transitions. [2022-10-17 11:04:47,296 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67544 states and 95082 transitions. [2022-10-17 11:04:48,194 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67544 to 49132. [2022-10-17 11:04:48,217 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 49132 states, 49132 states have (on average 1.4107709842872262) internal successors, (69314), 49131 states have internal predecessors, (69314), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:04:48,301 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49132 states to 49132 states and 69314 transitions. [2022-10-17 11:04:48,301 INFO L240 hiAutomatonCegarLoop]: Abstraction has 49132 states and 69314 transitions. [2022-10-17 11:04:48,301 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-10-17 11:04:48,302 INFO L428 stractBuchiCegarLoop]: Abstraction has 49132 states and 69314 transitions. [2022-10-17 11:04:48,302 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-10-17 11:04:48,302 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 49132 states and 69314 transitions. [2022-10-17 11:04:48,427 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 48733 [2022-10-17 11:04:48,427 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 11:04:48,428 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 11:04:48,429 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:04:48,430 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:04:48,430 INFO L748 eck$LassoCheckResult]: Stem: 583418#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 583358#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 583337#L1016 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 583308#L468 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 582749#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 582750#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 583100#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 583101#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 583016#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 582802#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 582803#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 582733#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 582734#L684 assume !(0 == ~M_E~0); 583247#L684-2 assume !(0 == ~T1_E~0); 583050#L689-1 assume !(0 == ~T2_E~0); 583051#L694-1 assume !(0 == ~T3_E~0); 583048#L699-1 assume !(0 == ~T4_E~0); 583049#L704-1 assume !(0 == ~T5_E~0); 583002#L709-1 assume !(0 == ~T6_E~0); 582943#L714-1 assume !(0 == ~E_M~0); 582944#L719-1 assume !(0 == ~E_1~0); 583211#L724-1 assume !(0 == ~E_2~0); 582704#L729-1 assume !(0 == ~E_3~0); 582705#L734-1 assume 0 == ~E_4~0;~E_4~0 := 1; 583297#L739-1 assume !(0 == ~E_5~0); 583298#L744-1 assume !(0 == ~E_6~0); 583214#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 583215#L334 assume !(1 == ~m_pc~0); 583464#L334-2 is_master_triggered_~__retres1~0#1 := 0; 583463#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 583462#L346 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 582872#L849 assume !(0 != activate_threads_~tmp~1#1); 582873#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 583461#L353 assume !(1 == ~t1_pc~0); 583460#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 583104#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 583105#L365 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 583068#L857 assume !(0 != activate_threads_~tmp___0~0#1); 582751#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 582752#L372 assume !(1 == ~t2_pc~0); 582857#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 582856#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 582985#L384 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 583282#L865 assume !(0 != activate_threads_~tmp___1~0#1); 583283#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 583454#L391 assume !(1 == ~t3_pc~0); 582577#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 582578#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 582782#L403 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 582991#L873 assume !(0 != activate_threads_~tmp___2~0#1); 583205#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 583450#L410 assume !(1 == ~t4_pc~0); 583124#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 583125#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 583171#L422 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 583448#L881 assume !(0 != activate_threads_~tmp___3~0#1); 582887#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 582888#L429 assume !(1 == ~t5_pc~0); 582708#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 582709#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 583459#L441 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 583133#L889 assume !(0 != activate_threads_~tmp___4~0#1); 583134#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 583164#L448 assume !(1 == ~t6_pc~0); 583440#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 583439#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 583438#L460 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 583331#L897 assume !(0 != activate_threads_~tmp___5~0#1); 583332#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 583398#L762 assume !(1 == ~M_E~0); 582924#L762-2 assume !(1 == ~T1_E~0); 582925#L767-1 assume !(1 == ~T2_E~0); 583339#L772-1 assume !(1 == ~T3_E~0); 583165#L777-1 assume !(1 == ~T4_E~0); 583166#L782-1 assume !(1 == ~T5_E~0); 583435#L787-1 assume !(1 == ~T6_E~0); 583434#L792-1 assume !(1 == ~E_M~0); 583433#L797-1 assume !(1 == ~E_1~0); 583432#L802-1 assume !(1 == ~E_2~0); 583431#L807-1 assume !(1 == ~E_3~0); 583430#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 583295#L817-1 assume !(1 == ~E_5~0); 583054#L822-1 assume !(1 == ~E_6~0); 583055#L827-1 assume { :end_inline_reset_delta_events } true; 583309#L1053-2 [2022-10-17 11:04:48,431 INFO L750 eck$LassoCheckResult]: Loop: 583309#L1053-2 assume !false; 619438#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 619436#L659 assume !false; 619434#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 619429#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 619422#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 619420#L556 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 619417#L570 assume !(0 != eval_~tmp~0#1); 619415#L674 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 619413#L468-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 619409#L684-3 assume !(0 == ~M_E~0); 619407#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 619405#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 619403#L694-3 assume !(0 == ~T3_E~0); 619400#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 619398#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 619397#L709-3 assume !(0 == ~T6_E~0); 619396#L714-3 assume !(0 == ~E_M~0); 619395#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 619394#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 619393#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 619391#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 619390#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 619389#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 619388#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 619387#L334-24 assume !(1 == ~m_pc~0); 619386#L334-26 is_master_triggered_~__retres1~0#1 := 0; 619385#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 619384#L346-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 619383#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 619382#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 619381#L353-24 assume !(1 == ~t1_pc~0); 619380#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 619379#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 619378#L365-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 619377#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 619376#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 619375#L372-24 assume 1 == ~t2_pc~0; 619373#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 619372#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 619371#L384-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 619370#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 619369#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 619368#L391-24 assume !(1 == ~t3_pc~0); 619367#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 619366#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 619365#L403-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 619364#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 619363#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 619362#L410-24 assume !(1 == ~t4_pc~0); 619361#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 619360#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 619359#L422-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 619358#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 619357#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 619356#L429-24 assume 1 == ~t5_pc~0; 590281#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 590278#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 590279#L441-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 590271#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 590272#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 590267#L448-24 assume !(1 == ~t6_pc~0); 590268#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 590263#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 590264#L460-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 590259#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 590260#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 590255#L762-3 assume !(1 == ~M_E~0); 590256#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 590251#L767-3 assume !(1 == ~T2_E~0); 590252#L772-3 assume !(1 == ~T3_E~0); 590247#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 590248#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 590243#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 590244#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 590239#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 590240#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 590235#L807-3 assume !(1 == ~E_3~0); 590236#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 619351#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 619350#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 619349#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 619345#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 619338#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 619336#L556-1 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 608342#L1072 assume !(0 == start_simulation_~tmp~3#1); 608343#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 619578#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 619576#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 619574#L556-2 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 619572#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 619569#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 619567#L1035 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 619565#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 583309#L1053-2 [2022-10-17 11:04:48,431 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:04:48,432 INFO L85 PathProgramCache]: Analyzing trace with hash 1437636361, now seen corresponding path program 1 times [2022-10-17 11:04:48,432 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:04:48,432 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [765036764] [2022-10-17 11:04:48,432 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:04:48,432 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:04:48,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:04:48,487 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:04:48,487 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:04:48,487 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [765036764] [2022-10-17 11:04:48,487 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [765036764] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:04:48,487 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:04:48,488 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:04:48,488 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [259531405] [2022-10-17 11:04:48,488 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:04:48,488 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 11:04:48,489 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:04:48,489 INFO L85 PathProgramCache]: Analyzing trace with hash -916407008, now seen corresponding path program 2 times [2022-10-17 11:04:48,489 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:04:48,489 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [476336165] [2022-10-17 11:04:48,490 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:04:48,490 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:04:48,501 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:04:48,527 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:04:48,527 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:04:48,528 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [476336165] [2022-10-17 11:04:48,528 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [476336165] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:04:48,528 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:04:48,528 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:04:48,528 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [924748914] [2022-10-17 11:04:48,529 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:04:48,529 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 11:04:48,529 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 11:04:48,529 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-10-17 11:04:48,530 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-10-17 11:04:48,530 INFO L87 Difference]: Start difference. First operand 49132 states and 69314 transitions. cyclomatic complexity: 20198 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:04:48,808 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 11:04:48,809 INFO L93 Difference]: Finished difference Result 60187 states and 84509 transitions. [2022-10-17 11:04:48,809 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 60187 states and 84509 transitions. [2022-10-17 11:04:49,059 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 59708 [2022-10-17 11:04:49,198 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 60187 states to 60187 states and 84509 transitions. [2022-10-17 11:04:49,199 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 60187 [2022-10-17 11:04:49,230 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 60187 [2022-10-17 11:04:49,230 INFO L73 IsDeterministic]: Start isDeterministic. Operand 60187 states and 84509 transitions. [2022-10-17 11:04:49,255 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 11:04:49,255 INFO L218 hiAutomatonCegarLoop]: Abstraction has 60187 states and 84509 transitions. [2022-10-17 11:04:49,286 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60187 states and 84509 transitions. [2022-10-17 11:04:50,112 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60187 to 42180. [2022-10-17 11:04:50,137 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 42180 states, 42180 states have (on average 1.4059743954480797) internal successors, (59304), 42179 states have internal predecessors, (59304), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:04:50,215 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42180 states to 42180 states and 59304 transitions. [2022-10-17 11:04:50,215 INFO L240 hiAutomatonCegarLoop]: Abstraction has 42180 states and 59304 transitions. [2022-10-17 11:04:50,215 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-10-17 11:04:50,216 INFO L428 stractBuchiCegarLoop]: Abstraction has 42180 states and 59304 transitions. [2022-10-17 11:04:50,216 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2022-10-17 11:04:50,216 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 42180 states and 59304 transitions. [2022-10-17 11:04:50,327 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 41843 [2022-10-17 11:04:50,327 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 11:04:50,327 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 11:04:50,329 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:04:50,331 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:04:50,332 INFO L748 eck$LassoCheckResult]: Stem: 692732#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 692664#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 692646#L1016 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 692615#L468 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 692080#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 692081#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 692422#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 692423#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 692341#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 692132#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 692133#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 692063#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 692064#L684 assume !(0 == ~M_E~0); 692567#L684-2 assume !(0 == ~T1_E~0); 692376#L689-1 assume !(0 == ~T2_E~0); 692377#L694-1 assume !(0 == ~T3_E~0); 692374#L699-1 assume !(0 == ~T4_E~0); 692375#L704-1 assume !(0 == ~T5_E~0); 692329#L709-1 assume !(0 == ~T6_E~0); 692265#L714-1 assume !(0 == ~E_M~0); 692266#L719-1 assume !(0 == ~E_1~0); 692530#L724-1 assume !(0 == ~E_2~0); 692034#L729-1 assume !(0 == ~E_3~0); 692035#L734-1 assume !(0 == ~E_4~0); 692611#L739-1 assume !(0 == ~E_5~0); 692221#L744-1 assume !(0 == ~E_6~0); 692222#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 691995#L334 assume !(1 == ~m_pc~0); 691996#L334-2 is_master_triggered_~__retres1~0#1 := 0; 692317#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 692028#L346 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 692029#L849 assume !(0 != activate_threads_~tmp~1#1); 692196#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 692128#L353 assume !(1 == ~t1_pc~0); 692129#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 692428#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 692044#L365 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 692045#L857 assume !(0 != activate_threads_~tmp___0~0#1); 692082#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 692083#L372 assume !(1 == ~t2_pc~0); 692182#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 692181#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 692311#L384 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 692599#L865 assume !(0 != activate_threads_~tmp___1~0#1); 691984#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 691985#L391 assume !(1 == ~t3_pc~0); 691906#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 691907#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 692112#L403 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 692316#L873 assume !(0 != activate_threads_~tmp___2~0#1); 692200#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 692201#L410 assume !(1 == ~t4_pc~0); 692444#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 692445#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 692492#L422 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 692603#L881 assume !(0 != activate_threads_~tmp___3~0#1); 692209#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 692210#L429 assume !(1 == ~t5_pc~0); 692038#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 692039#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 691969#L441 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 691970#L889 assume !(0 != activate_threads_~tmp___4~0#1); 692453#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 692191#L448 assume !(1 == ~t6_pc~0); 692113#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 692114#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 692450#L460 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 692547#L897 assume !(0 != activate_threads_~tmp___5~0#1); 692640#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 692709#L762 assume !(1 == ~M_E~0); 692244#L762-2 assume !(1 == ~T1_E~0); 692245#L767-1 assume !(1 == ~T2_E~0); 692649#L772-1 assume !(1 == ~T3_E~0); 692486#L777-1 assume !(1 == ~T4_E~0); 692355#L782-1 assume !(1 == ~T5_E~0); 692067#L787-1 assume !(1 == ~T6_E~0); 692065#L792-1 assume !(1 == ~E_M~0); 692066#L797-1 assume !(1 == ~E_1~0); 692101#L802-1 assume !(1 == ~E_2~0); 692323#L807-1 assume !(1 == ~E_3~0); 692324#L812-1 assume !(1 == ~E_4~0); 692609#L817-1 assume !(1 == ~E_5~0); 692380#L822-1 assume !(1 == ~E_6~0); 692381#L827-1 assume { :end_inline_reset_delta_events } true; 692616#L1053-2 [2022-10-17 11:04:50,333 INFO L750 eck$LassoCheckResult]: Loop: 692616#L1053-2 assume !false; 714091#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 714090#L659 assume !false; 714089#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 714087#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 714081#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 714079#L556 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 714076#L570 assume !(0 != eval_~tmp~0#1); 714074#L674 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 714072#L468-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 714070#L684-3 assume !(0 == ~M_E~0); 714068#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 714066#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 714065#L694-3 assume !(0 == ~T3_E~0); 714063#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 714061#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 714059#L709-3 assume !(0 == ~T6_E~0); 714057#L714-3 assume !(0 == ~E_M~0); 714055#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 714052#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 714050#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 714048#L734-3 assume !(0 == ~E_4~0); 714046#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 714044#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 714040#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 714038#L334-24 assume !(1 == ~m_pc~0); 714036#L334-26 is_master_triggered_~__retres1~0#1 := 0; 714034#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 714032#L346-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 714030#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 714028#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 714026#L353-24 assume !(1 == ~t1_pc~0); 714024#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 714022#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 714020#L365-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 714018#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 714014#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 714012#L372-24 assume !(1 == ~t2_pc~0); 714010#L372-26 is_transmit2_triggered_~__retres1~2#1 := 0; 714007#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 714004#L384-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 714002#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 714000#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 713998#L391-24 assume !(1 == ~t3_pc~0); 713996#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 713994#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 713992#L403-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 713990#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 713986#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 713984#L410-24 assume !(1 == ~t4_pc~0); 713982#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 713977#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 713972#L422-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 713969#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 713968#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 713967#L429-24 assume 1 == ~t5_pc~0; 713965#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 713966#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 714454#L441-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 713949#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 713947#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 713945#L448-24 assume !(1 == ~t6_pc~0); 713943#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 713941#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 713939#L460-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 713937#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 713935#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 713933#L762-3 assume !(1 == ~M_E~0); 711761#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 713930#L767-3 assume !(1 == ~T2_E~0); 713928#L772-3 assume !(1 == ~T3_E~0); 713926#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 713924#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 713922#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 713920#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 713918#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 713916#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 713915#L807-3 assume !(1 == ~E_3~0); 713914#L812-3 assume !(1 == ~E_4~0); 713913#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 713912#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 713911#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 713907#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 713900#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 713898#L556-1 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 697803#L1072 assume !(0 == start_simulation_~tmp~3#1); 697804#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 714752#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 714750#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 714748#L556-2 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 714746#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 714744#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 714741#L1035 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 714739#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 692616#L1053-2 [2022-10-17 11:04:50,334 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:04:50,335 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 1 times [2022-10-17 11:04:50,335 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:04:50,335 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1830277207] [2022-10-17 11:04:50,335 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:04:50,336 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:04:50,355 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 11:04:50,356 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 11:04:50,365 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 11:04:50,415 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 11:04:50,415 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:04:50,416 INFO L85 PathProgramCache]: Analyzing trace with hash 686716705, now seen corresponding path program 1 times [2022-10-17 11:04:50,416 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:04:50,416 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1045685749] [2022-10-17 11:04:50,416 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:04:50,416 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:04:50,428 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:04:50,455 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:04:50,455 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:04:50,455 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1045685749] [2022-10-17 11:04:50,456 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1045685749] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:04:50,456 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:04:50,456 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:04:50,456 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1383748848] [2022-10-17 11:04:50,456 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:04:50,457 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 11:04:50,457 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 11:04:50,457 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 11:04:50,457 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 11:04:50,458 INFO L87 Difference]: Start difference. First operand 42180 states and 59304 transitions. cyclomatic complexity: 17140 Second operand has 3 states, 3 states have (on average 31.333333333333332) internal successors, (94), 3 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:04:50,619 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 11:04:50,619 INFO L93 Difference]: Finished difference Result 49132 states and 68824 transitions. [2022-10-17 11:04:50,622 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 49132 states and 68824 transitions. [2022-10-17 11:04:50,796 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 48733 [2022-10-17 11:04:50,904 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 49132 states to 49132 states and 68824 transitions. [2022-10-17 11:04:50,904 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 49132 [2022-10-17 11:04:50,929 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 49132 [2022-10-17 11:04:50,929 INFO L73 IsDeterministic]: Start isDeterministic. Operand 49132 states and 68824 transitions. [2022-10-17 11:04:51,460 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 11:04:51,461 INFO L218 hiAutomatonCegarLoop]: Abstraction has 49132 states and 68824 transitions. [2022-10-17 11:04:51,499 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49132 states and 68824 transitions. [2022-10-17 11:04:51,758 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49132 to 49132. [2022-10-17 11:04:51,787 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 49132 states, 49132 states have (on average 1.4007978506879426) internal successors, (68824), 49131 states have internal predecessors, (68824), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:04:51,875 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49132 states to 49132 states and 68824 transitions. [2022-10-17 11:04:51,875 INFO L240 hiAutomatonCegarLoop]: Abstraction has 49132 states and 68824 transitions. [2022-10-17 11:04:51,875 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 11:04:51,876 INFO L428 stractBuchiCegarLoop]: Abstraction has 49132 states and 68824 transitions. [2022-10-17 11:04:51,876 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2022-10-17 11:04:51,876 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 49132 states and 68824 transitions. [2022-10-17 11:04:52,001 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 48733 [2022-10-17 11:04:52,001 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 11:04:52,002 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 11:04:52,003 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:04:52,003 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:04:52,004 INFO L748 eck$LassoCheckResult]: Stem: 784044#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 783990#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 783962#L1016 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 783934#L468 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 783395#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 783396#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 783745#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 783746#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 783662#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 783451#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 783452#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 783379#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 783380#L684 assume !(0 == ~M_E~0); 783882#L684-2 assume !(0 == ~T1_E~0); 783697#L689-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 783698#L694-1 assume !(0 == ~T3_E~0); 784039#L699-1 assume !(0 == ~T4_E~0); 784097#L704-1 assume !(0 == ~T5_E~0); 784096#L709-1 assume !(0 == ~T6_E~0); 784095#L714-1 assume !(0 == ~E_M~0); 784094#L719-1 assume !(0 == ~E_1~0); 784003#L724-1 assume !(0 == ~E_2~0); 784004#L729-1 assume !(0 == ~E_3~0); 783988#L734-1 assume !(0 == ~E_4~0); 783926#L739-1 assume !(0 == ~E_5~0); 783544#L744-1 assume !(0 == ~E_6~0); 783545#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 783853#L334 assume !(1 == ~m_pc~0); 784089#L334-2 is_master_triggered_~__retres1~0#1 := 0; 784088#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 784087#L346 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 783516#L849 assume !(0 != activate_threads_~tmp~1#1); 783517#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 783447#L353 assume !(1 == ~t1_pc~0); 783448#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 783914#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 783362#L365 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 783363#L857 assume !(0 != activate_threads_~tmp___0~0#1); 784083#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 783984#L372 assume !(1 == ~t2_pc~0); 783985#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 784082#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 784081#L384 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 784080#L865 assume !(0 != activate_threads_~tmp___1~0#1); 783300#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 783301#L391 assume !(1 == ~t3_pc~0); 783223#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 783224#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 783431#L403 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 783635#L873 assume !(0 != activate_threads_~tmp___2~0#1); 783845#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 784074#L410 assume !(1 == ~t4_pc~0); 783766#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 783767#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 783810#L422 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 784072#L881 assume !(0 != activate_threads_~tmp___3~0#1); 783529#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 783530#L429 assume !(1 == ~t5_pc~0); 783356#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 783357#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 784093#L441 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 783774#L889 assume !(0 != activate_threads_~tmp___4~0#1); 783775#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 783802#L448 assume !(1 == ~t6_pc~0); 784064#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 784063#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 784062#L460 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 783957#L897 assume !(0 != activate_threads_~tmp___5~0#1); 783958#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 784030#L762 assume !(1 == ~M_E~0); 783567#L762-2 assume !(1 == ~T1_E~0); 783568#L767-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 783965#L772-1 assume !(1 == ~T3_E~0); 783803#L777-1 assume !(1 == ~T4_E~0); 783677#L782-1 assume !(1 == ~T5_E~0); 783385#L787-1 assume !(1 == ~T6_E~0); 783383#L792-1 assume !(1 == ~E_M~0); 783384#L797-1 assume !(1 == ~E_1~0); 783417#L802-1 assume !(1 == ~E_2~0); 783641#L807-1 assume !(1 == ~E_3~0); 783642#L812-1 assume !(1 == ~E_4~0); 783922#L817-1 assume !(1 == ~E_5~0); 783700#L822-1 assume !(1 == ~E_6~0); 783701#L827-1 assume { :end_inline_reset_delta_events } true; 783935#L1053-2 [2022-10-17 11:04:52,004 INFO L750 eck$LassoCheckResult]: Loop: 783935#L1053-2 assume !false; 826692#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 826691#L659 assume !false; 826690#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 826687#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 826681#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 826680#L556 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 826677#L570 assume !(0 != eval_~tmp~0#1); 826676#L674 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 826675#L468-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 826674#L684-3 assume !(0 == ~M_E~0); 826673#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 826672#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 826670#L694-3 assume !(0 == ~T3_E~0); 826668#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 826666#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 826664#L709-3 assume !(0 == ~T6_E~0); 826662#L714-3 assume !(0 == ~E_M~0); 826660#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 826658#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 826656#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 826654#L734-3 assume !(0 == ~E_4~0); 826652#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 826650#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 826648#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 826646#L334-24 assume !(1 == ~m_pc~0); 826644#L334-26 is_master_triggered_~__retres1~0#1 := 0; 826642#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 826640#L346-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 826638#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 826636#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 826634#L353-24 assume !(1 == ~t1_pc~0); 826632#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 826630#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 826628#L365-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 826626#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 826624#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 826622#L372-24 assume 1 == ~t2_pc~0; 826618#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 826616#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 826614#L384-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 826612#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 826610#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 826608#L391-24 assume !(1 == ~t3_pc~0); 826606#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 826604#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 826602#L403-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 826600#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 826598#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 826596#L410-24 assume !(1 == ~t4_pc~0); 826594#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 826592#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 826590#L422-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 826588#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 826586#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 826582#L429-24 assume 1 == ~t5_pc~0; 826580#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 826581#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 826689#L441-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 826570#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 826568#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 826566#L448-24 assume !(1 == ~t6_pc~0); 826564#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 826562#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 826560#L460-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 826558#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 826556#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 826552#L762-3 assume !(1 == ~M_E~0); 826419#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 826550#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 826548#L772-3 assume !(1 == ~T3_E~0); 826546#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 826544#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 826542#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 826539#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 826537#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 826535#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 826533#L807-3 assume !(1 == ~E_3~0); 826531#L812-3 assume !(1 == ~E_4~0); 826529#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 826527#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 826525#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 826520#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 826513#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 826511#L556-1 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 826508#L1072 assume !(0 == start_simulation_~tmp~3#1); 826509#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 826724#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 826722#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 826720#L556-2 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 826718#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 826715#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 826713#L1035 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 826711#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 783935#L1053-2 [2022-10-17 11:04:52,005 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:04:52,005 INFO L85 PathProgramCache]: Analyzing trace with hash 2077618825, now seen corresponding path program 1 times [2022-10-17 11:04:52,005 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:04:52,005 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1064516398] [2022-10-17 11:04:52,006 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:04:52,006 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:04:52,016 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:04:52,057 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:04:52,057 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:04:52,057 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1064516398] [2022-10-17 11:04:52,057 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1064516398] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:04:52,057 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:04:52,058 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:04:52,058 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [133425946] [2022-10-17 11:04:52,058 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:04:52,058 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 11:04:52,059 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:04:52,059 INFO L85 PathProgramCache]: Analyzing trace with hash 305900766, now seen corresponding path program 1 times [2022-10-17 11:04:52,059 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:04:52,059 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1703314129] [2022-10-17 11:04:52,059 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:04:52,060 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:04:52,070 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:04:52,097 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:04:52,098 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:04:52,098 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1703314129] [2022-10-17 11:04:52,098 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1703314129] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:04:52,098 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:04:52,098 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:04:52,099 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2023593453] [2022-10-17 11:04:52,099 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:04:52,099 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 11:04:52,099 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 11:04:52,100 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-10-17 11:04:52,100 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-10-17 11:04:52,100 INFO L87 Difference]: Start difference. First operand 49132 states and 68824 transitions. cyclomatic complexity: 19708 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:04:52,348 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 11:04:52,349 INFO L93 Difference]: Finished difference Result 61110 states and 85570 transitions. [2022-10-17 11:04:52,349 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 61110 states and 85570 transitions. [2022-10-17 11:04:53,227 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 60637 [2022-10-17 11:04:53,407 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 61110 states to 61110 states and 85570 transitions. [2022-10-17 11:04:53,407 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 61110 [2022-10-17 11:04:53,439 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 61110 [2022-10-17 11:04:53,440 INFO L73 IsDeterministic]: Start isDeterministic. Operand 61110 states and 85570 transitions. [2022-10-17 11:04:53,468 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 11:04:53,468 INFO L218 hiAutomatonCegarLoop]: Abstraction has 61110 states and 85570 transitions. [2022-10-17 11:04:53,499 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61110 states and 85570 transitions. [2022-10-17 11:04:53,875 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61110 to 42180. [2022-10-17 11:04:53,902 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 42180 states, 42180 states have (on average 1.4033902323376009) internal successors, (59195), 42179 states have internal predecessors, (59195), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:04:53,988 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42180 states to 42180 states and 59195 transitions. [2022-10-17 11:04:53,988 INFO L240 hiAutomatonCegarLoop]: Abstraction has 42180 states and 59195 transitions. [2022-10-17 11:04:53,988 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-10-17 11:04:53,989 INFO L428 stractBuchiCegarLoop]: Abstraction has 42180 states and 59195 transitions. [2022-10-17 11:04:53,989 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2022-10-17 11:04:53,989 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 42180 states and 59195 transitions. [2022-10-17 11:04:54,109 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 41843 [2022-10-17 11:04:54,109 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 11:04:54,109 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 11:04:54,110 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:04:54,110 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:04:54,111 INFO L748 eck$LassoCheckResult]: Stem: 894278#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 894225#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 894205#L1016 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 894176#L468 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 893647#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 893648#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 893989#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 893990#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 893910#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 893701#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 893702#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 893631#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 893632#L684 assume !(0 == ~M_E~0); 894127#L684-2 assume !(0 == ~T1_E~0); 893945#L689-1 assume !(0 == ~T2_E~0); 893946#L694-1 assume !(0 == ~T3_E~0); 893943#L699-1 assume !(0 == ~T4_E~0); 893944#L704-1 assume !(0 == ~T5_E~0); 893897#L709-1 assume !(0 == ~T6_E~0); 893836#L714-1 assume !(0 == ~E_M~0); 893837#L719-1 assume !(0 == ~E_1~0); 894096#L724-1 assume !(0 == ~E_2~0); 893604#L729-1 assume !(0 == ~E_3~0); 893605#L734-1 assume !(0 == ~E_4~0); 894170#L739-1 assume !(0 == ~E_5~0); 893792#L744-1 assume !(0 == ~E_6~0); 893793#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 893565#L334 assume !(1 == ~m_pc~0); 893566#L334-2 is_master_triggered_~__retres1~0#1 := 0; 893887#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 893598#L346 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 893599#L849 assume !(0 != activate_threads_~tmp~1#1); 893764#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 893697#L353 assume !(1 == ~t1_pc~0); 893698#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 893993#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 893614#L365 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 893615#L857 assume !(0 != activate_threads_~tmp___0~0#1); 893651#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 893652#L372 assume !(1 == ~t2_pc~0); 893750#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 893749#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 893880#L384 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 894158#L865 assume !(0 != activate_threads_~tmp___1~0#1); 893552#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 893553#L391 assume !(1 == ~t3_pc~0); 893474#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 893475#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 893681#L403 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 893884#L873 assume !(0 != activate_threads_~tmp___2~0#1); 893769#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 893770#L410 assume !(1 == ~t4_pc~0); 894010#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 894011#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 894057#L422 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 894159#L881 assume !(0 != activate_threads_~tmp___3~0#1); 893777#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 893778#L429 assume !(1 == ~t5_pc~0); 893608#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 893609#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 893537#L441 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 893538#L889 assume !(0 != activate_threads_~tmp___4~0#1); 894022#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 893757#L448 assume !(1 == ~t6_pc~0); 893682#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 893683#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 894017#L460 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 894111#L897 assume !(0 != activate_threads_~tmp___5~0#1); 894199#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 894259#L762 assume !(1 == ~M_E~0); 893816#L762-2 assume !(1 == ~T1_E~0); 893817#L767-1 assume !(1 == ~T2_E~0); 894209#L772-1 assume !(1 == ~T3_E~0); 894048#L777-1 assume !(1 == ~T4_E~0); 893924#L782-1 assume !(1 == ~T5_E~0); 893637#L787-1 assume !(1 == ~T6_E~0); 893635#L792-1 assume !(1 == ~E_M~0); 893636#L797-1 assume !(1 == ~E_1~0); 893669#L802-1 assume !(1 == ~E_2~0); 893890#L807-1 assume !(1 == ~E_3~0); 893891#L812-1 assume !(1 == ~E_4~0); 894166#L817-1 assume !(1 == ~E_5~0); 893947#L822-1 assume !(1 == ~E_6~0); 893948#L827-1 assume { :end_inline_reset_delta_events } true; 894177#L1053-2 [2022-10-17 11:04:54,111 INFO L750 eck$LassoCheckResult]: Loop: 894177#L1053-2 assume !false; 924750#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 914959#L659 assume !false; 924729#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 924723#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 924715#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 924713#L556 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 924711#L570 assume !(0 != eval_~tmp~0#1); 924709#L674 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 924707#L468-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 924705#L684-3 assume !(0 == ~M_E~0); 924702#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 924700#L689-3 assume !(0 == ~T2_E~0); 924692#L694-3 assume !(0 == ~T3_E~0); 924686#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 923848#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 923846#L709-3 assume !(0 == ~T6_E~0); 923844#L714-3 assume !(0 == ~E_M~0); 923842#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 923840#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 923838#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 923836#L734-3 assume !(0 == ~E_4~0); 923834#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 923832#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 923830#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 923828#L334-24 assume !(1 == ~m_pc~0); 923826#L334-26 is_master_triggered_~__retres1~0#1 := 0; 923824#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 923820#L346-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 923818#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 923816#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 923814#L353-24 assume !(1 == ~t1_pc~0); 923811#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 923809#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 923384#L365-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 923383#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 923381#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 923379#L372-24 assume 1 == ~t2_pc~0; 923376#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 923374#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 923372#L384-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 923370#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 923368#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 923366#L391-24 assume !(1 == ~t3_pc~0); 923365#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 923363#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 923361#L403-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 923360#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 923359#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 923358#L410-24 assume !(1 == ~t4_pc~0); 923354#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 923352#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 923350#L422-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 923349#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 923348#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 923347#L429-24 assume 1 == ~t5_pc~0; 923346#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 923344#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 923342#L441-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 923339#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 923336#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 923334#L448-24 assume !(1 == ~t6_pc~0); 923332#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 923330#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 923328#L460-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 923325#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 923322#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 923320#L762-3 assume !(1 == ~M_E~0); 910006#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 923317#L767-3 assume !(1 == ~T2_E~0); 923315#L772-3 assume !(1 == ~T3_E~0); 923313#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 923310#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 923308#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 923306#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 923304#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 923302#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 922981#L807-3 assume !(1 == ~E_3~0); 900312#L812-3 assume !(1 == ~E_4~0); 900303#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 900300#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 900295#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 900296#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 913660#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 913658#L556-1 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 910453#L1072 assume !(0 == start_simulation_~tmp~3#1); 910454#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 924872#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 924871#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 924870#L556-2 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 924869#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 924868#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 924766#L1035 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 924763#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 894177#L1053-2 [2022-10-17 11:04:54,112 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:04:54,112 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 2 times [2022-10-17 11:04:54,112 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:04:54,112 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1947292979] [2022-10-17 11:04:54,113 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:04:54,113 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:04:54,126 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 11:04:54,127 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 11:04:54,135 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 11:04:54,165 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 11:04:54,166 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:04:54,166 INFO L85 PathProgramCache]: Analyzing trace with hash 2013207326, now seen corresponding path program 1 times [2022-10-17 11:04:54,166 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:04:54,166 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1636361699] [2022-10-17 11:04:54,166 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:04:54,167 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:04:54,178 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:04:54,206 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:04:54,207 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:04:54,207 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1636361699] [2022-10-17 11:04:54,207 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1636361699] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:04:54,207 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:04:54,208 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:04:54,208 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2112150933] [2022-10-17 11:04:54,208 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:04:54,208 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 11:04:54,209 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 11:04:54,209 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 11:04:54,209 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 11:04:54,209 INFO L87 Difference]: Start difference. First operand 42180 states and 59195 transitions. cyclomatic complexity: 17031 Second operand has 3 states, 3 states have (on average 31.333333333333332) internal successors, (94), 3 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:04:54,489 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 11:04:54,489 INFO L93 Difference]: Finished difference Result 66103 states and 92328 transitions. [2022-10-17 11:04:54,489 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 66103 states and 92328 transitions. [2022-10-17 11:04:55,156 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 65512 [2022-10-17 11:04:55,294 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 66103 states to 66103 states and 92328 transitions. [2022-10-17 11:04:55,295 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 66103 [2022-10-17 11:04:55,325 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 66103 [2022-10-17 11:04:55,325 INFO L73 IsDeterministic]: Start isDeterministic. Operand 66103 states and 92328 transitions. [2022-10-17 11:04:55,346 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 11:04:55,346 INFO L218 hiAutomatonCegarLoop]: Abstraction has 66103 states and 92328 transitions.