./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.07.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version dbf71c69 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_41aa0fa5-9bf3-4bd3-a25e-33627fdd9665/bin/uautomizer-J5u9QxTXDZ/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_41aa0fa5-9bf3-4bd3-a25e-33627fdd9665/bin/uautomizer-J5u9QxTXDZ/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_41aa0fa5-9bf3-4bd3-a25e-33627fdd9665/bin/uautomizer-J5u9QxTXDZ/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_41aa0fa5-9bf3-4bd3-a25e-33627fdd9665/bin/uautomizer-J5u9QxTXDZ/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.07.cil-2.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_41aa0fa5-9bf3-4bd3-a25e-33627fdd9665/bin/uautomizer-J5u9QxTXDZ/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_41aa0fa5-9bf3-4bd3-a25e-33627fdd9665/bin/uautomizer-J5u9QxTXDZ --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 32b030e5f1b46150870f8dd8e24821389f0ffe4175e43053767dc9109bffcf9b --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-dbf71c6-m [2022-10-17 10:57:20,062 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-10-17 10:57:20,069 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-10-17 10:57:20,133 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-10-17 10:57:20,134 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-10-17 10:57:20,140 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-10-17 10:57:20,143 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-10-17 10:57:20,148 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-10-17 10:57:20,152 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-10-17 10:57:20,158 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-10-17 10:57:20,160 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-10-17 10:57:20,163 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-10-17 10:57:20,164 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-10-17 10:57:20,167 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-10-17 10:57:20,169 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-10-17 10:57:20,172 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-10-17 10:57:20,175 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-10-17 10:57:20,176 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-10-17 10:57:20,179 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-10-17 10:57:20,191 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-10-17 10:57:20,193 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-10-17 10:57:20,195 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-10-17 10:57:20,199 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-10-17 10:57:20,201 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-10-17 10:57:20,213 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-10-17 10:57:20,214 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-10-17 10:57:20,214 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-10-17 10:57:20,216 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-10-17 10:57:20,217 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-10-17 10:57:20,220 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-10-17 10:57:20,221 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-10-17 10:57:20,222 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-10-17 10:57:20,225 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-10-17 10:57:20,226 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-10-17 10:57:20,228 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-10-17 10:57:20,228 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-10-17 10:57:20,229 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-10-17 10:57:20,229 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-10-17 10:57:20,230 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-10-17 10:57:20,231 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-10-17 10:57:20,232 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-10-17 10:57:20,233 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_41aa0fa5-9bf3-4bd3-a25e-33627fdd9665/bin/uautomizer-J5u9QxTXDZ/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-10-17 10:57:20,283 INFO L113 SettingsManager]: Loading preferences was successful [2022-10-17 10:57:20,284 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-10-17 10:57:20,284 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-10-17 10:57:20,285 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-10-17 10:57:20,286 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-10-17 10:57:20,287 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-10-17 10:57:20,287 INFO L138 SettingsManager]: * Use SBE=true [2022-10-17 10:57:20,287 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-10-17 10:57:20,288 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-10-17 10:57:20,288 INFO L138 SettingsManager]: * Use old map elimination=false [2022-10-17 10:57:20,289 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-10-17 10:57:20,289 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-10-17 10:57:20,290 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-10-17 10:57:20,290 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-10-17 10:57:20,290 INFO L138 SettingsManager]: * sizeof long=4 [2022-10-17 10:57:20,291 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-10-17 10:57:20,291 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-10-17 10:57:20,291 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-10-17 10:57:20,291 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-10-17 10:57:20,292 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-10-17 10:57:20,292 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-10-17 10:57:20,292 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-10-17 10:57:20,292 INFO L138 SettingsManager]: * sizeof long double=12 [2022-10-17 10:57:20,294 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-10-17 10:57:20,295 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-10-17 10:57:20,295 INFO L138 SettingsManager]: * Use constant arrays=true [2022-10-17 10:57:20,295 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-10-17 10:57:20,296 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-10-17 10:57:20,296 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-10-17 10:57:20,296 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-10-17 10:57:20,297 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-10-17 10:57:20,298 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-10-17 10:57:20,298 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_41aa0fa5-9bf3-4bd3-a25e-33627fdd9665/bin/uautomizer-J5u9QxTXDZ/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_41aa0fa5-9bf3-4bd3-a25e-33627fdd9665/bin/uautomizer-J5u9QxTXDZ Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 32b030e5f1b46150870f8dd8e24821389f0ffe4175e43053767dc9109bffcf9b [2022-10-17 10:57:20,591 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-10-17 10:57:20,626 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-10-17 10:57:20,629 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-10-17 10:57:20,631 INFO L271 PluginConnector]: Initializing CDTParser... [2022-10-17 10:57:20,632 INFO L275 PluginConnector]: CDTParser initialized [2022-10-17 10:57:20,633 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_41aa0fa5-9bf3-4bd3-a25e-33627fdd9665/bin/uautomizer-J5u9QxTXDZ/../../sv-benchmarks/c/systemc/token_ring.07.cil-2.c [2022-10-17 10:57:20,737 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_41aa0fa5-9bf3-4bd3-a25e-33627fdd9665/bin/uautomizer-J5u9QxTXDZ/data/cfc2669f5/04a84c0f184e4360b0e208df3f7886c5/FLAG6f5fc9653 [2022-10-17 10:57:21,348 INFO L306 CDTParser]: Found 1 translation units. [2022-10-17 10:57:21,348 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_41aa0fa5-9bf3-4bd3-a25e-33627fdd9665/sv-benchmarks/c/systemc/token_ring.07.cil-2.c [2022-10-17 10:57:21,375 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_41aa0fa5-9bf3-4bd3-a25e-33627fdd9665/bin/uautomizer-J5u9QxTXDZ/data/cfc2669f5/04a84c0f184e4360b0e208df3f7886c5/FLAG6f5fc9653 [2022-10-17 10:57:21,636 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_41aa0fa5-9bf3-4bd3-a25e-33627fdd9665/bin/uautomizer-J5u9QxTXDZ/data/cfc2669f5/04a84c0f184e4360b0e208df3f7886c5 [2022-10-17 10:57:21,639 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-10-17 10:57:21,640 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-10-17 10:57:21,645 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-10-17 10:57:21,646 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-10-17 10:57:21,650 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-10-17 10:57:21,652 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.10 10:57:21" (1/1) ... [2022-10-17 10:57:21,654 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5d65aab and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:57:21, skipping insertion in model container [2022-10-17 10:57:21,655 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.10 10:57:21" (1/1) ... [2022-10-17 10:57:21,664 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-10-17 10:57:21,739 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-10-17 10:57:21,989 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_41aa0fa5-9bf3-4bd3-a25e-33627fdd9665/sv-benchmarks/c/systemc/token_ring.07.cil-2.c[671,684] [2022-10-17 10:57:22,203 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-10-17 10:57:22,223 INFO L203 MainTranslator]: Completed pre-run [2022-10-17 10:57:22,245 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_41aa0fa5-9bf3-4bd3-a25e-33627fdd9665/sv-benchmarks/c/systemc/token_ring.07.cil-2.c[671,684] [2022-10-17 10:57:22,330 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-10-17 10:57:22,357 INFO L208 MainTranslator]: Completed translation [2022-10-17 10:57:22,358 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:57:22 WrapperNode [2022-10-17 10:57:22,358 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-10-17 10:57:22,359 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-10-17 10:57:22,360 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-10-17 10:57:22,360 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-10-17 10:57:22,369 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:57:22" (1/1) ... [2022-10-17 10:57:22,383 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:57:22" (1/1) ... [2022-10-17 10:57:22,513 INFO L138 Inliner]: procedures = 42, calls = 53, calls flagged for inlining = 48, calls inlined = 135, statements flattened = 2001 [2022-10-17 10:57:22,514 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-10-17 10:57:22,515 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-10-17 10:57:22,515 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-10-17 10:57:22,515 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-10-17 10:57:22,537 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:57:22" (1/1) ... [2022-10-17 10:57:22,538 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:57:22" (1/1) ... [2022-10-17 10:57:22,547 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:57:22" (1/1) ... [2022-10-17 10:57:22,554 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:57:22" (1/1) ... [2022-10-17 10:57:22,602 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:57:22" (1/1) ... [2022-10-17 10:57:22,658 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:57:22" (1/1) ... [2022-10-17 10:57:22,668 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:57:22" (1/1) ... [2022-10-17 10:57:22,682 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:57:22" (1/1) ... [2022-10-17 10:57:22,693 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-10-17 10:57:22,695 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-10-17 10:57:22,695 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-10-17 10:57:22,696 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-10-17 10:57:22,701 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:57:22" (1/1) ... [2022-10-17 10:57:22,711 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:57:22,729 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_41aa0fa5-9bf3-4bd3-a25e-33627fdd9665/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:57:22,743 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_41aa0fa5-9bf3-4bd3-a25e-33627fdd9665/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:57:22,751 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_41aa0fa5-9bf3-4bd3-a25e-33627fdd9665/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-10-17 10:57:22,793 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-10-17 10:57:22,793 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-10-17 10:57:22,793 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-10-17 10:57:22,793 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-10-17 10:57:22,909 INFO L235 CfgBuilder]: Building ICFG [2022-10-17 10:57:22,912 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-10-17 10:57:24,784 INFO L276 CfgBuilder]: Performing block encoding [2022-10-17 10:57:24,812 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-10-17 10:57:24,814 INFO L300 CfgBuilder]: Removed 10 assume(true) statements. [2022-10-17 10:57:24,819 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 17.10 10:57:24 BoogieIcfgContainer [2022-10-17 10:57:24,819 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-10-17 10:57:24,822 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-10-17 10:57:24,822 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-10-17 10:57:24,827 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-10-17 10:57:24,828 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-10-17 10:57:24,828 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 17.10 10:57:21" (1/3) ... [2022-10-17 10:57:24,836 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@5a20562f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.10 10:57:24, skipping insertion in model container [2022-10-17 10:57:24,836 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-10-17 10:57:24,837 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:57:22" (2/3) ... [2022-10-17 10:57:24,837 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@5a20562f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.10 10:57:24, skipping insertion in model container [2022-10-17 10:57:24,837 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-10-17 10:57:24,837 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 17.10 10:57:24" (3/3) ... [2022-10-17 10:57:24,839 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.07.cil-2.c [2022-10-17 10:57:24,941 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-10-17 10:57:24,941 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-10-17 10:57:24,941 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-10-17 10:57:24,942 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-10-17 10:57:24,942 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-10-17 10:57:24,942 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-10-17 10:57:24,942 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-10-17 10:57:24,942 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-10-17 10:57:24,953 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 843 states, 842 states have (on average 1.520190023752969) internal successors, (1280), 842 states have internal predecessors, (1280), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:57:25,039 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 736 [2022-10-17 10:57:25,039 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:57:25,039 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:57:25,065 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:57:25,065 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:57:25,065 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-10-17 10:57:25,068 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 843 states, 842 states have (on average 1.520190023752969) internal successors, (1280), 842 states have internal predecessors, (1280), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:57:25,114 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 736 [2022-10-17 10:57:25,114 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:57:25,114 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:57:25,123 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:57:25,123 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:57:25,135 INFO L748 eck$LassoCheckResult]: Stem: 410#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 769#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 43#L1153true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 682#L541true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 789#L548true assume !(1 == ~m_i~0);~m_st~0 := 2; 211#L548-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 388#L553-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 287#L558-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 746#L563-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 156#L568-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 41#L573-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 776#L578-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 131#L583-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 491#L781true assume !(0 == ~M_E~0); 807#L781-2true assume !(0 == ~T1_E~0); 835#L786-1true assume !(0 == ~T2_E~0); 22#L791-1true assume !(0 == ~T3_E~0); 374#L796-1true assume !(0 == ~T4_E~0); 345#L801-1true assume !(0 == ~T5_E~0); 376#L806-1true assume 0 == ~T6_E~0;~T6_E~0 := 1; 752#L811-1true assume !(0 == ~T7_E~0); 135#L816-1true assume !(0 == ~E_M~0); 613#L821-1true assume !(0 == ~E_1~0); 36#L826-1true assume !(0 == ~E_2~0); 344#L831-1true assume !(0 == ~E_3~0); 209#L836-1true assume !(0 == ~E_4~0); 493#L841-1true assume !(0 == ~E_5~0); 109#L846-1true assume 0 == ~E_6~0;~E_6~0 := 1; 782#L851-1true assume !(0 == ~E_7~0); 121#L856-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 633#L388true assume !(1 == ~m_pc~0); 118#L388-2true is_master_triggered_~__retres1~0#1 := 0; 463#L399true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 673#L400true activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 45#L967true assume !(0 != activate_threads_~tmp~1#1); 753#L967-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11#L407true assume 1 == ~t1_pc~0; 400#L408true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13#L418true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2#L419true activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 603#L975true assume !(0 != activate_threads_~tmp___0~0#1); 627#L975-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 186#L426true assume !(1 == ~t2_pc~0); 643#L426-2true is_transmit2_triggered_~__retres1~2#1 := 0; 737#L437true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 818#L438true activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 729#L983true assume !(0 != activate_threads_~tmp___1~0#1); 836#L983-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 237#L445true assume 1 == ~t3_pc~0; 827#L446true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 501#L456true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 119#L457true activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 424#L991true assume !(0 != activate_threads_~tmp___2~0#1); 497#L991-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 401#L464true assume !(1 == ~t4_pc~0); 123#L464-2true is_transmit4_triggered_~__retres1~4#1 := 0; 54#L475true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 243#L476true activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 834#L999true assume !(0 != activate_threads_~tmp___3~0#1); 221#L999-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 397#L483true assume 1 == ~t5_pc~0; 721#L484true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 577#L494true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 326#L495true activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 681#L1007true assume !(0 != activate_threads_~tmp___4~0#1); 176#L1007-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 441#L502true assume 1 == ~t6_pc~0; 372#L503true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 69#L513true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 471#L514true activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 312#L1015true assume !(0 != activate_threads_~tmp___5~0#1); 544#L1015-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 691#L521true assume !(1 == ~t7_pc~0); 646#L521-2true is_transmit7_triggered_~__retres1~7#1 := 0; 42#L532true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 97#L533true activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 593#L1023true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 554#L1023-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 449#L869true assume !(1 == ~M_E~0); 217#L869-2true assume !(1 == ~T1_E~0); 722#L874-1true assume !(1 == ~T2_E~0); 666#L879-1true assume !(1 == ~T3_E~0); 267#L884-1true assume 1 == ~T4_E~0;~T4_E~0 := 2; 6#L889-1true assume !(1 == ~T5_E~0); 139#L894-1true assume !(1 == ~T6_E~0); 824#L899-1true assume !(1 == ~T7_E~0); 415#L904-1true assume !(1 == ~E_M~0); 231#L909-1true assume !(1 == ~E_1~0); 360#L914-1true assume !(1 == ~E_2~0); 381#L919-1true assume !(1 == ~E_3~0); 185#L924-1true assume 1 == ~E_4~0;~E_4~0 := 2; 89#L929-1true assume !(1 == ~E_5~0); 686#L934-1true assume !(1 == ~E_6~0); 219#L939-1true assume !(1 == ~E_7~0); 542#L944-1true assume { :end_inline_reset_delta_events } true; 538#L1190-2true [2022-10-17 10:57:25,138 INFO L750 eck$LassoCheckResult]: Loop: 538#L1190-2true assume !false; 136#L1191true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 275#L756true assume !true; 822#L771true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 270#L541-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 385#L781-3true assume 0 == ~M_E~0;~M_E~0 := 1; 60#L781-5true assume !(0 == ~T1_E~0); 250#L786-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 298#L791-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 34#L796-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 617#L801-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 177#L806-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 293#L811-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 483#L816-3true assume 0 == ~E_M~0;~E_M~0 := 1; 644#L821-3true assume !(0 == ~E_1~0); 764#L826-3true assume 0 == ~E_2~0;~E_2~0 := 1; 421#L831-3true assume 0 == ~E_3~0;~E_3~0 := 1; 659#L836-3true assume 0 == ~E_4~0;~E_4~0 := 1; 114#L841-3true assume 0 == ~E_5~0;~E_5~0 := 1; 592#L846-3true assume 0 == ~E_6~0;~E_6~0 := 1; 311#L851-3true assume 0 == ~E_7~0;~E_7~0 := 1; 57#L856-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 745#L388-27true assume !(1 == ~m_pc~0); 792#L388-29true is_master_triggered_~__retres1~0#1 := 0; 760#L399-9true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 553#L400-9true activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 689#L967-27true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 158#L967-29true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 439#L407-27true assume 1 == ~t1_pc~0; 425#L408-9true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 525#L418-9true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 302#L419-9true activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 467#L975-27true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 328#L975-29true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 111#L426-27true assume 1 == ~t2_pc~0; 670#L427-9true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 115#L437-9true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 570#L438-9true activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 688#L983-27true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 588#L983-29true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 290#L445-27true assume 1 == ~t3_pc~0; 273#L446-9true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 32#L456-9true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 274#L457-9true activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 844#L991-27true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 365#L991-29true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 172#L464-27true assume 1 == ~t4_pc~0; 470#L465-9true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 63#L475-9true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 438#L476-9true activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 294#L999-27true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 107#L999-29true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 779#L483-27true assume !(1 == ~t5_pc~0); 571#L483-29true is_transmit5_triggered_~__retres1~5#1 := 0; 58#L494-9true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 624#L495-9true activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 535#L1007-27true assume !(0 != activate_threads_~tmp___4~0#1); 810#L1007-29true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 698#L502-27true assume !(1 == ~t6_pc~0); 308#L502-29true is_transmit6_triggered_~__retres1~6#1 := 0; 687#L513-9true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 612#L514-9true activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 444#L1015-27true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 734#L1015-29true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7#L521-27true assume !(1 == ~t7_pc~0); 817#L521-29true is_transmit7_triggered_~__retres1~7#1 := 0; 770#L532-9true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 283#L533-9true activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29#L1023-27true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 320#L1023-29true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 658#L869-3true assume 1 == ~M_E~0;~M_E~0 := 2; 442#L869-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 249#L874-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 286#L879-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 310#L884-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 281#L889-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 83#L894-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 411#L899-3true assume !(1 == ~T7_E~0); 99#L904-3true assume 1 == ~E_M~0;~E_M~0 := 2; 264#L909-3true assume 1 == ~E_1~0;~E_1~0 := 2; 70#L914-3true assume 1 == ~E_2~0;~E_2~0 := 2; 94#L919-3true assume 1 == ~E_3~0;~E_3~0 := 2; 604#L924-3true assume 1 == ~E_4~0;~E_4~0 := 2; 430#L929-3true assume 1 == ~E_5~0;~E_5~0 := 2; 362#L934-3true assume 1 == ~E_6~0;~E_6~0 := 2; 549#L939-3true assume !(1 == ~E_7~0); 103#L944-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 587#L596-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 652#L638-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 254#L639-1true start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 775#L1209true assume !(0 == start_simulation_~tmp~3#1); 306#L1209-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 292#L596-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 529#L638-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 333#L639-2true stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 595#L1164true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 26#L1171true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 155#L1172true start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 129#L1222true assume !(0 != start_simulation_~tmp___0~1#1); 538#L1190-2true [2022-10-17 10:57:25,146 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:57:25,146 INFO L85 PathProgramCache]: Analyzing trace with hash 1617538625, now seen corresponding path program 1 times [2022-10-17 10:57:25,157 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:57:25,158 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [591069585] [2022-10-17 10:57:25,158 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:57:25,159 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:57:25,288 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:57:25,496 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:57:25,496 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:57:25,498 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [591069585] [2022-10-17 10:57:25,500 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [591069585] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:57:25,500 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:57:25,501 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:57:25,503 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [325889604] [2022-10-17 10:57:25,504 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:57:25,511 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:57:25,515 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:57:25,515 INFO L85 PathProgramCache]: Analyzing trace with hash -1447158193, now seen corresponding path program 1 times [2022-10-17 10:57:25,516 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:57:25,516 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1362277448] [2022-10-17 10:57:25,517 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:57:25,518 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:57:25,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:57:25,597 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:57:25,598 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:57:25,598 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1362277448] [2022-10-17 10:57:25,598 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1362277448] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:57:25,599 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:57:25,599 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-10-17 10:57:25,599 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [309433191] [2022-10-17 10:57:25,599 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:57:25,601 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:57:25,602 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:57:25,640 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:57:25,641 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:57:25,646 INFO L87 Difference]: Start difference. First operand has 843 states, 842 states have (on average 1.520190023752969) internal successors, (1280), 842 states have internal predecessors, (1280), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:57:25,746 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:57:25,747 INFO L93 Difference]: Finished difference Result 841 states and 1255 transitions. [2022-10-17 10:57:25,748 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 841 states and 1255 transitions. [2022-10-17 10:57:25,762 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 732 [2022-10-17 10:57:25,779 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 841 states to 835 states and 1249 transitions. [2022-10-17 10:57:25,781 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 835 [2022-10-17 10:57:25,784 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 835 [2022-10-17 10:57:25,785 INFO L73 IsDeterministic]: Start isDeterministic. Operand 835 states and 1249 transitions. [2022-10-17 10:57:25,792 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:57:25,792 INFO L218 hiAutomatonCegarLoop]: Abstraction has 835 states and 1249 transitions. [2022-10-17 10:57:25,818 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 835 states and 1249 transitions. [2022-10-17 10:57:25,887 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 835 to 835. [2022-10-17 10:57:25,895 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 835 states, 835 states have (on average 1.495808383233533) internal successors, (1249), 834 states have internal predecessors, (1249), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:57:25,904 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 835 states to 835 states and 1249 transitions. [2022-10-17 10:57:25,906 INFO L240 hiAutomatonCegarLoop]: Abstraction has 835 states and 1249 transitions. [2022-10-17 10:57:25,907 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:57:25,915 INFO L428 stractBuchiCegarLoop]: Abstraction has 835 states and 1249 transitions. [2022-10-17 10:57:25,916 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-10-17 10:57:25,916 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 835 states and 1249 transitions. [2022-10-17 10:57:25,927 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 732 [2022-10-17 10:57:25,928 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:57:25,928 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:57:25,937 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:57:25,937 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:57:25,939 INFO L748 eck$LassoCheckResult]: Stem: 2328#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 2329#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1782#L1153 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1783#L541 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2503#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 2078#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2079#L553-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 2198#L558-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2199#L563-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1991#L568-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1778#L573-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1779#L578-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 1948#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1949#L781 assume !(0 == ~M_E~0); 2403#L781-2 assume !(0 == ~T1_E~0); 2526#L786-1 assume !(0 == ~T2_E~0); 1739#L791-1 assume !(0 == ~T3_E~0); 1740#L796-1 assume !(0 == ~T4_E~0); 2265#L801-1 assume !(0 == ~T5_E~0); 2266#L806-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2292#L811-1 assume !(0 == ~T7_E~0); 1957#L816-1 assume !(0 == ~E_M~0); 1958#L821-1 assume !(0 == ~E_1~0); 1767#L826-1 assume !(0 == ~E_2~0); 1768#L831-1 assume !(0 == ~E_3~0); 2075#L836-1 assume !(0 == ~E_4~0); 2076#L841-1 assume !(0 == ~E_5~0); 1910#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 1911#L851-1 assume !(0 == ~E_7~0); 1933#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1934#L388 assume !(1 == ~m_pc~0); 1927#L388-2 is_master_triggered_~__retres1~0#1 := 0; 1928#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2376#L400 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1786#L967 assume !(0 != activate_threads_~tmp~1#1); 1787#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1714#L407 assume 1 == ~t1_pc~0; 1715#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1719#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1693#L419 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1694#L975 assume !(0 != activate_threads_~tmp___0~0#1); 2474#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2037#L426 assume !(1 == ~t2_pc~0); 2038#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2489#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2518#L438 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2516#L983 assume !(0 != activate_threads_~tmp___1~0#1); 2517#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2117#L445 assume 1 == ~t3_pc~0; 2118#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2407#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1929#L457 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1930#L991 assume !(0 != activate_threads_~tmp___2~0#1); 2344#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2315#L464 assume !(1 == ~t4_pc~0); 1936#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1807#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1808#L476 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2128#L999 assume !(0 != activate_threads_~tmp___3~0#1); 2093#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2094#L483 assume 1 == ~t5_pc~0; 2312#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2454#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2247#L495 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2248#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 2021#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2022#L502 assume 1 == ~t6_pc~0; 2289#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1838#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1839#L514 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2231#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 2232#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2431#L521 assume !(1 == ~t7_pc~0); 2470#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1780#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1781#L533 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1888#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2438#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2365#L869 assume !(1 == ~M_E~0); 2086#L869-2 assume !(1 == ~T1_E~0); 2087#L874-1 assume !(1 == ~T2_E~0); 2499#L879-1 assume !(1 == ~T3_E~0); 2167#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1702#L889-1 assume !(1 == ~T5_E~0); 1703#L894-1 assume !(1 == ~T6_E~0); 1964#L899-1 assume !(1 == ~T7_E~0); 2332#L904-1 assume !(1 == ~E_M~0); 2109#L909-1 assume !(1 == ~E_1~0); 2110#L914-1 assume !(1 == ~E_2~0); 2279#L919-1 assume !(1 == ~E_3~0); 2036#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 1876#L929-1 assume !(1 == ~E_5~0); 1877#L934-1 assume !(1 == ~E_6~0); 2089#L939-1 assume !(1 == ~E_7~0); 2090#L944-1 assume { :end_inline_reset_delta_events } true; 1946#L1190-2 [2022-10-17 10:57:25,942 INFO L750 eck$LassoCheckResult]: Loop: 1946#L1190-2 assume !false; 1959#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1960#L756 assume !false; 2182#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2522#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1800#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2308#L639 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2131#L653 assume !(0 != eval_~tmp~0#1); 2133#L771 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2173#L541-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2174#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1819#L781-5 assume !(0 == ~T1_E~0); 1820#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2140#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1763#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1764#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2023#L806-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2024#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2206#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2393#L821-3 assume !(0 == ~E_1~0); 2490#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2339#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2340#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1920#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1921#L846-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2230#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1814#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1815#L388-27 assume 1 == ~m_pc~0; 2465#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2467#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2436#L400-9 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2437#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1994#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1995#L407-27 assume 1 == ~t1_pc~0; 2345#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2346#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2218#L419-9 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2219#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2250#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1914#L426-27 assume !(1 == ~t2_pc~0); 1915#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 1925#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1926#L438-9 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2450#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2463#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2201#L445-27 assume 1 == ~t3_pc~0; 2179#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1760#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1761#L457-9 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2181#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2284#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2015#L464-27 assume 1 == ~t4_pc~0; 2016#L465-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1759#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1826#L476-9 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2207#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1906#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1907#L483-27 assume 1 == ~t5_pc~0; 2412#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1816#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1817#L495-9 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2426#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 2427#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2506#L502-27 assume !(1 == ~t6_pc~0); 2226#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 2227#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2476#L514-9 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2362#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2363#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1704#L521-27 assume !(1 == ~t7_pc~0); 1705#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 2047#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2194#L533-9 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1754#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1755#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2242#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2359#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2138#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2139#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2197#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2193#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1864#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1865#L899-3 assume !(1 == ~T7_E~0); 1892#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1893#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1840#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1841#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1884#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2351#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2280#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2281#L939-3 assume !(1 == ~E_7~0); 1899#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1900#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1721#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2147#L639-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 2148#L1209 assume !(0 == start_simulation_~tmp~3#1); 2222#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2205#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1857#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2253#L639-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 2254#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1748#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1749#L1172 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1945#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 1946#L1190-2 [2022-10-17 10:57:25,943 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:57:25,944 INFO L85 PathProgramCache]: Analyzing trace with hash -736846657, now seen corresponding path program 1 times [2022-10-17 10:57:25,944 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:57:25,945 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [57780831] [2022-10-17 10:57:25,946 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:57:25,946 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:57:25,997 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:57:26,158 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:57:26,160 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:57:26,162 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [57780831] [2022-10-17 10:57:26,163 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [57780831] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:57:26,164 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:57:26,165 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:57:26,166 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1655680577] [2022-10-17 10:57:26,166 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:57:26,167 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:57:26,169 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:57:26,170 INFO L85 PathProgramCache]: Analyzing trace with hash -350291807, now seen corresponding path program 1 times [2022-10-17 10:57:26,171 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:57:26,172 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1361989587] [2022-10-17 10:57:26,172 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:57:26,173 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:57:26,239 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:57:26,406 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:57:26,406 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:57:26,406 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1361989587] [2022-10-17 10:57:26,407 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1361989587] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:57:26,407 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:57:26,407 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:57:26,408 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1117664523] [2022-10-17 10:57:26,408 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:57:26,409 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:57:26,413 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:57:26,414 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:57:26,414 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:57:26,415 INFO L87 Difference]: Start difference. First operand 835 states and 1249 transitions. cyclomatic complexity: 415 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:57:26,446 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:57:26,447 INFO L93 Difference]: Finished difference Result 835 states and 1248 transitions. [2022-10-17 10:57:26,447 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 835 states and 1248 transitions. [2022-10-17 10:57:26,464 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 732 [2022-10-17 10:57:26,474 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 835 states to 835 states and 1248 transitions. [2022-10-17 10:57:26,475 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 835 [2022-10-17 10:57:26,476 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 835 [2022-10-17 10:57:26,477 INFO L73 IsDeterministic]: Start isDeterministic. Operand 835 states and 1248 transitions. [2022-10-17 10:57:26,479 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:57:26,479 INFO L218 hiAutomatonCegarLoop]: Abstraction has 835 states and 1248 transitions. [2022-10-17 10:57:26,482 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 835 states and 1248 transitions. [2022-10-17 10:57:26,508 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 835 to 835. [2022-10-17 10:57:26,510 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 835 states, 835 states have (on average 1.4946107784431137) internal successors, (1248), 834 states have internal predecessors, (1248), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:57:26,516 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 835 states to 835 states and 1248 transitions. [2022-10-17 10:57:26,517 INFO L240 hiAutomatonCegarLoop]: Abstraction has 835 states and 1248 transitions. [2022-10-17 10:57:26,517 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:57:26,518 INFO L428 stractBuchiCegarLoop]: Abstraction has 835 states and 1248 transitions. [2022-10-17 10:57:26,518 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-10-17 10:57:26,519 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 835 states and 1248 transitions. [2022-10-17 10:57:26,526 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 732 [2022-10-17 10:57:26,527 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:57:26,527 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:57:26,531 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:57:26,531 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:57:26,534 INFO L748 eck$LassoCheckResult]: Stem: 4005#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 4006#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 3459#L1153 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3460#L541 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4180#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 3755#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3756#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3875#L558-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3876#L563-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3668#L568-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3455#L573-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3456#L578-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3625#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3626#L781 assume !(0 == ~M_E~0); 4080#L781-2 assume !(0 == ~T1_E~0); 4203#L786-1 assume !(0 == ~T2_E~0); 3416#L791-1 assume !(0 == ~T3_E~0); 3417#L796-1 assume !(0 == ~T4_E~0); 3942#L801-1 assume !(0 == ~T5_E~0); 3943#L806-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3969#L811-1 assume !(0 == ~T7_E~0); 3634#L816-1 assume !(0 == ~E_M~0); 3635#L821-1 assume !(0 == ~E_1~0); 3444#L826-1 assume !(0 == ~E_2~0); 3445#L831-1 assume !(0 == ~E_3~0); 3752#L836-1 assume !(0 == ~E_4~0); 3753#L841-1 assume !(0 == ~E_5~0); 3587#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 3588#L851-1 assume !(0 == ~E_7~0); 3610#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3611#L388 assume !(1 == ~m_pc~0); 3604#L388-2 is_master_triggered_~__retres1~0#1 := 0; 3605#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4053#L400 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3463#L967 assume !(0 != activate_threads_~tmp~1#1); 3464#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3391#L407 assume 1 == ~t1_pc~0; 3392#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3396#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3370#L419 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3371#L975 assume !(0 != activate_threads_~tmp___0~0#1); 4151#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3714#L426 assume !(1 == ~t2_pc~0); 3715#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4166#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4195#L438 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4193#L983 assume !(0 != activate_threads_~tmp___1~0#1); 4194#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3794#L445 assume 1 == ~t3_pc~0; 3795#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4084#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3606#L457 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3607#L991 assume !(0 != activate_threads_~tmp___2~0#1); 4021#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3992#L464 assume !(1 == ~t4_pc~0); 3613#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3484#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3485#L476 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3805#L999 assume !(0 != activate_threads_~tmp___3~0#1); 3770#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3771#L483 assume 1 == ~t5_pc~0; 3989#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4131#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3924#L495 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3925#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 3698#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3699#L502 assume 1 == ~t6_pc~0; 3966#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3515#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3516#L514 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3908#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 3909#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4108#L521 assume !(1 == ~t7_pc~0); 4147#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 3457#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3458#L533 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3565#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4115#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4042#L869 assume !(1 == ~M_E~0); 3763#L869-2 assume !(1 == ~T1_E~0); 3764#L874-1 assume !(1 == ~T2_E~0); 4176#L879-1 assume !(1 == ~T3_E~0); 3844#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3379#L889-1 assume !(1 == ~T5_E~0); 3380#L894-1 assume !(1 == ~T6_E~0); 3641#L899-1 assume !(1 == ~T7_E~0); 4009#L904-1 assume !(1 == ~E_M~0); 3786#L909-1 assume !(1 == ~E_1~0); 3787#L914-1 assume !(1 == ~E_2~0); 3956#L919-1 assume !(1 == ~E_3~0); 3713#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 3553#L929-1 assume !(1 == ~E_5~0); 3554#L934-1 assume !(1 == ~E_6~0); 3766#L939-1 assume !(1 == ~E_7~0); 3767#L944-1 assume { :end_inline_reset_delta_events } true; 3623#L1190-2 [2022-10-17 10:57:26,534 INFO L750 eck$LassoCheckResult]: Loop: 3623#L1190-2 assume !false; 3636#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3637#L756 assume !false; 3859#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 4199#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3477#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3985#L639 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3808#L653 assume !(0 != eval_~tmp~0#1); 3810#L771 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3850#L541-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3851#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3496#L781-5 assume !(0 == ~T1_E~0); 3497#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3817#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3440#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3441#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3700#L806-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3701#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3883#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4070#L821-3 assume !(0 == ~E_1~0); 4167#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4016#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4017#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3597#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3598#L846-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3907#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3491#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3492#L388-27 assume 1 == ~m_pc~0; 4142#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4144#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4113#L400-9 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4114#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3671#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3672#L407-27 assume 1 == ~t1_pc~0; 4022#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4023#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3895#L419-9 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3896#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3927#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3591#L426-27 assume !(1 == ~t2_pc~0); 3592#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 3602#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3603#L438-9 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4127#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4140#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3878#L445-27 assume 1 == ~t3_pc~0; 3856#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3437#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3438#L457-9 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3858#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3961#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3692#L464-27 assume !(1 == ~t4_pc~0); 3435#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 3436#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3503#L476-9 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3884#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3583#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3584#L483-27 assume 1 == ~t5_pc~0; 4089#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3493#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3494#L495-9 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4103#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 4104#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4183#L502-27 assume 1 == ~t6_pc~0; 4184#L503-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3904#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4153#L514-9 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4039#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4040#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3381#L521-27 assume !(1 == ~t7_pc~0); 3382#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 3724#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3871#L533-9 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3431#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3432#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3919#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4036#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3815#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3816#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3874#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3870#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3541#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3542#L899-3 assume !(1 == ~T7_E~0); 3569#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3570#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3517#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3518#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3561#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4028#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3957#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3958#L939-3 assume !(1 == ~E_7~0); 3576#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 3577#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3398#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3824#L639-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 3825#L1209 assume !(0 == start_simulation_~tmp~3#1); 3899#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 3882#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3534#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3930#L639-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 3931#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3425#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3426#L1172 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 3622#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 3623#L1190-2 [2022-10-17 10:57:26,536 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:57:26,537 INFO L85 PathProgramCache]: Analyzing trace with hash 33886909, now seen corresponding path program 1 times [2022-10-17 10:57:26,537 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:57:26,537 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1086284487] [2022-10-17 10:57:26,538 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:57:26,538 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:57:26,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:57:26,660 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:57:26,661 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:57:26,661 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1086284487] [2022-10-17 10:57:26,661 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1086284487] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:57:26,662 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:57:26,662 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:57:26,662 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1880616044] [2022-10-17 10:57:26,663 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:57:26,663 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:57:26,664 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:57:26,664 INFO L85 PathProgramCache]: Analyzing trace with hash -138895583, now seen corresponding path program 1 times [2022-10-17 10:57:26,664 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:57:26,665 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [440068289] [2022-10-17 10:57:26,665 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:57:26,665 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:57:26,723 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:57:26,792 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:57:26,793 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:57:26,794 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [440068289] [2022-10-17 10:57:26,794 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [440068289] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:57:26,795 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:57:26,795 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:57:26,795 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2086271459] [2022-10-17 10:57:26,796 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:57:26,797 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:57:26,797 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:57:26,798 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:57:26,798 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:57:26,799 INFO L87 Difference]: Start difference. First operand 835 states and 1248 transitions. cyclomatic complexity: 414 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:57:26,824 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:57:26,824 INFO L93 Difference]: Finished difference Result 835 states and 1247 transitions. [2022-10-17 10:57:26,824 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 835 states and 1247 transitions. [2022-10-17 10:57:26,836 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 732 [2022-10-17 10:57:26,846 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 835 states to 835 states and 1247 transitions. [2022-10-17 10:57:26,847 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 835 [2022-10-17 10:57:26,848 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 835 [2022-10-17 10:57:26,848 INFO L73 IsDeterministic]: Start isDeterministic. Operand 835 states and 1247 transitions. [2022-10-17 10:57:26,850 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:57:26,850 INFO L218 hiAutomatonCegarLoop]: Abstraction has 835 states and 1247 transitions. [2022-10-17 10:57:26,853 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 835 states and 1247 transitions. [2022-10-17 10:57:26,868 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 835 to 835. [2022-10-17 10:57:26,871 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 835 states, 835 states have (on average 1.4934131736526945) internal successors, (1247), 834 states have internal predecessors, (1247), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:57:26,876 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 835 states to 835 states and 1247 transitions. [2022-10-17 10:57:26,876 INFO L240 hiAutomatonCegarLoop]: Abstraction has 835 states and 1247 transitions. [2022-10-17 10:57:26,877 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:57:26,879 INFO L428 stractBuchiCegarLoop]: Abstraction has 835 states and 1247 transitions. [2022-10-17 10:57:26,880 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-10-17 10:57:26,880 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 835 states and 1247 transitions. [2022-10-17 10:57:26,887 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 732 [2022-10-17 10:57:26,888 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:57:26,888 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:57:26,897 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:57:26,897 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:57:26,898 INFO L748 eck$LassoCheckResult]: Stem: 5682#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 5683#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 5136#L1153 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5137#L541 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5857#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 5432#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5433#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5552#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5553#L563-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5345#L568-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5132#L573-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5133#L578-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5302#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5303#L781 assume !(0 == ~M_E~0); 5757#L781-2 assume !(0 == ~T1_E~0); 5880#L786-1 assume !(0 == ~T2_E~0); 5093#L791-1 assume !(0 == ~T3_E~0); 5094#L796-1 assume !(0 == ~T4_E~0); 5619#L801-1 assume !(0 == ~T5_E~0); 5620#L806-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5646#L811-1 assume !(0 == ~T7_E~0); 5311#L816-1 assume !(0 == ~E_M~0); 5312#L821-1 assume !(0 == ~E_1~0); 5121#L826-1 assume !(0 == ~E_2~0); 5122#L831-1 assume !(0 == ~E_3~0); 5429#L836-1 assume !(0 == ~E_4~0); 5430#L841-1 assume !(0 == ~E_5~0); 5264#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 5265#L851-1 assume !(0 == ~E_7~0); 5287#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5288#L388 assume !(1 == ~m_pc~0); 5281#L388-2 is_master_triggered_~__retres1~0#1 := 0; 5282#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5730#L400 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5140#L967 assume !(0 != activate_threads_~tmp~1#1); 5141#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5068#L407 assume 1 == ~t1_pc~0; 5069#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5073#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5047#L419 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5048#L975 assume !(0 != activate_threads_~tmp___0~0#1); 5828#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5391#L426 assume !(1 == ~t2_pc~0); 5392#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5843#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5872#L438 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5870#L983 assume !(0 != activate_threads_~tmp___1~0#1); 5871#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5471#L445 assume 1 == ~t3_pc~0; 5472#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5761#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5283#L457 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5284#L991 assume !(0 != activate_threads_~tmp___2~0#1); 5698#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5669#L464 assume !(1 == ~t4_pc~0); 5290#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5161#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5162#L476 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5482#L999 assume !(0 != activate_threads_~tmp___3~0#1); 5447#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5448#L483 assume 1 == ~t5_pc~0; 5666#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5808#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5601#L495 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5602#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 5375#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5376#L502 assume 1 == ~t6_pc~0; 5643#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5192#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5193#L514 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5585#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 5586#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5785#L521 assume !(1 == ~t7_pc~0); 5824#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 5134#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5135#L533 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5242#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 5792#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5719#L869 assume !(1 == ~M_E~0); 5440#L869-2 assume !(1 == ~T1_E~0); 5441#L874-1 assume !(1 == ~T2_E~0); 5853#L879-1 assume !(1 == ~T3_E~0); 5521#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5056#L889-1 assume !(1 == ~T5_E~0); 5057#L894-1 assume !(1 == ~T6_E~0); 5318#L899-1 assume !(1 == ~T7_E~0); 5686#L904-1 assume !(1 == ~E_M~0); 5463#L909-1 assume !(1 == ~E_1~0); 5464#L914-1 assume !(1 == ~E_2~0); 5633#L919-1 assume !(1 == ~E_3~0); 5390#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 5230#L929-1 assume !(1 == ~E_5~0); 5231#L934-1 assume !(1 == ~E_6~0); 5443#L939-1 assume !(1 == ~E_7~0); 5444#L944-1 assume { :end_inline_reset_delta_events } true; 5300#L1190-2 [2022-10-17 10:57:26,898 INFO L750 eck$LassoCheckResult]: Loop: 5300#L1190-2 assume !false; 5313#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5314#L756 assume !false; 5536#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5876#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 5154#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5662#L639 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 5485#L653 assume !(0 != eval_~tmp~0#1); 5487#L771 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5527#L541-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5528#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5173#L781-5 assume !(0 == ~T1_E~0); 5174#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5494#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5117#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5118#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5377#L806-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5378#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 5560#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5747#L821-3 assume !(0 == ~E_1~0); 5844#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5693#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5694#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5274#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5275#L846-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5584#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5168#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5169#L388-27 assume 1 == ~m_pc~0; 5819#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5821#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5790#L400-9 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5791#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5348#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5349#L407-27 assume 1 == ~t1_pc~0; 5699#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5700#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5572#L419-9 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5573#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5604#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5268#L426-27 assume !(1 == ~t2_pc~0); 5269#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 5279#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5280#L438-9 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5804#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5817#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5555#L445-27 assume 1 == ~t3_pc~0; 5533#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5114#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5115#L457-9 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5535#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5638#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5369#L464-27 assume !(1 == ~t4_pc~0); 5112#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 5113#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5180#L476-9 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5561#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5260#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5261#L483-27 assume 1 == ~t5_pc~0; 5766#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5170#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5171#L495-9 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5780#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 5781#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5860#L502-27 assume 1 == ~t6_pc~0; 5861#L503-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5581#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5830#L514-9 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5716#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5717#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5058#L521-27 assume !(1 == ~t7_pc~0); 5059#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 5401#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5548#L533-9 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5108#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 5109#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5596#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5713#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5492#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5493#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5551#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5547#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5218#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5219#L899-3 assume !(1 == ~T7_E~0); 5246#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5247#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5194#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5195#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5238#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5705#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5634#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5635#L939-3 assume !(1 == ~E_7~0); 5253#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5254#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 5075#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5501#L639-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 5502#L1209 assume !(0 == start_simulation_~tmp~3#1); 5576#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5559#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 5211#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5607#L639-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 5608#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5102#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5103#L1172 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 5299#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 5300#L1190-2 [2022-10-17 10:57:26,899 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:57:26,899 INFO L85 PathProgramCache]: Analyzing trace with hash 1028580607, now seen corresponding path program 1 times [2022-10-17 10:57:26,899 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:57:26,900 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1291936248] [2022-10-17 10:57:26,900 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:57:26,901 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:57:26,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:57:26,973 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:57:26,974 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:57:26,974 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1291936248] [2022-10-17 10:57:26,975 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1291936248] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:57:26,975 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:57:26,976 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:57:26,979 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1571020923] [2022-10-17 10:57:26,979 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:57:26,980 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:57:26,980 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:57:26,981 INFO L85 PathProgramCache]: Analyzing trace with hash -138895583, now seen corresponding path program 2 times [2022-10-17 10:57:26,981 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:57:26,986 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [435169488] [2022-10-17 10:57:26,987 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:57:26,987 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:57:27,016 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:57:27,084 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:57:27,084 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:57:27,084 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [435169488] [2022-10-17 10:57:27,085 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [435169488] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:57:27,085 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:57:27,085 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:57:27,085 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [459795773] [2022-10-17 10:57:27,086 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:57:27,086 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:57:27,087 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:57:27,089 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:57:27,089 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:57:27,090 INFO L87 Difference]: Start difference. First operand 835 states and 1247 transitions. cyclomatic complexity: 413 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:57:27,117 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:57:27,117 INFO L93 Difference]: Finished difference Result 835 states and 1246 transitions. [2022-10-17 10:57:27,117 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 835 states and 1246 transitions. [2022-10-17 10:57:27,127 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 732 [2022-10-17 10:57:27,137 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 835 states to 835 states and 1246 transitions. [2022-10-17 10:57:27,137 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 835 [2022-10-17 10:57:27,139 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 835 [2022-10-17 10:57:27,139 INFO L73 IsDeterministic]: Start isDeterministic. Operand 835 states and 1246 transitions. [2022-10-17 10:57:27,141 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:57:27,141 INFO L218 hiAutomatonCegarLoop]: Abstraction has 835 states and 1246 transitions. [2022-10-17 10:57:27,144 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 835 states and 1246 transitions. [2022-10-17 10:57:27,159 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 835 to 835. [2022-10-17 10:57:27,162 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 835 states, 835 states have (on average 1.4922155688622754) internal successors, (1246), 834 states have internal predecessors, (1246), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:57:27,167 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 835 states to 835 states and 1246 transitions. [2022-10-17 10:57:27,167 INFO L240 hiAutomatonCegarLoop]: Abstraction has 835 states and 1246 transitions. [2022-10-17 10:57:27,168 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:57:27,169 INFO L428 stractBuchiCegarLoop]: Abstraction has 835 states and 1246 transitions. [2022-10-17 10:57:27,169 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-10-17 10:57:27,169 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 835 states and 1246 transitions. [2022-10-17 10:57:27,177 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 732 [2022-10-17 10:57:27,177 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:57:27,177 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:57:27,179 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:57:27,179 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:57:27,180 INFO L748 eck$LassoCheckResult]: Stem: 7359#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 7360#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 6813#L1153 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6814#L541 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7534#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 7109#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7110#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7229#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7230#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7022#L568-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6809#L573-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6810#L578-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6982#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6983#L781 assume !(0 == ~M_E~0); 7435#L781-2 assume !(0 == ~T1_E~0); 7557#L786-1 assume !(0 == ~T2_E~0); 6770#L791-1 assume !(0 == ~T3_E~0); 6771#L796-1 assume !(0 == ~T4_E~0); 7296#L801-1 assume !(0 == ~T5_E~0); 7297#L806-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7323#L811-1 assume !(0 == ~T7_E~0); 6988#L816-1 assume !(0 == ~E_M~0); 6989#L821-1 assume !(0 == ~E_1~0); 6798#L826-1 assume !(0 == ~E_2~0); 6799#L831-1 assume !(0 == ~E_3~0); 7106#L836-1 assume !(0 == ~E_4~0); 7107#L841-1 assume !(0 == ~E_5~0); 6943#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 6944#L851-1 assume !(0 == ~E_7~0); 6964#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6965#L388 assume !(1 == ~m_pc~0); 6958#L388-2 is_master_triggered_~__retres1~0#1 := 0; 6959#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7407#L400 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6817#L967 assume !(0 != activate_threads_~tmp~1#1); 6818#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6745#L407 assume 1 == ~t1_pc~0; 6746#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6753#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6724#L419 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6725#L975 assume !(0 != activate_threads_~tmp___0~0#1); 7505#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7068#L426 assume !(1 == ~t2_pc~0); 7069#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7520#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7549#L438 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7547#L983 assume !(0 != activate_threads_~tmp___1~0#1); 7548#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7148#L445 assume 1 == ~t3_pc~0; 7149#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7438#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6960#L457 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6961#L991 assume !(0 != activate_threads_~tmp___2~0#1); 7375#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7346#L464 assume !(1 == ~t4_pc~0); 6967#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 6838#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6839#L476 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7161#L999 assume !(0 != activate_threads_~tmp___3~0#1); 7124#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7125#L483 assume 1 == ~t5_pc~0; 7343#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7485#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7278#L495 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7279#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 7052#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7053#L502 assume 1 == ~t6_pc~0; 7321#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6869#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6870#L514 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7262#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 7263#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7462#L521 assume !(1 == ~t7_pc~0); 7501#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 6811#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6812#L533 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6919#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 7469#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7398#L869 assume !(1 == ~M_E~0); 7117#L869-2 assume !(1 == ~T1_E~0); 7118#L874-1 assume !(1 == ~T2_E~0); 7530#L879-1 assume !(1 == ~T3_E~0); 7198#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6733#L889-1 assume !(1 == ~T5_E~0); 6734#L894-1 assume !(1 == ~T6_E~0); 6998#L899-1 assume !(1 == ~T7_E~0); 7365#L904-1 assume !(1 == ~E_M~0); 7140#L909-1 assume !(1 == ~E_1~0); 7141#L914-1 assume !(1 == ~E_2~0); 7310#L919-1 assume !(1 == ~E_3~0); 7067#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 6907#L929-1 assume !(1 == ~E_5~0); 6908#L934-1 assume !(1 == ~E_6~0); 7122#L939-1 assume !(1 == ~E_7~0); 7123#L944-1 assume { :end_inline_reset_delta_events } true; 6976#L1190-2 [2022-10-17 10:57:27,181 INFO L750 eck$LassoCheckResult]: Loop: 6976#L1190-2 assume !false; 6990#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6991#L756 assume !false; 7213#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 7553#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 6833#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 7339#L639 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 7164#L653 assume !(0 != eval_~tmp~0#1); 7166#L771 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7204#L541-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7205#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6850#L781-5 assume !(0 == ~T1_E~0); 6851#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7171#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6794#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6795#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7054#L806-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7055#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7238#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7424#L821-3 assume !(0 == ~E_1~0); 7521#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7370#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7371#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6951#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6952#L846-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7261#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 6845#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6846#L388-27 assume 1 == ~m_pc~0; 7496#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7498#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7467#L400-9 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7468#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7025#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7026#L407-27 assume 1 == ~t1_pc~0; 7376#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7377#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7247#L419-9 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7248#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7281#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6945#L426-27 assume !(1 == ~t2_pc~0); 6946#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 6956#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6957#L438-9 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7481#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7494#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7232#L445-27 assume 1 == ~t3_pc~0; 7208#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6791#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6792#L457-9 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7212#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7314#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7046#L464-27 assume !(1 == ~t4_pc~0); 6789#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 6790#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6857#L476-9 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7237#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6937#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6938#L483-27 assume 1 == ~t5_pc~0; 7443#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6847#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6848#L495-9 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7457#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 7458#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7537#L502-27 assume 1 == ~t6_pc~0; 7538#L503-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7258#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7507#L514-9 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7393#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7394#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6735#L521-27 assume !(1 == ~t7_pc~0); 6736#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 7078#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7225#L533-9 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6785#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 6786#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7273#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7390#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7169#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7170#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7228#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7224#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6895#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6896#L899-3 assume !(1 == ~T7_E~0); 6923#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6924#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6871#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6872#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6915#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7382#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7311#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 7312#L939-3 assume !(1 == ~E_7~0); 6929#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 6930#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 6751#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 7178#L639-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 7179#L1209 assume !(0 == start_simulation_~tmp~3#1); 7253#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 7236#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 6888#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 7284#L639-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 7285#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6779#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6780#L1172 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 6975#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 6976#L1190-2 [2022-10-17 10:57:27,181 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:57:27,182 INFO L85 PathProgramCache]: Analyzing trace with hash 1614856829, now seen corresponding path program 1 times [2022-10-17 10:57:27,182 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:57:27,182 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [294503136] [2022-10-17 10:57:27,182 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:57:27,183 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:57:27,201 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:57:27,246 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:57:27,247 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:57:27,247 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [294503136] [2022-10-17 10:57:27,247 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [294503136] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:57:27,247 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:57:27,248 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:57:27,248 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1905493027] [2022-10-17 10:57:27,248 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:57:27,249 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:57:27,249 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:57:27,249 INFO L85 PathProgramCache]: Analyzing trace with hash -138895583, now seen corresponding path program 3 times [2022-10-17 10:57:27,250 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:57:27,251 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [439380393] [2022-10-17 10:57:27,251 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:57:27,251 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:57:27,277 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:57:27,353 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:57:27,355 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:57:27,355 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [439380393] [2022-10-17 10:57:27,355 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [439380393] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:57:27,355 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:57:27,356 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:57:27,356 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [69440142] [2022-10-17 10:57:27,356 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:57:27,357 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:57:27,357 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:57:27,357 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:57:27,358 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:57:27,358 INFO L87 Difference]: Start difference. First operand 835 states and 1246 transitions. cyclomatic complexity: 412 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:57:27,382 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:57:27,383 INFO L93 Difference]: Finished difference Result 835 states and 1245 transitions. [2022-10-17 10:57:27,383 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 835 states and 1245 transitions. [2022-10-17 10:57:27,415 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 732 [2022-10-17 10:57:27,424 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 835 states to 835 states and 1245 transitions. [2022-10-17 10:57:27,425 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 835 [2022-10-17 10:57:27,426 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 835 [2022-10-17 10:57:27,426 INFO L73 IsDeterministic]: Start isDeterministic. Operand 835 states and 1245 transitions. [2022-10-17 10:57:27,428 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:57:27,428 INFO L218 hiAutomatonCegarLoop]: Abstraction has 835 states and 1245 transitions. [2022-10-17 10:57:27,430 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 835 states and 1245 transitions. [2022-10-17 10:57:27,445 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 835 to 835. [2022-10-17 10:57:27,447 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 835 states, 835 states have (on average 1.4910179640718564) internal successors, (1245), 834 states have internal predecessors, (1245), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:57:27,454 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 835 states to 835 states and 1245 transitions. [2022-10-17 10:57:27,454 INFO L240 hiAutomatonCegarLoop]: Abstraction has 835 states and 1245 transitions. [2022-10-17 10:57:27,454 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:57:27,458 INFO L428 stractBuchiCegarLoop]: Abstraction has 835 states and 1245 transitions. [2022-10-17 10:57:27,458 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-10-17 10:57:27,458 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 835 states and 1245 transitions. [2022-10-17 10:57:27,465 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 732 [2022-10-17 10:57:27,465 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:57:27,466 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:57:27,470 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:57:27,470 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:57:27,471 INFO L748 eck$LassoCheckResult]: Stem: 9036#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 9037#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 8490#L1153 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8491#L541 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9211#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 8786#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8787#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8906#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8907#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8699#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 8486#L573-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8487#L578-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8659#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8660#L781 assume !(0 == ~M_E~0); 9111#L781-2 assume !(0 == ~T1_E~0); 9234#L786-1 assume !(0 == ~T2_E~0); 8447#L791-1 assume !(0 == ~T3_E~0); 8448#L796-1 assume !(0 == ~T4_E~0); 8973#L801-1 assume !(0 == ~T5_E~0); 8974#L806-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9000#L811-1 assume !(0 == ~T7_E~0); 8665#L816-1 assume !(0 == ~E_M~0); 8666#L821-1 assume !(0 == ~E_1~0); 8475#L826-1 assume !(0 == ~E_2~0); 8476#L831-1 assume !(0 == ~E_3~0); 8783#L836-1 assume !(0 == ~E_4~0); 8784#L841-1 assume !(0 == ~E_5~0); 8618#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 8619#L851-1 assume !(0 == ~E_7~0); 8641#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8642#L388 assume !(1 == ~m_pc~0); 8635#L388-2 is_master_triggered_~__retres1~0#1 := 0; 8636#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9084#L400 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8494#L967 assume !(0 != activate_threads_~tmp~1#1); 8495#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8422#L407 assume 1 == ~t1_pc~0; 8423#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8430#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8401#L419 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8402#L975 assume !(0 != activate_threads_~tmp___0~0#1); 9182#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8745#L426 assume !(1 == ~t2_pc~0); 8746#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 9197#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9226#L438 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9224#L983 assume !(0 != activate_threads_~tmp___1~0#1); 9225#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8825#L445 assume 1 == ~t3_pc~0; 8826#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9115#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8637#L457 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8638#L991 assume !(0 != activate_threads_~tmp___2~0#1); 9052#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9023#L464 assume !(1 == ~t4_pc~0); 8644#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 8515#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8516#L476 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8836#L999 assume !(0 != activate_threads_~tmp___3~0#1); 8801#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8802#L483 assume 1 == ~t5_pc~0; 9020#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9162#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8955#L495 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8956#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 8729#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8730#L502 assume 1 == ~t6_pc~0; 8998#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8546#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8547#L514 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8939#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 8940#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9139#L521 assume !(1 == ~t7_pc~0); 9178#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 8488#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8489#L533 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8596#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9146#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9073#L869 assume !(1 == ~M_E~0); 8794#L869-2 assume !(1 == ~T1_E~0); 8795#L874-1 assume !(1 == ~T2_E~0); 9207#L879-1 assume !(1 == ~T3_E~0); 8875#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8410#L889-1 assume !(1 == ~T5_E~0); 8411#L894-1 assume !(1 == ~T6_E~0); 8672#L899-1 assume !(1 == ~T7_E~0); 9042#L904-1 assume !(1 == ~E_M~0); 8817#L909-1 assume !(1 == ~E_1~0); 8818#L914-1 assume !(1 == ~E_2~0); 8987#L919-1 assume !(1 == ~E_3~0); 8744#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 8584#L929-1 assume !(1 == ~E_5~0); 8585#L934-1 assume !(1 == ~E_6~0); 8797#L939-1 assume !(1 == ~E_7~0); 8798#L944-1 assume { :end_inline_reset_delta_events } true; 8653#L1190-2 [2022-10-17 10:57:27,472 INFO L750 eck$LassoCheckResult]: Loop: 8653#L1190-2 assume !false; 8667#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8668#L756 assume !false; 8890#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 9230#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8510#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 9016#L639 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 8839#L653 assume !(0 != eval_~tmp~0#1); 8841#L771 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8881#L541-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8882#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8527#L781-5 assume !(0 == ~T1_E~0); 8528#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8848#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8471#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8472#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8731#L806-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8732#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8914#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 9101#L821-3 assume !(0 == ~E_1~0); 9198#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9047#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9048#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8628#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8629#L846-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8938#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 8522#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8523#L388-27 assume 1 == ~m_pc~0; 9173#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 9175#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9144#L400-9 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9145#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8702#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8703#L407-27 assume 1 == ~t1_pc~0; 9053#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9054#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8926#L419-9 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8927#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8958#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8622#L426-27 assume 1 == ~t2_pc~0; 8624#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8633#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8634#L438-9 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9158#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9171#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8909#L445-27 assume 1 == ~t3_pc~0; 8887#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8468#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8469#L457-9 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8889#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8992#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8723#L464-27 assume !(1 == ~t4_pc~0); 8466#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 8467#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8534#L476-9 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8915#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8614#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8615#L483-27 assume 1 == ~t5_pc~0; 9120#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8524#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8525#L495-9 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9134#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 9135#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9214#L502-27 assume !(1 == ~t6_pc~0); 8934#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 8935#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9184#L514-9 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9070#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9071#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8412#L521-27 assume !(1 == ~t7_pc~0); 8413#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 8755#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8902#L533-9 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8462#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8463#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8948#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9067#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8846#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8847#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8905#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8901#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8572#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8573#L899-3 assume !(1 == ~T7_E~0); 8600#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8601#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8548#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8549#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8590#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9059#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8988#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8989#L939-3 assume !(1 == ~E_7~0); 8606#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 8607#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8428#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 8854#L639-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 8855#L1209 assume !(0 == start_simulation_~tmp~3#1); 8930#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 8913#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8565#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 8960#L639-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 8961#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8456#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8457#L1172 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 8652#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 8653#L1190-2 [2022-10-17 10:57:27,473 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:57:27,474 INFO L85 PathProgramCache]: Analyzing trace with hash -721535681, now seen corresponding path program 1 times [2022-10-17 10:57:27,474 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:57:27,475 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2039116135] [2022-10-17 10:57:27,475 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:57:27,475 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:57:27,490 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:57:27,525 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:57:27,525 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:57:27,525 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2039116135] [2022-10-17 10:57:27,526 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2039116135] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:57:27,526 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:57:27,526 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:57:27,532 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [256995546] [2022-10-17 10:57:27,532 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:57:27,533 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:57:27,536 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:57:27,536 INFO L85 PathProgramCache]: Analyzing trace with hash -1001713119, now seen corresponding path program 1 times [2022-10-17 10:57:27,537 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:57:27,537 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [196966793] [2022-10-17 10:57:27,537 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:57:27,537 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:57:27,557 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:57:27,606 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:57:27,606 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:57:27,607 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [196966793] [2022-10-17 10:57:27,609 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [196966793] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:57:27,609 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:57:27,609 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:57:27,610 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2103508233] [2022-10-17 10:57:27,610 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:57:27,611 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:57:27,611 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:57:27,612 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:57:27,612 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:57:27,612 INFO L87 Difference]: Start difference. First operand 835 states and 1245 transitions. cyclomatic complexity: 411 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:57:27,636 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:57:27,636 INFO L93 Difference]: Finished difference Result 835 states and 1244 transitions. [2022-10-17 10:57:27,637 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 835 states and 1244 transitions. [2022-10-17 10:57:27,646 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 732 [2022-10-17 10:57:27,654 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 835 states to 835 states and 1244 transitions. [2022-10-17 10:57:27,655 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 835 [2022-10-17 10:57:27,656 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 835 [2022-10-17 10:57:27,656 INFO L73 IsDeterministic]: Start isDeterministic. Operand 835 states and 1244 transitions. [2022-10-17 10:57:27,658 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:57:27,658 INFO L218 hiAutomatonCegarLoop]: Abstraction has 835 states and 1244 transitions. [2022-10-17 10:57:27,660 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 835 states and 1244 transitions. [2022-10-17 10:57:27,675 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 835 to 835. [2022-10-17 10:57:27,678 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 835 states, 835 states have (on average 1.4898203592814372) internal successors, (1244), 834 states have internal predecessors, (1244), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:57:27,683 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 835 states to 835 states and 1244 transitions. [2022-10-17 10:57:27,683 INFO L240 hiAutomatonCegarLoop]: Abstraction has 835 states and 1244 transitions. [2022-10-17 10:57:27,684 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:57:27,685 INFO L428 stractBuchiCegarLoop]: Abstraction has 835 states and 1244 transitions. [2022-10-17 10:57:27,686 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-10-17 10:57:27,686 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 835 states and 1244 transitions. [2022-10-17 10:57:27,693 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 732 [2022-10-17 10:57:27,693 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:57:27,693 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:57:27,695 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:57:27,695 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:57:27,696 INFO L748 eck$LassoCheckResult]: Stem: 10713#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 10714#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 10167#L1153 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10168#L541 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10888#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 10463#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10464#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10583#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10584#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10376#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 10163#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 10164#L578-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10333#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10334#L781 assume !(0 == ~M_E~0); 10788#L781-2 assume !(0 == ~T1_E~0); 10911#L786-1 assume !(0 == ~T2_E~0); 10124#L791-1 assume !(0 == ~T3_E~0); 10125#L796-1 assume !(0 == ~T4_E~0); 10650#L801-1 assume !(0 == ~T5_E~0); 10651#L806-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10677#L811-1 assume !(0 == ~T7_E~0); 10342#L816-1 assume !(0 == ~E_M~0); 10343#L821-1 assume !(0 == ~E_1~0); 10152#L826-1 assume !(0 == ~E_2~0); 10153#L831-1 assume !(0 == ~E_3~0); 10460#L836-1 assume !(0 == ~E_4~0); 10461#L841-1 assume !(0 == ~E_5~0); 10295#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 10296#L851-1 assume !(0 == ~E_7~0); 10318#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10319#L388 assume !(1 == ~m_pc~0); 10312#L388-2 is_master_triggered_~__retres1~0#1 := 0; 10313#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10761#L400 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10171#L967 assume !(0 != activate_threads_~tmp~1#1); 10172#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10099#L407 assume 1 == ~t1_pc~0; 10100#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10104#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10078#L419 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10079#L975 assume !(0 != activate_threads_~tmp___0~0#1); 10859#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10422#L426 assume !(1 == ~t2_pc~0); 10423#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 10874#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10903#L438 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10901#L983 assume !(0 != activate_threads_~tmp___1~0#1); 10902#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10502#L445 assume 1 == ~t3_pc~0; 10503#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10792#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10314#L457 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10315#L991 assume !(0 != activate_threads_~tmp___2~0#1); 10729#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10700#L464 assume !(1 == ~t4_pc~0); 10321#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 10192#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10193#L476 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10513#L999 assume !(0 != activate_threads_~tmp___3~0#1); 10478#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10479#L483 assume 1 == ~t5_pc~0; 10697#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10839#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10632#L495 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10633#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 10406#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10407#L502 assume 1 == ~t6_pc~0; 10674#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10223#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10224#L514 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10616#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 10617#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10816#L521 assume !(1 == ~t7_pc~0); 10855#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 10165#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10166#L533 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10273#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 10823#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10750#L869 assume !(1 == ~M_E~0); 10471#L869-2 assume !(1 == ~T1_E~0); 10472#L874-1 assume !(1 == ~T2_E~0); 10884#L879-1 assume !(1 == ~T3_E~0); 10552#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10087#L889-1 assume !(1 == ~T5_E~0); 10088#L894-1 assume !(1 == ~T6_E~0); 10349#L899-1 assume !(1 == ~T7_E~0); 10717#L904-1 assume !(1 == ~E_M~0); 10494#L909-1 assume !(1 == ~E_1~0); 10495#L914-1 assume !(1 == ~E_2~0); 10664#L919-1 assume !(1 == ~E_3~0); 10421#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 10261#L929-1 assume !(1 == ~E_5~0); 10262#L934-1 assume !(1 == ~E_6~0); 10474#L939-1 assume !(1 == ~E_7~0); 10475#L944-1 assume { :end_inline_reset_delta_events } true; 10331#L1190-2 [2022-10-17 10:57:27,697 INFO L750 eck$LassoCheckResult]: Loop: 10331#L1190-2 assume !false; 10344#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10345#L756 assume !false; 10567#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 10907#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 10185#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 10693#L639 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 10516#L653 assume !(0 != eval_~tmp~0#1); 10518#L771 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10558#L541-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10559#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10204#L781-5 assume !(0 == ~T1_E~0); 10205#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10525#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10148#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10149#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10408#L806-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10409#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 10591#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10778#L821-3 assume !(0 == ~E_1~0); 10875#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10724#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10725#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10305#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10306#L846-3 assume 0 == ~E_6~0;~E_6~0 := 1; 10615#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 10199#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10200#L388-27 assume 1 == ~m_pc~0; 10850#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 10852#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10821#L400-9 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10822#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10379#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10380#L407-27 assume 1 == ~t1_pc~0; 10730#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10731#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10603#L419-9 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10604#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10635#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10299#L426-27 assume !(1 == ~t2_pc~0); 10300#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 10310#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10311#L438-9 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10835#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 10848#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10586#L445-27 assume 1 == ~t3_pc~0; 10564#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10145#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10146#L457-9 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10566#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10669#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10400#L464-27 assume 1 == ~t4_pc~0; 10401#L465-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10144#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10211#L476-9 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10592#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10291#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10292#L483-27 assume 1 == ~t5_pc~0; 10797#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10201#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10202#L495-9 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10811#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 10812#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10891#L502-27 assume !(1 == ~t6_pc~0); 10611#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 10612#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10861#L514-9 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10747#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10748#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10089#L521-27 assume !(1 == ~t7_pc~0); 10090#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 10432#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10579#L533-9 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10139#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 10140#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10627#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10744#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10523#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10524#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10582#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10578#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10249#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10250#L899-3 assume !(1 == ~T7_E~0); 10277#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10278#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10225#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10226#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10269#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10736#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10665#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10666#L939-3 assume !(1 == ~E_7~0); 10284#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 10285#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 10106#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 10532#L639-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 10533#L1209 assume !(0 == start_simulation_~tmp~3#1); 10607#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 10590#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 10242#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 10638#L639-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 10639#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10133#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10134#L1172 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 10330#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 10331#L1190-2 [2022-10-17 10:57:27,697 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:57:27,698 INFO L85 PathProgramCache]: Analyzing trace with hash 1696948797, now seen corresponding path program 1 times [2022-10-17 10:57:27,698 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:57:27,698 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [636972512] [2022-10-17 10:57:27,698 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:57:27,699 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:57:27,712 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:57:27,746 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:57:27,746 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:57:27,746 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [636972512] [2022-10-17 10:57:27,747 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [636972512] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:57:27,747 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:57:27,747 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:57:27,747 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1441245447] [2022-10-17 10:57:27,748 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:57:27,748 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:57:27,748 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:57:27,749 INFO L85 PathProgramCache]: Analyzing trace with hash -350291807, now seen corresponding path program 2 times [2022-10-17 10:57:27,749 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:57:27,749 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [933105365] [2022-10-17 10:57:27,749 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:57:27,750 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:57:27,770 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:57:27,815 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:57:27,816 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:57:27,816 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [933105365] [2022-10-17 10:57:27,816 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [933105365] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:57:27,816 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:57:27,817 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:57:27,817 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1486743933] [2022-10-17 10:57:27,817 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:57:27,817 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:57:27,818 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:57:27,818 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:57:27,818 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:57:27,819 INFO L87 Difference]: Start difference. First operand 835 states and 1244 transitions. cyclomatic complexity: 410 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:57:27,850 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:57:27,851 INFO L93 Difference]: Finished difference Result 835 states and 1243 transitions. [2022-10-17 10:57:27,851 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 835 states and 1243 transitions. [2022-10-17 10:57:27,860 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 732 [2022-10-17 10:57:27,869 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 835 states to 835 states and 1243 transitions. [2022-10-17 10:57:27,869 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 835 [2022-10-17 10:57:27,871 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 835 [2022-10-17 10:57:27,871 INFO L73 IsDeterministic]: Start isDeterministic. Operand 835 states and 1243 transitions. [2022-10-17 10:57:27,874 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:57:27,874 INFO L218 hiAutomatonCegarLoop]: Abstraction has 835 states and 1243 transitions. [2022-10-17 10:57:27,877 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 835 states and 1243 transitions. [2022-10-17 10:57:27,893 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 835 to 835. [2022-10-17 10:57:27,895 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 835 states, 835 states have (on average 1.488622754491018) internal successors, (1243), 834 states have internal predecessors, (1243), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:57:27,900 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 835 states to 835 states and 1243 transitions. [2022-10-17 10:57:27,901 INFO L240 hiAutomatonCegarLoop]: Abstraction has 835 states and 1243 transitions. [2022-10-17 10:57:27,901 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:57:27,904 INFO L428 stractBuchiCegarLoop]: Abstraction has 835 states and 1243 transitions. [2022-10-17 10:57:27,904 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-10-17 10:57:27,905 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 835 states and 1243 transitions. [2022-10-17 10:57:27,911 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 732 [2022-10-17 10:57:27,912 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:57:27,912 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:57:27,914 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:57:27,914 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:57:27,915 INFO L748 eck$LassoCheckResult]: Stem: 12390#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 12391#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 11844#L1153 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11845#L541 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12565#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 12140#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12141#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12260#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12261#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12053#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 11840#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 11841#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 12010#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12011#L781 assume !(0 == ~M_E~0); 12465#L781-2 assume !(0 == ~T1_E~0); 12588#L786-1 assume !(0 == ~T2_E~0); 11801#L791-1 assume !(0 == ~T3_E~0); 11802#L796-1 assume !(0 == ~T4_E~0); 12327#L801-1 assume !(0 == ~T5_E~0); 12328#L806-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12354#L811-1 assume !(0 == ~T7_E~0); 12019#L816-1 assume !(0 == ~E_M~0); 12020#L821-1 assume !(0 == ~E_1~0); 11829#L826-1 assume !(0 == ~E_2~0); 11830#L831-1 assume !(0 == ~E_3~0); 12137#L836-1 assume !(0 == ~E_4~0); 12138#L841-1 assume !(0 == ~E_5~0); 11972#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 11973#L851-1 assume !(0 == ~E_7~0); 11995#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11996#L388 assume !(1 == ~m_pc~0); 11989#L388-2 is_master_triggered_~__retres1~0#1 := 0; 11990#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12438#L400 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11848#L967 assume !(0 != activate_threads_~tmp~1#1); 11849#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11776#L407 assume 1 == ~t1_pc~0; 11777#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11781#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11755#L419 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11756#L975 assume !(0 != activate_threads_~tmp___0~0#1); 12536#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12099#L426 assume !(1 == ~t2_pc~0); 12100#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 12551#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12580#L438 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12578#L983 assume !(0 != activate_threads_~tmp___1~0#1); 12579#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12179#L445 assume 1 == ~t3_pc~0; 12180#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12469#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11991#L457 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11992#L991 assume !(0 != activate_threads_~tmp___2~0#1); 12406#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12377#L464 assume !(1 == ~t4_pc~0); 11998#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 11869#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11870#L476 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12190#L999 assume !(0 != activate_threads_~tmp___3~0#1); 12155#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12156#L483 assume 1 == ~t5_pc~0; 12374#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12516#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12309#L495 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12310#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 12083#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12084#L502 assume 1 == ~t6_pc~0; 12351#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11900#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11901#L514 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12293#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 12294#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12493#L521 assume !(1 == ~t7_pc~0); 12532#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 11842#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11843#L533 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11950#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12500#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12427#L869 assume !(1 == ~M_E~0); 12148#L869-2 assume !(1 == ~T1_E~0); 12149#L874-1 assume !(1 == ~T2_E~0); 12561#L879-1 assume !(1 == ~T3_E~0); 12229#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11764#L889-1 assume !(1 == ~T5_E~0); 11765#L894-1 assume !(1 == ~T6_E~0); 12026#L899-1 assume !(1 == ~T7_E~0); 12394#L904-1 assume !(1 == ~E_M~0); 12171#L909-1 assume !(1 == ~E_1~0); 12172#L914-1 assume !(1 == ~E_2~0); 12341#L919-1 assume !(1 == ~E_3~0); 12098#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 11938#L929-1 assume !(1 == ~E_5~0); 11939#L934-1 assume !(1 == ~E_6~0); 12151#L939-1 assume !(1 == ~E_7~0); 12152#L944-1 assume { :end_inline_reset_delta_events } true; 12008#L1190-2 [2022-10-17 10:57:27,916 INFO L750 eck$LassoCheckResult]: Loop: 12008#L1190-2 assume !false; 12021#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12022#L756 assume !false; 12244#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 12584#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 11862#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 12370#L639 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 12193#L653 assume !(0 != eval_~tmp~0#1); 12195#L771 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12235#L541-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12236#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 11881#L781-5 assume !(0 == ~T1_E~0); 11882#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12202#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11825#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11826#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12085#L806-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12086#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12268#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12455#L821-3 assume !(0 == ~E_1~0); 12552#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12401#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12402#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11982#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 11983#L846-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12292#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 11876#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11877#L388-27 assume !(1 == ~m_pc~0); 12528#L388-29 is_master_triggered_~__retres1~0#1 := 0; 12529#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12498#L400-9 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12499#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12056#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12057#L407-27 assume 1 == ~t1_pc~0; 12407#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12408#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12280#L419-9 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12281#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12312#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11976#L426-27 assume !(1 == ~t2_pc~0); 11977#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 11987#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11988#L438-9 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12512#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12525#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12263#L445-27 assume 1 == ~t3_pc~0; 12241#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11822#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11823#L457-9 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12243#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12346#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12077#L464-27 assume !(1 == ~t4_pc~0); 11820#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 11821#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11888#L476-9 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12269#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11968#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11969#L483-27 assume 1 == ~t5_pc~0; 12474#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11878#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11879#L495-9 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12488#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 12489#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12568#L502-27 assume !(1 == ~t6_pc~0); 12288#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 12289#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12538#L514-9 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12424#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12425#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11766#L521-27 assume !(1 == ~t7_pc~0); 11767#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 12109#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12256#L533-9 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11816#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11817#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12304#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12421#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12200#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12201#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12259#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12255#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11926#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 11927#L899-3 assume !(1 == ~T7_E~0); 11954#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 11955#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11902#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11903#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11946#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12413#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12342#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12343#L939-3 assume !(1 == ~E_7~0); 11961#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 11962#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 11783#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 12209#L639-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 12210#L1209 assume !(0 == start_simulation_~tmp~3#1); 12284#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 12267#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 11919#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 12315#L639-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 12316#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11810#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11811#L1172 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 12007#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 12008#L1190-2 [2022-10-17 10:57:27,917 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:57:27,917 INFO L85 PathProgramCache]: Analyzing trace with hash -718887553, now seen corresponding path program 1 times [2022-10-17 10:57:27,917 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:57:27,917 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [937747089] [2022-10-17 10:57:27,917 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:57:27,919 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:57:27,937 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:57:28,080 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:57:28,080 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:57:28,080 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [937747089] [2022-10-17 10:57:28,081 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [937747089] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:57:28,081 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:57:28,081 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:57:28,081 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [410575357] [2022-10-17 10:57:28,084 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:57:28,084 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:57:28,085 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:57:28,085 INFO L85 PathProgramCache]: Analyzing trace with hash 1828583203, now seen corresponding path program 1 times [2022-10-17 10:57:28,085 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:57:28,085 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1577015849] [2022-10-17 10:57:28,086 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:57:28,086 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:57:28,116 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:57:28,172 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:57:28,172 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:57:28,172 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1577015849] [2022-10-17 10:57:28,175 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1577015849] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:57:28,175 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:57:28,175 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:57:28,177 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1699732315] [2022-10-17 10:57:28,177 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:57:28,177 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:57:28,178 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:57:28,178 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-10-17 10:57:28,179 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-10-17 10:57:28,179 INFO L87 Difference]: Start difference. First operand 835 states and 1243 transitions. cyclomatic complexity: 409 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:57:28,374 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:57:28,374 INFO L93 Difference]: Finished difference Result 1509 states and 2238 transitions. [2022-10-17 10:57:28,374 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1509 states and 2238 transitions. [2022-10-17 10:57:28,389 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1390 [2022-10-17 10:57:28,404 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1509 states to 1509 states and 2238 transitions. [2022-10-17 10:57:28,405 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1509 [2022-10-17 10:57:28,407 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1509 [2022-10-17 10:57:28,407 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1509 states and 2238 transitions. [2022-10-17 10:57:28,410 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:57:28,410 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1509 states and 2238 transitions. [2022-10-17 10:57:28,413 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1509 states and 2238 transitions. [2022-10-17 10:57:28,448 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1509 to 1509. [2022-10-17 10:57:28,452 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1509 states, 1509 states have (on average 1.4831013916500995) internal successors, (2238), 1508 states have internal predecessors, (2238), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:57:28,461 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1509 states to 1509 states and 2238 transitions. [2022-10-17 10:57:28,461 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1509 states and 2238 transitions. [2022-10-17 10:57:28,461 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-10-17 10:57:28,464 INFO L428 stractBuchiCegarLoop]: Abstraction has 1509 states and 2238 transitions. [2022-10-17 10:57:28,464 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-10-17 10:57:28,464 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1509 states and 2238 transitions. [2022-10-17 10:57:28,476 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1390 [2022-10-17 10:57:28,476 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:57:28,476 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:57:28,478 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:57:28,479 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:57:28,479 INFO L748 eck$LassoCheckResult]: Stem: 14759#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 14760#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 14198#L1153 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14199#L541 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14956#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 14498#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14499#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14620#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14621#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14410#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14194#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 14195#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 14365#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14366#L781 assume !(0 == ~M_E~0); 14841#L781-2 assume !(0 == ~T1_E~0); 14987#L786-1 assume !(0 == ~T2_E~0); 14155#L791-1 assume !(0 == ~T3_E~0); 14156#L796-1 assume !(0 == ~T4_E~0); 14691#L801-1 assume !(0 == ~T5_E~0); 14692#L806-1 assume !(0 == ~T6_E~0); 14720#L811-1 assume !(0 == ~T7_E~0); 14374#L816-1 assume !(0 == ~E_M~0); 14375#L821-1 assume !(0 == ~E_1~0); 14183#L826-1 assume !(0 == ~E_2~0); 14184#L831-1 assume !(0 == ~E_3~0); 14495#L836-1 assume !(0 == ~E_4~0); 14496#L841-1 assume !(0 == ~E_5~0); 14327#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 14328#L851-1 assume !(0 == ~E_7~0); 14350#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14351#L388 assume !(1 == ~m_pc~0); 14344#L388-2 is_master_triggered_~__retres1~0#1 := 0; 14345#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14811#L400 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 14202#L967 assume !(0 != activate_threads_~tmp~1#1); 14203#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14130#L407 assume 1 == ~t1_pc~0; 14131#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14135#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14109#L419 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14110#L975 assume !(0 != activate_threads_~tmp___0~0#1); 14920#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14456#L426 assume !(1 == ~t2_pc~0); 14457#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 14937#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14975#L438 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14973#L983 assume !(0 != activate_threads_~tmp___1~0#1); 14974#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14537#L445 assume 1 == ~t3_pc~0; 14538#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14846#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14346#L457 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14347#L991 assume !(0 != activate_threads_~tmp___2~0#1); 14776#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14746#L464 assume !(1 == ~t4_pc~0); 14353#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 14223#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14224#L476 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14548#L999 assume !(0 != activate_threads_~tmp___3~0#1); 14513#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14514#L483 assume 1 == ~t5_pc~0; 14743#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14898#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14671#L495 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14672#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 14440#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14441#L502 assume 1 == ~t6_pc~0; 14717#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 14254#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14255#L514 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14653#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 14654#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14871#L521 assume !(1 == ~t7_pc~0); 14915#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 14196#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14197#L533 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14305#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 14879#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14797#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 14798#L869-2 assume !(1 == ~T1_E~0); 15541#L874-1 assume !(1 == ~T2_E~0); 15539#L879-1 assume !(1 == ~T3_E~0); 15536#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15534#L889-1 assume !(1 == ~T5_E~0); 15532#L894-1 assume !(1 == ~T6_E~0); 14381#L899-1 assume !(1 == ~T7_E~0); 15529#L904-1 assume !(1 == ~E_M~0); 15527#L909-1 assume !(1 == ~E_1~0); 15524#L914-1 assume !(1 == ~E_2~0); 15522#L919-1 assume !(1 == ~E_3~0); 15520#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 15518#L929-1 assume !(1 == ~E_5~0); 15516#L934-1 assume !(1 == ~E_6~0); 15514#L939-1 assume !(1 == ~E_7~0); 15432#L944-1 assume { :end_inline_reset_delta_events } true; 15431#L1190-2 [2022-10-17 10:57:28,479 INFO L750 eck$LassoCheckResult]: Loop: 15431#L1190-2 assume !false; 15006#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 15005#L756 assume !false; 15004#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 15003#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 14738#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 14739#L639 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 14980#L653 assume !(0 != eval_~tmp~0#1); 14994#L771 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14594#L541-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14595#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 14993#L781-5 assume !(0 == ~T1_E~0); 15556#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15555#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 15554#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15553#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15552#L806-3 assume !(0 == ~T6_E~0); 15551#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 15550#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 15549#L821-3 assume !(0 == ~E_1~0); 15548#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 15547#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15546#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 15545#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15544#L846-3 assume 0 == ~E_6~0;~E_6~0 := 1; 15543#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 15542#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15540#L388-27 assume !(1 == ~m_pc~0); 15537#L388-29 is_master_triggered_~__retres1~0#1 := 0; 15535#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15533#L400-9 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 15531#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 15530#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15528#L407-27 assume 1 == ~t1_pc~0; 15525#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 15523#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15521#L419-9 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15519#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15517#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15515#L426-27 assume !(1 == ~t2_pc~0); 15512#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 15511#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15510#L438-9 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15509#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15508#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15507#L445-27 assume 1 == ~t3_pc~0; 15505#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15504#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15503#L457-9 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15502#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15501#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15500#L464-27 assume !(1 == ~t4_pc~0); 15498#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 15497#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15496#L476-9 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15495#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 15494#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15493#L483-27 assume 1 == ~t5_pc~0; 15491#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15490#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15489#L495-9 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15488#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 15487#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15486#L502-27 assume 1 == ~t6_pc~0; 15484#L503-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15483#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15482#L514-9 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15481#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 15480#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15479#L521-27 assume !(1 == ~t7_pc~0); 15477#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 15476#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15475#L533-9 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15474#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 15473#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15472#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14947#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15471#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15470#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15469#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15468#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 15467#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14281#L899-3 assume !(1 == ~T7_E~0); 15466#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 15465#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 15464#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15463#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 15462#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 15461#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 15460#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 15459#L939-3 assume !(1 == ~E_7~0); 15458#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 15455#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 15449#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 15448#L639-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 15447#L1209 assume !(0 == start_simulation_~tmp~3#1); 14655#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 15444#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 15438#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 15437#L639-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 15436#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15435#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 15434#L1172 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 15433#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 15431#L1190-2 [2022-10-17 10:57:28,480 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:57:28,480 INFO L85 PathProgramCache]: Analyzing trace with hash -1207876549, now seen corresponding path program 1 times [2022-10-17 10:57:28,481 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:57:28,481 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1598969825] [2022-10-17 10:57:28,481 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:57:28,481 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:57:28,499 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:57:28,571 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:57:28,571 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:57:28,571 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1598969825] [2022-10-17 10:57:28,571 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1598969825] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:57:28,571 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:57:28,572 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:57:28,572 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1195074334] [2022-10-17 10:57:28,572 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:57:28,573 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:57:28,573 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:57:28,573 INFO L85 PathProgramCache]: Analyzing trace with hash 1319064224, now seen corresponding path program 1 times [2022-10-17 10:57:28,573 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:57:28,574 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1400900793] [2022-10-17 10:57:28,574 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:57:28,574 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:57:28,591 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:57:28,636 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:57:28,636 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:57:28,636 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1400900793] [2022-10-17 10:57:28,636 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1400900793] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:57:28,636 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:57:28,636 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:57:28,637 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1594232152] [2022-10-17 10:57:28,637 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:57:28,637 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:57:28,638 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:57:28,638 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-10-17 10:57:28,638 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-10-17 10:57:28,638 INFO L87 Difference]: Start difference. First operand 1509 states and 2238 transitions. cyclomatic complexity: 731 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:57:28,851 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:57:28,851 INFO L93 Difference]: Finished difference Result 2723 states and 4027 transitions. [2022-10-17 10:57:28,852 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2723 states and 4027 transitions. [2022-10-17 10:57:28,879 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2590 [2022-10-17 10:57:28,954 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2723 states to 2723 states and 4027 transitions. [2022-10-17 10:57:28,956 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2723 [2022-10-17 10:57:28,959 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2723 [2022-10-17 10:57:28,960 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2723 states and 4027 transitions. [2022-10-17 10:57:28,965 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:57:28,965 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2723 states and 4027 transitions. [2022-10-17 10:57:28,970 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2723 states and 4027 transitions. [2022-10-17 10:57:29,039 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2723 to 2721. [2022-10-17 10:57:29,046 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2721 states, 2721 states have (on average 1.4792355751561925) internal successors, (4025), 2720 states have internal predecessors, (4025), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:57:29,066 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2721 states to 2721 states and 4025 transitions. [2022-10-17 10:57:29,066 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2721 states and 4025 transitions. [2022-10-17 10:57:29,067 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-10-17 10:57:29,068 INFO L428 stractBuchiCegarLoop]: Abstraction has 2721 states and 4025 transitions. [2022-10-17 10:57:29,068 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-10-17 10:57:29,069 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2721 states and 4025 transitions. [2022-10-17 10:57:29,089 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2590 [2022-10-17 10:57:29,089 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:57:29,090 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:57:29,092 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:57:29,092 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:57:29,093 INFO L748 eck$LassoCheckResult]: Stem: 19001#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 19002#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 18440#L1153 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 18441#L541 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19191#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 18740#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18741#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18864#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 18865#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 18652#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 18436#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 18437#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 18611#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18612#L781 assume !(0 == ~M_E~0); 19085#L781-2 assume !(0 == ~T1_E~0); 19219#L786-1 assume !(0 == ~T2_E~0); 18397#L791-1 assume !(0 == ~T3_E~0); 18398#L796-1 assume !(0 == ~T4_E~0); 18935#L801-1 assume !(0 == ~T5_E~0); 18936#L806-1 assume !(0 == ~T6_E~0); 18963#L811-1 assume !(0 == ~T7_E~0); 18618#L816-1 assume !(0 == ~E_M~0); 18619#L821-1 assume !(0 == ~E_1~0); 18425#L826-1 assume !(0 == ~E_2~0); 18426#L831-1 assume !(0 == ~E_3~0); 18737#L836-1 assume !(0 == ~E_4~0); 18738#L841-1 assume !(0 == ~E_5~0); 18571#L846-1 assume !(0 == ~E_6~0); 18572#L851-1 assume !(0 == ~E_7~0); 18592#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18593#L388 assume !(1 == ~m_pc~0); 18586#L388-2 is_master_triggered_~__retres1~0#1 := 0; 18587#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19054#L400 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 18444#L967 assume !(0 != activate_threads_~tmp~1#1); 18445#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18372#L407 assume 1 == ~t1_pc~0; 18373#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18380#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18351#L419 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 18352#L975 assume !(0 != activate_threads_~tmp___0~0#1); 19159#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18699#L426 assume !(1 == ~t2_pc~0); 18700#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 19176#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19211#L438 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19209#L983 assume !(0 != activate_threads_~tmp___1~0#1); 19210#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18780#L445 assume 1 == ~t3_pc~0; 18781#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19089#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18588#L457 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18589#L991 assume !(0 != activate_threads_~tmp___2~0#1); 19019#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18988#L464 assume !(1 == ~t4_pc~0); 18595#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 18465#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18466#L476 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18793#L999 assume !(0 != activate_threads_~tmp___3~0#1); 18755#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18756#L483 assume 1 == ~t5_pc~0; 18984#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19138#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18917#L495 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18918#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 18683#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18684#L502 assume 1 == ~t6_pc~0; 18961#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 18496#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18497#L514 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18899#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 18900#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19114#L521 assume !(1 == ~t7_pc~0); 19155#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 18438#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 18439#L533 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18547#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19121#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19044#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 18748#L869-2 assume !(1 == ~T1_E~0); 18749#L874-1 assume !(1 == ~T2_E~0); 19187#L879-1 assume !(1 == ~T3_E~0); 18832#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18360#L889-1 assume !(1 == ~T5_E~0); 18361#L894-1 assume !(1 == ~T6_E~0); 18628#L899-1 assume !(1 == ~T7_E~0); 19009#L904-1 assume !(1 == ~E_M~0); 18772#L909-1 assume !(1 == ~E_1~0); 18773#L914-1 assume !(1 == ~E_2~0); 18949#L919-1 assume !(1 == ~E_3~0); 18970#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 19275#L929-1 assume !(1 == ~E_5~0); 19273#L934-1 assume !(1 == ~E_6~0); 19261#L939-1 assume !(1 == ~E_7~0); 19253#L944-1 assume { :end_inline_reset_delta_events } true; 19247#L1190-2 [2022-10-17 10:57:29,094 INFO L750 eck$LassoCheckResult]: Loop: 19247#L1190-2 assume !false; 19242#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19241#L756 assume !false; 19240#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 19239#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 19231#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 19230#L639 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 19228#L653 assume !(0 != eval_~tmp~0#1); 19227#L771 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19226#L541-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19224#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 19225#L781-5 assume !(0 == ~T1_E~0); 20461#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 20460#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 20459#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 20458#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 20457#L806-3 assume !(0 == ~T6_E~0); 20456#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 20455#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 20454#L821-3 assume !(0 == ~E_1~0); 20191#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20076#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20010#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 20008#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 20005#L846-3 assume !(0 == ~E_6~0); 20003#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 19961#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19959#L388-27 assume !(1 == ~m_pc~0); 19956#L388-29 is_master_triggered_~__retres1~0#1 := 0; 19954#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19952#L400-9 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 19950#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19948#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19927#L407-27 assume 1 == ~t1_pc~0; 19924#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19894#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19876#L419-9 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 19857#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 19855#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19853#L426-27 assume !(1 == ~t2_pc~0); 19838#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 19818#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19793#L438-9 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19765#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19763#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19761#L445-27 assume 1 == ~t3_pc~0; 19741#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19738#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19736#L457-9 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19733#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 19705#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19703#L464-27 assume !(1 == ~t4_pc~0); 19700#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 19670#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19645#L476-9 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19643#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 19623#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19621#L483-27 assume 1 == ~t5_pc~0; 19604#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19602#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19600#L495-9 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19580#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 19555#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19553#L502-27 assume 1 == ~t6_pc~0; 19550#L503-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19549#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19548#L514-9 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19546#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 19545#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19544#L521-27 assume !(1 == ~t7_pc~0); 19515#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 19513#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19512#L533-9 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19511#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19509#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19507#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 19034#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 18801#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18802#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18863#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18897#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19430#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 18523#L899-3 assume !(1 == ~T7_E~0); 19429#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19390#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19388#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19386#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 19384#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 19382#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 19381#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19378#L939-3 assume !(1 == ~E_7~0); 19377#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 19356#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 19349#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 19348#L639-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 19347#L1209 assume !(0 == start_simulation_~tmp~3#1); 18901#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 19322#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 19315#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 19294#L639-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 19292#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19274#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19262#L1172 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 19254#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 19247#L1190-2 [2022-10-17 10:57:29,094 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:57:29,095 INFO L85 PathProgramCache]: Analyzing trace with hash -253936391, now seen corresponding path program 1 times [2022-10-17 10:57:29,095 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:57:29,095 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [851450443] [2022-10-17 10:57:29,095 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:57:29,096 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:57:29,114 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:57:29,213 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:57:29,213 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:57:29,213 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [851450443] [2022-10-17 10:57:29,214 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [851450443] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:57:29,214 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:57:29,214 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:57:29,214 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [151645224] [2022-10-17 10:57:29,215 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:57:29,216 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:57:29,217 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:57:29,217 INFO L85 PathProgramCache]: Analyzing trace with hash 176561758, now seen corresponding path program 1 times [2022-10-17 10:57:29,217 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:57:29,218 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1813660623] [2022-10-17 10:57:29,218 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:57:29,218 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:57:29,236 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:57:29,279 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:57:29,279 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:57:29,280 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1813660623] [2022-10-17 10:57:29,280 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1813660623] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:57:29,280 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:57:29,280 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:57:29,280 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1219163359] [2022-10-17 10:57:29,281 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:57:29,281 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:57:29,281 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:57:29,282 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-10-17 10:57:29,282 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-10-17 10:57:29,283 INFO L87 Difference]: Start difference. First operand 2721 states and 4025 transitions. cyclomatic complexity: 1308 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:57:29,615 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:57:29,615 INFO L93 Difference]: Finished difference Result 7498 states and 10918 transitions. [2022-10-17 10:57:29,615 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7498 states and 10918 transitions. [2022-10-17 10:57:29,674 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7117 [2022-10-17 10:57:29,746 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7498 states to 7498 states and 10918 transitions. [2022-10-17 10:57:29,746 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7498 [2022-10-17 10:57:29,756 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7498 [2022-10-17 10:57:29,757 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7498 states and 10918 transitions. [2022-10-17 10:57:29,769 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:57:29,769 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7498 states and 10918 transitions. [2022-10-17 10:57:29,780 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7498 states and 10918 transitions. [2022-10-17 10:57:30,040 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7498 to 7066. [2022-10-17 10:57:30,059 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7066 states, 7066 states have (on average 1.4613642796490236) internal successors, (10326), 7065 states have internal predecessors, (10326), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:57:30,088 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7066 states to 7066 states and 10326 transitions. [2022-10-17 10:57:30,089 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7066 states and 10326 transitions. [2022-10-17 10:57:30,089 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-10-17 10:57:30,090 INFO L428 stractBuchiCegarLoop]: Abstraction has 7066 states and 10326 transitions. [2022-10-17 10:57:30,090 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-10-17 10:57:30,090 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7066 states and 10326 transitions. [2022-10-17 10:57:30,130 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6917 [2022-10-17 10:57:30,130 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:57:30,130 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:57:30,133 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:57:30,133 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:57:30,133 INFO L748 eck$LassoCheckResult]: Stem: 29290#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 29291#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 28667#L1153 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28668#L541 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 29576#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 28981#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28982#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29114#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 29115#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 28888#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 28663#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 28664#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 28842#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 28843#L781 assume !(0 == ~M_E~0); 29396#L781-2 assume !(0 == ~T1_E~0); 29670#L786-1 assume !(0 == ~T2_E~0); 28624#L791-1 assume !(0 == ~T3_E~0); 28625#L796-1 assume !(0 == ~T4_E~0); 29202#L801-1 assume !(0 == ~T5_E~0); 29203#L806-1 assume !(0 == ~T6_E~0); 29245#L811-1 assume !(0 == ~T7_E~0); 28852#L816-1 assume !(0 == ~E_M~0); 28853#L821-1 assume !(0 == ~E_1~0); 28652#L826-1 assume !(0 == ~E_2~0); 28653#L831-1 assume !(0 == ~E_3~0); 28978#L836-1 assume !(0 == ~E_4~0); 28979#L841-1 assume !(0 == ~E_5~0); 28802#L846-1 assume !(0 == ~E_6~0); 28803#L851-1 assume !(0 == ~E_7~0); 28827#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28828#L388 assume !(1 == ~m_pc~0); 28821#L388-2 is_master_triggered_~__retres1~0#1 := 0; 28822#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29356#L400 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 28671#L967 assume !(0 != activate_threads_~tmp~1#1); 28672#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28601#L407 assume !(1 == ~t1_pc~0); 28602#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 28605#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28580#L419 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 28581#L975 assume !(0 != activate_threads_~tmp___0~0#1); 29512#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28937#L426 assume !(1 == ~t2_pc~0); 28938#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 29540#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29624#L438 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 29617#L983 assume !(0 != activate_threads_~tmp___1~0#1); 29618#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29020#L445 assume 1 == ~t3_pc~0; 29021#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 29403#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28823#L457 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 28824#L991 assume !(0 != activate_threads_~tmp___2~0#1); 29312#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29275#L464 assume !(1 == ~t4_pc~0); 28830#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 28692#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28693#L476 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 29031#L999 assume !(0 != activate_threads_~tmp___3~0#1); 28996#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28997#L483 assume 1 == ~t5_pc~0; 29272#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 29483#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29181#L495 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29182#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 28921#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28922#L502 assume 1 == ~t6_pc~0; 29242#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 28726#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28727#L514 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29158#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 29159#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29447#L521 assume !(1 == ~t7_pc~0); 29508#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 28665#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28666#L533 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 28779#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 29459#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29343#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 29344#L869-2 assume !(1 == ~T1_E~0); 32670#L874-1 assume !(1 == ~T2_E~0); 32669#L879-1 assume !(1 == ~T3_E~0); 32668#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 32667#L889-1 assume !(1 == ~T5_E~0); 32666#L894-1 assume !(1 == ~T6_E~0); 32665#L899-1 assume !(1 == ~T7_E~0); 32664#L904-1 assume !(1 == ~E_M~0); 32663#L909-1 assume !(1 == ~E_1~0); 32662#L914-1 assume !(1 == ~E_2~0); 29253#L919-1 assume !(1 == ~E_3~0); 28936#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 28766#L929-1 assume !(1 == ~E_5~0); 28767#L934-1 assume !(1 == ~E_6~0); 29579#L939-1 assume !(1 == ~E_7~0); 33663#L944-1 assume { :end_inline_reset_delta_events } true; 33657#L1190-2 [2022-10-17 10:57:30,134 INFO L750 eck$LassoCheckResult]: Loop: 33657#L1190-2 assume !false; 33652#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 33651#L756 assume !false; 33650#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 33649#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 33641#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 33640#L639 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 33638#L653 assume !(0 != eval_~tmp~0#1); 33637#L771 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 33636#L541-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 33633#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 33634#L781-5 assume !(0 == ~T1_E~0); 34232#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 34231#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 34230#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 34229#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 34228#L806-3 assume !(0 == ~T6_E~0); 34227#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 34226#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 34225#L821-3 assume !(0 == ~E_1~0); 34224#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 34223#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 34222#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 34221#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 34220#L846-3 assume !(0 == ~E_6~0); 34219#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 34218#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30739#L388-27 assume !(1 == ~m_pc~0); 30738#L388-29 is_master_triggered_~__retres1~0#1 := 0; 30737#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30736#L400-9 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 30735#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 30734#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30733#L407-27 assume !(1 == ~t1_pc~0); 30731#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 30729#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30727#L419-9 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 30724#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 30722#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30720#L426-27 assume !(1 == ~t2_pc~0); 30717#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 30714#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30712#L438-9 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 30710#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 30707#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30705#L445-27 assume 1 == ~t3_pc~0; 30645#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30643#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30641#L457-9 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 30637#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30622#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30611#L464-27 assume 1 == ~t4_pc~0; 30612#L465-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 34101#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 34099#L476-9 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 34097#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 34095#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 34093#L483-27 assume 1 == ~t5_pc~0; 33921#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 33919#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33917#L495-9 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33915#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 33913#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33912#L502-27 assume 1 == ~t6_pc~0; 33908#L503-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33906#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33903#L514-9 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33776#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 33773#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33770#L521-27 assume !(1 == ~t7_pc~0); 33766#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 33763#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33759#L533-9 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33756#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 33753#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33751#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 30357#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 33748#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 33745#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 33743#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 33742#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 33741#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 30334#L899-3 assume !(1 == ~T7_E~0); 30335#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 30326#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 30327#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 33730#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30312#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 30313#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 33724#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 33721#L939-3 assume !(1 == ~E_7~0); 33720#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 33716#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 33708#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 33706#L639-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 33704#L1209 assume !(0 == start_simulation_~tmp~3#1); 29162#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 33699#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 33690#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 33688#L639-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 33686#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 33685#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 33671#L1172 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 33664#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 33657#L1190-2 [2022-10-17 10:57:30,135 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:57:30,135 INFO L85 PathProgramCache]: Analyzing trace with hash -1285267206, now seen corresponding path program 1 times [2022-10-17 10:57:30,135 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:57:30,136 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1308049460] [2022-10-17 10:57:30,136 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:57:30,136 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:57:30,151 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:57:30,218 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:57:30,218 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:57:30,218 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1308049460] [2022-10-17 10:57:30,219 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1308049460] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:57:30,219 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:57:30,219 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:57:30,219 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [765193406] [2022-10-17 10:57:30,219 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:57:30,220 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:57:30,220 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:57:30,221 INFO L85 PathProgramCache]: Analyzing trace with hash -1504980962, now seen corresponding path program 1 times [2022-10-17 10:57:30,221 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:57:30,221 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1800426499] [2022-10-17 10:57:30,221 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:57:30,222 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:57:30,237 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:57:30,280 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:57:30,280 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:57:30,280 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1800426499] [2022-10-17 10:57:30,281 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1800426499] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:57:30,281 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:57:30,281 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:57:30,281 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [275398848] [2022-10-17 10:57:30,281 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:57:30,282 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:57:30,282 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:57:30,283 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-10-17 10:57:30,283 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-10-17 10:57:30,283 INFO L87 Difference]: Start difference. First operand 7066 states and 10326 transitions. cyclomatic complexity: 3268 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:57:30,656 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:57:30,657 INFO L93 Difference]: Finished difference Result 19679 states and 28431 transitions. [2022-10-17 10:57:30,657 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 19679 states and 28431 transitions. [2022-10-17 10:57:30,947 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 18975 [2022-10-17 10:57:31,058 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 19679 states to 19679 states and 28431 transitions. [2022-10-17 10:57:31,059 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19679 [2022-10-17 10:57:31,084 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19679 [2022-10-17 10:57:31,084 INFO L73 IsDeterministic]: Start isDeterministic. Operand 19679 states and 28431 transitions. [2022-10-17 10:57:31,111 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:57:31,111 INFO L218 hiAutomatonCegarLoop]: Abstraction has 19679 states and 28431 transitions. [2022-10-17 10:57:31,139 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19679 states and 28431 transitions. [2022-10-17 10:57:31,580 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19679 to 18731. [2022-10-17 10:57:31,625 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18731 states, 18731 states have (on average 1.4497357322086382) internal successors, (27155), 18730 states have internal predecessors, (27155), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:57:31,798 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18731 states to 18731 states and 27155 transitions. [2022-10-17 10:57:31,812 INFO L240 hiAutomatonCegarLoop]: Abstraction has 18731 states and 27155 transitions. [2022-10-17 10:57:31,813 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-10-17 10:57:31,814 INFO L428 stractBuchiCegarLoop]: Abstraction has 18731 states and 27155 transitions. [2022-10-17 10:57:31,814 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-10-17 10:57:31,814 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 18731 states and 27155 transitions. [2022-10-17 10:57:31,974 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 18543 [2022-10-17 10:57:31,974 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:57:31,974 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:57:31,976 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:57:31,977 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:57:31,977 INFO L748 eck$LassoCheckResult]: Stem: 55995#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 55996#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 55420#L1153 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 55421#L541 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 56227#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 55722#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 55723#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 55846#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 55847#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 55634#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 55416#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 55417#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 55591#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 55592#L781 assume !(0 == ~M_E~0); 56084#L781-2 assume !(0 == ~T1_E~0); 56298#L786-1 assume !(0 == ~T2_E~0); 55378#L791-1 assume !(0 == ~T3_E~0); 55379#L796-1 assume !(0 == ~T4_E~0); 55924#L801-1 assume !(0 == ~T5_E~0); 55925#L806-1 assume !(0 == ~T6_E~0); 55954#L811-1 assume !(0 == ~T7_E~0); 55600#L816-1 assume !(0 == ~E_M~0); 55601#L821-1 assume !(0 == ~E_1~0); 55406#L826-1 assume !(0 == ~E_2~0); 55407#L831-1 assume !(0 == ~E_3~0); 55719#L836-1 assume !(0 == ~E_4~0); 55720#L841-1 assume !(0 == ~E_5~0); 55551#L846-1 assume !(0 == ~E_6~0); 55552#L851-1 assume !(0 == ~E_7~0); 55574#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 55575#L388 assume !(1 == ~m_pc~0); 55568#L388-2 is_master_triggered_~__retres1~0#1 := 0; 55569#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 56055#L400 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 55424#L967 assume !(0 != activate_threads_~tmp~1#1); 55425#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 55356#L407 assume !(1 == ~t1_pc~0); 55357#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 55360#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 55335#L419 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 55336#L975 assume !(0 != activate_threads_~tmp___0~0#1); 56185#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 55682#L426 assume !(1 == ~t2_pc~0); 55683#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 56204#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 56264#L438 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 56261#L983 assume !(0 != activate_threads_~tmp___1~0#1); 56262#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 55762#L445 assume !(1 == ~t3_pc~0); 55763#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 56091#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 55570#L457 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 55571#L991 assume !(0 != activate_threads_~tmp___2~0#1); 56015#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 55980#L464 assume !(1 == ~t4_pc~0); 55577#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 55445#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 55446#L476 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 55772#L999 assume !(0 != activate_threads_~tmp___3~0#1); 55737#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 55738#L483 assume 1 == ~t5_pc~0; 55977#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 56162#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 55903#L495 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 55904#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 55666#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 55667#L502 assume 1 == ~t6_pc~0; 55951#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 55476#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 55477#L514 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 55881#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 55882#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 56129#L521 assume !(1 == ~t7_pc~0); 56181#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 55418#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 55419#L533 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 55528#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 56142#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 56041#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 55730#L869-2 assume !(1 == ~T1_E~0); 55731#L874-1 assume !(1 == ~T2_E~0); 56222#L879-1 assume !(1 == ~T3_E~0); 55814#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 55344#L889-1 assume !(1 == ~T5_E~0); 55345#L894-1 assume !(1 == ~T6_E~0); 55607#L899-1 assume !(1 == ~T7_E~0); 56001#L904-1 assume !(1 == ~E_M~0); 55752#L909-1 assume !(1 == ~E_1~0); 55753#L914-1 assume !(1 == ~E_2~0); 55939#L919-1 assume !(1 == ~E_3~0); 55681#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 55514#L929-1 assume !(1 == ~E_5~0); 55515#L934-1 assume !(1 == ~E_6~0); 55733#L939-1 assume !(1 == ~E_7~0); 55734#L944-1 assume { :end_inline_reset_delta_events } true; 71812#L1190-2 [2022-10-17 10:57:31,978 INFO L750 eck$LassoCheckResult]: Loop: 71812#L1190-2 assume !false; 71807#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 71806#L756 assume !false; 71805#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 71804#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 71796#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 71795#L639 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 71793#L653 assume !(0 != eval_~tmp~0#1); 71792#L771 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 71790#L541-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 71787#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 71785#L781-5 assume !(0 == ~T1_E~0); 71783#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 71781#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 71779#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 71777#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 71774#L806-3 assume !(0 == ~T6_E~0); 71772#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 71770#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 71768#L821-3 assume !(0 == ~E_1~0); 71766#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 71764#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 71761#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 71759#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 71757#L846-3 assume !(0 == ~E_6~0); 71755#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 71753#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 71751#L388-27 assume !(1 == ~m_pc~0); 71748#L388-29 is_master_triggered_~__retres1~0#1 := 0; 71744#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 56140#L400-9 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 56141#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 55637#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 55638#L407-27 assume !(1 == ~t1_pc~0); 56029#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 56109#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 55867#L419-9 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 55868#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 55906#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 55555#L426-27 assume !(1 == ~t2_pc~0); 55556#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 55566#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 55567#L438-9 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 56157#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 56173#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 55850#L445-27 assume !(1 == ~t3_pc~0); 55851#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 55399#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 55400#L457-9 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 55829#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 55944#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 55660#L464-27 assume !(1 == ~t4_pc~0); 55397#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 55398#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 55464#L476-9 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 55856#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 55547#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 55548#L483-27 assume 1 == ~t5_pc~0; 56099#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 55454#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 55455#L495-9 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 56119#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 56120#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 56238#L502-27 assume !(1 == ~t6_pc~0); 55876#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 55877#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 56188#L514-9 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 56036#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 56037#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 55346#L521-27 assume !(1 == ~t7_pc~0); 55347#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 55692#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 55842#L533-9 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 55393#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 55394#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 55896#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 56033#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 55782#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 55783#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 55845#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 55841#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 55502#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 55503#L899-3 assume !(1 == ~T7_E~0); 55532#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 55533#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 55478#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 55479#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 72378#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 72376#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 72374#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 56134#L939-3 assume !(1 == ~E_7~0); 55540#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 55541#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 55362#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 71968#L639-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 71962#L1209 assume !(0 == start_simulation_~tmp~3#1); 71960#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 71869#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 71859#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 71848#L639-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 71842#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 71838#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 71825#L1172 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 71818#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 71812#L1190-2 [2022-10-17 10:57:31,979 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:57:31,979 INFO L85 PathProgramCache]: Analyzing trace with hash 1116257915, now seen corresponding path program 1 times [2022-10-17 10:57:31,979 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:57:31,980 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1869489470] [2022-10-17 10:57:31,980 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:57:31,980 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:57:31,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:57:32,052 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:57:32,053 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:57:32,053 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1869489470] [2022-10-17 10:57:32,053 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1869489470] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:57:32,054 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:57:32,054 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-10-17 10:57:32,054 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [717937841] [2022-10-17 10:57:32,054 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:57:32,055 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:57:32,055 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:57:32,056 INFO L85 PathProgramCache]: Analyzing trace with hash 999702305, now seen corresponding path program 1 times [2022-10-17 10:57:32,056 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:57:32,056 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1760720223] [2022-10-17 10:57:32,056 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:57:32,057 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:57:32,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:57:32,121 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:57:32,121 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:57:32,122 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1760720223] [2022-10-17 10:57:32,122 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1760720223] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:57:32,122 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:57:32,122 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:57:32,123 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [808232695] [2022-10-17 10:57:32,123 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:57:32,123 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:57:32,124 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:57:32,124 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:57:32,124 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:57:32,125 INFO L87 Difference]: Start difference. First operand 18731 states and 27155 transitions. cyclomatic complexity: 8440 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 2 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:57:32,447 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:57:32,447 INFO L93 Difference]: Finished difference Result 36058 states and 51973 transitions. [2022-10-17 10:57:32,448 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 36058 states and 51973 transitions. [2022-10-17 10:57:32,885 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 35739 [2022-10-17 10:57:33,058 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 36058 states to 36058 states and 51973 transitions. [2022-10-17 10:57:33,058 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 36058 [2022-10-17 10:57:33,108 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 36058 [2022-10-17 10:57:33,108 INFO L73 IsDeterministic]: Start isDeterministic. Operand 36058 states and 51973 transitions. [2022-10-17 10:57:33,146 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:57:33,146 INFO L218 hiAutomatonCegarLoop]: Abstraction has 36058 states and 51973 transitions. [2022-10-17 10:57:33,191 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36058 states and 51973 transitions. [2022-10-17 10:57:34,015 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36058 to 35986. [2022-10-17 10:57:34,104 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 35986 states, 35986 states have (on average 1.442255321513922) internal successors, (51901), 35985 states have internal predecessors, (51901), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:57:34,267 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35986 states to 35986 states and 51901 transitions. [2022-10-17 10:57:34,268 INFO L240 hiAutomatonCegarLoop]: Abstraction has 35986 states and 51901 transitions. [2022-10-17 10:57:34,268 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:57:34,269 INFO L428 stractBuchiCegarLoop]: Abstraction has 35986 states and 51901 transitions. [2022-10-17 10:57:34,269 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-10-17 10:57:34,270 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 35986 states and 51901 transitions. [2022-10-17 10:57:34,620 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 35667 [2022-10-17 10:57:34,620 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:57:34,620 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:57:34,622 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:57:34,622 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:57:34,623 INFO L748 eck$LassoCheckResult]: Stem: 110802#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 110803#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 110216#L1153 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 110217#L541 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 111047#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 110522#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 110523#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 110648#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 110649#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 110432#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 110212#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 110213#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 110384#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 110385#L781 assume !(0 == ~M_E~0); 110895#L781-2 assume !(0 == ~T1_E~0); 111118#L786-1 assume !(0 == ~T2_E~0); 110174#L791-1 assume !(0 == ~T3_E~0); 110175#L796-1 assume !(0 == ~T4_E~0); 110725#L801-1 assume !(0 == ~T5_E~0); 110726#L806-1 assume !(0 == ~T6_E~0); 110761#L811-1 assume !(0 == ~T7_E~0); 110393#L816-1 assume !(0 == ~E_M~0); 110394#L821-1 assume !(0 == ~E_1~0); 110202#L826-1 assume !(0 == ~E_2~0); 110203#L831-1 assume !(0 == ~E_3~0); 110519#L836-1 assume !(0 == ~E_4~0); 110520#L841-1 assume !(0 == ~E_5~0); 110346#L846-1 assume !(0 == ~E_6~0); 110347#L851-1 assume !(0 == ~E_7~0); 110369#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 110370#L388 assume !(1 == ~m_pc~0); 110363#L388-2 is_master_triggered_~__retres1~0#1 := 0; 110364#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 110864#L400 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 110220#L967 assume !(0 != activate_threads_~tmp~1#1); 110221#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 110152#L407 assume !(1 == ~t1_pc~0); 110153#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 110156#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 110131#L419 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 110132#L975 assume !(0 != activate_threads_~tmp___0~0#1); 110998#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 110481#L426 assume !(1 == ~t2_pc~0); 110482#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 111022#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 111088#L438 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 111081#L983 assume !(0 != activate_threads_~tmp___1~0#1); 111082#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 110563#L445 assume !(1 == ~t3_pc~0); 110564#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 110899#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 110365#L457 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 110366#L991 assume !(0 != activate_threads_~tmp___2~0#1); 110820#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 110789#L464 assume !(1 == ~t4_pc~0); 110372#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 110241#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 110242#L476 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 110573#L999 assume !(0 != activate_threads_~tmp___3~0#1); 110537#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 110538#L483 assume !(1 == ~t5_pc~0); 110786#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 110975#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 110705#L495 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 110706#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 110466#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 110467#L502 assume 1 == ~t6_pc~0; 110758#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 110272#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 110273#L514 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 110685#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 110686#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 110940#L521 assume !(1 == ~t7_pc~0); 110994#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 110214#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 110215#L533 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 110324#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 110952#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 110847#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 110848#L869-2 assume !(1 == ~T1_E~0); 111076#L874-1 assume !(1 == ~T2_E~0); 111077#L879-1 assume !(1 == ~T3_E~0); 110614#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 110615#L889-1 assume !(1 == ~T5_E~0); 110401#L894-1 assume !(1 == ~T6_E~0); 110402#L899-1 assume !(1 == ~T7_E~0); 111123#L904-1 assume !(1 == ~E_M~0); 114679#L909-1 assume !(1 == ~E_1~0); 114677#L914-1 assume !(1 == ~E_2~0); 114675#L919-1 assume !(1 == ~E_3~0); 114673#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 114671#L929-1 assume !(1 == ~E_5~0); 114669#L934-1 assume !(1 == ~E_6~0); 114667#L939-1 assume !(1 == ~E_7~0); 114664#L944-1 assume { :end_inline_reset_delta_events } true; 114665#L1190-2 [2022-10-17 10:57:34,624 INFO L750 eck$LassoCheckResult]: Loop: 114665#L1190-2 assume !false; 133856#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 133854#L756 assume !false; 133852#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 133849#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 133840#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 133837#L639 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 133834#L653 assume !(0 != eval_~tmp~0#1); 133835#L771 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 135181#L541-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 135180#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 135179#L781-5 assume !(0 == ~T1_E~0); 135178#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 135177#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 135176#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 135175#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 135174#L806-3 assume !(0 == ~T6_E~0); 135173#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 135172#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 135171#L821-3 assume !(0 == ~E_1~0); 135170#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 135169#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 135168#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 135167#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 135166#L846-3 assume !(0 == ~E_6~0); 135165#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 135164#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 135163#L388-27 assume !(1 == ~m_pc~0); 135162#L388-29 is_master_triggered_~__retres1~0#1 := 0; 135161#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 135160#L400-9 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 135159#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 135158#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 135157#L407-27 assume !(1 == ~t1_pc~0); 135156#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 135155#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 135154#L419-9 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 135153#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 135152#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 135151#L426-27 assume 1 == ~t2_pc~0; 135150#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 135148#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 135147#L438-9 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 135146#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 135145#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 135144#L445-27 assume !(1 == ~t3_pc~0); 135143#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 135142#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 135141#L457-9 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 135140#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 135139#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 135138#L464-27 assume !(1 == ~t4_pc~0); 135136#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 135135#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 135134#L476-9 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 135133#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 135132#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 135131#L483-27 assume !(1 == ~t5_pc~0); 135130#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 135129#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 135128#L495-9 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 135127#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 135126#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 135125#L502-27 assume 1 == ~t6_pc~0; 135123#L503-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 135122#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 135121#L514-9 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 135120#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 135119#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 135118#L521-27 assume !(1 == ~t7_pc~0); 135116#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 135115#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 135114#L533-9 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 135113#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 135112#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 135111#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 134179#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 135110#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 135109#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 135108#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 135107#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 135106#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 134861#L899-3 assume !(1 == ~T7_E~0); 135105#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 135104#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 135103#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 135102#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 135101#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 135100#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 135099#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 134162#L939-3 assume !(1 == ~E_7~0); 135098#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 135095#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 135089#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 135088#L639-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 134072#L1209 assume !(0 == start_simulation_~tmp~3#1); 134071#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 134068#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 134062#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 134061#L639-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 134060#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 134059#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 134058#L1172 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 134057#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 114665#L1190-2 [2022-10-17 10:57:34,624 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:57:34,625 INFO L85 PathProgramCache]: Analyzing trace with hash -2127260292, now seen corresponding path program 1 times [2022-10-17 10:57:34,625 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:57:34,625 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1331473511] [2022-10-17 10:57:34,625 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:57:34,626 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:57:34,643 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:57:34,804 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:57:34,804 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:57:34,805 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1331473511] [2022-10-17 10:57:34,805 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1331473511] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:57:34,805 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:57:34,805 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:57:34,805 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1647168298] [2022-10-17 10:57:34,806 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:57:34,807 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:57:34,807 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:57:34,808 INFO L85 PathProgramCache]: Analyzing trace with hash -786207968, now seen corresponding path program 1 times [2022-10-17 10:57:34,808 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:57:34,808 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1557868332] [2022-10-17 10:57:34,808 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:57:34,808 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:57:34,827 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:57:34,872 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:57:34,872 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:57:34,872 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1557868332] [2022-10-17 10:57:34,872 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1557868332] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:57:34,872 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:57:34,873 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:57:34,873 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [38929238] [2022-10-17 10:57:34,873 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:57:34,874 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:57:34,874 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:57:34,874 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-10-17 10:57:34,875 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-10-17 10:57:34,875 INFO L87 Difference]: Start difference. First operand 35986 states and 51901 transitions. cyclomatic complexity: 15947 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:57:35,835 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:57:35,836 INFO L93 Difference]: Finished difference Result 99247 states and 142032 transitions. [2022-10-17 10:57:35,836 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 99247 states and 142032 transitions. [2022-10-17 10:57:36,862 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 96417 [2022-10-17 10:57:37,544 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 99247 states to 99247 states and 142032 transitions. [2022-10-17 10:57:37,545 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 99247 [2022-10-17 10:57:37,634 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 99247 [2022-10-17 10:57:37,634 INFO L73 IsDeterministic]: Start isDeterministic. Operand 99247 states and 142032 transitions. [2022-10-17 10:57:37,780 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:57:37,780 INFO L218 hiAutomatonCegarLoop]: Abstraction has 99247 states and 142032 transitions. [2022-10-17 10:57:37,874 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 99247 states and 142032 transitions. [2022-10-17 10:57:39,484 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 99247 to 95959. [2022-10-17 10:57:39,709 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 95959 states, 95959 states have (on average 1.4359466021946874) internal successors, (137792), 95958 states have internal predecessors, (137792), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:57:40,140 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 95959 states to 95959 states and 137792 transitions. [2022-10-17 10:57:40,140 INFO L240 hiAutomatonCegarLoop]: Abstraction has 95959 states and 137792 transitions. [2022-10-17 10:57:40,141 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-10-17 10:57:40,142 INFO L428 stractBuchiCegarLoop]: Abstraction has 95959 states and 137792 transitions. [2022-10-17 10:57:40,143 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-10-17 10:57:40,143 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 95959 states and 137792 transitions. [2022-10-17 10:57:40,420 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 95337 [2022-10-17 10:57:40,420 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:57:40,420 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:57:40,422 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:57:40,422 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:57:40,423 INFO L748 eck$LassoCheckResult]: Stem: 246061#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 246062#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 245459#L1153 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 245460#L541 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 246327#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 245768#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 245769#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 245900#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 245901#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 245671#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 245455#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 245456#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 245627#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 245628#L781 assume !(0 == ~M_E~0); 246156#L781-2 assume !(0 == ~T1_E~0); 246408#L786-1 assume !(0 == ~T2_E~0); 245417#L791-1 assume !(0 == ~T3_E~0); 245418#L796-1 assume !(0 == ~T4_E~0); 245984#L801-1 assume !(0 == ~T5_E~0); 245985#L806-1 assume !(0 == ~T6_E~0); 246019#L811-1 assume !(0 == ~T7_E~0); 245636#L816-1 assume !(0 == ~E_M~0); 245637#L821-1 assume !(0 == ~E_1~0); 245445#L826-1 assume !(0 == ~E_2~0); 245446#L831-1 assume !(0 == ~E_3~0); 245765#L836-1 assume !(0 == ~E_4~0); 245766#L841-1 assume !(0 == ~E_5~0); 245589#L846-1 assume !(0 == ~E_6~0); 245590#L851-1 assume !(0 == ~E_7~0); 245612#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 245613#L388 assume !(1 == ~m_pc~0); 245606#L388-2 is_master_triggered_~__retres1~0#1 := 0; 245607#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 246121#L400 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 245463#L967 assume !(0 != activate_threads_~tmp~1#1); 245464#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 245395#L407 assume !(1 == ~t1_pc~0); 245396#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 245399#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 245374#L419 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 245375#L975 assume !(0 != activate_threads_~tmp___0~0#1); 246264#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 245722#L426 assume !(1 == ~t2_pc~0); 245723#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 246293#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 246369#L438 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 246362#L983 assume !(0 != activate_threads_~tmp___1~0#1); 246363#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 245811#L445 assume !(1 == ~t3_pc~0); 245812#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 246161#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 245608#L457 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 245609#L991 assume !(0 != activate_threads_~tmp___2~0#1); 246082#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 246046#L464 assume !(1 == ~t4_pc~0); 245615#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 245484#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 245485#L476 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 245822#L999 assume !(0 != activate_threads_~tmp___3~0#1); 245785#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 245786#L483 assume !(1 == ~t5_pc~0); 246043#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 246241#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 245963#L495 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 245964#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 245707#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 245708#L502 assume !(1 == ~t6_pc~0); 245563#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 245516#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 245517#L514 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 245941#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 245942#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 246207#L521 assume !(1 == ~t7_pc~0); 246258#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 245457#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 245458#L533 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 245566#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 246218#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 246107#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 246108#L869-2 assume !(1 == ~T1_E~0); 246358#L874-1 assume !(1 == ~T2_E~0); 246359#L879-1 assume !(1 == ~T3_E~0); 245863#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 245864#L889-1 assume !(1 == ~T5_E~0); 245643#L894-1 assume !(1 == ~T6_E~0); 245644#L899-1 assume !(1 == ~T7_E~0); 246068#L904-1 assume !(1 == ~E_M~0); 246069#L909-1 assume !(1 == ~E_1~0); 246001#L914-1 assume !(1 == ~E_2~0); 246002#L919-1 assume !(1 == ~E_3~0); 245720#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 245721#L929-1 assume !(1 == ~E_5~0); 246330#L934-1 assume !(1 == ~E_6~0); 245781#L939-1 assume !(1 == ~E_7~0); 245782#L944-1 assume { :end_inline_reset_delta_events } true; 258868#L1190-2 [2022-10-17 10:57:40,424 INFO L750 eck$LassoCheckResult]: Loop: 258868#L1190-2 assume !false; 309014#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 309013#L756 assume !false; 309004#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 309002#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 308993#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 308991#L639 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 258783#L653 assume !(0 != eval_~tmp~0#1); 258784#L771 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 313754#L541-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 313753#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 313752#L781-5 assume !(0 == ~T1_E~0); 313751#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 313750#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 313749#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 313748#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 313747#L806-3 assume !(0 == ~T6_E~0); 313746#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 313745#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 313744#L821-3 assume !(0 == ~E_1~0); 313743#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 313742#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 313741#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 313740#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 313739#L846-3 assume !(0 == ~E_6~0); 313738#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 313737#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 313736#L388-27 assume !(1 == ~m_pc~0); 313735#L388-29 is_master_triggered_~__retres1~0#1 := 0; 313734#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 313733#L400-9 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 313732#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 313731#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 313730#L407-27 assume !(1 == ~t1_pc~0); 313729#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 313728#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 313727#L419-9 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 313726#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 313725#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 313724#L426-27 assume !(1 == ~t2_pc~0); 313722#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 313721#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 313720#L438-9 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 313719#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 313718#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 313717#L445-27 assume !(1 == ~t3_pc~0); 313716#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 313715#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 313714#L457-9 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 313713#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 313712#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 313711#L464-27 assume !(1 == ~t4_pc~0); 313709#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 313708#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 313707#L476-9 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 313706#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 313705#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 313704#L483-27 assume !(1 == ~t5_pc~0); 313703#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 313702#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 313701#L495-9 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 313700#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 313699#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 313698#L502-27 assume !(1 == ~t6_pc~0); 313697#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 313696#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 313695#L514-9 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 313694#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 313693#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 313692#L521-27 assume !(1 == ~t7_pc~0); 313690#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 313689#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 313688#L533-9 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 313687#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 313686#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 313685#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 305466#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 313684#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 313683#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 313682#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 313681#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 313680#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 259289#L899-3 assume !(1 == ~T7_E~0); 313679#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 313678#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 313677#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 313676#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 313675#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 313674#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 313673#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 309972#L939-3 assume !(1 == ~E_7~0); 313672#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 313669#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 313663#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 313662#L639-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 313593#L1209 assume !(0 == start_simulation_~tmp~3#1); 313592#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 313589#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 313582#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 313579#L639-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 313577#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 313575#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 313573#L1172 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 313571#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 258868#L1190-2 [2022-10-17 10:57:40,425 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:57:40,425 INFO L85 PathProgramCache]: Analyzing trace with hash 1196032317, now seen corresponding path program 1 times [2022-10-17 10:57:40,425 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:57:40,426 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1226822084] [2022-10-17 10:57:40,426 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:57:40,426 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:57:40,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:57:40,515 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:57:40,516 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:57:40,516 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1226822084] [2022-10-17 10:57:40,516 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1226822084] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:57:40,517 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:57:40,517 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-10-17 10:57:40,517 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [114423914] [2022-10-17 10:57:40,517 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:57:40,518 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:57:40,518 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:57:40,518 INFO L85 PathProgramCache]: Analyzing trace with hash -893739870, now seen corresponding path program 1 times [2022-10-17 10:57:40,519 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:57:40,519 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1328144781] [2022-10-17 10:57:40,519 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:57:40,519 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:57:40,536 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:57:40,579 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:57:40,580 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:57:40,580 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1328144781] [2022-10-17 10:57:40,580 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1328144781] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:57:40,580 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:57:40,580 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:57:40,581 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [217479706] [2022-10-17 10:57:40,581 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:57:40,582 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:57:40,582 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:57:40,582 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-10-17 10:57:40,582 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-10-17 10:57:40,583 INFO L87 Difference]: Start difference. First operand 95959 states and 137792 transitions. cyclomatic complexity: 41897 Second operand has 5 states, 5 states have (on average 19.0) internal successors, (95), 5 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:57:42,348 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:57:42,348 INFO L93 Difference]: Finished difference Result 218779 states and 317880 transitions. [2022-10-17 10:57:42,348 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 218779 states and 317880 transitions. [2022-10-17 10:57:44,247 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 217126 [2022-10-17 10:57:45,246 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 218779 states to 218779 states and 317880 transitions. [2022-10-17 10:57:45,247 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 218779 [2022-10-17 10:57:45,376 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 218779 [2022-10-17 10:57:45,377 INFO L73 IsDeterministic]: Start isDeterministic. Operand 218779 states and 317880 transitions. [2022-10-17 10:57:45,514 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:57:45,515 INFO L218 hiAutomatonCegarLoop]: Abstraction has 218779 states and 317880 transitions. [2022-10-17 10:57:45,726 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 218779 states and 317880 transitions. [2022-10-17 10:57:47,436 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 218779 to 99718. [2022-10-17 10:57:47,518 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 99718 states, 99718 states have (on average 1.4195130267353937) internal successors, (141551), 99717 states have internal predecessors, (141551), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:57:47,895 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99718 states to 99718 states and 141551 transitions. [2022-10-17 10:57:47,896 INFO L240 hiAutomatonCegarLoop]: Abstraction has 99718 states and 141551 transitions. [2022-10-17 10:57:47,896 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-10-17 10:57:47,897 INFO L428 stractBuchiCegarLoop]: Abstraction has 99718 states and 141551 transitions. [2022-10-17 10:57:47,897 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-10-17 10:57:47,897 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 99718 states and 141551 transitions. [2022-10-17 10:57:48,830 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 99093 [2022-10-17 10:57:48,831 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:57:48,831 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:57:48,846 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:57:48,846 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:57:48,846 INFO L748 eck$LassoCheckResult]: Stem: 560795#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 560796#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 560210#L1153 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 560211#L541 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 561046#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 560516#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 560517#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 560640#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 560641#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 560424#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 560206#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 560207#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 560383#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 560384#L781 assume !(0 == ~M_E~0); 560887#L781-2 assume !(0 == ~T1_E~0); 561112#L786-1 assume !(0 == ~T2_E~0); 560168#L791-1 assume !(0 == ~T3_E~0); 560169#L796-1 assume !(0 == ~T4_E~0); 560719#L801-1 assume !(0 == ~T5_E~0); 560720#L806-1 assume !(0 == ~T6_E~0); 560755#L811-1 assume !(0 == ~T7_E~0); 560389#L816-1 assume !(0 == ~E_M~0); 560390#L821-1 assume !(0 == ~E_1~0); 560196#L826-1 assume !(0 == ~E_2~0); 560197#L831-1 assume !(0 == ~E_3~0); 560513#L836-1 assume !(0 == ~E_4~0); 560514#L841-1 assume !(0 == ~E_5~0); 560342#L846-1 assume !(0 == ~E_6~0); 560343#L851-1 assume !(0 == ~E_7~0); 560364#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 560365#L388 assume !(1 == ~m_pc~0); 560358#L388-2 is_master_triggered_~__retres1~0#1 := 0; 560359#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 560856#L400 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 560214#L967 assume !(0 != activate_threads_~tmp~1#1); 560215#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 560146#L407 assume !(1 == ~t1_pc~0); 560147#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 560153#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 560125#L419 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 560126#L975 assume !(0 != activate_threads_~tmp___0~0#1); 560987#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 560470#L426 assume !(1 == ~t2_pc~0); 560471#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 561016#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 561077#L438 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 561071#L983 assume !(0 != activate_threads_~tmp___1~0#1); 561072#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 560554#L445 assume !(1 == ~t3_pc~0); 560555#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 560893#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 560360#L457 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 560361#L991 assume !(0 != activate_threads_~tmp___2~0#1); 560814#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 560780#L464 assume !(1 == ~t4_pc~0); 560367#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 560235#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 560236#L476 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 560567#L999 assume !(0 != activate_threads_~tmp___3~0#1); 560531#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 560532#L483 assume !(1 == ~t5_pc~0); 560778#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 560964#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 560695#L495 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 560696#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 560455#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 560456#L502 assume !(1 == ~t6_pc~0); 560314#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 560266#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 560267#L514 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 560677#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 560678#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 560934#L521 assume !(1 == ~t7_pc~0); 560983#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 560208#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 560209#L533 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 560976#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 560946#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 560840#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 560524#L869-2 assume !(1 == ~T1_E~0); 560525#L874-1 assume !(1 == ~T2_E~0); 561039#L879-1 assume !(1 == ~T3_E~0); 560607#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 560134#L889-1 assume !(1 == ~T5_E~0); 560135#L894-1 assume !(1 == ~T6_E~0); 560399#L899-1 assume !(1 == ~T7_E~0); 633704#L904-1 assume !(1 == ~E_M~0); 633703#L909-1 assume !(1 == ~E_1~0); 633702#L914-1 assume !(1 == ~E_2~0); 633701#L919-1 assume !(1 == ~E_3~0); 633700#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 633699#L929-1 assume !(1 == ~E_5~0); 633698#L934-1 assume !(1 == ~E_6~0); 561049#L939-1 assume !(1 == ~E_7~0); 633627#L944-1 assume { :end_inline_reset_delta_events } true; 633626#L1190-2 [2022-10-17 10:57:48,847 INFO L750 eck$LassoCheckResult]: Loop: 633626#L1190-2 assume !false; 633568#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 633567#L756 assume !false; 633565#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 633564#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 633502#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 633500#L639 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 633495#L653 assume !(0 != eval_~tmp~0#1); 633496#L771 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 636138#L541-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 636125#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 636054#L781-5 assume !(0 == ~T1_E~0); 636049#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 636045#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 636044#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 635951#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 635946#L806-3 assume !(0 == ~T6_E~0); 635940#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 635938#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 635936#L821-3 assume !(0 == ~E_1~0); 635927#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 635925#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 635923#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 635920#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 635915#L846-3 assume !(0 == ~E_6~0); 635913#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 635910#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 635909#L388-27 assume !(1 == ~m_pc~0); 635908#L388-29 is_master_triggered_~__retres1~0#1 := 0; 635907#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 635906#L400-9 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 635905#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 635904#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 635903#L407-27 assume !(1 == ~t1_pc~0); 635902#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 635901#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 635900#L419-9 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 635899#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 635898#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 635897#L426-27 assume 1 == ~t2_pc~0; 635896#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 635894#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 635893#L438-9 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 635892#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 635891#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 635890#L445-27 assume !(1 == ~t3_pc~0); 635889#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 635888#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 635887#L457-9 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 635886#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 635885#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 635884#L464-27 assume 1 == ~t4_pc~0; 635883#L465-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 635881#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 635880#L476-9 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 635879#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 635878#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 635877#L483-27 assume !(1 == ~t5_pc~0); 635876#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 635875#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 635874#L495-9 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 635873#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 635872#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 635871#L502-27 assume !(1 == ~t6_pc~0); 635870#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 635869#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 635868#L514-9 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 635867#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 635866#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 635865#L521-27 assume !(1 == ~t7_pc~0); 635864#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 635862#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 635860#L533-9 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 635858#L1023-27 assume !(0 != activate_threads_~tmp___6~0#1); 635856#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 635854#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 603519#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 635849#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 635847#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 635845#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 635843#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 635842#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 610488#L899-3 assume !(1 == ~T7_E~0); 635841#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 635840#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 635839#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 635838#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 635836#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 634174#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 634171#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 634166#L939-3 assume !(1 == ~E_7~0); 634164#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 634158#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 634149#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 634145#L639-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 634141#L1209 assume !(0 == start_simulation_~tmp~3#1); 634140#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 634128#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 634120#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 634115#L639-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 634103#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 634100#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 634097#L1172 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 633628#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 633626#L1190-2 [2022-10-17 10:57:48,847 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:57:48,848 INFO L85 PathProgramCache]: Analyzing trace with hash -492911425, now seen corresponding path program 1 times [2022-10-17 10:57:48,848 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:57:48,848 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [163887434] [2022-10-17 10:57:48,848 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:57:48,848 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:57:48,868 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:57:48,922 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:57:48,922 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:57:48,923 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [163887434] [2022-10-17 10:57:48,923 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [163887434] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:57:48,923 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:57:48,923 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-10-17 10:57:48,923 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1354163619] [2022-10-17 10:57:48,924 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:57:48,924 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:57:48,924 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:57:48,925 INFO L85 PathProgramCache]: Analyzing trace with hash -296004318, now seen corresponding path program 1 times [2022-10-17 10:57:48,925 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:57:48,925 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1792368039] [2022-10-17 10:57:48,925 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:57:48,926 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:57:48,942 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:57:48,985 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:57:48,985 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:57:48,985 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1792368039] [2022-10-17 10:57:48,985 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1792368039] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:57:48,986 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:57:48,986 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:57:48,986 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1048395817] [2022-10-17 10:57:48,986 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:57:48,987 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:57:48,987 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:57:48,987 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:57:48,988 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:57:48,988 INFO L87 Difference]: Start difference. First operand 99718 states and 141551 transitions. cyclomatic complexity: 41897 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 2 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)