./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.08.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version dbf71c69 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ed83a1ad-56ab-48dd-a4ce-2ae93b8e3699/bin/uautomizer-J5u9QxTXDZ/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ed83a1ad-56ab-48dd-a4ce-2ae93b8e3699/bin/uautomizer-J5u9QxTXDZ/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ed83a1ad-56ab-48dd-a4ce-2ae93b8e3699/bin/uautomizer-J5u9QxTXDZ/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ed83a1ad-56ab-48dd-a4ce-2ae93b8e3699/bin/uautomizer-J5u9QxTXDZ/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.08.cil-2.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ed83a1ad-56ab-48dd-a4ce-2ae93b8e3699/bin/uautomizer-J5u9QxTXDZ/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ed83a1ad-56ab-48dd-a4ce-2ae93b8e3699/bin/uautomizer-J5u9QxTXDZ --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 19daebdfafed51668fa57cd9e9dbb1892c2070de71da48d425d8df389215d260 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-dbf71c6-m [2022-10-17 10:47:01,596 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-10-17 10:47:01,598 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-10-17 10:47:01,628 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-10-17 10:47:01,629 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-10-17 10:47:01,630 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-10-17 10:47:01,632 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-10-17 10:47:01,634 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-10-17 10:47:01,636 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-10-17 10:47:01,638 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-10-17 10:47:01,639 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-10-17 10:47:01,640 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-10-17 10:47:01,641 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-10-17 10:47:01,642 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-10-17 10:47:01,644 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-10-17 10:47:01,645 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-10-17 10:47:01,646 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-10-17 10:47:01,648 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-10-17 10:47:01,650 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-10-17 10:47:01,653 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-10-17 10:47:01,655 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-10-17 10:47:01,657 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-10-17 10:47:01,658 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-10-17 10:47:01,660 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-10-17 10:47:01,665 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-10-17 10:47:01,665 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-10-17 10:47:01,666 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-10-17 10:47:01,667 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-10-17 10:47:01,667 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-10-17 10:47:01,669 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-10-17 10:47:01,669 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-10-17 10:47:01,670 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-10-17 10:47:01,671 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-10-17 10:47:01,672 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-10-17 10:47:01,673 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-10-17 10:47:01,674 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-10-17 10:47:01,675 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-10-17 10:47:01,675 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-10-17 10:47:01,676 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-10-17 10:47:01,677 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-10-17 10:47:01,678 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-10-17 10:47:01,679 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ed83a1ad-56ab-48dd-a4ce-2ae93b8e3699/bin/uautomizer-J5u9QxTXDZ/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-10-17 10:47:01,709 INFO L113 SettingsManager]: Loading preferences was successful [2022-10-17 10:47:01,710 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-10-17 10:47:01,710 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-10-17 10:47:01,710 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-10-17 10:47:01,721 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-10-17 10:47:01,721 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-10-17 10:47:01,721 INFO L138 SettingsManager]: * Use SBE=true [2022-10-17 10:47:01,722 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-10-17 10:47:01,722 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-10-17 10:47:01,722 INFO L138 SettingsManager]: * Use old map elimination=false [2022-10-17 10:47:01,723 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-10-17 10:47:01,724 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-10-17 10:47:01,724 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-10-17 10:47:01,724 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-10-17 10:47:01,724 INFO L138 SettingsManager]: * sizeof long=4 [2022-10-17 10:47:01,725 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-10-17 10:47:01,725 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-10-17 10:47:01,725 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-10-17 10:47:01,726 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-10-17 10:47:01,726 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-10-17 10:47:01,726 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-10-17 10:47:01,726 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-10-17 10:47:01,727 INFO L138 SettingsManager]: * sizeof long double=12 [2022-10-17 10:47:01,728 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-10-17 10:47:01,729 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-10-17 10:47:01,729 INFO L138 SettingsManager]: * Use constant arrays=true [2022-10-17 10:47:01,729 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-10-17 10:47:01,730 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-10-17 10:47:01,730 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-10-17 10:47:01,730 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-10-17 10:47:01,731 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-10-17 10:47:01,732 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-10-17 10:47:01,732 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ed83a1ad-56ab-48dd-a4ce-2ae93b8e3699/bin/uautomizer-J5u9QxTXDZ/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ed83a1ad-56ab-48dd-a4ce-2ae93b8e3699/bin/uautomizer-J5u9QxTXDZ Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 19daebdfafed51668fa57cd9e9dbb1892c2070de71da48d425d8df389215d260 [2022-10-17 10:47:02,044 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-10-17 10:47:02,063 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-10-17 10:47:02,066 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-10-17 10:47:02,067 INFO L271 PluginConnector]: Initializing CDTParser... [2022-10-17 10:47:02,068 INFO L275 PluginConnector]: CDTParser initialized [2022-10-17 10:47:02,070 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ed83a1ad-56ab-48dd-a4ce-2ae93b8e3699/bin/uautomizer-J5u9QxTXDZ/../../sv-benchmarks/c/systemc/token_ring.08.cil-2.c [2022-10-17 10:47:02,158 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ed83a1ad-56ab-48dd-a4ce-2ae93b8e3699/bin/uautomizer-J5u9QxTXDZ/data/aa62a22de/3489b4cd7cc641968bbe20ba7915e43f/FLAGd28e2aa5c [2022-10-17 10:47:02,632 INFO L306 CDTParser]: Found 1 translation units. [2022-10-17 10:47:02,633 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ed83a1ad-56ab-48dd-a4ce-2ae93b8e3699/sv-benchmarks/c/systemc/token_ring.08.cil-2.c [2022-10-17 10:47:02,646 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ed83a1ad-56ab-48dd-a4ce-2ae93b8e3699/bin/uautomizer-J5u9QxTXDZ/data/aa62a22de/3489b4cd7cc641968bbe20ba7915e43f/FLAGd28e2aa5c [2022-10-17 10:47:02,979 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ed83a1ad-56ab-48dd-a4ce-2ae93b8e3699/bin/uautomizer-J5u9QxTXDZ/data/aa62a22de/3489b4cd7cc641968bbe20ba7915e43f [2022-10-17 10:47:02,981 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-10-17 10:47:02,983 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-10-17 10:47:02,984 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-10-17 10:47:02,985 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-10-17 10:47:02,988 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-10-17 10:47:02,989 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.10 10:47:02" (1/1) ... [2022-10-17 10:47:02,990 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5dc4596d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:47:02, skipping insertion in model container [2022-10-17 10:47:02,990 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.10 10:47:02" (1/1) ... [2022-10-17 10:47:03,000 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-10-17 10:47:03,057 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-10-17 10:47:03,192 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ed83a1ad-56ab-48dd-a4ce-2ae93b8e3699/sv-benchmarks/c/systemc/token_ring.08.cil-2.c[671,684] [2022-10-17 10:47:03,336 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-10-17 10:47:03,346 INFO L203 MainTranslator]: Completed pre-run [2022-10-17 10:47:03,357 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ed83a1ad-56ab-48dd-a4ce-2ae93b8e3699/sv-benchmarks/c/systemc/token_ring.08.cil-2.c[671,684] [2022-10-17 10:47:03,458 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-10-17 10:47:03,481 INFO L208 MainTranslator]: Completed translation [2022-10-17 10:47:03,481 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:47:03 WrapperNode [2022-10-17 10:47:03,482 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-10-17 10:47:03,484 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-10-17 10:47:03,484 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-10-17 10:47:03,484 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-10-17 10:47:03,492 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:47:03" (1/1) ... [2022-10-17 10:47:03,521 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:47:03" (1/1) ... [2022-10-17 10:47:03,632 INFO L138 Inliner]: procedures = 44, calls = 56, calls flagged for inlining = 51, calls inlined = 158, statements flattened = 2370 [2022-10-17 10:47:03,633 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-10-17 10:47:03,633 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-10-17 10:47:03,634 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-10-17 10:47:03,634 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-10-17 10:47:03,643 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:47:03" (1/1) ... [2022-10-17 10:47:03,644 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:47:03" (1/1) ... [2022-10-17 10:47:03,652 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:47:03" (1/1) ... [2022-10-17 10:47:03,653 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:47:03" (1/1) ... [2022-10-17 10:47:03,689 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:47:03" (1/1) ... [2022-10-17 10:47:03,745 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:47:03" (1/1) ... [2022-10-17 10:47:03,749 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:47:03" (1/1) ... [2022-10-17 10:47:03,761 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:47:03" (1/1) ... [2022-10-17 10:47:03,775 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-10-17 10:47:03,777 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-10-17 10:47:03,777 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-10-17 10:47:03,778 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-10-17 10:47:03,782 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:47:03" (1/1) ... [2022-10-17 10:47:03,788 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:47:03,801 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ed83a1ad-56ab-48dd-a4ce-2ae93b8e3699/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:47:03,817 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ed83a1ad-56ab-48dd-a4ce-2ae93b8e3699/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:47:03,827 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ed83a1ad-56ab-48dd-a4ce-2ae93b8e3699/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-10-17 10:47:03,858 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-10-17 10:47:03,859 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-10-17 10:47:03,859 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-10-17 10:47:03,859 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-10-17 10:47:03,954 INFO L235 CfgBuilder]: Building ICFG [2022-10-17 10:47:03,957 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-10-17 10:47:05,636 INFO L276 CfgBuilder]: Performing block encoding [2022-10-17 10:47:05,656 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-10-17 10:47:05,656 INFO L300 CfgBuilder]: Removed 11 assume(true) statements. [2022-10-17 10:47:05,661 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 17.10 10:47:05 BoogieIcfgContainer [2022-10-17 10:47:05,661 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-10-17 10:47:05,662 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-10-17 10:47:05,662 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-10-17 10:47:05,666 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-10-17 10:47:05,667 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-10-17 10:47:05,667 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 17.10 10:47:02" (1/3) ... [2022-10-17 10:47:05,668 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@3357c2fc and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.10 10:47:05, skipping insertion in model container [2022-10-17 10:47:05,669 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-10-17 10:47:05,669 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:47:03" (2/3) ... [2022-10-17 10:47:05,669 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@3357c2fc and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.10 10:47:05, skipping insertion in model container [2022-10-17 10:47:05,669 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-10-17 10:47:05,670 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 17.10 10:47:05" (3/3) ... [2022-10-17 10:47:05,671 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.08.cil-2.c [2022-10-17 10:47:05,759 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-10-17 10:47:05,759 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-10-17 10:47:05,760 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-10-17 10:47:05,760 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-10-17 10:47:05,760 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-10-17 10:47:05,760 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-10-17 10:47:05,760 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-10-17 10:47:05,760 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-10-17 10:47:05,770 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1006 states, 1005 states have (on average 1.5154228855721392) internal successors, (1523), 1005 states have internal predecessors, (1523), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:47:05,853 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2022-10-17 10:47:05,853 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:47:05,853 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:47:05,869 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:47:05,870 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:47:05,870 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-10-17 10:47:05,873 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1006 states, 1005 states have (on average 1.5154228855721392) internal successors, (1523), 1005 states have internal predecessors, (1523), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:47:05,890 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2022-10-17 10:47:05,891 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:47:05,891 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:47:05,898 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:47:05,898 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:47:05,908 INFO L748 eck$LassoCheckResult]: Stem: 485#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 924#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 416#L1278true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 511#L602true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 304#L609true assume !(1 == ~m_i~0);~m_st~0 := 2; 1005#L609-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 65#L614-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 104#L619-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 710#L624-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 965#L629-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 50#L634-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 280#L639-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 854#L644-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 297#L649-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 107#L866true assume !(0 == ~M_E~0); 969#L866-2true assume !(0 == ~T1_E~0); 439#L871-1true assume !(0 == ~T2_E~0); 836#L876-1true assume !(0 == ~T3_E~0); 829#L881-1true assume !(0 == ~T4_E~0); 454#L886-1true assume 0 == ~T5_E~0;~T5_E~0 := 1; 275#L891-1true assume !(0 == ~T6_E~0); 442#L896-1true assume !(0 == ~T7_E~0); 574#L901-1true assume !(0 == ~T8_E~0); 465#L906-1true assume !(0 == ~E_M~0); 850#L911-1true assume !(0 == ~E_1~0); 303#L916-1true assume !(0 == ~E_2~0); 576#L921-1true assume !(0 == ~E_3~0); 731#L926-1true assume 0 == ~E_4~0;~E_4~0 := 1; 863#L931-1true assume !(0 == ~E_5~0); 890#L936-1true assume !(0 == ~E_6~0); 977#L941-1true assume !(0 == ~E_7~0); 306#L946-1true assume !(0 == ~E_8~0); 774#L951-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 895#L430true assume !(1 == ~m_pc~0); 678#L430-2true is_master_triggered_~__retres1~0#1 := 0; 19#L441true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 380#L442true activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 389#L1073true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 816#L1073-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 558#L449true assume 1 == ~t1_pc~0; 579#L450true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 812#L460true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2#L461true activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 901#L1081true assume !(0 != activate_threads_~tmp___0~0#1); 476#L1081-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 345#L468true assume !(1 == ~t2_pc~0); 225#L468-2true is_transmit2_triggered_~__retres1~2#1 := 0; 427#L479true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 279#L480true activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 218#L1089true assume !(0 != activate_threads_~tmp___1~0#1); 20#L1089-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 893#L487true assume 1 == ~t3_pc~0; 817#L488true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 67#L498true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 541#L499true activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 629#L1097true assume !(0 != activate_threads_~tmp___2~0#1); 261#L1097-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 342#L506true assume !(1 == ~t4_pc~0); 847#L506-2true is_transmit4_triggered_~__retres1~4#1 := 0; 970#L517true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 751#L518true activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 818#L1105true assume !(0 != activate_threads_~tmp___3~0#1); 336#L1105-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 226#L525true assume 1 == ~t5_pc~0; 187#L526true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 699#L536true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 309#L537true activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 954#L1113true assume !(0 != activate_threads_~tmp___4~0#1); 139#L1113-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 333#L544true assume !(1 == ~t6_pc~0); 227#L544-2true is_transmit6_triggered_~__retres1~6#1 := 0; 494#L555true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 997#L556true activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 31#L1121true assume !(0 != activate_threads_~tmp___5~0#1); 791#L1121-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 695#L563true assume 1 == ~t7_pc~0; 513#L564true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 44#L574true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 367#L575true activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 276#L1129true assume !(0 != activate_threads_~tmp___6~0#1); 111#L1129-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 495#L582true assume 1 == ~t8_pc~0; 72#L583true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 820#L593true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 980#L594true activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 252#L1137true assume !(0 != activate_threads_~tmp___7~0#1); 189#L1137-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 560#L964true assume 1 == ~M_E~0;~M_E~0 := 2; 815#L964-2true assume !(1 == ~T1_E~0); 140#L969-1true assume !(1 == ~T2_E~0); 744#L974-1true assume !(1 == ~T3_E~0); 596#L979-1true assume !(1 == ~T4_E~0); 949#L984-1true assume !(1 == ~T5_E~0); 230#L989-1true assume !(1 == ~T6_E~0); 448#L994-1true assume !(1 == ~T7_E~0); 162#L999-1true assume 1 == ~T8_E~0;~T8_E~0 := 2; 565#L1004-1true assume !(1 == ~E_M~0); 32#L1009-1true assume !(1 == ~E_1~0); 156#L1014-1true assume !(1 == ~E_2~0); 548#L1019-1true assume !(1 == ~E_3~0); 790#L1024-1true assume !(1 == ~E_4~0); 119#L1029-1true assume !(1 == ~E_5~0); 171#L1034-1true assume !(1 == ~E_6~0); 981#L1039-1true assume 1 == ~E_7~0;~E_7~0 := 2; 759#L1044-1true assume !(1 == ~E_8~0); 285#L1049-1true assume { :end_inline_reset_delta_events } true; 103#L1315-2true [2022-10-17 10:47:05,911 INFO L750 eck$LassoCheckResult]: Loop: 103#L1315-2true assume !false; 872#L1316true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 172#L841true assume false; 616#L856true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 986#L602-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 23#L866-3true assume 0 == ~M_E~0;~M_E~0 := 1; 825#L866-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 175#L871-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 264#L876-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 183#L881-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 665#L886-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 322#L891-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 451#L896-3true assume !(0 == ~T7_E~0); 239#L901-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 324#L906-3true assume 0 == ~E_M~0;~E_M~0 := 1; 586#L911-3true assume 0 == ~E_1~0;~E_1~0 := 1; 504#L916-3true assume 0 == ~E_2~0;~E_2~0 := 1; 199#L921-3true assume 0 == ~E_3~0;~E_3~0 := 1; 487#L926-3true assume 0 == ~E_4~0;~E_4~0 := 1; 582#L931-3true assume 0 == ~E_5~0;~E_5~0 := 1; 244#L936-3true assume !(0 == ~E_6~0); 335#L941-3true assume 0 == ~E_7~0;~E_7~0 := 1; 585#L946-3true assume 0 == ~E_8~0;~E_8~0 := 1; 176#L951-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 864#L430-30true assume 1 == ~m_pc~0; 190#L431-10true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 249#L441-10true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 74#L442-10true activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 530#L1073-30true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 916#L1073-32true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 538#L449-30true assume !(1 == ~t1_pc~0); 928#L449-32true is_transmit1_triggered_~__retres1~1#1 := 0; 30#L460-10true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 446#L461-10true activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 229#L1081-30true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 70#L1081-32true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 381#L468-30true assume !(1 == ~t2_pc~0); 799#L468-32true is_transmit2_triggered_~__retres1~2#1 := 0; 592#L479-10true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 897#L480-10true activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 317#L1089-30true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 772#L1089-32true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 221#L487-30true assume !(1 == ~t3_pc~0); 106#L487-32true is_transmit3_triggered_~__retres1~3#1 := 0; 842#L498-10true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 305#L499-10true activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 802#L1097-30true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 556#L1097-32true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 271#L506-30true assume 1 == ~t4_pc~0; 982#L507-10true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 287#L517-10true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 300#L518-10true activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 613#L1105-30true assume !(0 != activate_threads_~tmp___3~0#1); 222#L1105-32true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 971#L525-30true assume !(1 == ~t5_pc~0); 827#L525-32true is_transmit5_triggered_~__retres1~5#1 := 0; 919#L536-10true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 62#L537-10true activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 671#L1113-30true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 224#L1113-32true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 95#L544-30true assume !(1 == ~t6_pc~0); 740#L544-32true is_transmit6_triggered_~__retres1~6#1 := 0; 867#L555-10true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 991#L556-10true activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 701#L1121-30true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 993#L1121-32true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 661#L563-30true assume !(1 == ~t7_pc~0); 164#L563-32true is_transmit7_triggered_~__retres1~7#1 := 0; 89#L574-10true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 938#L575-10true activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 281#L1129-30true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 908#L1129-32true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 639#L582-30true assume !(1 == ~t8_pc~0); 132#L582-32true is_transmit8_triggered_~__retres1~8#1 := 0; 273#L593-10true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 692#L594-10true activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 990#L1137-30true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 903#L1137-32true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35#L964-3true assume 1 == ~M_E~0;~M_E~0 := 2; 101#L964-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 208#L969-3true assume !(1 == ~T2_E~0); 97#L974-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 920#L979-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 348#L984-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 985#L989-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 121#L994-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 823#L999-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 473#L1004-3true assume 1 == ~E_M~0;~E_M~0 := 2; 58#L1009-3true assume !(1 == ~E_1~0); 542#L1014-3true assume 1 == ~E_2~0;~E_2~0 := 2; 330#L1019-3true assume 1 == ~E_3~0;~E_3~0 := 2; 967#L1024-3true assume 1 == ~E_4~0;~E_4~0 := 2; 319#L1029-3true assume 1 == ~E_5~0;~E_5~0 := 2; 301#L1034-3true assume 1 == ~E_6~0;~E_6~0 := 2; 547#L1039-3true assume 1 == ~E_7~0;~E_7~0 := 2; 577#L1044-3true assume 1 == ~E_8~0;~E_8~0 := 2; 116#L1049-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 452#L662-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 686#L709-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 424#L710-1true start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 135#L1334true assume !(0 == start_simulation_~tmp~3#1); 811#L1334-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 145#L662-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 4#L709-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 334#L710-2true stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 917#L1289true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 734#L1296true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 496#L1297true start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 709#L1347true assume !(0 != start_simulation_~tmp___0~1#1); 103#L1315-2true [2022-10-17 10:47:05,918 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:47:05,918 INFO L85 PathProgramCache]: Analyzing trace with hash -1103313420, now seen corresponding path program 1 times [2022-10-17 10:47:05,928 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:47:05,928 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1964750603] [2022-10-17 10:47:05,929 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:47:05,929 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:47:06,037 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:47:06,233 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:47:06,234 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:47:06,236 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1964750603] [2022-10-17 10:47:06,237 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1964750603] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:47:06,237 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:47:06,237 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:47:06,239 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1674657474] [2022-10-17 10:47:06,240 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:47:06,245 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:47:06,249 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:47:06,249 INFO L85 PathProgramCache]: Analyzing trace with hash 209993047, now seen corresponding path program 1 times [2022-10-17 10:47:06,249 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:47:06,250 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1122089603] [2022-10-17 10:47:06,251 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:47:06,251 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:47:06,279 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:47:06,369 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:47:06,374 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:47:06,375 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1122089603] [2022-10-17 10:47:06,375 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1122089603] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:47:06,375 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:47:06,376 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-10-17 10:47:06,376 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1079819171] [2022-10-17 10:47:06,376 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:47:06,378 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:47:06,379 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:47:06,415 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:47:06,416 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:47:06,420 INFO L87 Difference]: Start difference. First operand has 1006 states, 1005 states have (on average 1.5154228855721392) internal successors, (1523), 1005 states have internal predecessors, (1523), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:47:06,528 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:47:06,529 INFO L93 Difference]: Finished difference Result 1004 states and 1496 transitions. [2022-10-17 10:47:06,530 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1004 states and 1496 transitions. [2022-10-17 10:47:06,546 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 883 [2022-10-17 10:47:06,563 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1004 states to 998 states and 1490 transitions. [2022-10-17 10:47:06,564 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 998 [2022-10-17 10:47:06,566 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 998 [2022-10-17 10:47:06,567 INFO L73 IsDeterministic]: Start isDeterministic. Operand 998 states and 1490 transitions. [2022-10-17 10:47:06,577 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:47:06,577 INFO L218 hiAutomatonCegarLoop]: Abstraction has 998 states and 1490 transitions. [2022-10-17 10:47:06,600 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 998 states and 1490 transitions. [2022-10-17 10:47:06,665 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 998 to 998. [2022-10-17 10:47:06,675 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 998 states, 998 states have (on average 1.4929859719438878) internal successors, (1490), 997 states have internal predecessors, (1490), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:47:06,680 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 998 states to 998 states and 1490 transitions. [2022-10-17 10:47:06,682 INFO L240 hiAutomatonCegarLoop]: Abstraction has 998 states and 1490 transitions. [2022-10-17 10:47:06,683 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:47:06,686 INFO L428 stractBuchiCegarLoop]: Abstraction has 998 states and 1490 transitions. [2022-10-17 10:47:06,687 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-10-17 10:47:06,687 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 998 states and 1490 transitions. [2022-10-17 10:47:06,695 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 883 [2022-10-17 10:47:06,695 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:47:06,695 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:47:06,698 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:47:06,698 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:47:06,699 INFO L748 eck$LassoCheckResult]: Stem: 2789#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 2790#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 2716#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2717#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2569#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 2570#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2155#L614-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 2156#L619-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2237#L624-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2948#L629-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2125#L634-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 2126#L639-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 2533#L644-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 2558#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2241#L866 assume !(0 == ~M_E~0); 2242#L866-2 assume !(0 == ~T1_E~0); 2744#L871-1 assume !(0 == ~T2_E~0); 2745#L876-1 assume !(0 == ~T3_E~0); 2995#L881-1 assume !(0 == ~T4_E~0); 2754#L886-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2524#L891-1 assume !(0 == ~T6_E~0); 2525#L896-1 assume !(0 == ~T7_E~0); 2747#L901-1 assume !(0 == ~T8_E~0); 2765#L906-1 assume !(0 == ~E_M~0); 2766#L911-1 assume !(0 == ~E_1~0); 2567#L916-1 assume !(0 == ~E_2~0); 2568#L921-1 assume !(0 == ~E_3~0); 2861#L926-1 assume 0 == ~E_4~0;~E_4~0 := 1; 2960#L931-1 assume !(0 == ~E_5~0); 3000#L936-1 assume !(0 == ~E_6~0); 3007#L941-1 assume !(0 == ~E_7~0); 2573#L946-1 assume !(0 == ~E_8~0); 2574#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2979#L430 assume !(1 == ~m_pc~0); 2432#L430-2 is_master_triggered_~__retres1~0#1 := 0; 2060#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2061#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2674#L1073 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2684#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2845#L449 assume 1 == ~t1_pc~0; 2846#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2245#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2019#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2020#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 2780#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2629#L468 assume !(1 == ~t2_pc~0); 2044#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2043#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2532#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2439#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 2062#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2063#L487 assume 1 == ~t3_pc~0; 2992#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2159#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2160#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2834#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 2498#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2499#L506 assume !(1 == ~t4_pc~0); 2625#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2670#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2970#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2971#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 2620#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2450#L525 assume 1 == ~t5_pc~0; 2385#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2104#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2577#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2578#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 2301#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2302#L544 assume !(1 == ~t6_pc~0); 2451#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2452#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2796#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2086#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 2087#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2936#L563 assume 1 == ~t7_pc~0; 2814#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2114#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2115#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2526#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 2246#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2247#L582 assume 1 == ~t8_pc~0; 2170#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 2171#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2993#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2487#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 2389#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2390#L964 assume 1 == ~M_E~0;~M_E~0 := 2; 2848#L964-2 assume !(1 == ~T1_E~0); 2303#L969-1 assume !(1 == ~T2_E~0); 2304#L974-1 assume !(1 == ~T3_E~0); 2873#L979-1 assume !(1 == ~T4_E~0); 2874#L984-1 assume !(1 == ~T5_E~0); 2457#L989-1 assume !(1 == ~T6_E~0); 2458#L994-1 assume !(1 == ~T7_E~0); 2343#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2344#L1004-1 assume !(1 == ~E_M~0); 2088#L1009-1 assume !(1 == ~E_1~0); 2089#L1014-1 assume !(1 == ~E_2~0); 2332#L1019-1 assume !(1 == ~E_3~0); 2837#L1024-1 assume !(1 == ~E_4~0); 2265#L1029-1 assume !(1 == ~E_5~0); 2266#L1034-1 assume !(1 == ~E_6~0); 2360#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 2974#L1044-1 assume !(1 == ~E_8~0); 2542#L1049-1 assume { :end_inline_reset_delta_events } true; 2235#L1315-2 [2022-10-17 10:47:06,700 INFO L750 eck$LassoCheckResult]: Loop: 2235#L1315-2 assume !false; 2236#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2022#L841 assume !false; 2361#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2296#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2297#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2137#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2057#L724 assume !(0 != eval_~tmp~0#1); 2059#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2887#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2068#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2069#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2364#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2365#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2378#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2379#L886-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2602#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2603#L896-3 assume !(0 == ~T7_E~0); 2470#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2471#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2604#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2807#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2410#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2411#L926-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2791#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2477#L936-3 assume !(0 == ~E_6~0); 2478#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2619#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2366#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2367#L430-30 assume 1 == ~m_pc~0; 2391#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2392#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2175#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2176#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2825#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2829#L449-30 assume 1 == ~t1_pc~0; 2394#L450-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2084#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2085#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2456#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2168#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2169#L468-30 assume 1 == ~t2_pc~0; 2260#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2261#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2870#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2593#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2594#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2444#L487-30 assume 1 == ~t3_pc~0; 2425#L488-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2240#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2571#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2572#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2844#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2518#L506-30 assume !(1 == ~t4_pc~0); 2519#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 2545#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2546#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2563#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 2445#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2446#L525-30 assume 1 == ~t5_pc~0; 2931#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2932#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2150#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2151#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2449#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2219#L544-30 assume 1 == ~t6_pc~0; 2027#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2028#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3001#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2941#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2942#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2918#L563-30 assume 1 == ~t7_pc~0; 2189#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2190#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2208#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2534#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2535#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2905#L582-30 assume 1 == ~t8_pc~0; 2867#L583-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 2287#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2522#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2935#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3008#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2093#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2094#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2231#L969-3 assume !(1 == ~T2_E~0); 2222#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2223#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2634#L984-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2635#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2268#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2269#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2778#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2140#L1009-3 assume !(1 == ~E_1~0); 2141#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2615#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2616#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2597#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2564#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2565#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2836#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2258#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2259#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2388#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2725#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 2292#L1334 assume !(0 == start_simulation_~tmp~3#1); 2294#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2312#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2023#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2024#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 2618#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2962#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2797#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 2798#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 2235#L1315-2 [2022-10-17 10:47:06,700 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:47:06,700 INFO L85 PathProgramCache]: Analyzing trace with hash 763395254, now seen corresponding path program 1 times [2022-10-17 10:47:06,701 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:47:06,701 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [634648457] [2022-10-17 10:47:06,701 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:47:06,701 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:47:06,740 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:47:06,814 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:47:06,814 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:47:06,814 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [634648457] [2022-10-17 10:47:06,814 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [634648457] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:47:06,815 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:47:06,815 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:47:06,815 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1080233121] [2022-10-17 10:47:06,815 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:47:06,816 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:47:06,816 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:47:06,816 INFO L85 PathProgramCache]: Analyzing trace with hash 1016404398, now seen corresponding path program 1 times [2022-10-17 10:47:06,817 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:47:06,817 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1940032510] [2022-10-17 10:47:06,817 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:47:06,817 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:47:06,845 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:47:06,910 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:47:06,910 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:47:06,910 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1940032510] [2022-10-17 10:47:06,911 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1940032510] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:47:06,911 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:47:06,911 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:47:06,911 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1456883613] [2022-10-17 10:47:06,911 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:47:06,912 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:47:06,912 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:47:06,913 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:47:06,913 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:47:06,913 INFO L87 Difference]: Start difference. First operand 998 states and 1490 transitions. cyclomatic complexity: 493 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:47:06,960 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:47:06,960 INFO L93 Difference]: Finished difference Result 998 states and 1489 transitions. [2022-10-17 10:47:06,960 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 998 states and 1489 transitions. [2022-10-17 10:47:06,970 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 883 [2022-10-17 10:47:06,979 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 998 states to 998 states and 1489 transitions. [2022-10-17 10:47:06,979 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 998 [2022-10-17 10:47:06,980 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 998 [2022-10-17 10:47:06,980 INFO L73 IsDeterministic]: Start isDeterministic. Operand 998 states and 1489 transitions. [2022-10-17 10:47:06,982 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:47:06,982 INFO L218 hiAutomatonCegarLoop]: Abstraction has 998 states and 1489 transitions. [2022-10-17 10:47:06,984 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 998 states and 1489 transitions. [2022-10-17 10:47:06,998 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 998 to 998. [2022-10-17 10:47:07,000 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 998 states, 998 states have (on average 1.4919839679358717) internal successors, (1489), 997 states have internal predecessors, (1489), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:47:07,005 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 998 states to 998 states and 1489 transitions. [2022-10-17 10:47:07,006 INFO L240 hiAutomatonCegarLoop]: Abstraction has 998 states and 1489 transitions. [2022-10-17 10:47:07,006 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:47:07,007 INFO L428 stractBuchiCegarLoop]: Abstraction has 998 states and 1489 transitions. [2022-10-17 10:47:07,007 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-10-17 10:47:07,007 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 998 states and 1489 transitions. [2022-10-17 10:47:07,014 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 883 [2022-10-17 10:47:07,014 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:47:07,015 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:47:07,017 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:47:07,017 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:47:07,018 INFO L748 eck$LassoCheckResult]: Stem: 4792#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 4793#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 4719#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4720#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4572#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 4573#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4158#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4159#L619-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4240#L624-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4951#L629-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4128#L634-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4129#L639-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4536#L644-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4561#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4244#L866 assume !(0 == ~M_E~0); 4245#L866-2 assume !(0 == ~T1_E~0); 4747#L871-1 assume !(0 == ~T2_E~0); 4748#L876-1 assume !(0 == ~T3_E~0); 4998#L881-1 assume !(0 == ~T4_E~0); 4757#L886-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4527#L891-1 assume !(0 == ~T6_E~0); 4528#L896-1 assume !(0 == ~T7_E~0); 4750#L901-1 assume !(0 == ~T8_E~0); 4768#L906-1 assume !(0 == ~E_M~0); 4769#L911-1 assume !(0 == ~E_1~0); 4570#L916-1 assume !(0 == ~E_2~0); 4571#L921-1 assume !(0 == ~E_3~0); 4864#L926-1 assume 0 == ~E_4~0;~E_4~0 := 1; 4963#L931-1 assume !(0 == ~E_5~0); 5003#L936-1 assume !(0 == ~E_6~0); 5010#L941-1 assume !(0 == ~E_7~0); 4576#L946-1 assume !(0 == ~E_8~0); 4577#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4982#L430 assume !(1 == ~m_pc~0); 4435#L430-2 is_master_triggered_~__retres1~0#1 := 0; 4063#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4064#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4677#L1073 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4687#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4848#L449 assume 1 == ~t1_pc~0; 4849#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4248#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4022#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4023#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 4783#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4632#L468 assume !(1 == ~t2_pc~0); 4047#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4046#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4535#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4442#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 4065#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4066#L487 assume 1 == ~t3_pc~0; 4995#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4162#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4163#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4837#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 4501#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4502#L506 assume !(1 == ~t4_pc~0); 4628#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4673#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4973#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4974#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 4623#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4453#L525 assume 1 == ~t5_pc~0; 4388#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4107#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4580#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4581#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 4304#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4305#L544 assume !(1 == ~t6_pc~0); 4454#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4455#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4799#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4089#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 4090#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4939#L563 assume 1 == ~t7_pc~0; 4817#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4117#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4118#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4529#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 4249#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4250#L582 assume 1 == ~t8_pc~0; 4173#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4174#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4996#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4490#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 4392#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4393#L964 assume 1 == ~M_E~0;~M_E~0 := 2; 4851#L964-2 assume !(1 == ~T1_E~0); 4306#L969-1 assume !(1 == ~T2_E~0); 4307#L974-1 assume !(1 == ~T3_E~0); 4876#L979-1 assume !(1 == ~T4_E~0); 4877#L984-1 assume !(1 == ~T5_E~0); 4460#L989-1 assume !(1 == ~T6_E~0); 4461#L994-1 assume !(1 == ~T7_E~0); 4346#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4347#L1004-1 assume !(1 == ~E_M~0); 4091#L1009-1 assume !(1 == ~E_1~0); 4092#L1014-1 assume !(1 == ~E_2~0); 4335#L1019-1 assume !(1 == ~E_3~0); 4840#L1024-1 assume !(1 == ~E_4~0); 4268#L1029-1 assume !(1 == ~E_5~0); 4269#L1034-1 assume !(1 == ~E_6~0); 4363#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 4977#L1044-1 assume !(1 == ~E_8~0); 4545#L1049-1 assume { :end_inline_reset_delta_events } true; 4238#L1315-2 [2022-10-17 10:47:07,018 INFO L750 eck$LassoCheckResult]: Loop: 4238#L1315-2 assume !false; 4239#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4025#L841 assume !false; 4364#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4299#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 4300#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4140#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 4060#L724 assume !(0 != eval_~tmp~0#1); 4062#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4890#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4071#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4072#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4367#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4368#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4381#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4382#L886-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4605#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4606#L896-3 assume !(0 == ~T7_E~0); 4473#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4474#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4607#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4810#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4413#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4414#L926-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4794#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4480#L936-3 assume !(0 == ~E_6~0); 4481#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4622#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4369#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4370#L430-30 assume 1 == ~m_pc~0; 4394#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4395#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4178#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4179#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4828#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4832#L449-30 assume 1 == ~t1_pc~0; 4397#L450-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4087#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4088#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4459#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4171#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4172#L468-30 assume 1 == ~t2_pc~0; 4263#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4264#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4873#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4596#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4597#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4447#L487-30 assume !(1 == ~t3_pc~0); 4242#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 4243#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4574#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4575#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4847#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4521#L506-30 assume !(1 == ~t4_pc~0); 4522#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 4548#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4549#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4566#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 4448#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4449#L525-30 assume 1 == ~t5_pc~0; 4934#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4935#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4153#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4154#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4452#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4222#L544-30 assume !(1 == ~t6_pc~0); 4032#L544-32 is_transmit6_triggered_~__retres1~6#1 := 0; 4031#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5004#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4944#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4945#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4921#L563-30 assume 1 == ~t7_pc~0; 4192#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4193#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4211#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4537#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4538#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4908#L582-30 assume !(1 == ~t8_pc~0); 4289#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 4290#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4525#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4938#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 5011#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4096#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4097#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4234#L969-3 assume !(1 == ~T2_E~0); 4225#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4226#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4637#L984-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4638#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4271#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4272#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4781#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4143#L1009-3 assume !(1 == ~E_1~0); 4144#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4618#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4619#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4600#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4567#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4568#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4839#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4261#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4262#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 4391#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4728#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 4295#L1334 assume !(0 == start_simulation_~tmp~3#1); 4297#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4315#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 4026#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4027#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 4621#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4965#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4800#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 4801#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 4238#L1315-2 [2022-10-17 10:47:07,019 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:47:07,019 INFO L85 PathProgramCache]: Analyzing trace with hash -1134101512, now seen corresponding path program 1 times [2022-10-17 10:47:07,019 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:47:07,019 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1958428316] [2022-10-17 10:47:07,019 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:47:07,020 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:47:07,037 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:47:07,118 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:47:07,118 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:47:07,119 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1958428316] [2022-10-17 10:47:07,119 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1958428316] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:47:07,119 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:47:07,119 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:47:07,120 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1018457756] [2022-10-17 10:47:07,126 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:47:07,127 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:47:07,127 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:47:07,128 INFO L85 PathProgramCache]: Analyzing trace with hash 1452394673, now seen corresponding path program 1 times [2022-10-17 10:47:07,128 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:47:07,128 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [741373498] [2022-10-17 10:47:07,128 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:47:07,128 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:47:07,147 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:47:07,216 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:47:07,221 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:47:07,221 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [741373498] [2022-10-17 10:47:07,223 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [741373498] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:47:07,223 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:47:07,223 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:47:07,224 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1260033590] [2022-10-17 10:47:07,224 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:47:07,224 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:47:07,226 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:47:07,226 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:47:07,226 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:47:07,227 INFO L87 Difference]: Start difference. First operand 998 states and 1489 transitions. cyclomatic complexity: 492 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:47:07,251 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:47:07,251 INFO L93 Difference]: Finished difference Result 998 states and 1488 transitions. [2022-10-17 10:47:07,251 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 998 states and 1488 transitions. [2022-10-17 10:47:07,283 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 883 [2022-10-17 10:47:07,292 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 998 states to 998 states and 1488 transitions. [2022-10-17 10:47:07,292 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 998 [2022-10-17 10:47:07,294 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 998 [2022-10-17 10:47:07,294 INFO L73 IsDeterministic]: Start isDeterministic. Operand 998 states and 1488 transitions. [2022-10-17 10:47:07,296 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:47:07,296 INFO L218 hiAutomatonCegarLoop]: Abstraction has 998 states and 1488 transitions. [2022-10-17 10:47:07,298 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 998 states and 1488 transitions. [2022-10-17 10:47:07,314 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 998 to 998. [2022-10-17 10:47:07,317 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 998 states, 998 states have (on average 1.4909819639278556) internal successors, (1488), 997 states have internal predecessors, (1488), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:47:07,323 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 998 states to 998 states and 1488 transitions. [2022-10-17 10:47:07,323 INFO L240 hiAutomatonCegarLoop]: Abstraction has 998 states and 1488 transitions. [2022-10-17 10:47:07,323 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:47:07,324 INFO L428 stractBuchiCegarLoop]: Abstraction has 998 states and 1488 transitions. [2022-10-17 10:47:07,325 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-10-17 10:47:07,325 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 998 states and 1488 transitions. [2022-10-17 10:47:07,332 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 883 [2022-10-17 10:47:07,332 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:47:07,333 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:47:07,335 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:47:07,335 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:47:07,336 INFO L748 eck$LassoCheckResult]: Stem: 6795#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 6796#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 6722#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6723#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6575#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 6576#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6161#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6162#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6243#L624-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 6954#L629-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6131#L634-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6132#L639-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6539#L644-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 6564#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6247#L866 assume !(0 == ~M_E~0); 6248#L866-2 assume !(0 == ~T1_E~0); 6750#L871-1 assume !(0 == ~T2_E~0); 6751#L876-1 assume !(0 == ~T3_E~0); 7001#L881-1 assume !(0 == ~T4_E~0); 6760#L886-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6530#L891-1 assume !(0 == ~T6_E~0); 6531#L896-1 assume !(0 == ~T7_E~0); 6753#L901-1 assume !(0 == ~T8_E~0); 6771#L906-1 assume !(0 == ~E_M~0); 6772#L911-1 assume !(0 == ~E_1~0); 6573#L916-1 assume !(0 == ~E_2~0); 6574#L921-1 assume !(0 == ~E_3~0); 6867#L926-1 assume 0 == ~E_4~0;~E_4~0 := 1; 6966#L931-1 assume !(0 == ~E_5~0); 7006#L936-1 assume !(0 == ~E_6~0); 7013#L941-1 assume !(0 == ~E_7~0); 6579#L946-1 assume !(0 == ~E_8~0); 6580#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6985#L430 assume !(1 == ~m_pc~0); 6438#L430-2 is_master_triggered_~__retres1~0#1 := 0; 6066#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6067#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6680#L1073 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6690#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6851#L449 assume 1 == ~t1_pc~0; 6852#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6251#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6025#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6026#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 6786#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6635#L468 assume !(1 == ~t2_pc~0); 6050#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 6049#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6538#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6445#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 6068#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6069#L487 assume 1 == ~t3_pc~0; 6998#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6165#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6166#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6840#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 6504#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6505#L506 assume !(1 == ~t4_pc~0); 6631#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 6676#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6976#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6977#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 6626#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6456#L525 assume 1 == ~t5_pc~0; 6391#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6110#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6583#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6584#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 6307#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6308#L544 assume !(1 == ~t6_pc~0); 6457#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 6458#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6802#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6092#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 6093#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6942#L563 assume 1 == ~t7_pc~0; 6820#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6120#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6121#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6532#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 6252#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6253#L582 assume 1 == ~t8_pc~0; 6176#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 6177#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6999#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6493#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 6395#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6396#L964 assume 1 == ~M_E~0;~M_E~0 := 2; 6854#L964-2 assume !(1 == ~T1_E~0); 6309#L969-1 assume !(1 == ~T2_E~0); 6310#L974-1 assume !(1 == ~T3_E~0); 6879#L979-1 assume !(1 == ~T4_E~0); 6880#L984-1 assume !(1 == ~T5_E~0); 6463#L989-1 assume !(1 == ~T6_E~0); 6464#L994-1 assume !(1 == ~T7_E~0); 6349#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6350#L1004-1 assume !(1 == ~E_M~0); 6094#L1009-1 assume !(1 == ~E_1~0); 6095#L1014-1 assume !(1 == ~E_2~0); 6338#L1019-1 assume !(1 == ~E_3~0); 6843#L1024-1 assume !(1 == ~E_4~0); 6271#L1029-1 assume !(1 == ~E_5~0); 6272#L1034-1 assume !(1 == ~E_6~0); 6366#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 6980#L1044-1 assume !(1 == ~E_8~0); 6548#L1049-1 assume { :end_inline_reset_delta_events } true; 6241#L1315-2 [2022-10-17 10:47:07,337 INFO L750 eck$LassoCheckResult]: Loop: 6241#L1315-2 assume !false; 6242#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6028#L841 assume !false; 6367#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 6302#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 6303#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 6143#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 6063#L724 assume !(0 != eval_~tmp~0#1); 6065#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6893#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6074#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6075#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6370#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6371#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6384#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6385#L886-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6608#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6609#L896-3 assume !(0 == ~T7_E~0); 6476#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 6477#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 6610#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6813#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6416#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6417#L926-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6797#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6483#L936-3 assume !(0 == ~E_6~0); 6484#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 6625#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 6372#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6373#L430-30 assume 1 == ~m_pc~0; 6397#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 6398#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6181#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6182#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6831#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6835#L449-30 assume 1 == ~t1_pc~0; 6400#L450-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6090#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6091#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6462#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6174#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6175#L468-30 assume 1 == ~t2_pc~0; 6266#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6267#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6876#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6599#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6600#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6450#L487-30 assume !(1 == ~t3_pc~0); 6245#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 6246#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6577#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6578#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6850#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6524#L506-30 assume !(1 == ~t4_pc~0); 6525#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 6551#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6552#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6569#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 6451#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6452#L525-30 assume 1 == ~t5_pc~0; 6937#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6938#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6156#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6157#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6455#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6225#L544-30 assume 1 == ~t6_pc~0; 6033#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6034#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7007#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6947#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6948#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6924#L563-30 assume 1 == ~t7_pc~0; 6195#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6196#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6214#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6540#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 6541#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6911#L582-30 assume !(1 == ~t8_pc~0); 6292#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 6293#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6528#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6941#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7014#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6099#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6100#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6237#L969-3 assume !(1 == ~T2_E~0); 6228#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6229#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6640#L984-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6641#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6274#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6275#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6784#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6146#L1009-3 assume !(1 == ~E_1~0); 6147#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6621#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6622#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6603#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6570#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6571#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 6842#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 6264#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 6265#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 6394#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 6731#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 6298#L1334 assume !(0 == start_simulation_~tmp~3#1); 6300#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 6318#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 6029#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 6030#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 6624#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6968#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6803#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 6804#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 6241#L1315-2 [2022-10-17 10:47:07,337 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:47:07,338 INFO L85 PathProgramCache]: Analyzing trace with hash 2129824886, now seen corresponding path program 1 times [2022-10-17 10:47:07,338 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:47:07,338 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [252520692] [2022-10-17 10:47:07,339 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:47:07,339 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:47:07,355 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:47:07,391 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:47:07,391 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:47:07,391 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [252520692] [2022-10-17 10:47:07,392 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [252520692] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:47:07,392 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:47:07,392 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:47:07,392 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1738100700] [2022-10-17 10:47:07,393 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:47:07,393 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:47:07,394 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:47:07,394 INFO L85 PathProgramCache]: Analyzing trace with hash -15808656, now seen corresponding path program 1 times [2022-10-17 10:47:07,394 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:47:07,394 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [85124858] [2022-10-17 10:47:07,395 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:47:07,395 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:47:07,413 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:47:07,461 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:47:07,461 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:47:07,461 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [85124858] [2022-10-17 10:47:07,462 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [85124858] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:47:07,462 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:47:07,462 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:47:07,462 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [143706918] [2022-10-17 10:47:07,463 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:47:07,463 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:47:07,463 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:47:07,464 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:47:07,464 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:47:07,465 INFO L87 Difference]: Start difference. First operand 998 states and 1488 transitions. cyclomatic complexity: 491 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:47:07,492 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:47:07,492 INFO L93 Difference]: Finished difference Result 998 states and 1487 transitions. [2022-10-17 10:47:07,492 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 998 states and 1487 transitions. [2022-10-17 10:47:07,501 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 883 [2022-10-17 10:47:07,510 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 998 states to 998 states and 1487 transitions. [2022-10-17 10:47:07,511 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 998 [2022-10-17 10:47:07,512 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 998 [2022-10-17 10:47:07,512 INFO L73 IsDeterministic]: Start isDeterministic. Operand 998 states and 1487 transitions. [2022-10-17 10:47:07,514 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:47:07,514 INFO L218 hiAutomatonCegarLoop]: Abstraction has 998 states and 1487 transitions. [2022-10-17 10:47:07,516 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 998 states and 1487 transitions. [2022-10-17 10:47:07,531 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 998 to 998. [2022-10-17 10:47:07,533 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 998 states, 998 states have (on average 1.4899799599198398) internal successors, (1487), 997 states have internal predecessors, (1487), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:47:07,538 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 998 states to 998 states and 1487 transitions. [2022-10-17 10:47:07,538 INFO L240 hiAutomatonCegarLoop]: Abstraction has 998 states and 1487 transitions. [2022-10-17 10:47:07,539 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:47:07,540 INFO L428 stractBuchiCegarLoop]: Abstraction has 998 states and 1487 transitions. [2022-10-17 10:47:07,540 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-10-17 10:47:07,540 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 998 states and 1487 transitions. [2022-10-17 10:47:07,546 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 883 [2022-10-17 10:47:07,546 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:47:07,547 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:47:07,548 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:47:07,549 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:47:07,549 INFO L748 eck$LassoCheckResult]: Stem: 8798#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 8799#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 8725#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8726#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8578#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 8579#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8164#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8165#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8246#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8957#L629-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8134#L634-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8135#L639-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8542#L644-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8567#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8250#L866 assume !(0 == ~M_E~0); 8251#L866-2 assume !(0 == ~T1_E~0); 8753#L871-1 assume !(0 == ~T2_E~0); 8754#L876-1 assume !(0 == ~T3_E~0); 9004#L881-1 assume !(0 == ~T4_E~0); 8763#L886-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8533#L891-1 assume !(0 == ~T6_E~0); 8534#L896-1 assume !(0 == ~T7_E~0); 8756#L901-1 assume !(0 == ~T8_E~0); 8774#L906-1 assume !(0 == ~E_M~0); 8775#L911-1 assume !(0 == ~E_1~0); 8576#L916-1 assume !(0 == ~E_2~0); 8577#L921-1 assume !(0 == ~E_3~0); 8870#L926-1 assume 0 == ~E_4~0;~E_4~0 := 1; 8969#L931-1 assume !(0 == ~E_5~0); 9009#L936-1 assume !(0 == ~E_6~0); 9016#L941-1 assume !(0 == ~E_7~0); 8582#L946-1 assume !(0 == ~E_8~0); 8583#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8988#L430 assume !(1 == ~m_pc~0); 8441#L430-2 is_master_triggered_~__retres1~0#1 := 0; 8069#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8070#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8683#L1073 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8693#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8854#L449 assume 1 == ~t1_pc~0; 8855#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8254#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8028#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8029#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 8789#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8638#L468 assume !(1 == ~t2_pc~0); 8053#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 8052#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8541#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8448#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 8071#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8072#L487 assume 1 == ~t3_pc~0; 9001#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8168#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8169#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8843#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 8507#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8508#L506 assume !(1 == ~t4_pc~0); 8634#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 8679#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8979#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8980#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 8629#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8459#L525 assume 1 == ~t5_pc~0; 8394#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8113#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8586#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8587#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 8310#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8311#L544 assume !(1 == ~t6_pc~0); 8460#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 8461#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8805#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8095#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 8096#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8945#L563 assume 1 == ~t7_pc~0; 8823#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8123#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8124#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8535#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 8255#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8256#L582 assume 1 == ~t8_pc~0; 8179#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8180#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9002#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8496#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 8398#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8399#L964 assume 1 == ~M_E~0;~M_E~0 := 2; 8857#L964-2 assume !(1 == ~T1_E~0); 8312#L969-1 assume !(1 == ~T2_E~0); 8313#L974-1 assume !(1 == ~T3_E~0); 8882#L979-1 assume !(1 == ~T4_E~0); 8883#L984-1 assume !(1 == ~T5_E~0); 8466#L989-1 assume !(1 == ~T6_E~0); 8467#L994-1 assume !(1 == ~T7_E~0); 8352#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8353#L1004-1 assume !(1 == ~E_M~0); 8097#L1009-1 assume !(1 == ~E_1~0); 8098#L1014-1 assume !(1 == ~E_2~0); 8341#L1019-1 assume !(1 == ~E_3~0); 8846#L1024-1 assume !(1 == ~E_4~0); 8274#L1029-1 assume !(1 == ~E_5~0); 8275#L1034-1 assume !(1 == ~E_6~0); 8369#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 8983#L1044-1 assume !(1 == ~E_8~0); 8551#L1049-1 assume { :end_inline_reset_delta_events } true; 8244#L1315-2 [2022-10-17 10:47:07,550 INFO L750 eck$LassoCheckResult]: Loop: 8244#L1315-2 assume !false; 8245#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8031#L841 assume !false; 8370#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 8305#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 8306#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 8146#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 8066#L724 assume !(0 != eval_~tmp~0#1); 8068#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8896#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8077#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8078#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8373#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8374#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8387#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8388#L886-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8611#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8612#L896-3 assume !(0 == ~T7_E~0); 8479#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 8480#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8613#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8816#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8419#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8420#L926-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8800#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8486#L936-3 assume !(0 == ~E_6~0); 8487#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 8628#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 8375#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8376#L430-30 assume 1 == ~m_pc~0; 8400#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 8401#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8184#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8185#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8834#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8838#L449-30 assume 1 == ~t1_pc~0; 8403#L450-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8093#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8094#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8465#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8177#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8178#L468-30 assume 1 == ~t2_pc~0; 8269#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8270#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8879#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8602#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8603#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8453#L487-30 assume 1 == ~t3_pc~0; 8434#L488-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8249#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8580#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8581#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8853#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8527#L506-30 assume !(1 == ~t4_pc~0); 8528#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 8554#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8555#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8572#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 8454#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8455#L525-30 assume 1 == ~t5_pc~0; 8940#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8941#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8159#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8160#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8458#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8228#L544-30 assume 1 == ~t6_pc~0; 8036#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8037#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9010#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8950#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8951#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8927#L563-30 assume 1 == ~t7_pc~0; 8198#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8199#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8217#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8543#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8544#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8914#L582-30 assume !(1 == ~t8_pc~0); 8295#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 8296#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8531#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8944#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 9017#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8102#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8103#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8240#L969-3 assume !(1 == ~T2_E~0); 8231#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8232#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8643#L984-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8644#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8277#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8278#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8787#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8149#L1009-3 assume !(1 == ~E_1~0); 8150#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8624#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8625#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8606#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8573#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8574#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8845#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 8267#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 8268#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 8397#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 8734#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 8301#L1334 assume !(0 == start_simulation_~tmp~3#1); 8303#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 8321#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 8032#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 8033#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 8627#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8971#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8806#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 8807#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 8244#L1315-2 [2022-10-17 10:47:07,550 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:47:07,550 INFO L85 PathProgramCache]: Analyzing trace with hash -258739144, now seen corresponding path program 1 times [2022-10-17 10:47:07,551 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:47:07,551 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1955911825] [2022-10-17 10:47:07,551 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:47:07,551 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:47:07,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:47:07,593 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:47:07,593 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:47:07,593 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1955911825] [2022-10-17 10:47:07,594 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1955911825] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:47:07,594 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:47:07,594 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:47:07,594 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [988751374] [2022-10-17 10:47:07,595 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:47:07,595 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:47:07,595 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:47:07,596 INFO L85 PathProgramCache]: Analyzing trace with hash 2141664367, now seen corresponding path program 1 times [2022-10-17 10:47:07,596 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:47:07,596 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2064289422] [2022-10-17 10:47:07,596 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:47:07,597 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:47:07,620 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:47:07,660 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:47:07,660 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:47:07,661 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2064289422] [2022-10-17 10:47:07,661 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2064289422] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:47:07,661 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:47:07,661 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:47:07,661 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [82797792] [2022-10-17 10:47:07,662 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:47:07,662 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:47:07,662 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:47:07,663 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:47:07,663 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:47:07,663 INFO L87 Difference]: Start difference. First operand 998 states and 1487 transitions. cyclomatic complexity: 490 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:47:07,686 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:47:07,686 INFO L93 Difference]: Finished difference Result 998 states and 1486 transitions. [2022-10-17 10:47:07,686 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 998 states and 1486 transitions. [2022-10-17 10:47:07,695 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 883 [2022-10-17 10:47:07,703 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 998 states to 998 states and 1486 transitions. [2022-10-17 10:47:07,704 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 998 [2022-10-17 10:47:07,705 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 998 [2022-10-17 10:47:07,705 INFO L73 IsDeterministic]: Start isDeterministic. Operand 998 states and 1486 transitions. [2022-10-17 10:47:07,706 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:47:07,706 INFO L218 hiAutomatonCegarLoop]: Abstraction has 998 states and 1486 transitions. [2022-10-17 10:47:07,708 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 998 states and 1486 transitions. [2022-10-17 10:47:07,722 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 998 to 998. [2022-10-17 10:47:07,724 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 998 states, 998 states have (on average 1.4889779559118237) internal successors, (1486), 997 states have internal predecessors, (1486), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:47:07,728 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 998 states to 998 states and 1486 transitions. [2022-10-17 10:47:07,729 INFO L240 hiAutomatonCegarLoop]: Abstraction has 998 states and 1486 transitions. [2022-10-17 10:47:07,729 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:47:07,730 INFO L428 stractBuchiCegarLoop]: Abstraction has 998 states and 1486 transitions. [2022-10-17 10:47:07,730 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-10-17 10:47:07,730 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 998 states and 1486 transitions. [2022-10-17 10:47:07,736 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 883 [2022-10-17 10:47:07,736 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:47:07,737 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:47:07,738 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:47:07,739 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:47:07,739 INFO L748 eck$LassoCheckResult]: Stem: 10801#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 10802#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 10728#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10729#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10581#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 10582#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10167#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10168#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10249#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10960#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 10137#L634-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 10138#L639-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10545#L644-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 10570#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10253#L866 assume !(0 == ~M_E~0); 10254#L866-2 assume !(0 == ~T1_E~0); 10756#L871-1 assume !(0 == ~T2_E~0); 10757#L876-1 assume !(0 == ~T3_E~0); 11007#L881-1 assume !(0 == ~T4_E~0); 10766#L886-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10536#L891-1 assume !(0 == ~T6_E~0); 10537#L896-1 assume !(0 == ~T7_E~0); 10759#L901-1 assume !(0 == ~T8_E~0); 10777#L906-1 assume !(0 == ~E_M~0); 10778#L911-1 assume !(0 == ~E_1~0); 10579#L916-1 assume !(0 == ~E_2~0); 10580#L921-1 assume !(0 == ~E_3~0); 10873#L926-1 assume 0 == ~E_4~0;~E_4~0 := 1; 10972#L931-1 assume !(0 == ~E_5~0); 11012#L936-1 assume !(0 == ~E_6~0); 11019#L941-1 assume !(0 == ~E_7~0); 10585#L946-1 assume !(0 == ~E_8~0); 10586#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10991#L430 assume !(1 == ~m_pc~0); 10444#L430-2 is_master_triggered_~__retres1~0#1 := 0; 10072#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10073#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10686#L1073 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10696#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10857#L449 assume 1 == ~t1_pc~0; 10858#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10257#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10031#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10032#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 10792#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10641#L468 assume !(1 == ~t2_pc~0); 10056#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 10055#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10544#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10451#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 10074#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10075#L487 assume 1 == ~t3_pc~0; 11004#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10171#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10172#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10846#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 10510#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10511#L506 assume !(1 == ~t4_pc~0); 10637#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 10682#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10982#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10983#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 10632#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10462#L525 assume 1 == ~t5_pc~0; 10397#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10116#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10589#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10590#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 10313#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10314#L544 assume !(1 == ~t6_pc~0); 10463#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 10464#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10808#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10098#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 10099#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10948#L563 assume 1 == ~t7_pc~0; 10826#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10126#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10127#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10538#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 10258#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10259#L582 assume 1 == ~t8_pc~0; 10182#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 10183#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11005#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10499#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 10401#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10402#L964 assume 1 == ~M_E~0;~M_E~0 := 2; 10860#L964-2 assume !(1 == ~T1_E~0); 10315#L969-1 assume !(1 == ~T2_E~0); 10316#L974-1 assume !(1 == ~T3_E~0); 10885#L979-1 assume !(1 == ~T4_E~0); 10886#L984-1 assume !(1 == ~T5_E~0); 10469#L989-1 assume !(1 == ~T6_E~0); 10470#L994-1 assume !(1 == ~T7_E~0); 10355#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 10356#L1004-1 assume !(1 == ~E_M~0); 10100#L1009-1 assume !(1 == ~E_1~0); 10101#L1014-1 assume !(1 == ~E_2~0); 10344#L1019-1 assume !(1 == ~E_3~0); 10849#L1024-1 assume !(1 == ~E_4~0); 10277#L1029-1 assume !(1 == ~E_5~0); 10278#L1034-1 assume !(1 == ~E_6~0); 10372#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 10986#L1044-1 assume !(1 == ~E_8~0); 10554#L1049-1 assume { :end_inline_reset_delta_events } true; 10247#L1315-2 [2022-10-17 10:47:07,740 INFO L750 eck$LassoCheckResult]: Loop: 10247#L1315-2 assume !false; 10248#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10034#L841 assume !false; 10373#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 10308#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 10309#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 10149#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 10069#L724 assume !(0 != eval_~tmp~0#1); 10071#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10899#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10080#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10081#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10376#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10377#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10390#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10391#L886-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10614#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10615#L896-3 assume !(0 == ~T7_E~0); 10482#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 10483#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10616#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10819#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10422#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10423#L926-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10803#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10489#L936-3 assume !(0 == ~E_6~0); 10490#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 10631#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 10378#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10379#L430-30 assume 1 == ~m_pc~0; 10403#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 10404#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10187#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10188#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10837#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10841#L449-30 assume 1 == ~t1_pc~0; 10406#L450-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10096#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10097#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10468#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10180#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10181#L468-30 assume 1 == ~t2_pc~0; 10272#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10273#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10882#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10605#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 10606#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10456#L487-30 assume 1 == ~t3_pc~0; 10437#L488-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10252#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10583#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10584#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10856#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10530#L506-30 assume !(1 == ~t4_pc~0); 10531#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 10557#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10558#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10575#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 10457#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10458#L525-30 assume !(1 == ~t5_pc~0); 10945#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 10944#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10162#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10163#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10461#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10231#L544-30 assume 1 == ~t6_pc~0; 10039#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10040#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11013#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10953#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10954#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10930#L563-30 assume 1 == ~t7_pc~0; 10201#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10202#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10220#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10546#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 10547#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10917#L582-30 assume !(1 == ~t8_pc~0); 10298#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 10299#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10534#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10947#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 11020#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10105#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10106#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10243#L969-3 assume !(1 == ~T2_E~0); 10234#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10235#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10646#L984-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10647#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10280#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 10281#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 10790#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10152#L1009-3 assume !(1 == ~E_1~0); 10153#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10627#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10628#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10609#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10576#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10577#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 10848#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 10270#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 10271#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 10400#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 10737#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 10304#L1334 assume !(0 == start_simulation_~tmp~3#1); 10306#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 10324#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 10035#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 10036#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 10630#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10974#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10809#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 10810#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 10247#L1315-2 [2022-10-17 10:47:07,741 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:47:07,741 INFO L85 PathProgramCache]: Analyzing trace with hash -1859810250, now seen corresponding path program 1 times [2022-10-17 10:47:07,741 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:47:07,741 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [29359757] [2022-10-17 10:47:07,742 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:47:07,742 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:47:07,754 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:47:07,782 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:47:07,783 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:47:07,783 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [29359757] [2022-10-17 10:47:07,783 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [29359757] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:47:07,783 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:47:07,783 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:47:07,784 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [229677296] [2022-10-17 10:47:07,784 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:47:07,784 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:47:07,785 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:47:07,785 INFO L85 PathProgramCache]: Analyzing trace with hash 1033535728, now seen corresponding path program 1 times [2022-10-17 10:47:07,785 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:47:07,786 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [976909516] [2022-10-17 10:47:07,786 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:47:07,786 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:47:07,800 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:47:07,836 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:47:07,836 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:47:07,837 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [976909516] [2022-10-17 10:47:07,837 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [976909516] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:47:07,837 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:47:07,837 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:47:07,838 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [247697090] [2022-10-17 10:47:07,838 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:47:07,838 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:47:07,839 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:47:07,839 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:47:07,839 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:47:07,839 INFO L87 Difference]: Start difference. First operand 998 states and 1486 transitions. cyclomatic complexity: 489 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:47:07,864 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:47:07,865 INFO L93 Difference]: Finished difference Result 998 states and 1485 transitions. [2022-10-17 10:47:07,865 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 998 states and 1485 transitions. [2022-10-17 10:47:07,873 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 883 [2022-10-17 10:47:07,882 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 998 states to 998 states and 1485 transitions. [2022-10-17 10:47:07,882 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 998 [2022-10-17 10:47:07,883 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 998 [2022-10-17 10:47:07,883 INFO L73 IsDeterministic]: Start isDeterministic. Operand 998 states and 1485 transitions. [2022-10-17 10:47:07,885 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:47:07,885 INFO L218 hiAutomatonCegarLoop]: Abstraction has 998 states and 1485 transitions. [2022-10-17 10:47:07,887 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 998 states and 1485 transitions. [2022-10-17 10:47:07,900 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 998 to 998. [2022-10-17 10:47:07,903 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 998 states, 998 states have (on average 1.4879759519038076) internal successors, (1485), 997 states have internal predecessors, (1485), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:47:07,908 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 998 states to 998 states and 1485 transitions. [2022-10-17 10:47:07,908 INFO L240 hiAutomatonCegarLoop]: Abstraction has 998 states and 1485 transitions. [2022-10-17 10:47:07,909 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:47:07,909 INFO L428 stractBuchiCegarLoop]: Abstraction has 998 states and 1485 transitions. [2022-10-17 10:47:07,910 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-10-17 10:47:07,910 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 998 states and 1485 transitions. [2022-10-17 10:47:07,915 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 883 [2022-10-17 10:47:07,916 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:47:07,916 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:47:07,918 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:47:07,918 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:47:07,918 INFO L748 eck$LassoCheckResult]: Stem: 12804#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 12805#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 12731#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12732#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12584#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 12585#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12170#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12171#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12252#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12963#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 12140#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 12141#L639-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12548#L644-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12573#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12256#L866 assume !(0 == ~M_E~0); 12257#L866-2 assume !(0 == ~T1_E~0); 12759#L871-1 assume !(0 == ~T2_E~0); 12760#L876-1 assume !(0 == ~T3_E~0); 13010#L881-1 assume !(0 == ~T4_E~0); 12769#L886-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12539#L891-1 assume !(0 == ~T6_E~0); 12540#L896-1 assume !(0 == ~T7_E~0); 12762#L901-1 assume !(0 == ~T8_E~0); 12780#L906-1 assume !(0 == ~E_M~0); 12781#L911-1 assume !(0 == ~E_1~0); 12582#L916-1 assume !(0 == ~E_2~0); 12583#L921-1 assume !(0 == ~E_3~0); 12876#L926-1 assume 0 == ~E_4~0;~E_4~0 := 1; 12975#L931-1 assume !(0 == ~E_5~0); 13015#L936-1 assume !(0 == ~E_6~0); 13022#L941-1 assume !(0 == ~E_7~0); 12588#L946-1 assume !(0 == ~E_8~0); 12589#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12994#L430 assume !(1 == ~m_pc~0); 12447#L430-2 is_master_triggered_~__retres1~0#1 := 0; 12075#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12076#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12689#L1073 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12699#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12860#L449 assume 1 == ~t1_pc~0; 12861#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12260#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12034#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12035#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 12795#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12644#L468 assume !(1 == ~t2_pc~0); 12059#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 12058#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12547#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12454#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 12077#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12078#L487 assume 1 == ~t3_pc~0; 13007#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12174#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12175#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12849#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 12513#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12514#L506 assume !(1 == ~t4_pc~0); 12640#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 12685#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12985#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12986#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 12635#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12465#L525 assume 1 == ~t5_pc~0; 12400#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12119#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12592#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12593#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 12316#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12317#L544 assume !(1 == ~t6_pc~0); 12466#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 12467#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12811#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12101#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 12102#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12951#L563 assume 1 == ~t7_pc~0; 12829#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12129#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12130#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12541#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 12261#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12262#L582 assume 1 == ~t8_pc~0; 12185#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12186#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13008#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12502#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 12404#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12405#L964 assume 1 == ~M_E~0;~M_E~0 := 2; 12863#L964-2 assume !(1 == ~T1_E~0); 12318#L969-1 assume !(1 == ~T2_E~0); 12319#L974-1 assume !(1 == ~T3_E~0); 12888#L979-1 assume !(1 == ~T4_E~0); 12889#L984-1 assume !(1 == ~T5_E~0); 12472#L989-1 assume !(1 == ~T6_E~0); 12473#L994-1 assume !(1 == ~T7_E~0); 12358#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 12359#L1004-1 assume !(1 == ~E_M~0); 12103#L1009-1 assume !(1 == ~E_1~0); 12104#L1014-1 assume !(1 == ~E_2~0); 12347#L1019-1 assume !(1 == ~E_3~0); 12852#L1024-1 assume !(1 == ~E_4~0); 12280#L1029-1 assume !(1 == ~E_5~0); 12281#L1034-1 assume !(1 == ~E_6~0); 12375#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 12989#L1044-1 assume !(1 == ~E_8~0); 12557#L1049-1 assume { :end_inline_reset_delta_events } true; 12250#L1315-2 [2022-10-17 10:47:07,919 INFO L750 eck$LassoCheckResult]: Loop: 12250#L1315-2 assume !false; 12251#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12037#L841 assume !false; 12376#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 12311#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 12312#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 12152#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 12072#L724 assume !(0 != eval_~tmp~0#1); 12074#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12902#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12083#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12084#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12379#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12380#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 12393#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12394#L886-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12617#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12618#L896-3 assume !(0 == ~T7_E~0); 12485#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12486#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12619#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12822#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12425#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12426#L926-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12806#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12492#L936-3 assume !(0 == ~E_6~0); 12493#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12634#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12381#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12382#L430-30 assume 1 == ~m_pc~0; 12406#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 12407#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12190#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12191#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12840#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12844#L449-30 assume 1 == ~t1_pc~0; 12409#L450-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12099#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12100#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12471#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12183#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12184#L468-30 assume 1 == ~t2_pc~0; 12275#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12276#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12885#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12608#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12609#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12459#L487-30 assume 1 == ~t3_pc~0; 12440#L488-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12255#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12586#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12587#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12859#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12533#L506-30 assume !(1 == ~t4_pc~0); 12534#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 12560#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12561#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12578#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 12460#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12461#L525-30 assume 1 == ~t5_pc~0; 12946#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12947#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12165#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12166#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12464#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12234#L544-30 assume 1 == ~t6_pc~0; 12042#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12043#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13016#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12956#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12957#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12933#L563-30 assume 1 == ~t7_pc~0; 12204#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12205#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12223#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12549#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12550#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12920#L582-30 assume 1 == ~t8_pc~0; 12882#L583-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12302#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12537#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12950#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 13023#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12108#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12109#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12246#L969-3 assume !(1 == ~T2_E~0); 12237#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12238#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12649#L984-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12650#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12283#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 12284#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 12793#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12155#L1009-3 assume !(1 == ~E_1~0); 12156#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12630#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12631#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12612#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12579#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12580#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12851#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12273#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 12274#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 12403#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 12740#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 12307#L1334 assume !(0 == start_simulation_~tmp~3#1); 12309#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 12327#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 12038#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 12039#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 12633#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12977#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12812#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 12813#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 12250#L1315-2 [2022-10-17 10:47:07,920 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:47:07,920 INFO L85 PathProgramCache]: Analyzing trace with hash -803079048, now seen corresponding path program 1 times [2022-10-17 10:47:07,920 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:47:07,921 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [701729355] [2022-10-17 10:47:07,921 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:47:07,921 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:47:07,932 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:47:07,969 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:47:07,969 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:47:07,969 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [701729355] [2022-10-17 10:47:07,970 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [701729355] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:47:07,970 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:47:07,970 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:47:07,970 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1513322729] [2022-10-17 10:47:07,970 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:47:07,971 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:47:07,971 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:47:07,971 INFO L85 PathProgramCache]: Analyzing trace with hash 1016404398, now seen corresponding path program 2 times [2022-10-17 10:47:07,971 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:47:07,972 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1275785486] [2022-10-17 10:47:07,972 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:47:07,972 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:47:07,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:47:08,022 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:47:08,023 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:47:08,023 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1275785486] [2022-10-17 10:47:08,023 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1275785486] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:47:08,023 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:47:08,024 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:47:08,024 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [510289169] [2022-10-17 10:47:08,024 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:47:08,024 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:47:08,025 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:47:08,025 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:47:08,025 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:47:08,025 INFO L87 Difference]: Start difference. First operand 998 states and 1485 transitions. cyclomatic complexity: 488 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:47:08,048 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:47:08,048 INFO L93 Difference]: Finished difference Result 998 states and 1484 transitions. [2022-10-17 10:47:08,048 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 998 states and 1484 transitions. [2022-10-17 10:47:08,057 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 883 [2022-10-17 10:47:08,065 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 998 states to 998 states and 1484 transitions. [2022-10-17 10:47:08,065 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 998 [2022-10-17 10:47:08,066 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 998 [2022-10-17 10:47:08,067 INFO L73 IsDeterministic]: Start isDeterministic. Operand 998 states and 1484 transitions. [2022-10-17 10:47:08,068 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:47:08,068 INFO L218 hiAutomatonCegarLoop]: Abstraction has 998 states and 1484 transitions. [2022-10-17 10:47:08,071 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 998 states and 1484 transitions. [2022-10-17 10:47:08,084 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 998 to 998. [2022-10-17 10:47:08,087 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 998 states, 998 states have (on average 1.4869739478957915) internal successors, (1484), 997 states have internal predecessors, (1484), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:47:08,092 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 998 states to 998 states and 1484 transitions. [2022-10-17 10:47:08,092 INFO L240 hiAutomatonCegarLoop]: Abstraction has 998 states and 1484 transitions. [2022-10-17 10:47:08,092 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:47:08,093 INFO L428 stractBuchiCegarLoop]: Abstraction has 998 states and 1484 transitions. [2022-10-17 10:47:08,093 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-10-17 10:47:08,093 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 998 states and 1484 transitions. [2022-10-17 10:47:08,099 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 883 [2022-10-17 10:47:08,099 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:47:08,100 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:47:08,101 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:47:08,102 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:47:08,102 INFO L748 eck$LassoCheckResult]: Stem: 14807#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 14808#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 14734#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14735#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14587#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 14588#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14173#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14174#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14255#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14966#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14143#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 14144#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 14551#L644-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 14576#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14259#L866 assume !(0 == ~M_E~0); 14260#L866-2 assume !(0 == ~T1_E~0); 14762#L871-1 assume !(0 == ~T2_E~0); 14763#L876-1 assume !(0 == ~T3_E~0); 15013#L881-1 assume !(0 == ~T4_E~0); 14772#L886-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14542#L891-1 assume !(0 == ~T6_E~0); 14543#L896-1 assume !(0 == ~T7_E~0); 14765#L901-1 assume !(0 == ~T8_E~0); 14783#L906-1 assume !(0 == ~E_M~0); 14784#L911-1 assume !(0 == ~E_1~0); 14585#L916-1 assume !(0 == ~E_2~0); 14586#L921-1 assume !(0 == ~E_3~0); 14879#L926-1 assume 0 == ~E_4~0;~E_4~0 := 1; 14978#L931-1 assume !(0 == ~E_5~0); 15018#L936-1 assume !(0 == ~E_6~0); 15025#L941-1 assume !(0 == ~E_7~0); 14591#L946-1 assume !(0 == ~E_8~0); 14592#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14997#L430 assume !(1 == ~m_pc~0); 14450#L430-2 is_master_triggered_~__retres1~0#1 := 0; 14078#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14079#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14692#L1073 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14702#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14863#L449 assume 1 == ~t1_pc~0; 14864#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14263#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14037#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14038#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 14798#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14647#L468 assume !(1 == ~t2_pc~0); 14062#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 14061#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14550#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14457#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 14080#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14081#L487 assume 1 == ~t3_pc~0; 15010#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14177#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14178#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14852#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 14516#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14517#L506 assume !(1 == ~t4_pc~0); 14643#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 14688#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14988#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14989#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 14638#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14468#L525 assume 1 == ~t5_pc~0; 14403#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14122#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14595#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14596#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 14319#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14320#L544 assume !(1 == ~t6_pc~0); 14469#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 14470#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14814#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14104#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 14105#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14954#L563 assume 1 == ~t7_pc~0; 14832#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14132#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14133#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14544#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 14264#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14265#L582 assume 1 == ~t8_pc~0; 14188#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 14189#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15011#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14505#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 14407#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14408#L964 assume 1 == ~M_E~0;~M_E~0 := 2; 14866#L964-2 assume !(1 == ~T1_E~0); 14321#L969-1 assume !(1 == ~T2_E~0); 14322#L974-1 assume !(1 == ~T3_E~0); 14891#L979-1 assume !(1 == ~T4_E~0); 14892#L984-1 assume !(1 == ~T5_E~0); 14475#L989-1 assume !(1 == ~T6_E~0); 14476#L994-1 assume !(1 == ~T7_E~0); 14361#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14362#L1004-1 assume !(1 == ~E_M~0); 14106#L1009-1 assume !(1 == ~E_1~0); 14107#L1014-1 assume !(1 == ~E_2~0); 14350#L1019-1 assume !(1 == ~E_3~0); 14855#L1024-1 assume !(1 == ~E_4~0); 14283#L1029-1 assume !(1 == ~E_5~0); 14284#L1034-1 assume !(1 == ~E_6~0); 14378#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 14992#L1044-1 assume !(1 == ~E_8~0); 14560#L1049-1 assume { :end_inline_reset_delta_events } true; 14253#L1315-2 [2022-10-17 10:47:08,103 INFO L750 eck$LassoCheckResult]: Loop: 14253#L1315-2 assume !false; 14254#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14040#L841 assume !false; 14379#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 14314#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 14315#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 14155#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 14075#L724 assume !(0 != eval_~tmp~0#1); 14077#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14905#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14086#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 14087#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14382#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14383#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14396#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14397#L886-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14620#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14621#L896-3 assume !(0 == ~T7_E~0); 14488#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 14489#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 14622#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14825#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14428#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14429#L926-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14809#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14495#L936-3 assume !(0 == ~E_6~0); 14496#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 14637#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 14384#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14385#L430-30 assume 1 == ~m_pc~0; 14409#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 14410#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14193#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14194#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14843#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14847#L449-30 assume 1 == ~t1_pc~0; 14412#L450-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14102#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14103#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14474#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14186#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14187#L468-30 assume 1 == ~t2_pc~0; 14278#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14279#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14888#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14611#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14612#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14462#L487-30 assume !(1 == ~t3_pc~0); 14257#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 14258#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14589#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14590#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14862#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14536#L506-30 assume !(1 == ~t4_pc~0); 14537#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 14563#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14564#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14581#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 14463#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14464#L525-30 assume 1 == ~t5_pc~0; 14949#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14950#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14168#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14169#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14467#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14237#L544-30 assume 1 == ~t6_pc~0; 14045#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 14046#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15019#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14959#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 14960#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14936#L563-30 assume !(1 == ~t7_pc~0); 14209#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 14208#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14226#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14552#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 14553#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14923#L582-30 assume !(1 == ~t8_pc~0); 14304#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 14305#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14540#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14953#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 15026#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14111#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14112#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14249#L969-3 assume !(1 == ~T2_E~0); 14240#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14241#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14652#L984-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14653#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14286#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14287#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14796#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 14158#L1009-3 assume !(1 == ~E_1~0); 14159#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14633#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14634#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14615#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14582#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14583#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 14854#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 14276#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 14277#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 14406#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 14743#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 14310#L1334 assume !(0 == start_simulation_~tmp~3#1); 14312#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 14330#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 14041#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 14042#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 14636#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14980#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14815#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 14816#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 14253#L1315-2 [2022-10-17 10:47:08,103 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:47:08,104 INFO L85 PathProgramCache]: Analyzing trace with hash 2140503030, now seen corresponding path program 1 times [2022-10-17 10:47:08,104 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:47:08,104 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [729367409] [2022-10-17 10:47:08,104 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:47:08,105 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:47:08,116 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:47:08,145 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:47:08,145 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:47:08,145 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [729367409] [2022-10-17 10:47:08,145 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [729367409] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:47:08,146 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:47:08,146 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:47:08,146 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1436553553] [2022-10-17 10:47:08,146 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:47:08,147 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:47:08,147 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:47:08,147 INFO L85 PathProgramCache]: Analyzing trace with hash 1882721649, now seen corresponding path program 1 times [2022-10-17 10:47:08,147 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:47:08,148 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1389661951] [2022-10-17 10:47:08,148 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:47:08,148 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:47:08,162 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:47:08,198 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:47:08,198 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:47:08,198 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1389661951] [2022-10-17 10:47:08,199 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1389661951] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:47:08,199 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:47:08,199 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:47:08,199 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1413870089] [2022-10-17 10:47:08,199 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:47:08,200 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:47:08,200 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:47:08,200 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:47:08,201 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:47:08,201 INFO L87 Difference]: Start difference. First operand 998 states and 1484 transitions. cyclomatic complexity: 487 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:47:08,223 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:47:08,224 INFO L93 Difference]: Finished difference Result 998 states and 1483 transitions. [2022-10-17 10:47:08,224 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 998 states and 1483 transitions. [2022-10-17 10:47:08,232 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 883 [2022-10-17 10:47:08,240 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 998 states to 998 states and 1483 transitions. [2022-10-17 10:47:08,241 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 998 [2022-10-17 10:47:08,242 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 998 [2022-10-17 10:47:08,242 INFO L73 IsDeterministic]: Start isDeterministic. Operand 998 states and 1483 transitions. [2022-10-17 10:47:08,244 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:47:08,244 INFO L218 hiAutomatonCegarLoop]: Abstraction has 998 states and 1483 transitions. [2022-10-17 10:47:08,246 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 998 states and 1483 transitions. [2022-10-17 10:47:08,259 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 998 to 998. [2022-10-17 10:47:08,262 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 998 states, 998 states have (on average 1.4859719438877756) internal successors, (1483), 997 states have internal predecessors, (1483), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:47:08,267 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 998 states to 998 states and 1483 transitions. [2022-10-17 10:47:08,267 INFO L240 hiAutomatonCegarLoop]: Abstraction has 998 states and 1483 transitions. [2022-10-17 10:47:08,267 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:47:08,268 INFO L428 stractBuchiCegarLoop]: Abstraction has 998 states and 1483 transitions. [2022-10-17 10:47:08,268 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-10-17 10:47:08,268 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 998 states and 1483 transitions. [2022-10-17 10:47:08,274 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 883 [2022-10-17 10:47:08,274 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:47:08,275 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:47:08,276 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:47:08,277 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:47:08,277 INFO L748 eck$LassoCheckResult]: Stem: 16810#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 16811#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 16737#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16738#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16590#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 16591#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16176#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16177#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16258#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16969#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 16146#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 16147#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 16554#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 16579#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16262#L866 assume !(0 == ~M_E~0); 16263#L866-2 assume !(0 == ~T1_E~0); 16765#L871-1 assume !(0 == ~T2_E~0); 16766#L876-1 assume !(0 == ~T3_E~0); 17016#L881-1 assume !(0 == ~T4_E~0); 16775#L886-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16545#L891-1 assume !(0 == ~T6_E~0); 16546#L896-1 assume !(0 == ~T7_E~0); 16768#L901-1 assume !(0 == ~T8_E~0); 16786#L906-1 assume !(0 == ~E_M~0); 16787#L911-1 assume !(0 == ~E_1~0); 16588#L916-1 assume !(0 == ~E_2~0); 16589#L921-1 assume !(0 == ~E_3~0); 16882#L926-1 assume 0 == ~E_4~0;~E_4~0 := 1; 16981#L931-1 assume !(0 == ~E_5~0); 17021#L936-1 assume !(0 == ~E_6~0); 17028#L941-1 assume !(0 == ~E_7~0); 16594#L946-1 assume !(0 == ~E_8~0); 16595#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17000#L430 assume !(1 == ~m_pc~0); 16453#L430-2 is_master_triggered_~__retres1~0#1 := 0; 16081#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16082#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16695#L1073 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16705#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16866#L449 assume 1 == ~t1_pc~0; 16867#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16266#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16040#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16041#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 16801#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16650#L468 assume !(1 == ~t2_pc~0); 16065#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 16064#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16553#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16460#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 16083#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16084#L487 assume 1 == ~t3_pc~0; 17013#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16180#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16181#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16855#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 16519#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16520#L506 assume !(1 == ~t4_pc~0); 16646#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 16691#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16991#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16992#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 16641#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16471#L525 assume 1 == ~t5_pc~0; 16406#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16125#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16598#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16599#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 16322#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16323#L544 assume !(1 == ~t6_pc~0); 16472#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 16473#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16817#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16107#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 16108#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16957#L563 assume 1 == ~t7_pc~0; 16835#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16135#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16136#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16547#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 16267#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16268#L582 assume 1 == ~t8_pc~0; 16191#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16192#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17014#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 16508#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 16410#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16411#L964 assume 1 == ~M_E~0;~M_E~0 := 2; 16869#L964-2 assume !(1 == ~T1_E~0); 16324#L969-1 assume !(1 == ~T2_E~0); 16325#L974-1 assume !(1 == ~T3_E~0); 16894#L979-1 assume !(1 == ~T4_E~0); 16895#L984-1 assume !(1 == ~T5_E~0); 16478#L989-1 assume !(1 == ~T6_E~0); 16479#L994-1 assume !(1 == ~T7_E~0); 16364#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16365#L1004-1 assume !(1 == ~E_M~0); 16109#L1009-1 assume !(1 == ~E_1~0); 16110#L1014-1 assume !(1 == ~E_2~0); 16353#L1019-1 assume !(1 == ~E_3~0); 16858#L1024-1 assume !(1 == ~E_4~0); 16286#L1029-1 assume !(1 == ~E_5~0); 16287#L1034-1 assume !(1 == ~E_6~0); 16381#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 16995#L1044-1 assume !(1 == ~E_8~0); 16563#L1049-1 assume { :end_inline_reset_delta_events } true; 16256#L1315-2 [2022-10-17 10:47:08,278 INFO L750 eck$LassoCheckResult]: Loop: 16256#L1315-2 assume !false; 16257#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16043#L841 assume !false; 16382#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 16317#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 16318#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 16158#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 16078#L724 assume !(0 != eval_~tmp~0#1); 16080#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16908#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16089#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 16090#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 16385#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16386#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16399#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 16400#L886-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16623#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 16624#L896-3 assume !(0 == ~T7_E~0); 16491#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16492#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 16625#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16828#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16431#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 16432#L926-3 assume 0 == ~E_4~0;~E_4~0 := 1; 16812#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 16498#L936-3 assume !(0 == ~E_6~0); 16499#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 16640#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 16387#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16388#L430-30 assume 1 == ~m_pc~0; 16412#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 16413#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16196#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16197#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16846#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16850#L449-30 assume !(1 == ~t1_pc~0); 16416#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 16105#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16106#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16477#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 16189#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16190#L468-30 assume 1 == ~t2_pc~0; 16281#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 16282#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16891#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16614#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16615#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16465#L487-30 assume !(1 == ~t3_pc~0); 16260#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 16261#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16592#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16593#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16865#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16539#L506-30 assume !(1 == ~t4_pc~0); 16540#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 16566#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16567#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16584#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 16466#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16467#L525-30 assume 1 == ~t5_pc~0; 16952#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16953#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16171#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16172#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 16470#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16240#L544-30 assume 1 == ~t6_pc~0; 16048#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 16049#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17022#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16962#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 16963#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16939#L563-30 assume 1 == ~t7_pc~0; 16210#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16211#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16229#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16555#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 16556#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16926#L582-30 assume !(1 == ~t8_pc~0); 16307#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 16308#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16543#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 16956#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 17029#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16114#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 16115#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16252#L969-3 assume !(1 == ~T2_E~0); 16243#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16244#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16655#L984-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16656#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16289#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 16290#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16799#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 16161#L1009-3 assume !(1 == ~E_1~0); 16162#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16636#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16637#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16618#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16585#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16586#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16857#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 16279#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 16280#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 16409#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 16746#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 16313#L1334 assume !(0 == start_simulation_~tmp~3#1); 16315#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 16333#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 16044#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 16045#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 16639#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16983#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16818#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 16819#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 16256#L1315-2 [2022-10-17 10:47:08,279 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:47:08,279 INFO L85 PathProgramCache]: Analyzing trace with hash -535489352, now seen corresponding path program 1 times [2022-10-17 10:47:08,279 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:47:08,279 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [425339317] [2022-10-17 10:47:08,279 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:47:08,280 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:47:08,294 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:47:08,377 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:47:08,377 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:47:08,378 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [425339317] [2022-10-17 10:47:08,378 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [425339317] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:47:08,378 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:47:08,378 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:47:08,378 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [15112986] [2022-10-17 10:47:08,379 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:47:08,379 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:47:08,379 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:47:08,379 INFO L85 PathProgramCache]: Analyzing trace with hash -952835855, now seen corresponding path program 1 times [2022-10-17 10:47:08,380 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:47:08,380 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2102565238] [2022-10-17 10:47:08,380 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:47:08,380 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:47:08,394 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:47:08,430 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:47:08,430 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:47:08,431 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2102565238] [2022-10-17 10:47:08,431 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2102565238] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:47:08,431 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:47:08,431 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:47:08,431 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [565047235] [2022-10-17 10:47:08,431 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:47:08,432 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:47:08,432 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:47:08,432 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-10-17 10:47:08,433 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-10-17 10:47:08,433 INFO L87 Difference]: Start difference. First operand 998 states and 1483 transitions. cyclomatic complexity: 486 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:47:08,546 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:47:08,547 INFO L93 Difference]: Finished difference Result 1816 states and 2689 transitions. [2022-10-17 10:47:08,547 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1816 states and 2689 transitions. [2022-10-17 10:47:08,560 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1683 [2022-10-17 10:47:08,574 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1816 states to 1816 states and 2689 transitions. [2022-10-17 10:47:08,574 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1816 [2022-10-17 10:47:08,576 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1816 [2022-10-17 10:47:08,577 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1816 states and 2689 transitions. [2022-10-17 10:47:08,579 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:47:08,580 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1816 states and 2689 transitions. [2022-10-17 10:47:08,582 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1816 states and 2689 transitions. [2022-10-17 10:47:08,610 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1816 to 1816. [2022-10-17 10:47:08,614 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1816 states, 1816 states have (on average 1.480726872246696) internal successors, (2689), 1815 states have internal predecessors, (2689), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:47:08,622 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1816 states to 1816 states and 2689 transitions. [2022-10-17 10:47:08,622 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1816 states and 2689 transitions. [2022-10-17 10:47:08,623 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-10-17 10:47:08,623 INFO L428 stractBuchiCegarLoop]: Abstraction has 1816 states and 2689 transitions. [2022-10-17 10:47:08,623 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-10-17 10:47:08,624 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1816 states and 2689 transitions. [2022-10-17 10:47:08,631 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1683 [2022-10-17 10:47:08,632 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:47:08,632 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:47:08,634 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:47:08,634 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:47:08,634 INFO L748 eck$LassoCheckResult]: Stem: 19638#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 19639#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 19563#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19564#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19415#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 19416#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19000#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19001#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 19082#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19800#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 18970#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 18971#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 19378#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 19404#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19086#L866 assume !(0 == ~M_E~0); 19087#L866-2 assume !(0 == ~T1_E~0); 19591#L871-1 assume !(0 == ~T2_E~0); 19592#L876-1 assume !(0 == ~T3_E~0); 19848#L881-1 assume !(0 == ~T4_E~0); 19602#L886-1 assume !(0 == ~T5_E~0); 19369#L891-1 assume !(0 == ~T6_E~0); 19370#L896-1 assume !(0 == ~T7_E~0); 19594#L901-1 assume !(0 == ~T8_E~0); 19614#L906-1 assume !(0 == ~E_M~0); 19615#L911-1 assume !(0 == ~E_1~0); 19413#L916-1 assume !(0 == ~E_2~0); 19414#L921-1 assume !(0 == ~E_3~0); 19712#L926-1 assume 0 == ~E_4~0;~E_4~0 := 1; 19812#L931-1 assume !(0 == ~E_5~0); 19853#L936-1 assume !(0 == ~E_6~0); 19861#L941-1 assume !(0 == ~E_7~0); 19419#L946-1 assume !(0 == ~E_8~0); 19420#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19831#L430 assume !(1 == ~m_pc~0); 19277#L430-2 is_master_triggered_~__retres1~0#1 := 0; 18905#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18906#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 19520#L1073 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19530#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19695#L449 assume 1 == ~t1_pc~0; 19696#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19090#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18864#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18865#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 19629#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19475#L468 assume !(1 == ~t2_pc~0); 18889#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 18888#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19377#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19284#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 18907#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18908#L487 assume 1 == ~t3_pc~0; 19844#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19004#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19005#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19684#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 19343#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19344#L506 assume !(1 == ~t4_pc~0); 19471#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 19516#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19822#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19823#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 19466#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19295#L525 assume 1 == ~t5_pc~0; 19230#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 18949#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19423#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19424#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 19146#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19147#L544 assume !(1 == ~t6_pc~0); 19296#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 19297#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19645#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18931#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 18932#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19788#L563 assume 1 == ~t7_pc~0; 19663#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 18959#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 18960#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19371#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 19091#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19092#L582 assume 1 == ~t8_pc~0; 19015#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 19016#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19845#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19332#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 19234#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19235#L964 assume !(1 == ~M_E~0); 19698#L964-2 assume !(1 == ~T1_E~0); 20095#L969-1 assume !(1 == ~T2_E~0); 20090#L974-1 assume !(1 == ~T3_E~0); 20086#L979-1 assume !(1 == ~T4_E~0); 20082#L984-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19302#L989-1 assume !(1 == ~T6_E~0); 19303#L994-1 assume !(1 == ~T7_E~0); 19188#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19189#L1004-1 assume !(1 == ~E_M~0); 18933#L1009-1 assume !(1 == ~E_1~0); 18934#L1014-1 assume !(1 == ~E_2~0); 19177#L1019-1 assume !(1 == ~E_3~0); 19687#L1024-1 assume !(1 == ~E_4~0); 19110#L1029-1 assume !(1 == ~E_5~0); 19111#L1034-1 assume !(1 == ~E_6~0); 19205#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 19826#L1044-1 assume !(1 == ~E_8~0); 19387#L1049-1 assume { :end_inline_reset_delta_events } true; 19388#L1315-2 [2022-10-17 10:47:08,635 INFO L750 eck$LassoCheckResult]: Loop: 19388#L1315-2 assume !false; 19890#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19889#L841 assume !false; 19888#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 19883#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 19878#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 19877#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 19875#L724 assume !(0 != eval_~tmp~0#1); 19874#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19873#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19872#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 19846#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19209#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19210#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19223#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 19224#L886-3 assume !(0 == ~T5_E~0); 19448#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 19449#L896-3 assume !(0 == ~T7_E~0); 19315#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 19316#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 19450#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 19656#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 19255#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 19256#L926-3 assume 0 == ~E_4~0;~E_4~0 := 1; 19640#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 19322#L936-3 assume !(0 == ~E_6~0); 19323#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 19465#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 19211#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19212#L430-30 assume 1 == ~m_pc~0; 19236#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 19237#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19020#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 19021#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19675#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19679#L449-30 assume 1 == ~t1_pc~0; 19239#L450-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18929#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18930#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19301#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 19013#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19014#L468-30 assume 1 == ~t2_pc~0; 19105#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19106#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19721#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19439#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19440#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19289#L487-30 assume 1 == ~t3_pc~0; 19270#L488-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19085#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19417#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19418#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 19694#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19363#L506-30 assume !(1 == ~t4_pc~0); 19364#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 19391#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19392#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19409#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 19290#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19291#L525-30 assume 1 == ~t5_pc~0; 19783#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19784#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18995#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18996#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 19774#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20401#L544-30 assume !(1 == ~t6_pc~0); 20400#L544-32 is_transmit6_triggered_~__retres1~6#1 := 0; 20398#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20397#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20396#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 19871#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19769#L563-30 assume 1 == ~t7_pc~0; 19034#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19035#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19053#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19379#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19380#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19756#L582-30 assume 1 == ~t8_pc~0; 19718#L583-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 19132#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19367#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19787#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 19862#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18938#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 18939#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19076#L969-3 assume !(1 == ~T2_E~0); 19067#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 19068#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19480#L984-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19481#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 19113#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19114#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19627#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 18985#L1009-3 assume !(1 == ~E_1~0); 18986#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19461#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 19462#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 19443#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 19410#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19411#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19686#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 19103#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 19104#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 19233#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 19572#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 19137#L1334 assume !(0 == start_simulation_~tmp~3#1); 19139#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 19157#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 18868#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 18869#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 19464#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19814#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19646#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 19647#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 19388#L1315-2 [2022-10-17 10:47:08,636 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:47:08,636 INFO L85 PathProgramCache]: Analyzing trace with hash -1799592066, now seen corresponding path program 1 times [2022-10-17 10:47:08,636 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:47:08,636 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1319480841] [2022-10-17 10:47:08,637 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:47:08,637 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:47:08,649 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:47:08,703 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:47:08,703 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:47:08,703 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1319480841] [2022-10-17 10:47:08,703 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1319480841] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:47:08,703 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:47:08,704 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:47:08,704 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1537047325] [2022-10-17 10:47:08,704 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:47:08,704 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:47:08,705 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:47:08,705 INFO L85 PathProgramCache]: Analyzing trace with hash -779318671, now seen corresponding path program 1 times [2022-10-17 10:47:08,705 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:47:08,706 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1186287216] [2022-10-17 10:47:08,706 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:47:08,706 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:47:08,719 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:47:08,785 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:47:08,786 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:47:08,786 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1186287216] [2022-10-17 10:47:08,786 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1186287216] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:47:08,786 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:47:08,786 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:47:08,786 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1343880368] [2022-10-17 10:47:08,786 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:47:08,787 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:47:08,787 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:47:08,787 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-10-17 10:47:08,788 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-10-17 10:47:08,788 INFO L87 Difference]: Start difference. First operand 1816 states and 2689 transitions. cyclomatic complexity: 875 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:47:08,977 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:47:08,978 INFO L93 Difference]: Finished difference Result 3306 states and 4884 transitions. [2022-10-17 10:47:08,978 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3306 states and 4884 transitions. [2022-10-17 10:47:09,003 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3153 [2022-10-17 10:47:09,033 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3306 states to 3306 states and 4884 transitions. [2022-10-17 10:47:09,033 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3306 [2022-10-17 10:47:09,037 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3306 [2022-10-17 10:47:09,037 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3306 states and 4884 transitions. [2022-10-17 10:47:09,043 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:47:09,043 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3306 states and 4884 transitions. [2022-10-17 10:47:09,048 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3306 states and 4884 transitions. [2022-10-17 10:47:09,117 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3306 to 3304. [2022-10-17 10:47:09,125 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3304 states, 3304 states have (on average 1.4776029055690072) internal successors, (4882), 3303 states have internal predecessors, (4882), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:47:09,138 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3304 states to 3304 states and 4882 transitions. [2022-10-17 10:47:09,138 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3304 states and 4882 transitions. [2022-10-17 10:47:09,138 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-10-17 10:47:09,139 INFO L428 stractBuchiCegarLoop]: Abstraction has 3304 states and 4882 transitions. [2022-10-17 10:47:09,139 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-10-17 10:47:09,140 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3304 states and 4882 transitions. [2022-10-17 10:47:09,154 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3153 [2022-10-17 10:47:09,154 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:47:09,155 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:47:09,156 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:47:09,157 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:47:09,157 INFO L748 eck$LassoCheckResult]: Stem: 24780#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 24781#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 24702#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 24703#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 24553#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 24554#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24133#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 24134#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 24215#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 24965#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 24103#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 24104#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 24517#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 24542#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24219#L866 assume !(0 == ~M_E~0); 24220#L866-2 assume !(0 == ~T1_E~0); 24732#L871-1 assume !(0 == ~T2_E~0); 24733#L876-1 assume !(0 == ~T3_E~0); 25023#L881-1 assume !(0 == ~T4_E~0); 24744#L886-1 assume !(0 == ~T5_E~0); 24508#L891-1 assume !(0 == ~T6_E~0); 24509#L896-1 assume !(0 == ~T7_E~0); 24736#L901-1 assume !(0 == ~T8_E~0); 24756#L906-1 assume !(0 == ~E_M~0); 24757#L911-1 assume !(0 == ~E_1~0); 24551#L916-1 assume !(0 == ~E_2~0); 24552#L921-1 assume !(0 == ~E_3~0); 24860#L926-1 assume !(0 == ~E_4~0); 24977#L931-1 assume !(0 == ~E_5~0); 25033#L936-1 assume !(0 == ~E_6~0); 25043#L941-1 assume !(0 == ~E_7~0); 24557#L946-1 assume !(0 == ~E_8~0); 24558#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25005#L430 assume !(1 == ~m_pc~0); 24413#L430-2 is_master_triggered_~__retres1~0#1 := 0; 24037#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24038#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 24659#L1073 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 24669#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24840#L449 assume 1 == ~t1_pc~0; 24841#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24224#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23996#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 23997#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 24771#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24613#L468 assume !(1 == ~t2_pc~0); 24021#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 24020#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24516#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 24421#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 24039#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24040#L487 assume 1 == ~t3_pc~0; 25020#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 24137#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24138#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 24829#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 24482#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24483#L506 assume !(1 == ~t4_pc~0); 24609#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 24655#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24991#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24992#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 24604#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24434#L525 assume 1 == ~t5_pc~0; 24366#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 24082#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24561#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24562#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 24280#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 24281#L544 assume !(1 == ~t6_pc~0); 24435#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 24436#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24788#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24063#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 24064#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24953#L563 assume 1 == ~t7_pc~0; 24807#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 24092#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24093#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24510#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 24225#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24226#L582 assume 1 == ~t8_pc~0; 24148#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 24149#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25021#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24471#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 24370#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24371#L964 assume !(1 == ~M_E~0); 24843#L964-2 assume !(1 == ~T1_E~0); 25141#L969-1 assume !(1 == ~T2_E~0); 24986#L974-1 assume !(1 == ~T3_E~0); 24987#L979-1 assume !(1 == ~T4_E~0); 25058#L984-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 24441#L989-1 assume !(1 == ~T6_E~0); 24442#L994-1 assume !(1 == ~T7_E~0); 24323#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 24324#L1004-1 assume !(1 == ~E_M~0); 24065#L1009-1 assume !(1 == ~E_1~0); 24066#L1014-1 assume !(1 == ~E_2~0); 25131#L1019-1 assume !(1 == ~E_3~0); 25119#L1024-1 assume 1 == ~E_4~0;~E_4~0 := 2; 25117#L1029-1 assume !(1 == ~E_5~0); 25115#L1034-1 assume !(1 == ~E_6~0); 25113#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 25111#L1044-1 assume !(1 == ~E_8~0); 25109#L1049-1 assume { :end_inline_reset_delta_events } true; 25102#L1315-2 [2022-10-17 10:47:09,157 INFO L750 eck$LassoCheckResult]: Loop: 25102#L1315-2 assume !false; 25097#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 25096#L841 assume !false; 25095#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 25090#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 25085#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 25084#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 25082#L724 assume !(0 != eval_~tmp~0#1); 25081#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25080#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25078#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 25079#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 26591#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 26590#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 26589#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 26588#L886-3 assume !(0 == ~T5_E~0); 26586#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 26583#L896-3 assume !(0 == ~T7_E~0); 26581#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 26578#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 26574#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 26571#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 26568#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 26564#L926-3 assume !(0 == ~E_4~0); 26562#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 26558#L936-3 assume !(0 == ~E_6~0); 26555#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 26553#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 26551#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26549#L430-30 assume 1 == ~m_pc~0; 26546#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 26541#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26503#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 26450#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 26447#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26445#L449-30 assume !(1 == ~t1_pc~0); 26442#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 26440#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26438#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 26436#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 26433#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26432#L468-30 assume 1 == ~t2_pc~0; 26429#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 26426#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26395#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 26392#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 26383#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26375#L487-30 assume 1 == ~t3_pc~0; 24406#L488-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 24218#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24555#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 24556#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 24839#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24502#L506-30 assume !(1 == ~t4_pc~0); 24503#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 24529#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24530#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24547#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 24429#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24430#L525-30 assume 1 == ~t5_pc~0; 24946#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 24947#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24128#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24129#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 24433#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 24197#L544-30 assume 1 == ~t6_pc~0; 24004#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 24005#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25035#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24958#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 24959#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24928#L563-30 assume 1 == ~t7_pc~0; 24167#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 24168#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24186#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24518#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 24519#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24910#L582-30 assume 1 == ~t8_pc~0; 24912#L583-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 25319#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25317#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25315#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 25294#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25256#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 24071#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25242#L969-3 assume !(1 == ~T2_E~0); 25239#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25230#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25217#L984-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25205#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 25198#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 25192#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 25187#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 25181#L1009-3 assume !(1 == ~E_1~0); 25177#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 25174#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 25166#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 25163#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 25162#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 25161#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 25160#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 25159#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 25148#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 25140#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 25139#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 25138#L1334 assume !(0 == start_simulation_~tmp~3#1); 24923#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 25128#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 25118#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 25116#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 25114#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 25112#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 25110#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 25108#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 25102#L1315-2 [2022-10-17 10:47:09,158 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:47:09,159 INFO L85 PathProgramCache]: Analyzing trace with hash -1616610622, now seen corresponding path program 1 times [2022-10-17 10:47:09,159 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:47:09,159 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [82138268] [2022-10-17 10:47:09,159 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:47:09,159 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:47:09,174 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:47:09,235 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:47:09,236 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:47:09,236 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [82138268] [2022-10-17 10:47:09,236 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [82138268] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:47:09,236 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:47:09,236 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-10-17 10:47:09,236 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1112781428] [2022-10-17 10:47:09,236 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:47:09,237 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:47:09,238 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:47:09,238 INFO L85 PathProgramCache]: Analyzing trace with hash -830163917, now seen corresponding path program 1 times [2022-10-17 10:47:09,238 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:47:09,238 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1590507798] [2022-10-17 10:47:09,238 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:47:09,238 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:47:09,256 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:47:09,301 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:47:09,301 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:47:09,301 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1590507798] [2022-10-17 10:47:09,302 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1590507798] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:47:09,302 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:47:09,302 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:47:09,302 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [228699133] [2022-10-17 10:47:09,302 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:47:09,303 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:47:09,303 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:47:09,303 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-10-17 10:47:09,303 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-10-17 10:47:09,304 INFO L87 Difference]: Start difference. First operand 3304 states and 4882 transitions. cyclomatic complexity: 1582 Second operand has 5 states, 5 states have (on average 21.2) internal successors, (106), 5 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:47:09,656 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:47:09,656 INFO L93 Difference]: Finished difference Result 9486 states and 13948 transitions. [2022-10-17 10:47:09,656 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9486 states and 13948 transitions. [2022-10-17 10:47:09,710 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 9108 [2022-10-17 10:47:09,775 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9486 states to 9486 states and 13948 transitions. [2022-10-17 10:47:09,775 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9486 [2022-10-17 10:47:09,785 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9486 [2022-10-17 10:47:09,785 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9486 states and 13948 transitions. [2022-10-17 10:47:09,798 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:47:09,798 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9486 states and 13948 transitions. [2022-10-17 10:47:09,809 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9486 states and 13948 transitions. [2022-10-17 10:47:09,911 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9486 to 3424. [2022-10-17 10:47:09,919 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3424 states, 3424 states have (on average 1.4608644859813085) internal successors, (5002), 3423 states have internal predecessors, (5002), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:47:09,930 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3424 states to 3424 states and 5002 transitions. [2022-10-17 10:47:09,930 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3424 states and 5002 transitions. [2022-10-17 10:47:09,931 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-10-17 10:47:09,931 INFO L428 stractBuchiCegarLoop]: Abstraction has 3424 states and 5002 transitions. [2022-10-17 10:47:09,931 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-10-17 10:47:09,931 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3424 states and 5002 transitions. [2022-10-17 10:47:09,947 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3270 [2022-10-17 10:47:09,947 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:47:09,947 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:47:09,949 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:47:09,949 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:47:09,950 INFO L748 eck$LassoCheckResult]: Stem: 37602#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 37603#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 37524#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 37525#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 37359#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 37360#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36936#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 36937#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 37019#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 37795#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 36906#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 36907#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 37325#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 37348#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 37023#L866 assume !(0 == ~M_E~0); 37024#L866-2 assume !(0 == ~T1_E~0); 37553#L871-1 assume !(0 == ~T2_E~0); 37554#L876-1 assume !(0 == ~T3_E~0); 37865#L881-1 assume !(0 == ~T4_E~0); 37564#L886-1 assume !(0 == ~T5_E~0); 37314#L891-1 assume !(0 == ~T6_E~0); 37315#L896-1 assume !(0 == ~T7_E~0); 37556#L901-1 assume !(0 == ~T8_E~0); 37577#L906-1 assume !(0 == ~E_M~0); 37578#L911-1 assume !(0 == ~E_1~0); 37357#L916-1 assume !(0 == ~E_2~0); 37358#L921-1 assume !(0 == ~E_3~0); 37685#L926-1 assume !(0 == ~E_4~0); 37811#L931-1 assume !(0 == ~E_5~0); 37876#L936-1 assume !(0 == ~E_6~0); 37892#L941-1 assume !(0 == ~E_7~0); 37364#L946-1 assume !(0 == ~E_8~0); 37365#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37840#L430 assume !(1 == ~m_pc~0); 37220#L430-2 is_master_triggered_~__retres1~0#1 := 0; 36842#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36843#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 37483#L1073 assume !(0 != activate_threads_~tmp~1#1); 37484#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37668#L449 assume 1 == ~t1_pc~0; 37669#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 37027#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36799#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 36800#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 37592#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37423#L468 assume !(1 == ~t2_pc~0); 36826#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 36825#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 37322#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 37227#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 36844#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36845#L487 assume 1 == ~t3_pc~0; 37860#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 36940#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36941#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 37653#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 37287#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37288#L506 assume !(1 == ~t4_pc~0); 37417#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 37465#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37826#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 37827#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 37412#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37236#L525 assume 1 == ~t5_pc~0; 37172#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 36885#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37367#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 37368#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 37083#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 37084#L544 assume !(1 == ~t6_pc~0); 37237#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 37238#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37609#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36866#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 36867#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37782#L563 assume 1 == ~t7_pc~0; 37628#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 36895#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 36896#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 37321#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 37030#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 37031#L582 assume 1 == ~t8_pc~0; 36951#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 36952#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37861#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37275#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 37173#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37174#L964 assume !(1 == ~M_E~0); 37672#L964-2 assume !(1 == ~T1_E~0); 37085#L969-1 assume !(1 == ~T2_E~0); 37086#L974-1 assume !(1 == ~T3_E~0); 37703#L979-1 assume !(1 == ~T4_E~0); 37704#L984-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 37243#L989-1 assume !(1 == ~T6_E~0); 37244#L994-1 assume !(1 == ~T7_E~0); 37129#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 37130#L1004-1 assume !(1 == ~E_M~0); 36868#L1009-1 assume !(1 == ~E_1~0); 36869#L1014-1 assume !(1 == ~E_2~0); 38102#L1019-1 assume !(1 == ~E_3~0); 38078#L1024-1 assume 1 == ~E_4~0;~E_4~0 := 2; 38061#L1029-1 assume !(1 == ~E_5~0); 38040#L1034-1 assume !(1 == ~E_6~0); 38026#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 38015#L1044-1 assume !(1 == ~E_8~0); 38006#L1049-1 assume { :end_inline_reset_delta_events } true; 37999#L1315-2 [2022-10-17 10:47:09,950 INFO L750 eck$LassoCheckResult]: Loop: 37999#L1315-2 assume !false; 37994#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 37993#L841 assume !false; 37992#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 37987#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 37982#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 37981#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 37979#L724 assume !(0 != eval_~tmp~0#1); 37978#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 37977#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 37976#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 37863#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 37148#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 37149#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 37162#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 37163#L886-3 assume !(0 == ~T5_E~0); 37392#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 37393#L896-3 assume !(0 == ~T7_E~0); 37256#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 37257#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 37394#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 37621#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 37194#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 37195#L926-3 assume !(0 == ~E_4~0); 37604#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 40079#L936-3 assume !(0 == ~E_6~0); 40075#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 37695#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 37150#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37151#L430-30 assume 1 == ~m_pc~0; 37175#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 37176#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36956#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 36957#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 40018#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40016#L449-30 assume !(1 == ~t1_pc~0); 40012#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 40010#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40008#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 40006#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 40004#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40002#L468-30 assume 1 == ~t2_pc~0; 39998#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 39996#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39994#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 39992#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 39990#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39988#L487-30 assume !(1 == ~t3_pc~0); 39984#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 39982#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 39980#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 39978#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 39976#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 39974#L506-30 assume 1 == ~t4_pc~0; 39970#L507-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 39968#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39966#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 39964#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 39963#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 39962#L525-30 assume 1 == ~t5_pc~0; 39960#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 39959#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 39958#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 39957#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 39956#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 39955#L544-30 assume 1 == ~t6_pc~0; 39953#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 39952#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 39951#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 37787#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 37788#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37756#L563-30 assume 1 == ~t7_pc~0; 36967#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 36968#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 36990#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 37323#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 37324#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 37739#L582-30 assume !(1 == ~t8_pc~0); 37740#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 38459#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 38457#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 38428#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 38426#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38424#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 36871#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 38368#L969-3 assume !(1 == ~T2_E~0); 38366#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 38364#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 38347#L984-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 38343#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 38332#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 38330#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 38329#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 38327#L1009-3 assume !(1 == ~E_1~0); 38307#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 38306#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 38284#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 38280#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 38278#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 38276#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 38274#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 38273#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 38265#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 38111#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 38109#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 38107#L1334 assume !(0 == start_simulation_~tmp~3#1); 37753#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 38087#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 38077#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 38060#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 38039#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 38025#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 38014#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 38005#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 37999#L1315-2 [2022-10-17 10:47:09,951 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:47:09,951 INFO L85 PathProgramCache]: Analyzing trace with hash -2109236796, now seen corresponding path program 1 times [2022-10-17 10:47:09,951 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:47:09,951 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [533694876] [2022-10-17 10:47:09,951 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:47:09,951 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:47:09,994 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:47:10,047 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:47:10,047 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:47:10,047 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [533694876] [2022-10-17 10:47:10,047 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [533694876] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:47:10,047 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:47:10,048 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:47:10,048 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [516866697] [2022-10-17 10:47:10,048 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:47:10,048 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:47:10,049 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:47:10,049 INFO L85 PathProgramCache]: Analyzing trace with hash 1404058164, now seen corresponding path program 1 times [2022-10-17 10:47:10,049 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:47:10,049 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [189361653] [2022-10-17 10:47:10,049 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:47:10,049 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:47:10,062 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:47:10,095 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:47:10,095 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:47:10,095 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [189361653] [2022-10-17 10:47:10,095 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [189361653] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:47:10,096 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:47:10,096 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:47:10,096 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1958794988] [2022-10-17 10:47:10,096 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:47:10,096 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:47:10,097 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:47:10,097 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-10-17 10:47:10,097 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-10-17 10:47:10,097 INFO L87 Difference]: Start difference. First operand 3424 states and 5002 transitions. cyclomatic complexity: 1582 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:47:10,358 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:47:10,358 INFO L93 Difference]: Finished difference Result 9389 states and 13529 transitions. [2022-10-17 10:47:10,358 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9389 states and 13529 transitions. [2022-10-17 10:47:10,411 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8960 [2022-10-17 10:47:10,463 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9389 states to 9389 states and 13529 transitions. [2022-10-17 10:47:10,463 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9389 [2022-10-17 10:47:10,473 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9389 [2022-10-17 10:47:10,473 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9389 states and 13529 transitions. [2022-10-17 10:47:10,485 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:47:10,486 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9389 states and 13529 transitions. [2022-10-17 10:47:10,498 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9389 states and 13529 transitions. [2022-10-17 10:47:10,720 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9389 to 8901. [2022-10-17 10:47:10,745 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8901 states, 8901 states have (on average 1.4448938321536906) internal successors, (12861), 8900 states have internal predecessors, (12861), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:47:10,781 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8901 states to 8901 states and 12861 transitions. [2022-10-17 10:47:10,781 INFO L240 hiAutomatonCegarLoop]: Abstraction has 8901 states and 12861 transitions. [2022-10-17 10:47:10,782 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-10-17 10:47:10,784 INFO L428 stractBuchiCegarLoop]: Abstraction has 8901 states and 12861 transitions. [2022-10-17 10:47:10,784 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-10-17 10:47:10,784 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8901 states and 12861 transitions. [2022-10-17 10:47:10,824 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8732 [2022-10-17 10:47:10,824 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:47:10,824 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:47:10,826 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:47:10,826 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:47:10,827 INFO L748 eck$LassoCheckResult]: Stem: 50435#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 50436#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 50351#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 50352#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 50182#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 50183#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 49760#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 49761#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 49842#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 50656#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 49730#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 49731#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 50146#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 50171#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 49846#L866 assume !(0 == ~M_E~0); 49847#L866-2 assume !(0 == ~T1_E~0); 50381#L871-1 assume !(0 == ~T2_E~0); 50382#L876-1 assume !(0 == ~T3_E~0); 50740#L881-1 assume !(0 == ~T4_E~0); 50394#L886-1 assume !(0 == ~T5_E~0); 50137#L891-1 assume !(0 == ~T6_E~0); 50138#L896-1 assume !(0 == ~T7_E~0); 50385#L901-1 assume !(0 == ~T8_E~0); 50405#L906-1 assume !(0 == ~E_M~0); 50406#L911-1 assume !(0 == ~E_1~0); 50180#L916-1 assume !(0 == ~E_2~0); 50181#L921-1 assume !(0 == ~E_3~0); 50537#L926-1 assume !(0 == ~E_4~0); 50672#L931-1 assume !(0 == ~E_5~0); 50754#L936-1 assume !(0 == ~E_6~0); 50772#L941-1 assume !(0 == ~E_7~0); 50188#L946-1 assume !(0 == ~E_8~0); 50189#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 50711#L430 assume !(1 == ~m_pc~0); 50625#L430-2 is_master_triggered_~__retres1~0#1 := 0; 49663#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 49664#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 50304#L1073 assume !(0 != activate_threads_~tmp~1#1); 50314#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 50515#L449 assume !(1 == ~t1_pc~0); 49849#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 49850#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 49622#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 49623#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 50422#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50247#L468 assume !(1 == ~t2_pc~0); 49647#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 49646#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50145#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 50047#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 49665#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49666#L487 assume 1 == ~t3_pc~0; 50735#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 49764#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49765#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 50499#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 50112#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 50113#L506 assume !(1 == ~t4_pc~0); 50243#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 50297#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 50692#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 50693#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 50235#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 50058#L525 assume 1 == ~t5_pc~0; 49997#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 49707#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 50191#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 50192#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 49907#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 49908#L544 assume !(1 == ~t6_pc~0); 50059#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 50060#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 50442#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 49689#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 49690#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50640#L563 assume 1 == ~t7_pc~0; 50461#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 49717#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49718#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 50139#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 49851#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 49852#L582 assume 1 == ~t8_pc~0; 49775#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 49776#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 50736#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 50099#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 49998#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49999#L964 assume !(1 == ~M_E~0); 50519#L964-2 assume !(1 == ~T1_E~0); 49909#L969-1 assume !(1 == ~T2_E~0); 49910#L974-1 assume !(1 == ~T3_E~0); 50557#L979-1 assume !(1 == ~T4_E~0); 50558#L984-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 53913#L989-1 assume !(1 == ~T6_E~0); 53912#L994-1 assume !(1 == ~T7_E~0); 53911#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 53910#L1004-1 assume !(1 == ~E_M~0); 53909#L1009-1 assume !(1 == ~E_1~0); 53908#L1014-1 assume !(1 == ~E_2~0); 53907#L1019-1 assume !(1 == ~E_3~0); 53906#L1024-1 assume 1 == ~E_4~0;~E_4~0 := 2; 49871#L1029-1 assume !(1 == ~E_5~0); 49872#L1034-1 assume !(1 == ~E_6~0); 49968#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 50702#L1044-1 assume !(1 == ~E_8~0); 50155#L1049-1 assume { :end_inline_reset_delta_events } true; 49840#L1315-2 [2022-10-17 10:47:10,827 INFO L750 eck$LassoCheckResult]: Loop: 49840#L1315-2 assume !false; 49841#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 49625#L841 assume !false; 49969#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 49902#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 49903#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 49742#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 49660#L724 assume !(0 != eval_~tmp~0#1); 49662#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 50573#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 49671#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 49672#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 49972#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 49973#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 49986#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 49987#L886-3 assume !(0 == ~T5_E~0); 50215#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 50216#L896-3 assume !(0 == ~T7_E~0); 50082#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 50083#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 50217#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 50454#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 50020#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 50021#L926-3 assume !(0 == ~E_4~0); 50437#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 50088#L936-3 assume !(0 == ~E_6~0); 50089#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 50234#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 58153#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 58151#L430-30 assume !(1 == ~m_pc~0); 58149#L430-32 is_master_triggered_~__retres1~0#1 := 0; 58147#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 58145#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 58143#L1073-30 assume !(0 != activate_threads_~tmp~1#1); 58140#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 58138#L449-30 assume !(1 == ~t1_pc~0); 58136#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 58134#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 58132#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 58130#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 58127#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 58125#L468-30 assume 1 == ~t2_pc~0; 58121#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 58119#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 58117#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 58116#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 58113#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 58111#L487-30 assume !(1 == ~t3_pc~0); 58108#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 58106#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 58104#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 58102#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 58099#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 58097#L506-30 assume 1 == ~t4_pc~0; 58094#L507-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 58092#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 58090#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 58088#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 58087#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 58086#L525-30 assume 1 == ~t5_pc~0; 58084#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 57950#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 57949#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 57948#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 57947#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 57946#L544-30 assume 1 == ~t6_pc~0; 57944#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 57943#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 57942#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 57940#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 57939#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 57938#L563-30 assume !(1 == ~t7_pc~0); 57936#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 57933#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 57931#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 57929#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 57925#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 57923#L582-30 assume !(1 == ~t8_pc~0); 57920#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 57918#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 57915#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 57913#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 57911#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 57910#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 54657#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 57907#L969-3 assume !(1 == ~T2_E~0); 57905#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 57903#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 57901#L984-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 57392#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 57897#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 57895#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 57893#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 57891#L1009-3 assume !(1 == ~E_1~0); 57889#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 57886#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 57884#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 54427#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 57881#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 57880#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 57879#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 57878#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 57858#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 57854#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 56843#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 50830#L1334 assume !(0 == start_simulation_~tmp~3#1); 50612#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 49918#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 49626#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 49627#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 50233#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 50675#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 50443#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 50444#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 49840#L1315-2 [2022-10-17 10:47:10,828 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:47:10,828 INFO L85 PathProgramCache]: Analyzing trace with hash 28257477, now seen corresponding path program 1 times [2022-10-17 10:47:10,828 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:47:10,828 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1167308465] [2022-10-17 10:47:10,828 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:47:10,829 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:47:10,844 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:47:10,903 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:47:10,903 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:47:10,903 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1167308465] [2022-10-17 10:47:10,903 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1167308465] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:47:10,903 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:47:10,904 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:47:10,904 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [661255018] [2022-10-17 10:47:10,904 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:47:10,905 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:47:10,905 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:47:10,905 INFO L85 PathProgramCache]: Analyzing trace with hash 1027563768, now seen corresponding path program 1 times [2022-10-17 10:47:10,905 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:47:10,906 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1543010397] [2022-10-17 10:47:10,906 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:47:10,906 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:47:10,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:47:11,042 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:47:11,043 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:47:11,043 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1543010397] [2022-10-17 10:47:11,043 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1543010397] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:47:11,043 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:47:11,044 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:47:11,044 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [622833144] [2022-10-17 10:47:11,044 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:47:11,045 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:47:11,045 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:47:11,045 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-10-17 10:47:11,045 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-10-17 10:47:11,046 INFO L87 Difference]: Start difference. First operand 8901 states and 12861 transitions. cyclomatic complexity: 3968 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:47:11,402 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:47:11,402 INFO L93 Difference]: Finished difference Result 25288 states and 36118 transitions. [2022-10-17 10:47:11,402 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 25288 states and 36118 transitions. [2022-10-17 10:47:11,561 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 24508 [2022-10-17 10:47:11,675 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 25288 states to 25288 states and 36118 transitions. [2022-10-17 10:47:11,675 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 25288 [2022-10-17 10:47:11,704 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 25288 [2022-10-17 10:47:11,704 INFO L73 IsDeterministic]: Start isDeterministic. Operand 25288 states and 36118 transitions. [2022-10-17 10:47:11,852 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:47:11,852 INFO L218 hiAutomatonCegarLoop]: Abstraction has 25288 states and 36118 transitions. [2022-10-17 10:47:11,891 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25288 states and 36118 transitions. [2022-10-17 10:47:12,265 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25288 to 24458. [2022-10-17 10:47:12,301 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24458 states, 24458 states have (on average 1.4311881592934828) internal successors, (35004), 24457 states have internal predecessors, (35004), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:47:12,381 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24458 states to 24458 states and 35004 transitions. [2022-10-17 10:47:12,382 INFO L240 hiAutomatonCegarLoop]: Abstraction has 24458 states and 35004 transitions. [2022-10-17 10:47:12,382 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-10-17 10:47:12,383 INFO L428 stractBuchiCegarLoop]: Abstraction has 24458 states and 35004 transitions. [2022-10-17 10:47:12,383 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-10-17 10:47:12,383 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 24458 states and 35004 transitions. [2022-10-17 10:47:12,475 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 24250 [2022-10-17 10:47:12,476 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:47:12,476 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:47:12,478 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:47:12,478 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:47:12,478 INFO L748 eck$LassoCheckResult]: Stem: 84620#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 84621#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 84539#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 84540#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 84381#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 84382#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 83957#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 83958#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 84039#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 84826#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 83928#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 83929#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 84347#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 84370#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 84045#L866 assume !(0 == ~M_E~0); 84046#L866-2 assume !(0 == ~T1_E~0); 84570#L871-1 assume !(0 == ~T2_E~0); 84571#L876-1 assume !(0 == ~T3_E~0); 84892#L881-1 assume !(0 == ~T4_E~0); 84581#L886-1 assume !(0 == ~T5_E~0); 84336#L891-1 assume !(0 == ~T6_E~0); 84337#L896-1 assume !(0 == ~T7_E~0); 84573#L901-1 assume !(0 == ~T8_E~0); 84595#L906-1 assume !(0 == ~E_M~0); 84596#L911-1 assume !(0 == ~E_1~0); 84379#L916-1 assume !(0 == ~E_2~0); 84380#L921-1 assume !(0 == ~E_3~0); 84713#L926-1 assume !(0 == ~E_4~0); 84838#L931-1 assume !(0 == ~E_5~0); 84903#L936-1 assume !(0 == ~E_6~0); 84914#L941-1 assume !(0 == ~E_7~0); 84386#L946-1 assume !(0 == ~E_8~0); 84387#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 84872#L430 assume !(1 == ~m_pc~0); 84801#L430-2 is_master_triggered_~__retres1~0#1 := 0; 83864#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 83865#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 84495#L1073 assume !(0 != activate_threads_~tmp~1#1); 84506#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 84694#L449 assume !(1 == ~t1_pc~0); 84048#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 84049#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 83821#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 83822#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 84610#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 84445#L468 assume !(1 == ~t2_pc~0); 83848#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 83847#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 84344#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 84254#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 83866#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 83867#L487 assume !(1 == ~t3_pc~0); 83985#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 83961#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 83962#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 84678#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 84312#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 84313#L506 assume !(1 == ~t4_pc~0); 84439#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 84491#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 84856#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 84857#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 84434#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 84263#L525 assume 1 == ~t5_pc~0; 84198#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 83906#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 84389#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 84390#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 84106#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 84107#L544 assume !(1 == ~t6_pc~0); 84264#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 84265#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 84627#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 83888#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 83889#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 84813#L563 assume 1 == ~t7_pc~0; 84648#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 83916#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 83917#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 84343#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 84052#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 84053#L582 assume 1 == ~t8_pc~0; 83972#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 83973#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 84889#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 84302#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 84199#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 84200#L964 assume !(1 == ~M_E~0); 84697#L964-2 assume !(1 == ~T1_E~0); 88031#L969-1 assume !(1 == ~T2_E~0); 88030#L974-1 assume !(1 == ~T3_E~0); 84731#L979-1 assume !(1 == ~T4_E~0); 84732#L984-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 88028#L989-1 assume !(1 == ~T6_E~0); 88029#L994-1 assume !(1 == ~T7_E~0); 88027#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 87989#L1004-1 assume !(1 == ~E_M~0); 87990#L1009-1 assume !(1 == ~E_1~0); 84142#L1014-1 assume !(1 == ~E_2~0); 84143#L1019-1 assume !(1 == ~E_3~0); 87966#L1024-1 assume 1 == ~E_4~0;~E_4~0 := 2; 87965#L1029-1 assume !(1 == ~E_5~0); 87964#L1034-1 assume !(1 == ~E_6~0); 87963#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 87962#L1044-1 assume !(1 == ~E_8~0); 87961#L1049-1 assume { :end_inline_reset_delta_events } true; 87950#L1315-2 [2022-10-17 10:47:12,479 INFO L750 eck$LassoCheckResult]: Loop: 87950#L1315-2 assume !false; 87942#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 87939#L841 assume !false; 87933#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 87934#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 107272#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 107271#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 107269#L724 assume !(0 != eval_~tmp~0#1); 107270#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 107712#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 107711#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 107710#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 107709#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 107708#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 107707#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 107706#L886-3 assume !(0 == ~T5_E~0); 107705#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 107704#L896-3 assume !(0 == ~T7_E~0); 107703#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 107702#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 107701#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 107700#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 107699#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 107698#L926-3 assume !(0 == ~E_4~0); 107697#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 107696#L936-3 assume !(0 == ~E_6~0); 107695#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 107694#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 107693#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 107692#L430-30 assume !(1 == ~m_pc~0); 107691#L430-32 is_master_triggered_~__retres1~0#1 := 0; 107690#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 107689#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 107688#L1073-30 assume !(0 != activate_threads_~tmp~1#1); 107687#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 107686#L449-30 assume !(1 == ~t1_pc~0); 107685#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 107684#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 107683#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 107682#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 107681#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 107680#L468-30 assume !(1 == ~t2_pc~0); 107679#L468-32 is_transmit2_triggered_~__retres1~2#1 := 0; 107677#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 107676#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 107675#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 107674#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 107673#L487-30 assume !(1 == ~t3_pc~0); 107672#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 107671#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 107670#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 107669#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 107668#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 107667#L506-30 assume 1 == ~t4_pc~0; 107665#L507-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 107664#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 107663#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 107662#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 107661#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 107660#L525-30 assume !(1 == ~t5_pc~0); 107659#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 107657#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 107656#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 107655#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 107654#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 107653#L544-30 assume 1 == ~t6_pc~0; 107651#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 107650#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 107649#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 107648#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 107647#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 107646#L563-30 assume !(1 == ~t7_pc~0); 107645#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 107643#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 107642#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 107641#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 107640#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 107639#L582-30 assume !(1 == ~t8_pc~0); 107637#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 107636#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 107635#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 107634#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 107633#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 107632#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 88128#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 107631#L969-3 assume !(1 == ~T2_E~0); 107630#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 88117#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 88118#L984-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 107324#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 107323#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 107322#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 107321#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 107320#L1009-3 assume !(1 == ~E_1~0); 107319#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 107318#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 107317#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 99740#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 107316#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 107315#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 107314#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 107313#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 107306#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 107303#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 107302#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 107301#L1334 assume !(0 == start_simulation_~tmp~3#1); 107300#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 88054#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 88046#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 88045#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 88044#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 88043#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 88019#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 87960#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 87950#L1315-2 [2022-10-17 10:47:12,479 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:47:12,480 INFO L85 PathProgramCache]: Analyzing trace with hash -1079871162, now seen corresponding path program 1 times [2022-10-17 10:47:12,480 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:47:12,480 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [485661073] [2022-10-17 10:47:12,480 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:47:12,480 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:47:12,495 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:47:12,677 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:47:12,677 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:47:12,677 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [485661073] [2022-10-17 10:47:12,678 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [485661073] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:47:12,678 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:47:12,678 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-10-17 10:47:12,678 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [408434072] [2022-10-17 10:47:12,678 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:47:12,681 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:47:12,682 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:47:12,682 INFO L85 PathProgramCache]: Analyzing trace with hash 2051423162, now seen corresponding path program 1 times [2022-10-17 10:47:12,682 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:47:12,682 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1265894246] [2022-10-17 10:47:12,682 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:47:12,682 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:47:12,697 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:47:12,742 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:47:12,742 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:47:12,742 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1265894246] [2022-10-17 10:47:12,742 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1265894246] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:47:12,742 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:47:12,742 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:47:12,743 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [657925633] [2022-10-17 10:47:12,743 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:47:12,743 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:47:12,744 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:47:12,744 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:47:12,744 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:47:12,744 INFO L87 Difference]: Start difference. First operand 24458 states and 35004 transitions. cyclomatic complexity: 10562 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 2 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:47:13,178 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:47:13,178 INFO L93 Difference]: Finished difference Result 46152 states and 65785 transitions. [2022-10-17 10:47:13,178 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 46152 states and 65785 transitions. [2022-10-17 10:47:13,436 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 45813 [2022-10-17 10:47:13,762 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 46152 states to 46152 states and 65785 transitions. [2022-10-17 10:47:13,762 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 46152 [2022-10-17 10:47:13,805 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 46152 [2022-10-17 10:47:13,805 INFO L73 IsDeterministic]: Start isDeterministic. Operand 46152 states and 65785 transitions. [2022-10-17 10:47:13,848 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:47:13,848 INFO L218 hiAutomatonCegarLoop]: Abstraction has 46152 states and 65785 transitions. [2022-10-17 10:47:13,891 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 46152 states and 65785 transitions. [2022-10-17 10:47:14,514 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 46152 to 46080. [2022-10-17 10:47:14,742 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 46080 states, 46080 states have (on average 1.4260633680555554) internal successors, (65713), 46079 states have internal predecessors, (65713), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:47:15,016 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46080 states to 46080 states and 65713 transitions. [2022-10-17 10:47:15,017 INFO L240 hiAutomatonCegarLoop]: Abstraction has 46080 states and 65713 transitions. [2022-10-17 10:47:15,021 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:47:15,022 INFO L428 stractBuchiCegarLoop]: Abstraction has 46080 states and 65713 transitions. [2022-10-17 10:47:15,022 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-10-17 10:47:15,022 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 46080 states and 65713 transitions. [2022-10-17 10:47:15,369 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 45741 [2022-10-17 10:47:15,369 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:47:15,370 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:47:15,372 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:47:15,372 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:47:15,373 INFO L748 eck$LassoCheckResult]: Stem: 155282#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 155283#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 155192#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 155193#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 155010#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 155011#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 154573#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 154574#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 154658#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 155548#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 154544#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 154545#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 154976#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 154999#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 154664#L866 assume !(0 == ~M_E~0); 154665#L866-2 assume !(0 == ~T1_E~0); 155226#L871-1 assume !(0 == ~T2_E~0); 155227#L876-1 assume !(0 == ~T3_E~0); 155649#L881-1 assume !(0 == ~T4_E~0); 155238#L886-1 assume !(0 == ~T5_E~0); 154965#L891-1 assume !(0 == ~T6_E~0); 154966#L896-1 assume !(0 == ~T7_E~0); 155229#L901-1 assume !(0 == ~T8_E~0); 155252#L906-1 assume !(0 == ~E_M~0); 155253#L911-1 assume !(0 == ~E_1~0); 155008#L916-1 assume !(0 == ~E_2~0); 155009#L921-1 assume !(0 == ~E_3~0); 155393#L926-1 assume !(0 == ~E_4~0); 155566#L931-1 assume !(0 == ~E_5~0); 155677#L936-1 assume !(0 == ~E_6~0); 155696#L941-1 assume !(0 == ~E_7~0); 155016#L946-1 assume !(0 == ~E_8~0); 155017#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 155614#L430 assume !(1 == ~m_pc~0); 155509#L430-2 is_master_triggered_~__retres1~0#1 := 0; 154480#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 154481#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 155136#L1073 assume !(0 != activate_threads_~tmp~1#1); 155153#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 155372#L449 assume !(1 == ~t1_pc~0); 154667#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 154668#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 154438#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 154439#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 155268#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 155077#L468 assume !(1 == ~t2_pc~0); 154464#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 154463#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 154973#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 154873#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 154482#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 154483#L487 assume !(1 == ~t3_pc~0); 154601#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 154577#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 154578#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 155350#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 154938#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 154939#L506 assume !(1 == ~t4_pc~0); 155073#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 155127#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 155587#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 155588#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 155069#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 154883#L525 assume !(1 == ~t5_pc~0); 154521#L525-2 is_transmit5_triggered_~__retres1~5#1 := 0; 154522#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 155020#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 155021#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 154726#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 154727#L544 assume !(1 == ~t6_pc~0); 154884#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 154885#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 155291#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 154504#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 154505#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 155525#L563 assume 1 == ~t7_pc~0; 155310#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 154532#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 154533#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 154972#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 154671#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 154672#L582 assume 1 == ~t8_pc~0; 154588#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 154589#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 155642#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 154926#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 154820#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 154821#L964 assume !(1 == ~M_E~0); 155376#L964-2 assume !(1 == ~T1_E~0); 154728#L969-1 assume !(1 == ~T2_E~0); 154729#L974-1 assume !(1 == ~T3_E~0); 155413#L979-1 assume !(1 == ~T4_E~0); 155414#L984-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 164107#L989-1 assume !(1 == ~T6_E~0); 164106#L994-1 assume !(1 == ~T7_E~0); 164105#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 164104#L1004-1 assume !(1 == ~E_M~0); 164103#L1009-1 assume !(1 == ~E_1~0); 164102#L1014-1 assume !(1 == ~E_2~0); 164101#L1019-1 assume !(1 == ~E_3~0); 164100#L1024-1 assume 1 == ~E_4~0;~E_4~0 := 2; 155624#L1029-1 assume !(1 == ~E_5~0); 169726#L1034-1 assume !(1 == ~E_6~0); 169724#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 169721#L1044-1 assume !(1 == ~E_8~0); 169719#L1049-1 assume { :end_inline_reset_delta_events } true; 169713#L1315-2 [2022-10-17 10:47:15,373 INFO L750 eck$LassoCheckResult]: Loop: 169713#L1315-2 assume !false; 169708#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 164092#L841 assume !false; 164093#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 164035#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 164031#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 164009#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 164010#L724 assume !(0 != eval_~tmp~0#1); 169688#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 171106#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 171103#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 171101#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 171099#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 171085#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 171079#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 171074#L886-3 assume !(0 == ~T5_E~0); 171069#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 171063#L896-3 assume !(0 == ~T7_E~0); 171059#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 171054#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 171049#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 171044#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 171038#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 171033#L926-3 assume !(0 == ~E_4~0); 171028#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 171021#L936-3 assume !(0 == ~E_6~0); 171017#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 171013#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 171009#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 171005#L430-30 assume !(1 == ~m_pc~0); 171001#L430-32 is_master_triggered_~__retres1~0#1 := 0; 170996#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 170990#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 170986#L1073-30 assume !(0 != activate_threads_~tmp~1#1); 170981#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 170978#L449-30 assume !(1 == ~t1_pc~0); 170975#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 169964#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 169961#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 169959#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 169957#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 169955#L468-30 assume 1 == ~t2_pc~0; 169952#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 169950#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 169948#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 169946#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 169944#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 169942#L487-30 assume !(1 == ~t3_pc~0); 169940#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 169938#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 169935#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 169933#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 169931#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 169929#L506-30 assume 1 == ~t4_pc~0; 169926#L507-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 169924#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 169922#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 169920#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 169918#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 169916#L525-30 assume !(1 == ~t5_pc~0); 169914#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 169912#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 169909#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 169907#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 169905#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 169903#L544-30 assume 1 == ~t6_pc~0; 169900#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 169898#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 169895#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 169893#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 169891#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 169889#L563-30 assume 1 == ~t7_pc~0; 169886#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 169884#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 169881#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 169879#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 169877#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 169875#L582-30 assume !(1 == ~t8_pc~0); 169872#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 169870#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 169868#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 169866#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 169864#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 169862#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 165714#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 169859#L969-3 assume !(1 == ~T2_E~0); 169857#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 169855#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 169853#L984-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 169849#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 169847#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 169845#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 169843#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 169841#L1009-3 assume !(1 == ~E_1~0); 169839#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 169837#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 169835#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 169832#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 169830#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 169828#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 169826#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 169824#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 169781#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 169776#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 169774#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 169772#L1334 assume !(0 == start_simulation_~tmp~3#1); 169769#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 169748#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 169739#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 169737#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 169735#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 169733#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 169731#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 169718#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 169713#L1315-2 [2022-10-17 10:47:15,374 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:47:15,374 INFO L85 PathProgramCache]: Analyzing trace with hash 818659143, now seen corresponding path program 1 times [2022-10-17 10:47:15,374 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:47:15,374 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [120093190] [2022-10-17 10:47:15,374 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:47:15,375 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:47:15,403 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:47:15,477 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:47:15,478 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:47:15,478 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [120093190] [2022-10-17 10:47:15,478 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [120093190] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:47:15,478 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:47:15,479 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:47:15,479 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1539768212] [2022-10-17 10:47:15,479 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:47:15,479 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:47:15,480 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:47:15,480 INFO L85 PathProgramCache]: Analyzing trace with hash -1979095176, now seen corresponding path program 1 times [2022-10-17 10:47:15,480 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:47:15,480 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1685254467] [2022-10-17 10:47:15,481 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:47:15,481 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:47:15,500 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:47:15,545 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:47:15,546 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:47:15,546 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1685254467] [2022-10-17 10:47:15,546 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1685254467] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:47:15,546 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:47:15,547 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:47:15,547 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [564873283] [2022-10-17 10:47:15,547 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:47:15,547 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:47:15,548 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:47:15,548 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-10-17 10:47:15,548 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-10-17 10:47:15,548 INFO L87 Difference]: Start difference. First operand 46080 states and 65713 transitions. cyclomatic complexity: 19665 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:47:16,719 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:47:16,720 INFO L93 Difference]: Finished difference Result 127381 states and 180324 transitions. [2022-10-17 10:47:16,721 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 127381 states and 180324 transitions. [2022-10-17 10:47:17,542 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 124307 [2022-10-17 10:47:18,044 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 127381 states to 127381 states and 180324 transitions. [2022-10-17 10:47:18,045 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 127381 [2022-10-17 10:47:18,189 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 127381 [2022-10-17 10:47:18,190 INFO L73 IsDeterministic]: Start isDeterministic. Operand 127381 states and 180324 transitions. [2022-10-17 10:47:18,335 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:47:18,335 INFO L218 hiAutomatonCegarLoop]: Abstraction has 127381 states and 180324 transitions. [2022-10-17 10:47:18,433 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 127381 states and 180324 transitions. [2022-10-17 10:47:19,904 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 127381 to 123869. [2022-10-17 10:47:20,015 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 123869 states, 123869 states have (on average 1.419209003059684) internal successors, (175796), 123868 states have internal predecessors, (175796), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:47:20,715 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 123869 states to 123869 states and 175796 transitions. [2022-10-17 10:47:20,716 INFO L240 hiAutomatonCegarLoop]: Abstraction has 123869 states and 175796 transitions. [2022-10-17 10:47:20,721 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-10-17 10:47:20,722 INFO L428 stractBuchiCegarLoop]: Abstraction has 123869 states and 175796 transitions. [2022-10-17 10:47:20,722 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-10-17 10:47:20,722 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 123869 states and 175796 transitions. [2022-10-17 10:47:21,068 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 123227 [2022-10-17 10:47:21,068 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:47:21,068 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:47:21,071 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:47:21,071 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:47:21,072 INFO L748 eck$LassoCheckResult]: Stem: 328755#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 328756#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 328655#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 328656#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 328484#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 328485#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 328045#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 328046#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 328129#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 329020#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 328017#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 328018#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 328449#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 328473#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 328135#L866 assume !(0 == ~M_E~0); 328136#L866-2 assume !(0 == ~T1_E~0); 328689#L871-1 assume !(0 == ~T2_E~0); 328690#L876-1 assume !(0 == ~T3_E~0); 329114#L881-1 assume !(0 == ~T4_E~0); 328705#L886-1 assume !(0 == ~T5_E~0); 328438#L891-1 assume !(0 == ~T6_E~0); 328439#L896-1 assume !(0 == ~T7_E~0); 328693#L901-1 assume !(0 == ~T8_E~0); 328722#L906-1 assume !(0 == ~E_M~0); 328723#L911-1 assume !(0 == ~E_1~0); 328482#L916-1 assume !(0 == ~E_2~0); 328483#L921-1 assume !(0 == ~E_3~0); 328861#L926-1 assume !(0 == ~E_4~0); 329035#L931-1 assume !(0 == ~E_5~0); 329139#L936-1 assume !(0 == ~E_6~0); 329166#L941-1 assume !(0 == ~E_7~0); 328490#L946-1 assume !(0 == ~E_8~0); 328491#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 329078#L430 assume !(1 == ~m_pc~0); 328985#L430-2 is_master_triggered_~__retres1~0#1 := 0; 327952#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 327953#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 328607#L1073 assume !(0 != activate_threads_~tmp~1#1); 328619#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 328838#L449 assume !(1 == ~t1_pc~0); 328138#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 328139#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 327909#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 327910#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 328740#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 328552#L468 assume !(1 == ~t2_pc~0); 327936#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 327935#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 328446#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 328348#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 327954#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 327955#L487 assume !(1 == ~t3_pc~0); 328073#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 328049#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 328050#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 328823#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 328414#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 328415#L506 assume !(1 == ~t4_pc~0); 328546#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 328599#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 329056#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 329057#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 328544#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 328357#L525 assume !(1 == ~t5_pc~0); 327993#L525-2 is_transmit5_triggered_~__retres1~5#1 := 0; 327994#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 328493#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 328494#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 328196#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 328197#L544 assume !(1 == ~t6_pc~0); 328358#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 328359#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 328766#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 327976#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 327977#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 329001#L563 assume !(1 == ~t7_pc~0); 328762#L563-2 is_transmit7_triggered_~__retres1~7#1 := 0; 328004#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 328005#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 328445#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 328142#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 328143#L582 assume 1 == ~t8_pc~0; 328060#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 328061#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 329111#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 328403#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 328293#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 328294#L964 assume !(1 == ~M_E~0); 328843#L964-2 assume !(1 == ~T1_E~0); 328198#L969-1 assume !(1 == ~T2_E~0); 328199#L974-1 assume !(1 == ~T3_E~0); 328879#L979-1 assume !(1 == ~T4_E~0); 328880#L984-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 344800#L989-1 assume !(1 == ~T6_E~0); 328698#L994-1 assume !(1 == ~T7_E~0); 328699#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 328847#L1004-1 assume !(1 == ~E_M~0); 328848#L1009-1 assume !(1 == ~E_1~0); 328234#L1014-1 assume !(1 == ~E_2~0); 328235#L1019-1 assume !(1 == ~E_3~0); 329088#L1024-1 assume 1 == ~E_4~0;~E_4~0 := 2; 329089#L1029-1 assume !(1 == ~E_5~0); 345354#L1034-1 assume !(1 == ~E_6~0); 345353#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 345352#L1044-1 assume !(1 == ~E_8~0); 345350#L1049-1 assume { :end_inline_reset_delta_events } true; 345351#L1315-2 [2022-10-17 10:47:21,072 INFO L750 eck$LassoCheckResult]: Loop: 345351#L1315-2 assume !false; 398800#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 398799#L841 assume !false; 398798#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 337138#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 337132#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 337130#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 337115#L724 assume !(0 != eval_~tmp~0#1); 337117#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 399156#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 399155#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 399154#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 399153#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 399152#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 399151#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 399150#L886-3 assume !(0 == ~T5_E~0); 399149#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 399148#L896-3 assume !(0 == ~T7_E~0); 399147#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 399146#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 399145#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 399144#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 399143#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 399142#L926-3 assume !(0 == ~E_4~0); 399141#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 399140#L936-3 assume !(0 == ~E_6~0); 399139#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 399138#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 399137#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 399136#L430-30 assume !(1 == ~m_pc~0); 399135#L430-32 is_master_triggered_~__retres1~0#1 := 0; 399134#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 399133#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 399132#L1073-30 assume !(0 != activate_threads_~tmp~1#1); 399131#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 399130#L449-30 assume !(1 == ~t1_pc~0); 399129#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 399128#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 399127#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 399126#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 399125#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 399124#L468-30 assume 1 == ~t2_pc~0; 399122#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 399121#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 399120#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 399119#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 399118#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 399117#L487-30 assume !(1 == ~t3_pc~0); 399116#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 399115#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 399114#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 399113#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 399112#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 399111#L506-30 assume !(1 == ~t4_pc~0); 399110#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 399108#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 399107#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 399106#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 399105#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 399104#L525-30 assume !(1 == ~t5_pc~0); 399103#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 399102#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 399101#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 399100#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 399099#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 399098#L544-30 assume 1 == ~t6_pc~0; 399096#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 399095#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 399094#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 399093#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 399092#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 399091#L563-30 assume !(1 == ~t7_pc~0); 399090#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 399089#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 399088#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 399087#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 399086#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 399085#L582-30 assume 1 == ~t8_pc~0; 399084#L583-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 399082#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 399081#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 399080#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 399079#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 399078#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 393491#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 399075#L969-3 assume !(1 == ~T2_E~0); 399074#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 399073#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 399072#L984-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 393988#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 399071#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 399070#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 399069#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 399068#L1009-3 assume !(1 == ~E_1~0); 399067#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 399066#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 399065#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 399062#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 399061#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 399060#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 399059#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 399058#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 399033#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 399030#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 399029#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 399028#L1334 assume !(0 == start_simulation_~tmp~3#1); 399026#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 399024#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 399016#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 399015#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 399014#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 399013#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 399012#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 399011#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 345351#L1315-2 [2022-10-17 10:47:21,073 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:47:21,073 INFO L85 PathProgramCache]: Analyzing trace with hash -952811832, now seen corresponding path program 1 times [2022-10-17 10:47:21,073 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:47:21,073 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [142875833] [2022-10-17 10:47:21,074 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:47:21,074 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:47:21,088 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:47:21,134 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:47:21,135 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:47:21,135 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [142875833] [2022-10-17 10:47:21,135 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [142875833] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:47:21,135 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:47:21,135 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-10-17 10:47:21,136 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [461855072] [2022-10-17 10:47:21,136 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:47:21,136 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:47:21,136 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:47:21,137 INFO L85 PathProgramCache]: Analyzing trace with hash -177292679, now seen corresponding path program 1 times [2022-10-17 10:47:21,137 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:47:21,137 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1885288547] [2022-10-17 10:47:21,137 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:47:21,137 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:47:21,150 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:47:21,191 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:47:21,192 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:47:21,192 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1885288547] [2022-10-17 10:47:21,192 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1885288547] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:47:21,192 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:47:21,192 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:47:21,193 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [842698231] [2022-10-17 10:47:21,193 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:47:21,193 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:47:21,193 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:47:21,194 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:47:21,194 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:47:21,194 INFO L87 Difference]: Start difference. First operand 123869 states and 175796 transitions. cyclomatic complexity: 51991 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 2 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:47:22,499 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:47:22,499 INFO L93 Difference]: Finished difference Result 232565 states and 329282 transitions. [2022-10-17 10:47:22,499 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 232565 states and 329282 transitions. [2022-10-17 10:47:23,980 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 230996 [2022-10-17 10:47:24,687 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 232565 states to 232565 states and 329282 transitions. [2022-10-17 10:47:24,688 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 232565 [2022-10-17 10:47:24,795 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 232565 [2022-10-17 10:47:24,795 INFO L73 IsDeterministic]: Start isDeterministic. Operand 232565 states and 329282 transitions. [2022-10-17 10:47:24,899 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:47:24,900 INFO L218 hiAutomatonCegarLoop]: Abstraction has 232565 states and 329282 transitions. [2022-10-17 10:47:25,051 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 232565 states and 329282 transitions. [2022-10-17 10:47:27,221 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 232565 to 232133. [2022-10-17 10:47:27,398 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 232133 states, 232133 states have (on average 1.416644768300931) internal successors, (328850), 232132 states have internal predecessors, (328850), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:47:28,885 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 232133 states to 232133 states and 328850 transitions. [2022-10-17 10:47:28,885 INFO L240 hiAutomatonCegarLoop]: Abstraction has 232133 states and 328850 transitions. [2022-10-17 10:47:28,886 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:47:28,886 INFO L428 stractBuchiCegarLoop]: Abstraction has 232133 states and 328850 transitions. [2022-10-17 10:47:28,886 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-10-17 10:47:28,886 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 232133 states and 328850 transitions. [2022-10-17 10:47:29,588 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 230564 [2022-10-17 10:47:29,589 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:47:29,589 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:47:29,591 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:47:29,592 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:47:29,592 INFO L748 eck$LassoCheckResult]: Stem: 685166#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 685167#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 685077#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 685078#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 684914#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 684915#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 684482#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 684483#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 684563#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 685425#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 684454#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 684455#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 684881#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 684902#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 684569#L866 assume !(0 == ~M_E~0); 684570#L866-2 assume !(0 == ~T1_E~0); 685112#L871-1 assume !(0 == ~T2_E~0); 685113#L876-1 assume !(0 == ~T3_E~0); 685515#L881-1 assume !(0 == ~T4_E~0); 685124#L886-1 assume !(0 == ~T5_E~0); 684870#L891-1 assume !(0 == ~T6_E~0); 684871#L896-1 assume !(0 == ~T7_E~0); 685115#L901-1 assume !(0 == ~T8_E~0); 685139#L906-1 assume !(0 == ~E_M~0); 685140#L911-1 assume !(0 == ~E_1~0); 684912#L916-1 assume !(0 == ~E_2~0); 684913#L921-1 assume !(0 == ~E_3~0); 685263#L926-1 assume !(0 == ~E_4~0); 685441#L931-1 assume !(0 == ~E_5~0); 685533#L936-1 assume !(0 == ~E_6~0); 685551#L941-1 assume !(0 == ~E_7~0); 684919#L946-1 assume !(0 == ~E_8~0); 684920#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 685479#L430 assume !(1 == ~m_pc~0); 685391#L430-2 is_master_triggered_~__retres1~0#1 := 0; 684392#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 684393#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 685029#L1073 assume !(0 != activate_threads_~tmp~1#1); 685042#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 685244#L449 assume !(1 == ~t1_pc~0); 684572#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 684573#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 684350#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 684351#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 685155#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 684978#L468 assume !(1 == ~t2_pc~0); 684376#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 684375#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 684878#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 684782#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 684394#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 684395#L487 assume !(1 == ~t3_pc~0); 684507#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 684486#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 684487#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 685226#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 684846#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 684847#L506 assume !(1 == ~t4_pc~0); 684971#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 685025#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 685458#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 685459#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 684970#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 684792#L525 assume !(1 == ~t5_pc~0); 684431#L525-2 is_transmit5_triggered_~__retres1~5#1 := 0; 684432#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 684922#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 684923#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 684634#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 684635#L544 assume !(1 == ~t6_pc~0); 684793#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 684794#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 685175#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 684416#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 684417#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 685405#L563 assume !(1 == ~t7_pc~0); 685171#L563-2 is_transmit7_triggered_~__retres1~7#1 := 0; 684442#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 684443#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 684877#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 684576#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 684577#L582 assume !(1 == ~t8_pc~0); 685178#L582-2 is_transmit8_triggered_~__retres1~8#1 := 0; 685510#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 685511#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 684836#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 684724#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 684725#L964 assume !(1 == ~M_E~0); 685247#L964-2 assume !(1 == ~T1_E~0); 737258#L969-1 assume !(1 == ~T2_E~0); 737256#L974-1 assume !(1 == ~T3_E~0); 737254#L979-1 assume !(1 == ~T4_E~0); 737251#L984-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 737249#L989-1 assume !(1 == ~T6_E~0); 737247#L994-1 assume !(1 == ~T7_E~0); 737245#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 737243#L1004-1 assume !(1 == ~E_M~0); 737241#L1009-1 assume !(1 == ~E_1~0); 737239#L1014-1 assume !(1 == ~E_2~0); 737237#L1019-1 assume !(1 == ~E_3~0); 737235#L1024-1 assume 1 == ~E_4~0;~E_4~0 := 2; 684594#L1029-1 assume !(1 == ~E_5~0); 684595#L1034-1 assume !(1 == ~E_6~0); 684693#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 685469#L1044-1 assume !(1 == ~E_8~0); 684889#L1049-1 assume { :end_inline_reset_delta_events } true; 684890#L1315-2 [2022-10-17 10:47:29,593 INFO L750 eck$LassoCheckResult]: Loop: 684890#L1315-2 assume !false; 743259#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 743257#L841 assume !false; 743255#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 743241#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 743235#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 743233#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 743231#L724 assume !(0 != eval_~tmp~0#1); 743232#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 743639#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 743637#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 743635#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 743633#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 743631#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 743629#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 743627#L886-3 assume !(0 == ~T5_E~0); 743625#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 743622#L896-3 assume !(0 == ~T7_E~0); 743620#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 743618#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 743616#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 743614#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 743612#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 743610#L926-3 assume !(0 == ~E_4~0); 743608#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 743606#L936-3 assume !(0 == ~E_6~0); 743604#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 743602#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 743600#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 743597#L430-30 assume !(1 == ~m_pc~0); 743595#L430-32 is_master_triggered_~__retres1~0#1 := 0; 743593#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 743591#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 743589#L1073-30 assume !(0 != activate_threads_~tmp~1#1); 743587#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 743585#L449-30 assume !(1 == ~t1_pc~0); 743583#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 743581#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 743579#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 743577#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 743575#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 743572#L468-30 assume !(1 == ~t2_pc~0); 743570#L468-32 is_transmit2_triggered_~__retres1~2#1 := 0; 743567#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 743565#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 743563#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 743561#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 743559#L487-30 assume !(1 == ~t3_pc~0); 743557#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 743555#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 743553#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 743551#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 743549#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 743547#L506-30 assume !(1 == ~t4_pc~0); 743545#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 743542#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 743540#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 743538#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 743536#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 743534#L525-30 assume !(1 == ~t5_pc~0); 743532#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 743530#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 743528#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 743526#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 743524#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 743522#L544-30 assume 1 == ~t6_pc~0; 743519#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 743517#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 743515#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 743513#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 743511#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 743509#L563-30 assume !(1 == ~t7_pc~0); 743507#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 743505#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 743503#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 743501#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 743500#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 743499#L582-30 assume !(1 == ~t8_pc~0); 743498#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 743497#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 743495#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 743493#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 743491#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 743489#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 724551#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 743486#L969-3 assume !(1 == ~T2_E~0); 743484#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 743482#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 743480#L984-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 740979#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 743477#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 743475#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 743473#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 743470#L1009-3 assume !(1 == ~E_1~0); 743468#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 743466#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 743464#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 737308#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 743461#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 743459#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 743457#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 743455#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 743438#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 743434#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 743432#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 743430#L1334 assume !(0 == start_simulation_~tmp~3#1); 743427#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 743419#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 743410#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 743408#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 743406#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 743404#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 743402#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 743400#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 684890#L1315-2 [2022-10-17 10:47:29,593 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:47:29,594 INFO L85 PathProgramCache]: Analyzing trace with hash 1284551433, now seen corresponding path program 1 times [2022-10-17 10:47:29,594 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:47:29,594 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [362456007] [2022-10-17 10:47:29,594 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:47:29,595 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:47:29,612 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:47:29,681 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:47:29,682 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:47:29,682 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [362456007] [2022-10-17 10:47:29,682 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [362456007] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:47:29,682 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:47:29,683 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:47:29,683 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1207540979] [2022-10-17 10:47:29,683 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:47:29,683 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:47:29,684 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:47:29,684 INFO L85 PathProgramCache]: Analyzing trace with hash -1215011973, now seen corresponding path program 1 times [2022-10-17 10:47:29,684 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:47:29,684 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1652117133] [2022-10-17 10:47:29,685 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:47:29,685 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:47:29,700 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:47:29,740 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:47:29,740 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:47:29,740 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1652117133] [2022-10-17 10:47:29,740 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1652117133] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:47:29,740 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:47:29,741 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:47:29,741 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [955269039] [2022-10-17 10:47:29,741 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:47:29,741 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:47:29,742 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:47:29,742 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-10-17 10:47:29,742 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-10-17 10:47:29,742 INFO L87 Difference]: Start difference. First operand 232133 states and 328850 transitions. cyclomatic complexity: 96845 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:47:31,178 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:47:31,178 INFO L93 Difference]: Finished difference Result 177412 states and 250686 transitions. [2022-10-17 10:47:31,179 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 177412 states and 250686 transitions. [2022-10-17 10:47:31,840 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 176230