./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.09.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version dbf71c69 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_65b0ab96-2d5b-41f3-831b-40a13c2afcbd/bin/uautomizer-J5u9QxTXDZ/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_65b0ab96-2d5b-41f3-831b-40a13c2afcbd/bin/uautomizer-J5u9QxTXDZ/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_65b0ab96-2d5b-41f3-831b-40a13c2afcbd/bin/uautomizer-J5u9QxTXDZ/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_65b0ab96-2d5b-41f3-831b-40a13c2afcbd/bin/uautomizer-J5u9QxTXDZ/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.09.cil-2.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_65b0ab96-2d5b-41f3-831b-40a13c2afcbd/bin/uautomizer-J5u9QxTXDZ/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_65b0ab96-2d5b-41f3-831b-40a13c2afcbd/bin/uautomizer-J5u9QxTXDZ --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash ae06fa96255229a08f1e8c01eaa7f353b1ba462dacd64e058a3c6957598773d9 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-dbf71c6-m [2022-10-17 10:24:20,530 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-10-17 10:24:20,534 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-10-17 10:24:20,600 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-10-17 10:24:20,601 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-10-17 10:24:20,606 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-10-17 10:24:20,610 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-10-17 10:24:20,617 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-10-17 10:24:20,620 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-10-17 10:24:20,627 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-10-17 10:24:20,628 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-10-17 10:24:20,632 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-10-17 10:24:20,632 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-10-17 10:24:20,635 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-10-17 10:24:20,638 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-10-17 10:24:20,641 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-10-17 10:24:20,643 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-10-17 10:24:20,644 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-10-17 10:24:20,646 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-10-17 10:24:20,656 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-10-17 10:24:20,658 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-10-17 10:24:20,660 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-10-17 10:24:20,664 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-10-17 10:24:20,666 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-10-17 10:24:20,678 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-10-17 10:24:20,679 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-10-17 10:24:20,679 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-10-17 10:24:20,682 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-10-17 10:24:20,682 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-10-17 10:24:20,685 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-10-17 10:24:20,686 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-10-17 10:24:20,687 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-10-17 10:24:20,690 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-10-17 10:24:20,691 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-10-17 10:24:20,693 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-10-17 10:24:20,693 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-10-17 10:24:20,694 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-10-17 10:24:20,694 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-10-17 10:24:20,695 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-10-17 10:24:20,696 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-10-17 10:24:20,697 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-10-17 10:24:20,698 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_65b0ab96-2d5b-41f3-831b-40a13c2afcbd/bin/uautomizer-J5u9QxTXDZ/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-10-17 10:24:20,754 INFO L113 SettingsManager]: Loading preferences was successful [2022-10-17 10:24:20,754 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-10-17 10:24:20,755 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-10-17 10:24:20,755 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-10-17 10:24:20,758 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-10-17 10:24:20,758 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-10-17 10:24:20,758 INFO L138 SettingsManager]: * Use SBE=true [2022-10-17 10:24:20,758 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-10-17 10:24:20,759 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-10-17 10:24:20,759 INFO L138 SettingsManager]: * Use old map elimination=false [2022-10-17 10:24:20,760 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-10-17 10:24:20,761 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-10-17 10:24:20,761 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-10-17 10:24:20,761 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-10-17 10:24:20,761 INFO L138 SettingsManager]: * sizeof long=4 [2022-10-17 10:24:20,762 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-10-17 10:24:20,762 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-10-17 10:24:20,762 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-10-17 10:24:20,762 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-10-17 10:24:20,763 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-10-17 10:24:20,763 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-10-17 10:24:20,763 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-10-17 10:24:20,763 INFO L138 SettingsManager]: * sizeof long double=12 [2022-10-17 10:24:20,765 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-10-17 10:24:20,766 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-10-17 10:24:20,766 INFO L138 SettingsManager]: * Use constant arrays=true [2022-10-17 10:24:20,766 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-10-17 10:24:20,767 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-10-17 10:24:20,767 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-10-17 10:24:20,767 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-10-17 10:24:20,768 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-10-17 10:24:20,769 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-10-17 10:24:20,769 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_65b0ab96-2d5b-41f3-831b-40a13c2afcbd/bin/uautomizer-J5u9QxTXDZ/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_65b0ab96-2d5b-41f3-831b-40a13c2afcbd/bin/uautomizer-J5u9QxTXDZ Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> ae06fa96255229a08f1e8c01eaa7f353b1ba462dacd64e058a3c6957598773d9 [2022-10-17 10:24:21,104 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-10-17 10:24:21,136 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-10-17 10:24:21,140 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-10-17 10:24:21,142 INFO L271 PluginConnector]: Initializing CDTParser... [2022-10-17 10:24:21,143 INFO L275 PluginConnector]: CDTParser initialized [2022-10-17 10:24:21,144 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_65b0ab96-2d5b-41f3-831b-40a13c2afcbd/bin/uautomizer-J5u9QxTXDZ/../../sv-benchmarks/c/systemc/token_ring.09.cil-2.c [2022-10-17 10:24:21,235 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_65b0ab96-2d5b-41f3-831b-40a13c2afcbd/bin/uautomizer-J5u9QxTXDZ/data/5377112dc/02bd7335f0db4eb99dcac60bf0027cfb/FLAGc9a3a8338 [2022-10-17 10:24:21,788 INFO L306 CDTParser]: Found 1 translation units. [2022-10-17 10:24:21,789 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_65b0ab96-2d5b-41f3-831b-40a13c2afcbd/sv-benchmarks/c/systemc/token_ring.09.cil-2.c [2022-10-17 10:24:21,806 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_65b0ab96-2d5b-41f3-831b-40a13c2afcbd/bin/uautomizer-J5u9QxTXDZ/data/5377112dc/02bd7335f0db4eb99dcac60bf0027cfb/FLAGc9a3a8338 [2022-10-17 10:24:22,072 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_65b0ab96-2d5b-41f3-831b-40a13c2afcbd/bin/uautomizer-J5u9QxTXDZ/data/5377112dc/02bd7335f0db4eb99dcac60bf0027cfb [2022-10-17 10:24:22,075 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-10-17 10:24:22,076 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-10-17 10:24:22,078 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-10-17 10:24:22,079 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-10-17 10:24:22,082 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-10-17 10:24:22,083 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.10 10:24:22" (1/1) ... [2022-10-17 10:24:22,085 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@31a1fc5b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:24:22, skipping insertion in model container [2022-10-17 10:24:22,085 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.10 10:24:22" (1/1) ... [2022-10-17 10:24:22,093 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-10-17 10:24:22,148 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-10-17 10:24:22,369 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_65b0ab96-2d5b-41f3-831b-40a13c2afcbd/sv-benchmarks/c/systemc/token_ring.09.cil-2.c[671,684] [2022-10-17 10:24:22,511 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-10-17 10:24:22,531 INFO L203 MainTranslator]: Completed pre-run [2022-10-17 10:24:22,554 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_65b0ab96-2d5b-41f3-831b-40a13c2afcbd/sv-benchmarks/c/systemc/token_ring.09.cil-2.c[671,684] [2022-10-17 10:24:22,651 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-10-17 10:24:22,696 INFO L208 MainTranslator]: Completed translation [2022-10-17 10:24:22,697 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:24:22 WrapperNode [2022-10-17 10:24:22,697 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-10-17 10:24:22,700 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-10-17 10:24:22,700 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-10-17 10:24:22,701 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-10-17 10:24:22,710 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:24:22" (1/1) ... [2022-10-17 10:24:22,729 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:24:22" (1/1) ... [2022-10-17 10:24:22,869 INFO L138 Inliner]: procedures = 46, calls = 59, calls flagged for inlining = 54, calls inlined = 183, statements flattened = 2769 [2022-10-17 10:24:22,869 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-10-17 10:24:22,870 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-10-17 10:24:22,871 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-10-17 10:24:22,871 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-10-17 10:24:22,883 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:24:22" (1/1) ... [2022-10-17 10:24:22,883 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:24:22" (1/1) ... [2022-10-17 10:24:22,898 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:24:22" (1/1) ... [2022-10-17 10:24:22,899 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:24:22" (1/1) ... [2022-10-17 10:24:22,960 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:24:22" (1/1) ... [2022-10-17 10:24:23,008 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:24:22" (1/1) ... [2022-10-17 10:24:23,015 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:24:22" (1/1) ... [2022-10-17 10:24:23,027 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:24:22" (1/1) ... [2022-10-17 10:24:23,043 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-10-17 10:24:23,044 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-10-17 10:24:23,044 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-10-17 10:24:23,044 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-10-17 10:24:23,045 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:24:22" (1/1) ... [2022-10-17 10:24:23,073 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:24:23,091 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_65b0ab96-2d5b-41f3-831b-40a13c2afcbd/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:24:23,110 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_65b0ab96-2d5b-41f3-831b-40a13c2afcbd/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:24:23,112 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_65b0ab96-2d5b-41f3-831b-40a13c2afcbd/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-10-17 10:24:23,159 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-10-17 10:24:23,159 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-10-17 10:24:23,160 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-10-17 10:24:23,160 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-10-17 10:24:23,311 INFO L235 CfgBuilder]: Building ICFG [2022-10-17 10:24:23,314 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-10-17 10:24:25,593 INFO L276 CfgBuilder]: Performing block encoding [2022-10-17 10:24:25,626 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-10-17 10:24:25,628 INFO L300 CfgBuilder]: Removed 12 assume(true) statements. [2022-10-17 10:24:25,633 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 17.10 10:24:25 BoogieIcfgContainer [2022-10-17 10:24:25,634 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-10-17 10:24:25,636 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-10-17 10:24:25,636 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-10-17 10:24:25,641 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-10-17 10:24:25,643 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-10-17 10:24:25,643 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 17.10 10:24:22" (1/3) ... [2022-10-17 10:24:25,644 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@519c79ac and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.10 10:24:25, skipping insertion in model container [2022-10-17 10:24:25,645 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-10-17 10:24:25,645 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:24:22" (2/3) ... [2022-10-17 10:24:25,645 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@519c79ac and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.10 10:24:25, skipping insertion in model container [2022-10-17 10:24:25,646 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-10-17 10:24:25,646 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 17.10 10:24:25" (3/3) ... [2022-10-17 10:24:25,647 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.09.cil-2.c [2022-10-17 10:24:25,784 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-10-17 10:24:25,784 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-10-17 10:24:25,785 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-10-17 10:24:25,785 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-10-17 10:24:25,785 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-10-17 10:24:25,785 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-10-17 10:24:25,785 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-10-17 10:24:25,785 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-10-17 10:24:25,798 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1183 states, 1182 states have (on average 1.5109983079526226) internal successors, (1786), 1182 states have internal predecessors, (1786), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:24:25,905 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1052 [2022-10-17 10:24:25,906 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:24:25,906 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:24:25,927 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:24:25,927 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:24:25,927 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-10-17 10:24:25,932 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1183 states, 1182 states have (on average 1.5109983079526226) internal successors, (1786), 1182 states have internal predecessors, (1786), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:24:25,957 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1052 [2022-10-17 10:24:25,957 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:24:25,957 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:24:25,964 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:24:25,965 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:24:25,977 INFO L748 eck$LassoCheckResult]: Stem: 561#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 1075#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1020#L1403true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 587#L663true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 493#L670true assume !(1 == ~m_i~0);~m_st~0 := 2; 300#L670-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 813#L675-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 897#L680-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1011#L685-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 875#L690-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1163#L695-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 377#L700-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 369#L705-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 510#L710-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 253#L715-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 754#L951true assume !(0 == ~M_E~0); 108#L951-2true assume !(0 == ~T1_E~0); 195#L956-1true assume !(0 == ~T2_E~0); 1132#L961-1true assume !(0 == ~T3_E~0); 508#L966-1true assume 0 == ~T4_E~0;~T4_E~0 := 1; 636#L971-1true assume !(0 == ~T5_E~0); 1064#L976-1true assume !(0 == ~T6_E~0); 609#L981-1true assume !(0 == ~T7_E~0); 402#L986-1true assume !(0 == ~T8_E~0); 224#L991-1true assume !(0 == ~T9_E~0); 1105#L996-1true assume !(0 == ~E_M~0); 984#L1001-1true assume !(0 == ~E_1~0); 560#L1006-1true assume 0 == ~E_2~0;~E_2~0 := 1; 898#L1011-1true assume !(0 == ~E_3~0); 936#L1016-1true assume !(0 == ~E_4~0); 1077#L1021-1true assume !(0 == ~E_5~0); 21#L1026-1true assume !(0 == ~E_6~0); 1141#L1031-1true assume !(0 == ~E_7~0); 519#L1036-1true assume !(0 == ~E_8~0); 516#L1041-1true assume !(0 == ~E_9~0); 824#L1046-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1067#L472true assume 1 == ~m_pc~0; 1019#L473true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 542#L483true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1017#L484true activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 552#L1179true assume !(0 != activate_threads_~tmp~1#1); 25#L1179-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 869#L491true assume 1 == ~t1_pc~0; 558#L492true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 620#L502true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 513#L503true activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11#L1187true assume !(0 != activate_threads_~tmp___0~0#1); 22#L1187-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 807#L510true assume !(1 == ~t2_pc~0); 6#L510-2true is_transmit2_triggered_~__retres1~2#1 := 0; 978#L521true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 827#L522true activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1140#L1195true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 135#L1195-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 406#L529true assume 1 == ~t3_pc~0; 346#L530true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 746#L540true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 957#L541true activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1055#L1203true assume !(0 != activate_threads_~tmp___2~0#1); 97#L1203-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1106#L548true assume !(1 == ~t4_pc~0); 307#L548-2true is_transmit4_triggered_~__retres1~4#1 := 0; 200#L559true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 893#L560true activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 68#L1211true assume !(0 != activate_threads_~tmp___3~0#1); 618#L1211-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 46#L567true assume 1 == ~t5_pc~0; 865#L568true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1081#L578true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 159#L579true activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1009#L1219true assume !(0 != activate_threads_~tmp___4~0#1); 804#L1219-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 102#L586true assume !(1 == ~t6_pc~0); 138#L586-2true is_transmit6_triggered_~__retres1~6#1 := 0; 1005#L597true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1167#L598true activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1171#L1227true assume !(0 != activate_threads_~tmp___5~0#1); 798#L1227-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1103#L605true assume 1 == ~t7_pc~0; 736#L606true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 544#L616true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 511#L617true activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1088#L1235true assume !(0 != activate_threads_~tmp___6~0#1); 1076#L1235-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 487#L624true assume !(1 == ~t8_pc~0); 1041#L624-2true is_transmit8_triggered_~__retres1~8#1 := 0; 596#L635true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 536#L636true activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 767#L1243true assume !(0 != activate_threads_~tmp___7~0#1); 1147#L1243-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 32#L643true assume 1 == ~t9_pc~0; 832#L644true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 691#L654true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 611#L655true activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 227#L1251true assume !(0 != activate_threads_~tmp___8~0#1); 1102#L1251-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 123#L1059true assume !(1 == ~M_E~0); 1175#L1059-2true assume 1 == ~T1_E~0;~T1_E~0 := 2; 211#L1064-1true assume !(1 == ~T2_E~0); 699#L1069-1true assume !(1 == ~T3_E~0); 1063#L1074-1true assume !(1 == ~T4_E~0); 762#L1079-1true assume !(1 == ~T5_E~0); 735#L1084-1true assume !(1 == ~T6_E~0); 908#L1089-1true assume !(1 == ~T7_E~0); 789#L1094-1true assume !(1 == ~T8_E~0); 426#L1099-1true assume 1 == ~T9_E~0;~T9_E~0 := 2; 924#L1104-1true assume !(1 == ~E_M~0); 600#L1109-1true assume !(1 == ~E_1~0); 294#L1114-1true assume !(1 == ~E_2~0); 1111#L1119-1true assume !(1 == ~E_3~0); 330#L1124-1true assume !(1 == ~E_4~0); 30#L1129-1true assume !(1 == ~E_5~0); 496#L1134-1true assume !(1 == ~E_6~0); 193#L1139-1true assume 1 == ~E_7~0;~E_7~0 := 2; 305#L1144-1true assume !(1 == ~E_8~0); 1152#L1149-1true assume !(1 == ~E_9~0); 105#L1154-1true assume { :end_inline_reset_delta_events } true; 173#L1440-2true [2022-10-17 10:24:25,982 INFO L750 eck$LassoCheckResult]: Loop: 173#L1440-2true assume !false; 963#L1441true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 825#L926true assume false; 422#L941true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 764#L663-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 244#L951-3true assume !(0 == ~M_E~0); 1142#L951-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 650#L956-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 490#L961-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 319#L966-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 917#L971-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 537#L976-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 40#L981-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 237#L986-3true assume !(0 == ~T8_E~0); 31#L991-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 628#L996-3true assume 0 == ~E_M~0;~E_M~0 := 1; 761#L1001-3true assume 0 == ~E_1~0;~E_1~0 := 1; 304#L1006-3true assume 0 == ~E_2~0;~E_2~0 := 1; 657#L1011-3true assume 0 == ~E_3~0;~E_3~0 := 1; 895#L1016-3true assume 0 == ~E_4~0;~E_4~0 := 1; 708#L1021-3true assume 0 == ~E_5~0;~E_5~0 := 1; 439#L1026-3true assume !(0 == ~E_6~0); 1058#L1031-3true assume 0 == ~E_7~0;~E_7~0 := 1; 626#L1036-3true assume 0 == ~E_8~0;~E_8~0 := 1; 1117#L1041-3true assume 0 == ~E_9~0;~E_9~0 := 1; 694#L1046-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 649#L472-33true assume 1 == ~m_pc~0; 770#L473-11true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 903#L483-11true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10#L484-11true activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 654#L1179-33true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 324#L1179-35true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1044#L491-33true assume 1 == ~t1_pc~0; 553#L492-11true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 955#L502-11true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1183#L503-11true activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1000#L1187-33true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1062#L1187-35true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 604#L510-33true assume 1 == ~t2_pc~0; 658#L511-11true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 986#L521-11true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 509#L522-11true activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 715#L1195-33true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3#L1195-35true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 151#L529-33true assume 1 == ~t3_pc~0; 16#L530-11true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 142#L540-11true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 946#L541-11true activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1006#L1203-33true assume !(0 != activate_threads_~tmp___2~0#1); 60#L1203-35true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 182#L548-33true assume !(1 == ~t4_pc~0); 1162#L548-35true is_transmit4_triggered_~__retres1~4#1 := 0; 569#L559-11true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 277#L560-11true activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 280#L1211-33true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 147#L1211-35true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 910#L567-33true assume 1 == ~t5_pc~0; 413#L568-11true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 352#L578-11true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 956#L579-11true activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1029#L1219-33true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1118#L1219-35true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 507#L586-33true assume 1 == ~t6_pc~0; 477#L587-11true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 545#L597-11true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 435#L598-11true activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1137#L1227-33true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 156#L1227-35true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 260#L605-33true assume !(1 == ~t7_pc~0); 531#L605-35true is_transmit7_triggered_~__retres1~7#1 := 0; 119#L616-11true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 356#L617-11true activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1107#L1235-33true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 65#L1235-35true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 141#L624-33true assume !(1 == ~t8_pc~0); 145#L624-35true is_transmit8_triggered_~__retres1~8#1 := 0; 1038#L635-11true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 129#L636-11true activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 269#L1243-33true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1153#L1243-35true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 120#L643-33true assume !(1 == ~t9_pc~0); 165#L643-35true is_transmit9_triggered_~__retres1~9#1 := 0; 458#L654-11true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1098#L655-11true activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 424#L1251-33true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 784#L1251-35true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 61#L1059-3true assume 1 == ~M_E~0;~M_E~0 := 2; 338#L1059-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1169#L1064-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 375#L1069-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 610#L1074-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 858#L1079-3true assume !(1 == ~T5_E~0); 521#L1084-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 457#L1089-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 571#L1094-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 395#L1099-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 630#L1104-3true assume 1 == ~E_M~0;~E_M~0 := 2; 931#L1109-3true assume 1 == ~E_1~0;~E_1~0 := 2; 617#L1114-3true assume 1 == ~E_2~0;~E_2~0 := 2; 1030#L1119-3true assume !(1 == ~E_3~0); 1166#L1124-3true assume 1 == ~E_4~0;~E_4~0 := 2; 1060#L1129-3true assume 1 == ~E_5~0;~E_5~0 := 2; 215#L1134-3true assume 1 == ~E_6~0;~E_6~0 := 2; 471#L1139-3true assume 1 == ~E_7~0;~E_7~0 := 2; 316#L1144-3true assume 1 == ~E_8~0;~E_8~0 := 2; 427#L1149-3true assume 1 == ~E_9~0;~E_9~0 := 2; 1158#L1154-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1094#L728-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 728#L780-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 12#L781-1true start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 15#L1459true assume !(0 == start_simulation_~tmp~3#1); 711#L1459-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 890#L728-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 526#L780-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1133#L781-2true stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 242#L1414true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 341#L1421true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 481#L1422true start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 707#L1472true assume !(0 != start_simulation_~tmp___0~1#1); 173#L1440-2true [2022-10-17 10:24:25,990 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:24:25,991 INFO L85 PathProgramCache]: Analyzing trace with hash -986421749, now seen corresponding path program 1 times [2022-10-17 10:24:26,003 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:24:26,003 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [166223407] [2022-10-17 10:24:26,004 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:24:26,005 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:24:26,146 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:24:26,412 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:24:26,412 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:24:26,414 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [166223407] [2022-10-17 10:24:26,415 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [166223407] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:24:26,415 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:24:26,416 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:24:26,418 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [593705397] [2022-10-17 10:24:26,419 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:24:26,428 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:24:26,430 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:24:26,431 INFO L85 PathProgramCache]: Analyzing trace with hash 1458919769, now seen corresponding path program 1 times [2022-10-17 10:24:26,431 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:24:26,432 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [807024572] [2022-10-17 10:24:26,432 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:24:26,433 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:24:26,466 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:24:26,555 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:24:26,556 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:24:26,556 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [807024572] [2022-10-17 10:24:26,556 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [807024572] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:24:26,557 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:24:26,557 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-10-17 10:24:26,557 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [958167896] [2022-10-17 10:24:26,557 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:24:26,559 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:24:26,559 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:24:26,618 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:24:26,619 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:24:26,625 INFO L87 Difference]: Start difference. First operand has 1183 states, 1182 states have (on average 1.5109983079526226) internal successors, (1786), 1182 states have internal predecessors, (1786), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:24:26,755 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:24:26,755 INFO L93 Difference]: Finished difference Result 1181 states and 1757 transitions. [2022-10-17 10:24:26,757 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1181 states and 1757 transitions. [2022-10-17 10:24:26,769 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1048 [2022-10-17 10:24:26,784 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1181 states to 1175 states and 1751 transitions. [2022-10-17 10:24:26,785 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1175 [2022-10-17 10:24:26,788 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1175 [2022-10-17 10:24:26,788 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1175 states and 1751 transitions. [2022-10-17 10:24:26,795 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:24:26,795 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1175 states and 1751 transitions. [2022-10-17 10:24:26,817 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1175 states and 1751 transitions. [2022-10-17 10:24:26,868 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1175 to 1175. [2022-10-17 10:24:26,879 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1175 states, 1175 states have (on average 1.490212765957447) internal successors, (1751), 1174 states have internal predecessors, (1751), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:24:26,884 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1175 states to 1175 states and 1751 transitions. [2022-10-17 10:24:26,886 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1175 states and 1751 transitions. [2022-10-17 10:24:26,887 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:24:26,892 INFO L428 stractBuchiCegarLoop]: Abstraction has 1175 states and 1751 transitions. [2022-10-17 10:24:26,893 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-10-17 10:24:26,893 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1175 states and 1751 transitions. [2022-10-17 10:24:26,903 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1048 [2022-10-17 10:24:26,903 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:24:26,904 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:24:26,911 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:24:26,911 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:24:26,913 INFO L748 eck$LassoCheckResult]: Stem: 3275#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 3276#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 3535#L1403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3294#L663 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3195#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 2945#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2946#L675-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 3453#L680-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3485#L685-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3477#L690-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3478#L695-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3058#L700-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3048#L705-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 3049#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2869#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2870#L951 assume !(0 == ~M_E~0); 2608#L951-2 assume !(0 == ~T1_E~0); 2609#L956-1 assume !(0 == ~T2_E~0); 2769#L961-1 assume !(0 == ~T3_E~0); 3210#L966-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3211#L971-1 assume !(0 == ~T5_E~0); 3350#L976-1 assume !(0 == ~T6_E~0); 3321#L981-1 assume !(0 == ~T7_E~0); 3094#L986-1 assume !(0 == ~T8_E~0); 2822#L991-1 assume !(0 == ~T9_E~0); 2823#L996-1 assume !(0 == ~E_M~0); 3516#L1001-1 assume !(0 == ~E_1~0); 3273#L1006-1 assume 0 == ~E_2~0;~E_2~0 := 1; 3274#L1011-1 assume !(0 == ~E_3~0); 3487#L1016-1 assume !(0 == ~E_4~0); 3499#L1021-1 assume !(0 == ~E_5~0); 2415#L1026-1 assume !(0 == ~E_6~0); 2416#L1031-1 assume !(0 == ~E_7~0); 3222#L1036-1 assume !(0 == ~E_8~0); 3218#L1041-1 assume !(0 == ~E_9~0); 3219#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3460#L472 assume 1 == ~m_pc~0; 3534#L473 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3253#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3254#L484 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3261#L1179 assume !(0 != activate_threads_~tmp~1#1); 2423#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2424#L491 assume 1 == ~t1_pc~0; 3270#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2920#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3216#L503 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2395#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 2396#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2419#L510 assume !(1 == ~t2_pc~0); 2382#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2383#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3463#L522 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3464#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2664#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2665#L529 assume 1 == ~t3_pc~0; 3015#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3016#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3427#L541 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3509#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 2585#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2586#L548 assume !(1 == ~t4_pc~0); 2483#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2482#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2777#L560 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2527#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 2528#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2470#L567 assume 1 == ~t5_pc~0; 2471#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2529#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2710#L579 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2711#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 3448#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2596#L586 assume !(1 == ~t6_pc~0); 2597#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2670#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3531#L598 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3547#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 3444#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3445#L605 assume 1 == ~t7_pc~0; 3424#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3075#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3214#L617 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3215#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 3543#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3190#L624 assume !(1 == ~t8_pc~0); 2658#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 2657#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3246#L636 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3247#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 3432#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2438#L643 assume 1 == ~t9_pc~0; 2439#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3389#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3323#L655 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2829#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 2830#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2640#L1059 assume !(1 == ~M_E~0); 2641#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2797#L1064-1 assume !(1 == ~T2_E~0); 2798#L1069-1 assume !(1 == ~T3_E~0); 3396#L1074-1 assume !(1 == ~T4_E~0); 3430#L1079-1 assume !(1 == ~T5_E~0); 3422#L1084-1 assume !(1 == ~T6_E~0); 3423#L1089-1 assume !(1 == ~T7_E~0); 3440#L1094-1 assume !(1 == ~T8_E~0); 3123#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3124#L1104-1 assume !(1 == ~E_M~0); 3309#L1109-1 assume !(1 == ~E_1~0); 2938#L1114-1 assume !(1 == ~E_2~0); 2939#L1119-1 assume !(1 == ~E_3~0); 2991#L1124-1 assume !(1 == ~E_4~0); 2434#L1129-1 assume !(1 == ~E_5~0); 2435#L1134-1 assume !(1 == ~E_6~0); 2765#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 2766#L1144-1 assume !(1 == ~E_8~0); 2953#L1149-1 assume !(1 == ~E_9~0); 2602#L1154-1 assume { :end_inline_reset_delta_events } true; 2603#L1440-2 [2022-10-17 10:24:26,914 INFO L750 eck$LassoCheckResult]: Loop: 2603#L1440-2 assume !false; 2732#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2374#L926 assume !false; 2993#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2994#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2692#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2693#L781 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2698#L795 assume !(0 != eval_~tmp~0#1); 2699#L941 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3118#L663-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2854#L951-3 assume !(0 == ~M_E~0); 2855#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3358#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3194#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2977#L966-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2978#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3248#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2456#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2457#L986-3 assume !(0 == ~T8_E~0); 2436#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 2437#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3344#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2949#L1006-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2950#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3366#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3401#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3141#L1026-3 assume !(0 == ~E_6~0); 3142#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3338#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3339#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 3394#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3356#L472-33 assume !(1 == ~m_pc~0); 2555#L472-35 is_master_triggered_~__retres1~0#1 := 0; 2556#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2391#L484-11 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2392#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2982#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2983#L491-33 assume !(1 == ~t1_pc~0); 2489#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 2490#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3507#L503-11 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3526#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3527#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3315#L510-33 assume 1 == ~t2_pc~0; 3316#L511-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3311#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3212#L522-11 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3213#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2375#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2376#L529-33 assume 1 == ~t3_pc~0; 2403#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2404#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2677#L541-11 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3503#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 2506#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2507#L548-33 assume 1 == ~t4_pc~0; 2750#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2871#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2911#L560-11 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2912#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2687#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2688#L567-33 assume 1 == ~t5_pc~0; 3108#L568-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2793#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3026#L579-11 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3508#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3539#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3209#L586-33 assume !(1 == ~t6_pc~0); 2810#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 2811#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3135#L598-11 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3136#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2702#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2703#L605-33 assume !(1 == ~t7_pc~0); 2878#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 2625#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2626#L617-11 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3030#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2518#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2519#L624-33 assume 1 == ~t8_pc~0; 2673#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 2681#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2652#L636-11 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2653#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2894#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2627#L643-33 assume 1 == ~t9_pc~0; 2628#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 2720#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3166#L655-11 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3119#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3120#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2508#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2509#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3005#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3055#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3056#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3322#L1079-3 assume !(1 == ~T5_E~0); 3225#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3164#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3165#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3087#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3088#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3345#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3326#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3327#L1119-3 assume !(1 == ~E_3~0); 3538#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3542#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2805#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2806#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2964#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2965#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3125#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3545#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2511#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2393#L781-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 2394#L1459 assume !(0 == start_simulation_~tmp~3#1); 2402#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3402#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2690#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 3233#L781-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 2852#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2853#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3006#L1422 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 3186#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 2603#L1440-2 [2022-10-17 10:24:26,915 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:24:26,915 INFO L85 PathProgramCache]: Analyzing trace with hash 1581400585, now seen corresponding path program 1 times [2022-10-17 10:24:26,915 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:24:26,915 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [355827383] [2022-10-17 10:24:26,916 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:24:26,916 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:24:26,938 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:24:27,001 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:24:27,001 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:24:27,002 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [355827383] [2022-10-17 10:24:27,002 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [355827383] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:24:27,002 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:24:27,002 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:24:27,003 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1919715313] [2022-10-17 10:24:27,003 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:24:27,003 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:24:27,004 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:24:27,004 INFO L85 PathProgramCache]: Analyzing trace with hash 634879174, now seen corresponding path program 1 times [2022-10-17 10:24:27,004 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:24:27,004 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1493022859] [2022-10-17 10:24:27,005 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:24:27,005 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:24:27,038 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:24:27,168 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:24:27,168 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:24:27,169 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1493022859] [2022-10-17 10:24:27,169 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1493022859] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:24:27,169 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:24:27,169 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:24:27,170 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2136738344] [2022-10-17 10:24:27,170 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:24:27,170 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:24:27,171 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:24:27,171 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:24:27,171 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:24:27,172 INFO L87 Difference]: Start difference. First operand 1175 states and 1751 transitions. cyclomatic complexity: 577 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:24:27,206 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:24:27,206 INFO L93 Difference]: Finished difference Result 1175 states and 1750 transitions. [2022-10-17 10:24:27,207 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1175 states and 1750 transitions. [2022-10-17 10:24:27,220 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1048 [2022-10-17 10:24:27,232 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1175 states to 1175 states and 1750 transitions. [2022-10-17 10:24:27,232 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1175 [2022-10-17 10:24:27,233 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1175 [2022-10-17 10:24:27,234 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1175 states and 1750 transitions. [2022-10-17 10:24:27,236 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:24:27,236 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1175 states and 1750 transitions. [2022-10-17 10:24:27,239 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1175 states and 1750 transitions. [2022-10-17 10:24:27,259 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1175 to 1175. [2022-10-17 10:24:27,262 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1175 states, 1175 states have (on average 1.4893617021276595) internal successors, (1750), 1174 states have internal predecessors, (1750), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:24:27,269 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1175 states to 1175 states and 1750 transitions. [2022-10-17 10:24:27,269 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1175 states and 1750 transitions. [2022-10-17 10:24:27,270 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:24:27,270 INFO L428 stractBuchiCegarLoop]: Abstraction has 1175 states and 1750 transitions. [2022-10-17 10:24:27,271 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-10-17 10:24:27,271 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1175 states and 1750 transitions. [2022-10-17 10:24:27,281 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1048 [2022-10-17 10:24:27,281 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:24:27,281 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:24:27,284 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:24:27,284 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:24:27,285 INFO L748 eck$LassoCheckResult]: Stem: 5632#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 5633#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 5892#L1403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5651#L663 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5552#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 5302#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5303#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5810#L680-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 5842#L685-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5834#L690-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5835#L695-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5415#L700-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5405#L705-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 5406#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 5227#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5228#L951 assume !(0 == ~M_E~0); 4967#L951-2 assume !(0 == ~T1_E~0); 4968#L956-1 assume !(0 == ~T2_E~0); 5126#L961-1 assume !(0 == ~T3_E~0); 5567#L966-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5568#L971-1 assume !(0 == ~T5_E~0); 5707#L976-1 assume !(0 == ~T6_E~0); 5678#L981-1 assume !(0 == ~T7_E~0); 5454#L986-1 assume !(0 == ~T8_E~0); 5179#L991-1 assume !(0 == ~T9_E~0); 5180#L996-1 assume !(0 == ~E_M~0); 5874#L1001-1 assume !(0 == ~E_1~0); 5630#L1006-1 assume 0 == ~E_2~0;~E_2~0 := 1; 5631#L1011-1 assume !(0 == ~E_3~0); 5844#L1016-1 assume !(0 == ~E_4~0); 5856#L1021-1 assume !(0 == ~E_5~0); 4772#L1026-1 assume !(0 == ~E_6~0); 4773#L1031-1 assume !(0 == ~E_7~0); 5581#L1036-1 assume !(0 == ~E_8~0); 5577#L1041-1 assume !(0 == ~E_9~0); 5578#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5817#L472 assume 1 == ~m_pc~0; 5891#L473 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5610#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5611#L484 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5618#L1179 assume !(0 != activate_threads_~tmp~1#1); 4780#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4781#L491 assume 1 == ~t1_pc~0; 5627#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5277#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5573#L503 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4752#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 4753#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4776#L510 assume !(1 == ~t2_pc~0); 4739#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4740#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5820#L522 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5821#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5021#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5022#L529 assume 1 == ~t3_pc~0; 5372#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5373#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5784#L541 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5866#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 4942#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4943#L548 assume !(1 == ~t4_pc~0); 4840#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4839#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5136#L560 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4884#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 4885#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4829#L567 assume 1 == ~t5_pc~0; 4830#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4886#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5067#L579 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5068#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 5805#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4953#L586 assume !(1 == ~t6_pc~0); 4954#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 5029#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5888#L598 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5904#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 5801#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5802#L605 assume 1 == ~t7_pc~0; 5781#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5436#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5571#L617 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5572#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 5900#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5547#L624 assume !(1 == ~t8_pc~0); 5015#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 5014#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5603#L636 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5604#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 5789#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4795#L643 assume 1 == ~t9_pc~0; 4796#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 5746#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5680#L655 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5186#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 5187#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4997#L1059 assume !(1 == ~M_E~0); 4998#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5154#L1064-1 assume !(1 == ~T2_E~0); 5155#L1069-1 assume !(1 == ~T3_E~0); 5753#L1074-1 assume !(1 == ~T4_E~0); 5788#L1079-1 assume !(1 == ~T5_E~0); 5779#L1084-1 assume !(1 == ~T6_E~0); 5780#L1089-1 assume !(1 == ~T7_E~0); 5797#L1094-1 assume !(1 == ~T8_E~0); 5480#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 5481#L1104-1 assume !(1 == ~E_M~0); 5668#L1109-1 assume !(1 == ~E_1~0); 5295#L1114-1 assume !(1 == ~E_2~0); 5296#L1119-1 assume !(1 == ~E_3~0); 5348#L1124-1 assume !(1 == ~E_4~0); 4791#L1129-1 assume !(1 == ~E_5~0); 4792#L1134-1 assume !(1 == ~E_6~0); 5122#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 5123#L1144-1 assume !(1 == ~E_8~0); 5310#L1149-1 assume !(1 == ~E_9~0); 4959#L1154-1 assume { :end_inline_reset_delta_events } true; 4960#L1440-2 [2022-10-17 10:24:27,286 INFO L750 eck$LassoCheckResult]: Loop: 4960#L1440-2 assume !false; 5091#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4731#L926 assume !false; 5350#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 5351#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 5049#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 5050#L781 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 5055#L795 assume !(0 != eval_~tmp~0#1); 5056#L941 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5475#L663-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5211#L951-3 assume !(0 == ~M_E~0); 5212#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5715#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5551#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5335#L966-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5336#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5605#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4813#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4814#L986-3 assume !(0 == ~T8_E~0); 4793#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4794#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5701#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5306#L1006-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5307#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5723#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5758#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5499#L1026-3 assume !(0 == ~E_6~0); 5500#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5695#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 5696#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 5751#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5713#L472-33 assume !(1 == ~m_pc~0); 4912#L472-35 is_master_triggered_~__retres1~0#1 := 0; 4913#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4748#L484-11 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4749#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5339#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5340#L491-33 assume 1 == ~t1_pc~0; 5619#L492-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4847#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5865#L503-11 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5883#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5884#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5669#L510-33 assume !(1 == ~t2_pc~0); 5666#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 5667#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5569#L522-11 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5570#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4732#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4733#L529-33 assume 1 == ~t3_pc~0; 4760#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4761#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5034#L541-11 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5860#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 4863#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4864#L548-33 assume 1 == ~t4_pc~0; 5104#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5226#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5266#L560-11 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5267#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5044#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5045#L567-33 assume 1 == ~t5_pc~0; 5464#L568-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5150#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5382#L579-11 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5864#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5895#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5566#L586-33 assume !(1 == ~t6_pc~0); 5168#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 5169#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5492#L598-11 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5493#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5061#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5062#L605-33 assume !(1 == ~t7_pc~0); 5238#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 4982#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4983#L617-11 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5387#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4875#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4876#L624-33 assume 1 == ~t8_pc~0; 5032#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 5041#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5009#L636-11 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5010#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 5251#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4984#L643-33 assume 1 == ~t9_pc~0; 4985#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 5077#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5523#L655-11 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5476#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 5477#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4865#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4866#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5362#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5412#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5413#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5679#L1079-3 assume !(1 == ~T5_E~0); 5582#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5521#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5522#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 5444#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 5445#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5702#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5683#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5684#L1119-3 assume !(1 == ~E_3~0); 5896#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5899#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5162#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5163#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5324#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 5325#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 5482#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 5902#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 4868#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 4750#L781-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 4751#L1459 assume !(0 == start_simulation_~tmp~3#1); 4759#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 5759#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 5047#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 5590#L781-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 5209#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5210#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5364#L1422 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 5543#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 4960#L1440-2 [2022-10-17 10:24:27,286 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:24:27,286 INFO L85 PathProgramCache]: Analyzing trace with hash -1066203769, now seen corresponding path program 1 times [2022-10-17 10:24:27,287 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:24:27,287 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1753104094] [2022-10-17 10:24:27,287 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:24:27,287 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:24:27,308 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:24:27,353 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:24:27,353 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:24:27,353 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1753104094] [2022-10-17 10:24:27,354 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1753104094] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:24:27,354 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:24:27,354 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:24:27,354 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [134688656] [2022-10-17 10:24:27,354 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:24:27,355 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:24:27,355 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:24:27,356 INFO L85 PathProgramCache]: Analyzing trace with hash -714854010, now seen corresponding path program 1 times [2022-10-17 10:24:27,356 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:24:27,356 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [494600311] [2022-10-17 10:24:27,356 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:24:27,357 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:24:27,379 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:24:27,438 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:24:27,438 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:24:27,438 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [494600311] [2022-10-17 10:24:27,439 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [494600311] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:24:27,439 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:24:27,439 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:24:27,439 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1005446027] [2022-10-17 10:24:27,439 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:24:27,440 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:24:27,440 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:24:27,441 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:24:27,441 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:24:27,441 INFO L87 Difference]: Start difference. First operand 1175 states and 1750 transitions. cyclomatic complexity: 576 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:24:27,469 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:24:27,470 INFO L93 Difference]: Finished difference Result 1175 states and 1749 transitions. [2022-10-17 10:24:27,470 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1175 states and 1749 transitions. [2022-10-17 10:24:27,481 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1048 [2022-10-17 10:24:27,491 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1175 states to 1175 states and 1749 transitions. [2022-10-17 10:24:27,491 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1175 [2022-10-17 10:24:27,493 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1175 [2022-10-17 10:24:27,493 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1175 states and 1749 transitions. [2022-10-17 10:24:27,495 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:24:27,495 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1175 states and 1749 transitions. [2022-10-17 10:24:27,498 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1175 states and 1749 transitions. [2022-10-17 10:24:27,530 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1175 to 1175. [2022-10-17 10:24:27,533 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1175 states, 1175 states have (on average 1.4885106382978723) internal successors, (1749), 1174 states have internal predecessors, (1749), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:24:27,539 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1175 states to 1175 states and 1749 transitions. [2022-10-17 10:24:27,539 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1175 states and 1749 transitions. [2022-10-17 10:24:27,540 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:24:27,542 INFO L428 stractBuchiCegarLoop]: Abstraction has 1175 states and 1749 transitions. [2022-10-17 10:24:27,543 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-10-17 10:24:27,543 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1175 states and 1749 transitions. [2022-10-17 10:24:27,551 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1048 [2022-10-17 10:24:27,551 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:24:27,552 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:24:27,554 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:24:27,554 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:24:27,555 INFO L748 eck$LassoCheckResult]: Stem: 7989#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 7990#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 8250#L1403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8010#L663 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7909#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 7661#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7662#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8167#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8199#L685-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 8191#L690-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8192#L695-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7772#L700-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 7762#L705-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 7763#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 7584#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7585#L951 assume !(0 == ~M_E~0); 7326#L951-2 assume !(0 == ~T1_E~0); 7327#L956-1 assume !(0 == ~T2_E~0); 7483#L961-1 assume !(0 == ~T3_E~0); 7924#L966-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7925#L971-1 assume !(0 == ~T5_E~0); 8064#L976-1 assume !(0 == ~T6_E~0); 8035#L981-1 assume !(0 == ~T7_E~0); 7811#L986-1 assume !(0 == ~T8_E~0); 7536#L991-1 assume !(0 == ~T9_E~0); 7537#L996-1 assume !(0 == ~E_M~0); 8231#L1001-1 assume !(0 == ~E_1~0); 7987#L1006-1 assume 0 == ~E_2~0;~E_2~0 := 1; 7988#L1011-1 assume !(0 == ~E_3~0); 8202#L1016-1 assume !(0 == ~E_4~0); 8213#L1021-1 assume !(0 == ~E_5~0); 7129#L1026-1 assume !(0 == ~E_6~0); 7130#L1031-1 assume !(0 == ~E_7~0); 7938#L1036-1 assume !(0 == ~E_8~0); 7934#L1041-1 assume !(0 == ~E_9~0); 7935#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8174#L472 assume 1 == ~m_pc~0; 8248#L473 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7967#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7968#L484 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7975#L1179 assume !(0 != activate_threads_~tmp~1#1); 7137#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7138#L491 assume 1 == ~t1_pc~0; 7986#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7636#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7930#L503 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7109#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 7110#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7133#L510 assume !(1 == ~t2_pc~0); 7096#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7097#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8177#L522 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8178#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7378#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7379#L529 assume 1 == ~t3_pc~0; 7729#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7730#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8141#L541 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8223#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 7299#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7300#L548 assume !(1 == ~t4_pc~0); 7197#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 7196#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7493#L560 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7241#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 7242#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7189#L567 assume 1 == ~t5_pc~0; 7190#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7243#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7427#L579 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7428#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 8162#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7310#L586 assume !(1 == ~t6_pc~0); 7311#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 7386#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8245#L598 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8261#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 8158#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8159#L605 assume 1 == ~t7_pc~0; 8139#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7796#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7928#L617 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7929#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 8257#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7904#L624 assume !(1 == ~t8_pc~0); 7372#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 7371#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7960#L636 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7961#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 8146#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7154#L643 assume 1 == ~t9_pc~0; 7155#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8104#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8038#L655 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7543#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 7544#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7354#L1059 assume !(1 == ~M_E~0); 7355#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7511#L1064-1 assume !(1 == ~T2_E~0); 7512#L1069-1 assume !(1 == ~T3_E~0); 8110#L1074-1 assume !(1 == ~T4_E~0); 8145#L1079-1 assume !(1 == ~T5_E~0); 8136#L1084-1 assume !(1 == ~T6_E~0); 8137#L1089-1 assume !(1 == ~T7_E~0); 8154#L1094-1 assume !(1 == ~T8_E~0); 7837#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7838#L1104-1 assume !(1 == ~E_M~0); 8025#L1109-1 assume !(1 == ~E_1~0); 7652#L1114-1 assume !(1 == ~E_2~0); 7653#L1119-1 assume !(1 == ~E_3~0); 7706#L1124-1 assume !(1 == ~E_4~0); 7150#L1129-1 assume !(1 == ~E_5~0); 7151#L1134-1 assume !(1 == ~E_6~0); 7481#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 7482#L1144-1 assume !(1 == ~E_8~0); 7667#L1149-1 assume !(1 == ~E_9~0); 7316#L1154-1 assume { :end_inline_reset_delta_events } true; 7317#L1440-2 [2022-10-17 10:24:27,556 INFO L750 eck$LassoCheckResult]: Loop: 7317#L1440-2 assume !false; 7448#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7088#L926 assume !false; 7707#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 7708#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 7406#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 7407#L781 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 7412#L795 assume !(0 != eval_~tmp~0#1); 7413#L941 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7832#L663-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7570#L951-3 assume !(0 == ~M_E~0); 7571#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8073#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7908#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7692#L966-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7693#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7962#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7176#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7177#L986-3 assume !(0 == ~T8_E~0); 7148#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 7149#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8058#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7663#L1006-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7664#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8080#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8115#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7855#L1026-3 assume !(0 == ~E_6~0); 7856#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 8052#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 8053#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 8108#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8069#L472-33 assume !(1 == ~m_pc~0); 7266#L472-35 is_master_triggered_~__retres1~0#1 := 0; 7267#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7105#L484-11 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7106#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7696#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7697#L491-33 assume !(1 == ~t1_pc~0); 7203#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 7204#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8221#L503-11 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8240#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8241#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8029#L510-33 assume !(1 == ~t2_pc~0); 8023#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 8024#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7926#L522-11 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7927#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7089#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7090#L529-33 assume 1 == ~t3_pc~0; 7117#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7118#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7391#L541-11 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8217#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 7220#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7221#L548-33 assume 1 == ~t4_pc~0; 7462#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7583#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7623#L560-11 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7624#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7401#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7402#L567-33 assume !(1 == ~t5_pc~0); 7506#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 7507#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7739#L579-11 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8222#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8252#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7923#L586-33 assume !(1 == ~t6_pc~0); 7525#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 7526#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7849#L598-11 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7850#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7418#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7419#L605-33 assume !(1 == ~t7_pc~0); 7595#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 7346#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7347#L617-11 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7744#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 7232#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7233#L624-33 assume 1 == ~t8_pc~0; 7389#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 7398#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7366#L636-11 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7367#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7608#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7348#L643-33 assume 1 == ~t9_pc~0; 7349#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7434#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7880#L655-11 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7833#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 7834#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7222#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7223#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7719#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7769#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7770#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8036#L1079-3 assume !(1 == ~T5_E~0); 7939#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7878#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 7879#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 7801#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7802#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8059#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8041#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8042#L1119-3 assume !(1 == ~E_3~0); 8253#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8256#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7519#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 7520#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 7683#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 7684#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 7839#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 8259#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 7225#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 7107#L781-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 7108#L1459 assume !(0 == start_simulation_~tmp~3#1); 7116#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 8117#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 7404#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 7947#L781-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 7566#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7567#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7721#L1422 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 7900#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 7317#L1440-2 [2022-10-17 10:24:27,556 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:24:27,557 INFO L85 PathProgramCache]: Analyzing trace with hash 1065146953, now seen corresponding path program 1 times [2022-10-17 10:24:27,557 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:24:27,557 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1543067379] [2022-10-17 10:24:27,558 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:24:27,560 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:24:27,581 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:24:27,624 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:24:27,625 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:24:27,625 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1543067379] [2022-10-17 10:24:27,626 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1543067379] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:24:27,626 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:24:27,627 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:24:27,630 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1520770164] [2022-10-17 10:24:27,630 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:24:27,632 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:24:27,632 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:24:27,633 INFO L85 PathProgramCache]: Analyzing trace with hash -1623165560, now seen corresponding path program 1 times [2022-10-17 10:24:27,633 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:24:27,638 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [662165852] [2022-10-17 10:24:27,639 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:24:27,639 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:24:27,671 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:24:27,752 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:24:27,753 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:24:27,753 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [662165852] [2022-10-17 10:24:27,753 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [662165852] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:24:27,754 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:24:27,754 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:24:27,755 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1079782867] [2022-10-17 10:24:27,755 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:24:27,756 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:24:27,757 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:24:27,759 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:24:27,760 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:24:27,760 INFO L87 Difference]: Start difference. First operand 1175 states and 1749 transitions. cyclomatic complexity: 575 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:24:27,794 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:24:27,795 INFO L93 Difference]: Finished difference Result 1175 states and 1748 transitions. [2022-10-17 10:24:27,795 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1175 states and 1748 transitions. [2022-10-17 10:24:27,807 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1048 [2022-10-17 10:24:27,819 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1175 states to 1175 states and 1748 transitions. [2022-10-17 10:24:27,819 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1175 [2022-10-17 10:24:27,821 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1175 [2022-10-17 10:24:27,821 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1175 states and 1748 transitions. [2022-10-17 10:24:27,824 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:24:27,824 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1175 states and 1748 transitions. [2022-10-17 10:24:27,827 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1175 states and 1748 transitions. [2022-10-17 10:24:27,846 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1175 to 1175. [2022-10-17 10:24:27,850 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1175 states, 1175 states have (on average 1.4876595744680852) internal successors, (1748), 1174 states have internal predecessors, (1748), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:24:27,857 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1175 states to 1175 states and 1748 transitions. [2022-10-17 10:24:27,858 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1175 states and 1748 transitions. [2022-10-17 10:24:27,858 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:24:27,859 INFO L428 stractBuchiCegarLoop]: Abstraction has 1175 states and 1748 transitions. [2022-10-17 10:24:27,859 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-10-17 10:24:27,860 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1175 states and 1748 transitions. [2022-10-17 10:24:27,872 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1048 [2022-10-17 10:24:27,872 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:24:27,872 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:24:27,876 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:24:27,877 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:24:27,877 INFO L748 eck$LassoCheckResult]: Stem: 10346#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 10347#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 10606#L1403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10365#L663 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10266#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 10016#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10017#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10524#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10556#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10548#L690-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 10549#L695-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 10129#L700-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10119#L705-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 10120#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 9940#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9941#L951 assume !(0 == ~M_E~0); 9679#L951-2 assume !(0 == ~T1_E~0); 9680#L956-1 assume !(0 == ~T2_E~0); 9840#L961-1 assume !(0 == ~T3_E~0); 10281#L966-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10282#L971-1 assume !(0 == ~T5_E~0); 10421#L976-1 assume !(0 == ~T6_E~0); 10392#L981-1 assume !(0 == ~T7_E~0); 10165#L986-1 assume !(0 == ~T8_E~0); 9893#L991-1 assume !(0 == ~T9_E~0); 9894#L996-1 assume !(0 == ~E_M~0); 10587#L1001-1 assume !(0 == ~E_1~0); 10344#L1006-1 assume 0 == ~E_2~0;~E_2~0 := 1; 10345#L1011-1 assume !(0 == ~E_3~0); 10557#L1016-1 assume !(0 == ~E_4~0); 10570#L1021-1 assume !(0 == ~E_5~0); 9486#L1026-1 assume !(0 == ~E_6~0); 9487#L1031-1 assume !(0 == ~E_7~0); 10293#L1036-1 assume !(0 == ~E_8~0); 10289#L1041-1 assume !(0 == ~E_9~0); 10290#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10531#L472 assume 1 == ~m_pc~0; 10605#L473 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 10324#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10325#L484 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10332#L1179 assume !(0 != activate_threads_~tmp~1#1); 9494#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9495#L491 assume 1 == ~t1_pc~0; 10341#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9991#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10287#L503 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9464#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 9465#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9488#L510 assume !(1 == ~t2_pc~0); 9453#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 9454#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10533#L522 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10534#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9735#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9736#L529 assume 1 == ~t3_pc~0; 10086#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10087#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10498#L541 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10580#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 9656#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9657#L548 assume !(1 == ~t4_pc~0); 9554#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 9553#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9848#L560 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9596#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 9597#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9541#L567 assume 1 == ~t5_pc~0; 9542#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9598#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9781#L579 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9782#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 10519#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9667#L586 assume !(1 == ~t6_pc~0); 9668#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 9741#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10602#L598 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10618#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 10515#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10516#L605 assume 1 == ~t7_pc~0; 10495#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10145#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10285#L617 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10286#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 10614#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10261#L624 assume !(1 == ~t8_pc~0); 9729#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 9728#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10317#L636 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 10318#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 10503#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9509#L643 assume 1 == ~t9_pc~0; 9510#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 10460#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 10394#L655 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9898#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 9899#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9711#L1059 assume !(1 == ~M_E~0); 9712#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9868#L1064-1 assume !(1 == ~T2_E~0); 9869#L1069-1 assume !(1 == ~T3_E~0); 10467#L1074-1 assume !(1 == ~T4_E~0); 10501#L1079-1 assume !(1 == ~T5_E~0); 10493#L1084-1 assume !(1 == ~T6_E~0); 10494#L1089-1 assume !(1 == ~T7_E~0); 10511#L1094-1 assume !(1 == ~T8_E~0); 10194#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 10195#L1104-1 assume !(1 == ~E_M~0); 10380#L1109-1 assume !(1 == ~E_1~0); 10009#L1114-1 assume !(1 == ~E_2~0); 10010#L1119-1 assume !(1 == ~E_3~0); 10062#L1124-1 assume !(1 == ~E_4~0); 9505#L1129-1 assume !(1 == ~E_5~0); 9506#L1134-1 assume !(1 == ~E_6~0); 9836#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 9837#L1144-1 assume !(1 == ~E_8~0); 10022#L1149-1 assume !(1 == ~E_9~0); 9673#L1154-1 assume { :end_inline_reset_delta_events } true; 9674#L1440-2 [2022-10-17 10:24:27,878 INFO L750 eck$LassoCheckResult]: Loop: 9674#L1440-2 assume !false; 9803#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9445#L926 assume !false; 10064#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 10065#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 9760#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 9761#L781 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 9768#L795 assume !(0 != eval_~tmp~0#1); 9769#L941 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10189#L663-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9925#L951-3 assume !(0 == ~M_E~0); 9926#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10429#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10265#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10045#L966-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10046#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10319#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9525#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 9526#L986-3 assume !(0 == ~T8_E~0); 9507#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 9508#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10415#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10020#L1006-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10021#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10437#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10472#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10212#L1026-3 assume !(0 == ~E_6~0); 10213#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 10409#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 10410#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 10465#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10427#L472-33 assume !(1 == ~m_pc~0); 9626#L472-35 is_master_triggered_~__retres1~0#1 := 0; 9627#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9462#L484-11 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9463#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10053#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10054#L491-33 assume !(1 == ~t1_pc~0); 9560#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 9561#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10578#L503-11 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10597#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10598#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10386#L510-33 assume 1 == ~t2_pc~0; 10387#L511-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10382#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10283#L522-11 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10284#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9446#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9447#L529-33 assume 1 == ~t3_pc~0; 9474#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9475#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9748#L541-11 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10574#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 9577#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9578#L548-33 assume 1 == ~t4_pc~0; 9819#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9942#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9980#L560-11 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9981#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9758#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9759#L567-33 assume 1 == ~t5_pc~0; 10179#L568-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9864#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10096#L579-11 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10579#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10609#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10280#L586-33 assume !(1 == ~t6_pc~0); 9882#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 9883#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10208#L598-11 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10209#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9775#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9776#L605-33 assume !(1 == ~t7_pc~0); 9952#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 9703#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9704#L617-11 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10101#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9589#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9590#L624-33 assume 1 == ~t8_pc~0; 9746#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 9755#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9723#L636-11 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9724#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 9965#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9705#L643-33 assume 1 == ~t9_pc~0; 9706#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 9791#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 10237#L655-11 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 10190#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 10191#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9579#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9580#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10076#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10127#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10128#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10393#L1079-3 assume !(1 == ~T5_E~0); 10296#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10235#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 10236#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 10158#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 10159#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10416#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10398#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10399#L1119-3 assume !(1 == ~E_3~0); 10610#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10613#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9876#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 9877#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 10040#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 10041#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 10196#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 10616#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 9584#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 9466#L781-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 9467#L1459 assume !(0 == start_simulation_~tmp~3#1); 9473#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 10474#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 9763#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 10304#L781-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 9923#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9924#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10080#L1422 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 10257#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 9674#L1440-2 [2022-10-17 10:24:27,879 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:24:27,879 INFO L85 PathProgramCache]: Analyzing trace with hash 2103731527, now seen corresponding path program 1 times [2022-10-17 10:24:27,880 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:24:27,880 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1665005760] [2022-10-17 10:24:27,880 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:24:27,880 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:24:27,899 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:24:27,952 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:24:27,953 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:24:27,953 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1665005760] [2022-10-17 10:24:27,953 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1665005760] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:24:27,954 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:24:27,954 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:24:27,955 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2040080255] [2022-10-17 10:24:27,955 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:24:27,956 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:24:27,956 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:24:27,957 INFO L85 PathProgramCache]: Analyzing trace with hash 634879174, now seen corresponding path program 2 times [2022-10-17 10:24:27,957 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:24:27,959 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1340938594] [2022-10-17 10:24:27,959 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:24:27,959 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:24:27,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:24:28,041 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:24:28,043 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:24:28,043 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1340938594] [2022-10-17 10:24:28,044 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1340938594] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:24:28,044 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:24:28,044 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:24:28,044 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1073742097] [2022-10-17 10:24:28,045 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:24:28,045 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:24:28,045 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:24:28,046 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:24:28,046 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:24:28,047 INFO L87 Difference]: Start difference. First operand 1175 states and 1748 transitions. cyclomatic complexity: 574 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:24:28,117 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:24:28,117 INFO L93 Difference]: Finished difference Result 1175 states and 1747 transitions. [2022-10-17 10:24:28,117 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1175 states and 1747 transitions. [2022-10-17 10:24:28,132 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1048 [2022-10-17 10:24:28,144 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1175 states to 1175 states and 1747 transitions. [2022-10-17 10:24:28,145 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1175 [2022-10-17 10:24:28,146 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1175 [2022-10-17 10:24:28,147 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1175 states and 1747 transitions. [2022-10-17 10:24:28,150 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:24:28,151 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1175 states and 1747 transitions. [2022-10-17 10:24:28,154 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1175 states and 1747 transitions. [2022-10-17 10:24:28,172 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1175 to 1175. [2022-10-17 10:24:28,176 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1175 states, 1175 states have (on average 1.4868085106382978) internal successors, (1747), 1174 states have internal predecessors, (1747), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:24:28,182 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1175 states to 1175 states and 1747 transitions. [2022-10-17 10:24:28,182 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1175 states and 1747 transitions. [2022-10-17 10:24:28,183 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:24:28,186 INFO L428 stractBuchiCegarLoop]: Abstraction has 1175 states and 1747 transitions. [2022-10-17 10:24:28,186 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-10-17 10:24:28,187 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1175 states and 1747 transitions. [2022-10-17 10:24:28,196 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1048 [2022-10-17 10:24:28,196 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:24:28,197 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:24:28,199 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:24:28,200 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:24:28,200 INFO L748 eck$LassoCheckResult]: Stem: 12703#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 12704#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 12963#L1403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12722#L663 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12623#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 12373#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12374#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12881#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12913#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12905#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 12906#L695-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 12486#L700-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12476#L705-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12477#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 12297#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12298#L951 assume !(0 == ~M_E~0); 12036#L951-2 assume !(0 == ~T1_E~0); 12037#L956-1 assume !(0 == ~T2_E~0); 12197#L961-1 assume !(0 == ~T3_E~0); 12638#L966-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12639#L971-1 assume !(0 == ~T5_E~0); 12778#L976-1 assume !(0 == ~T6_E~0); 12749#L981-1 assume !(0 == ~T7_E~0); 12522#L986-1 assume !(0 == ~T8_E~0); 12250#L991-1 assume !(0 == ~T9_E~0); 12251#L996-1 assume !(0 == ~E_M~0); 12944#L1001-1 assume !(0 == ~E_1~0); 12701#L1006-1 assume 0 == ~E_2~0;~E_2~0 := 1; 12702#L1011-1 assume !(0 == ~E_3~0); 12914#L1016-1 assume !(0 == ~E_4~0); 12927#L1021-1 assume !(0 == ~E_5~0); 11843#L1026-1 assume !(0 == ~E_6~0); 11844#L1031-1 assume !(0 == ~E_7~0); 12650#L1036-1 assume !(0 == ~E_8~0); 12646#L1041-1 assume !(0 == ~E_9~0); 12647#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12888#L472 assume 1 == ~m_pc~0; 12962#L473 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 12681#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12682#L484 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12689#L1179 assume !(0 != activate_threads_~tmp~1#1); 11851#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11852#L491 assume 1 == ~t1_pc~0; 12698#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12348#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12644#L503 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11821#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 11822#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11845#L510 assume !(1 == ~t2_pc~0); 11810#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 11811#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12890#L522 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12891#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12092#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12093#L529 assume 1 == ~t3_pc~0; 12443#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12444#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12855#L541 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12937#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 12013#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12014#L548 assume !(1 == ~t4_pc~0); 11911#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 11910#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12205#L560 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11953#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 11954#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11898#L567 assume 1 == ~t5_pc~0; 11899#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11955#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12138#L579 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12139#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 12876#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12024#L586 assume !(1 == ~t6_pc~0); 12025#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 12098#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12959#L598 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12975#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 12872#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12873#L605 assume 1 == ~t7_pc~0; 12852#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12502#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12642#L617 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12643#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 12971#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12618#L624 assume !(1 == ~t8_pc~0); 12086#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 12085#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12674#L636 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12675#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 12860#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11866#L643 assume 1 == ~t9_pc~0; 11867#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12817#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12751#L655 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12255#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 12256#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12068#L1059 assume !(1 == ~M_E~0); 12069#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12225#L1064-1 assume !(1 == ~T2_E~0); 12226#L1069-1 assume !(1 == ~T3_E~0); 12824#L1074-1 assume !(1 == ~T4_E~0); 12858#L1079-1 assume !(1 == ~T5_E~0); 12850#L1084-1 assume !(1 == ~T6_E~0); 12851#L1089-1 assume !(1 == ~T7_E~0); 12868#L1094-1 assume !(1 == ~T8_E~0); 12551#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 12552#L1104-1 assume !(1 == ~E_M~0); 12737#L1109-1 assume !(1 == ~E_1~0); 12366#L1114-1 assume !(1 == ~E_2~0); 12367#L1119-1 assume !(1 == ~E_3~0); 12419#L1124-1 assume !(1 == ~E_4~0); 11862#L1129-1 assume !(1 == ~E_5~0); 11863#L1134-1 assume !(1 == ~E_6~0); 12193#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 12194#L1144-1 assume !(1 == ~E_8~0); 12379#L1149-1 assume !(1 == ~E_9~0); 12030#L1154-1 assume { :end_inline_reset_delta_events } true; 12031#L1440-2 [2022-10-17 10:24:28,201 INFO L750 eck$LassoCheckResult]: Loop: 12031#L1440-2 assume !false; 12160#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11802#L926 assume !false; 12421#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 12422#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 12117#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 12118#L781 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 12125#L795 assume !(0 != eval_~tmp~0#1); 12126#L941 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12546#L663-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12282#L951-3 assume !(0 == ~M_E~0); 12283#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12786#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12622#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 12402#L966-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12403#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12676#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11882#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11883#L986-3 assume !(0 == ~T8_E~0); 11864#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 11865#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12772#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12377#L1006-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12378#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12794#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12829#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12569#L1026-3 assume !(0 == ~E_6~0); 12570#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12766#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12767#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 12822#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12784#L472-33 assume 1 == ~m_pc~0; 12785#L473-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 11984#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11819#L484-11 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11820#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12410#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12411#L491-33 assume 1 == ~t1_pc~0; 12690#L492-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11918#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12935#L503-11 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12954#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12955#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12743#L510-33 assume !(1 == ~t2_pc~0); 12738#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 12739#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12640#L522-11 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12641#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11803#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11804#L529-33 assume 1 == ~t3_pc~0; 11831#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11832#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12105#L541-11 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12931#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 11934#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11935#L548-33 assume 1 == ~t4_pc~0; 12176#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12299#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12337#L560-11 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12338#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12115#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12116#L567-33 assume 1 == ~t5_pc~0; 12536#L568-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12221#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12453#L579-11 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12936#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12966#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12637#L586-33 assume 1 == ~t6_pc~0; 12610#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12240#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12565#L598-11 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12566#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12132#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12133#L605-33 assume !(1 == ~t7_pc~0); 12309#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 12060#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12061#L617-11 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12458#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11946#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11947#L624-33 assume 1 == ~t8_pc~0; 12103#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12112#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12080#L636-11 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12081#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12322#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12062#L643-33 assume !(1 == ~t9_pc~0); 12064#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 12148#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12594#L655-11 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12547#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 12548#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11936#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 11937#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12433#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12484#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12485#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12750#L1079-3 assume !(1 == ~T5_E~0); 12653#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12592#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 12593#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 12515#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 12516#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12773#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12755#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12756#L1119-3 assume !(1 == ~E_3~0); 12967#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12970#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12233#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12234#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12397#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12398#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 12553#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 12973#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 11941#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 11823#L781-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 11824#L1459 assume !(0 == start_simulation_~tmp~3#1); 11830#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 12831#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 12120#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 12661#L781-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 12280#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12281#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12437#L1422 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 12614#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 12031#L1440-2 [2022-10-17 10:24:28,203 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:24:28,204 INFO L85 PathProgramCache]: Analyzing trace with hash -218070391, now seen corresponding path program 1 times [2022-10-17 10:24:28,204 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:24:28,204 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [370917126] [2022-10-17 10:24:28,205 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:24:28,205 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:24:28,227 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:24:28,269 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:24:28,269 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:24:28,269 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [370917126] [2022-10-17 10:24:28,270 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [370917126] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:24:28,270 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:24:28,270 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:24:28,276 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [488964164] [2022-10-17 10:24:28,276 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:24:28,278 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:24:28,281 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:24:28,281 INFO L85 PathProgramCache]: Analyzing trace with hash 1265732613, now seen corresponding path program 1 times [2022-10-17 10:24:28,281 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:24:28,282 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1758137561] [2022-10-17 10:24:28,282 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:24:28,282 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:24:28,304 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:24:28,357 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:24:28,358 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:24:28,358 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1758137561] [2022-10-17 10:24:28,360 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1758137561] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:24:28,361 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:24:28,361 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:24:28,361 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1121465661] [2022-10-17 10:24:28,362 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:24:28,362 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:24:28,363 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:24:28,364 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:24:28,364 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:24:28,365 INFO L87 Difference]: Start difference. First operand 1175 states and 1747 transitions. cyclomatic complexity: 573 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:24:28,399 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:24:28,400 INFO L93 Difference]: Finished difference Result 1175 states and 1746 transitions. [2022-10-17 10:24:28,400 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1175 states and 1746 transitions. [2022-10-17 10:24:28,413 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1048 [2022-10-17 10:24:28,426 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1175 states to 1175 states and 1746 transitions. [2022-10-17 10:24:28,426 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1175 [2022-10-17 10:24:28,428 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1175 [2022-10-17 10:24:28,428 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1175 states and 1746 transitions. [2022-10-17 10:24:28,431 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:24:28,431 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1175 states and 1746 transitions. [2022-10-17 10:24:28,434 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1175 states and 1746 transitions. [2022-10-17 10:24:28,453 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1175 to 1175. [2022-10-17 10:24:28,457 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1175 states, 1175 states have (on average 1.4859574468085106) internal successors, (1746), 1174 states have internal predecessors, (1746), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:24:28,464 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1175 states to 1175 states and 1746 transitions. [2022-10-17 10:24:28,464 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1175 states and 1746 transitions. [2022-10-17 10:24:28,465 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:24:28,467 INFO L428 stractBuchiCegarLoop]: Abstraction has 1175 states and 1746 transitions. [2022-10-17 10:24:28,468 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-10-17 10:24:28,468 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1175 states and 1746 transitions. [2022-10-17 10:24:28,481 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1048 [2022-10-17 10:24:28,481 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:24:28,481 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:24:28,484 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:24:28,484 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:24:28,485 INFO L748 eck$LassoCheckResult]: Stem: 15060#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 15061#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 15320#L1403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15079#L663 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14980#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 14730#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14731#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15238#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15270#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 15262#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 15263#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 14843#L700-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 14833#L705-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 14834#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 14654#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14655#L951 assume !(0 == ~M_E~0); 14393#L951-2 assume !(0 == ~T1_E~0); 14394#L956-1 assume !(0 == ~T2_E~0); 14554#L961-1 assume !(0 == ~T3_E~0); 14995#L966-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14996#L971-1 assume !(0 == ~T5_E~0); 15135#L976-1 assume !(0 == ~T6_E~0); 15106#L981-1 assume !(0 == ~T7_E~0); 14879#L986-1 assume !(0 == ~T8_E~0); 14607#L991-1 assume !(0 == ~T9_E~0); 14608#L996-1 assume !(0 == ~E_M~0); 15301#L1001-1 assume !(0 == ~E_1~0); 15058#L1006-1 assume 0 == ~E_2~0;~E_2~0 := 1; 15059#L1011-1 assume !(0 == ~E_3~0); 15271#L1016-1 assume !(0 == ~E_4~0); 15284#L1021-1 assume !(0 == ~E_5~0); 14200#L1026-1 assume !(0 == ~E_6~0); 14201#L1031-1 assume !(0 == ~E_7~0); 15007#L1036-1 assume !(0 == ~E_8~0); 15003#L1041-1 assume !(0 == ~E_9~0); 15004#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15245#L472 assume 1 == ~m_pc~0; 15319#L473 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 15038#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15039#L484 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15046#L1179 assume !(0 != activate_threads_~tmp~1#1); 14208#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14209#L491 assume 1 == ~t1_pc~0; 15055#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14705#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15001#L503 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14178#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 14179#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14202#L510 assume !(1 == ~t2_pc~0); 14167#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 14168#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15247#L522 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15248#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14449#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14450#L529 assume 1 == ~t3_pc~0; 14800#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14801#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15212#L541 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15294#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 14370#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14371#L548 assume !(1 == ~t4_pc~0); 14268#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 14267#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14562#L560 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14310#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 14311#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14255#L567 assume 1 == ~t5_pc~0; 14256#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14312#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14495#L579 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14496#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 15233#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14381#L586 assume !(1 == ~t6_pc~0); 14382#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 14455#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15316#L598 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15332#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 15229#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15230#L605 assume 1 == ~t7_pc~0; 15209#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14859#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14999#L617 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15000#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 15328#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14975#L624 assume !(1 == ~t8_pc~0); 14443#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 14442#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15031#L636 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 15032#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 15217#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14223#L643 assume 1 == ~t9_pc~0; 14224#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 15174#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15108#L655 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14612#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 14613#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14425#L1059 assume !(1 == ~M_E~0); 14426#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14582#L1064-1 assume !(1 == ~T2_E~0); 14583#L1069-1 assume !(1 == ~T3_E~0); 15181#L1074-1 assume !(1 == ~T4_E~0); 15215#L1079-1 assume !(1 == ~T5_E~0); 15207#L1084-1 assume !(1 == ~T6_E~0); 15208#L1089-1 assume !(1 == ~T7_E~0); 15225#L1094-1 assume !(1 == ~T8_E~0); 14908#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14909#L1104-1 assume !(1 == ~E_M~0); 15094#L1109-1 assume !(1 == ~E_1~0); 14723#L1114-1 assume !(1 == ~E_2~0); 14724#L1119-1 assume !(1 == ~E_3~0); 14776#L1124-1 assume !(1 == ~E_4~0); 14219#L1129-1 assume !(1 == ~E_5~0); 14220#L1134-1 assume !(1 == ~E_6~0); 14550#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 14551#L1144-1 assume !(1 == ~E_8~0); 14736#L1149-1 assume !(1 == ~E_9~0); 14387#L1154-1 assume { :end_inline_reset_delta_events } true; 14388#L1440-2 [2022-10-17 10:24:28,486 INFO L750 eck$LassoCheckResult]: Loop: 14388#L1440-2 assume !false; 14517#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14159#L926 assume !false; 14778#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 14779#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 14474#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 14475#L781 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 14482#L795 assume !(0 != eval_~tmp~0#1); 14483#L941 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14903#L663-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14639#L951-3 assume !(0 == ~M_E~0); 14640#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15143#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14979#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14759#L966-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14760#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15033#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14239#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 14240#L986-3 assume !(0 == ~T8_E~0); 14221#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 14222#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 15129#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14734#L1006-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14735#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15151#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 15186#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14926#L1026-3 assume !(0 == ~E_6~0); 14927#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 15123#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 15124#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 15179#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15141#L472-33 assume !(1 == ~m_pc~0); 14340#L472-35 is_master_triggered_~__retres1~0#1 := 0; 14341#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14176#L484-11 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14177#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14767#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14768#L491-33 assume !(1 == ~t1_pc~0); 14274#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 14275#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15292#L503-11 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15311#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15312#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15100#L510-33 assume !(1 == ~t2_pc~0); 15095#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 15096#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14997#L522-11 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14998#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14160#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14161#L529-33 assume 1 == ~t3_pc~0; 14188#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14189#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14462#L541-11 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15288#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 14291#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14292#L548-33 assume 1 == ~t4_pc~0; 14533#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14656#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14694#L560-11 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14695#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14472#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14473#L567-33 assume !(1 == ~t5_pc~0); 14577#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 14578#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14810#L579-11 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15293#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15323#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14994#L586-33 assume !(1 == ~t6_pc~0); 14596#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 14597#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14922#L598-11 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14923#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 14489#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14490#L605-33 assume !(1 == ~t7_pc~0); 14666#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 14417#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14418#L617-11 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14815#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 14303#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14304#L624-33 assume 1 == ~t8_pc~0; 14460#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 14469#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14437#L636-11 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14438#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 14679#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14419#L643-33 assume 1 == ~t9_pc~0; 14420#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 14505#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14951#L655-11 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14904#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 14905#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14293#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14294#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14790#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14841#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14842#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15107#L1079-3 assume !(1 == ~T5_E~0); 15010#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14949#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14950#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14872#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14873#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 15130#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 15112#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15113#L1119-3 assume !(1 == ~E_3~0); 15324#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 15327#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14590#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14591#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 14754#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 14755#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 14910#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 15330#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 14298#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 14180#L781-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 14181#L1459 assume !(0 == start_simulation_~tmp~3#1); 14187#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 15188#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 14477#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 15018#L781-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 14637#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14638#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14794#L1422 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 14971#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 14388#L1440-2 [2022-10-17 10:24:28,487 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:24:28,487 INFO L85 PathProgramCache]: Analyzing trace with hash 1923790087, now seen corresponding path program 1 times [2022-10-17 10:24:28,487 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:24:28,487 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1301671396] [2022-10-17 10:24:28,488 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:24:28,488 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:24:28,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:24:28,560 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:24:28,560 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:24:28,560 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1301671396] [2022-10-17 10:24:28,561 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1301671396] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:24:28,561 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:24:28,561 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:24:28,561 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [886456354] [2022-10-17 10:24:28,562 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:24:28,562 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:24:28,562 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:24:28,563 INFO L85 PathProgramCache]: Analyzing trace with hash -1623165560, now seen corresponding path program 2 times [2022-10-17 10:24:28,563 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:24:28,563 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1675600829] [2022-10-17 10:24:28,563 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:24:28,564 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:24:28,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:24:28,691 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:24:28,692 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:24:28,692 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1675600829] [2022-10-17 10:24:28,692 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1675600829] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:24:28,692 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:24:28,693 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:24:28,693 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1816587391] [2022-10-17 10:24:28,693 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:24:28,694 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:24:28,694 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:24:28,694 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:24:28,695 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:24:28,695 INFO L87 Difference]: Start difference. First operand 1175 states and 1746 transitions. cyclomatic complexity: 572 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:24:28,729 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:24:28,729 INFO L93 Difference]: Finished difference Result 1175 states and 1745 transitions. [2022-10-17 10:24:28,729 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1175 states and 1745 transitions. [2022-10-17 10:24:28,742 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1048 [2022-10-17 10:24:28,755 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1175 states to 1175 states and 1745 transitions. [2022-10-17 10:24:28,756 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1175 [2022-10-17 10:24:28,757 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1175 [2022-10-17 10:24:28,758 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1175 states and 1745 transitions. [2022-10-17 10:24:28,760 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:24:28,760 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1175 states and 1745 transitions. [2022-10-17 10:24:28,764 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1175 states and 1745 transitions. [2022-10-17 10:24:28,783 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1175 to 1175. [2022-10-17 10:24:28,786 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1175 states, 1175 states have (on average 1.4851063829787234) internal successors, (1745), 1174 states have internal predecessors, (1745), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:24:28,793 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1175 states to 1175 states and 1745 transitions. [2022-10-17 10:24:28,794 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1175 states and 1745 transitions. [2022-10-17 10:24:28,794 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:24:28,795 INFO L428 stractBuchiCegarLoop]: Abstraction has 1175 states and 1745 transitions. [2022-10-17 10:24:28,795 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-10-17 10:24:28,795 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1175 states and 1745 transitions. [2022-10-17 10:24:28,803 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1048 [2022-10-17 10:24:28,804 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:24:28,804 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:24:28,806 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:24:28,807 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:24:28,807 INFO L748 eck$LassoCheckResult]: Stem: 17417#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 17418#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 17677#L1403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17436#L663 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17337#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 17087#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17088#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17595#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17627#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 17619#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 17620#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 17200#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 17190#L705-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 17191#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 17011#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17012#L951 assume !(0 == ~M_E~0); 16750#L951-2 assume !(0 == ~T1_E~0); 16751#L956-1 assume !(0 == ~T2_E~0); 16911#L961-1 assume !(0 == ~T3_E~0); 17352#L966-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17353#L971-1 assume !(0 == ~T5_E~0); 17492#L976-1 assume !(0 == ~T6_E~0); 17463#L981-1 assume !(0 == ~T7_E~0); 17236#L986-1 assume !(0 == ~T8_E~0); 16964#L991-1 assume !(0 == ~T9_E~0); 16965#L996-1 assume !(0 == ~E_M~0); 17658#L1001-1 assume !(0 == ~E_1~0); 17415#L1006-1 assume 0 == ~E_2~0;~E_2~0 := 1; 17416#L1011-1 assume !(0 == ~E_3~0); 17628#L1016-1 assume !(0 == ~E_4~0); 17641#L1021-1 assume !(0 == ~E_5~0); 16557#L1026-1 assume !(0 == ~E_6~0); 16558#L1031-1 assume !(0 == ~E_7~0); 17364#L1036-1 assume !(0 == ~E_8~0); 17360#L1041-1 assume !(0 == ~E_9~0); 17361#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17602#L472 assume 1 == ~m_pc~0; 17676#L473 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 17395#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17396#L484 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 17403#L1179 assume !(0 != activate_threads_~tmp~1#1); 16565#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16566#L491 assume 1 == ~t1_pc~0; 17412#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17062#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17358#L503 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16537#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 16538#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16559#L510 assume !(1 == ~t2_pc~0); 16524#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 16525#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17605#L522 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17606#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16806#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16807#L529 assume 1 == ~t3_pc~0; 17157#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17158#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17569#L541 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17651#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 16727#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16728#L548 assume !(1 == ~t4_pc~0); 16625#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 16624#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16919#L560 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16667#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 16668#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16612#L567 assume 1 == ~t5_pc~0; 16613#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16669#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16852#L579 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16853#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 17590#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16738#L586 assume !(1 == ~t6_pc~0); 16739#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 16812#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17673#L598 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17689#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 17586#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17587#L605 assume 1 == ~t7_pc~0; 17566#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 17216#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17356#L617 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17357#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 17685#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17332#L624 assume !(1 == ~t8_pc~0); 16800#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 16799#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17388#L636 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17389#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 17574#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16580#L643 assume 1 == ~t9_pc~0; 16581#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 17531#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17465#L655 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 16971#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 16972#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16782#L1059 assume !(1 == ~M_E~0); 16783#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16939#L1064-1 assume !(1 == ~T2_E~0); 16940#L1069-1 assume !(1 == ~T3_E~0); 17538#L1074-1 assume !(1 == ~T4_E~0); 17572#L1079-1 assume !(1 == ~T5_E~0); 17564#L1084-1 assume !(1 == ~T6_E~0); 17565#L1089-1 assume !(1 == ~T7_E~0); 17582#L1094-1 assume !(1 == ~T8_E~0); 17265#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 17266#L1104-1 assume !(1 == ~E_M~0); 17451#L1109-1 assume !(1 == ~E_1~0); 17080#L1114-1 assume !(1 == ~E_2~0); 17081#L1119-1 assume !(1 == ~E_3~0); 17133#L1124-1 assume !(1 == ~E_4~0); 16576#L1129-1 assume !(1 == ~E_5~0); 16577#L1134-1 assume !(1 == ~E_6~0); 16907#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 16908#L1144-1 assume !(1 == ~E_8~0); 17095#L1149-1 assume !(1 == ~E_9~0); 16744#L1154-1 assume { :end_inline_reset_delta_events } true; 16745#L1440-2 [2022-10-17 10:24:28,808 INFO L750 eck$LassoCheckResult]: Loop: 16745#L1440-2 assume !false; 16874#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16516#L926 assume !false; 17135#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 17136#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 16834#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 16835#L781 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 16840#L795 assume !(0 != eval_~tmp~0#1); 16841#L941 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17260#L663-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16996#L951-3 assume !(0 == ~M_E~0); 16997#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17500#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17336#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17117#L966-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17118#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17390#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 16598#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16599#L986-3 assume !(0 == ~T8_E~0); 16578#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 16579#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 17486#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 17091#L1006-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17092#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17508#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 17543#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 17283#L1026-3 assume !(0 == ~E_6~0); 17284#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 17480#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 17481#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 17536#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17498#L472-33 assume !(1 == ~m_pc~0); 16697#L472-35 is_master_triggered_~__retres1~0#1 := 0; 16698#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16533#L484-11 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16534#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 17124#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17125#L491-33 assume !(1 == ~t1_pc~0); 16631#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 16632#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17649#L503-11 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17668#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17669#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17457#L510-33 assume 1 == ~t2_pc~0; 17458#L511-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17453#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17354#L522-11 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17355#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16517#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16518#L529-33 assume 1 == ~t3_pc~0; 16545#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16546#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16819#L541-11 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17645#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 16648#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16649#L548-33 assume 1 == ~t4_pc~0; 16892#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17013#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17051#L560-11 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17052#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 16829#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16830#L567-33 assume 1 == ~t5_pc~0; 17250#L568-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16935#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17168#L579-11 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17650#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 17681#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17351#L586-33 assume !(1 == ~t6_pc~0); 16953#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 16954#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17279#L598-11 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17280#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 16846#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16847#L605-33 assume 1 == ~t7_pc~0; 17024#L606-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16774#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16775#L617-11 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17173#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 16660#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16661#L624-33 assume 1 == ~t8_pc~0; 16817#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16826#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16794#L636-11 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16795#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 17036#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16776#L643-33 assume 1 == ~t9_pc~0; 16777#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 16862#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17308#L655-11 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17261#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 17262#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16650#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 16651#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17147#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17198#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17199#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 17464#L1079-3 assume !(1 == ~T5_E~0); 17367#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17306#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 17307#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 17229#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 17230#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 17487#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17468#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 17469#L1119-3 assume !(1 == ~E_3~0); 17680#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17684#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16947#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16948#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 17106#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 17107#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 17267#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 17687#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 16653#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 16535#L781-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 16536#L1459 assume !(0 == start_simulation_~tmp~3#1); 16544#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 17544#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 16832#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 17375#L781-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 16994#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16995#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 17148#L1422 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 17327#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 16745#L1440-2 [2022-10-17 10:24:28,809 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:24:28,809 INFO L85 PathProgramCache]: Analyzing trace with hash -1747895607, now seen corresponding path program 1 times [2022-10-17 10:24:28,809 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:24:28,810 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1186600027] [2022-10-17 10:24:28,810 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:24:28,810 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:24:28,826 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:24:28,865 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:24:28,866 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:24:28,866 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1186600027] [2022-10-17 10:24:28,866 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1186600027] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:24:28,866 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:24:28,867 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:24:28,867 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1437399426] [2022-10-17 10:24:28,867 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:24:28,868 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:24:28,868 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:24:28,868 INFO L85 PathProgramCache]: Analyzing trace with hash -1559246907, now seen corresponding path program 1 times [2022-10-17 10:24:28,869 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:24:28,869 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1677095375] [2022-10-17 10:24:28,869 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:24:28,869 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:24:28,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:24:28,938 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:24:28,939 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:24:28,939 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1677095375] [2022-10-17 10:24:28,939 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1677095375] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:24:28,939 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:24:28,940 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:24:28,940 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1885718668] [2022-10-17 10:24:28,940 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:24:28,940 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:24:28,941 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:24:28,941 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:24:28,941 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:24:28,942 INFO L87 Difference]: Start difference. First operand 1175 states and 1745 transitions. cyclomatic complexity: 571 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:24:28,973 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:24:28,974 INFO L93 Difference]: Finished difference Result 1175 states and 1744 transitions. [2022-10-17 10:24:28,974 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1175 states and 1744 transitions. [2022-10-17 10:24:28,984 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1048 [2022-10-17 10:24:28,996 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1175 states to 1175 states and 1744 transitions. [2022-10-17 10:24:28,996 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1175 [2022-10-17 10:24:28,998 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1175 [2022-10-17 10:24:28,998 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1175 states and 1744 transitions. [2022-10-17 10:24:29,001 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:24:29,001 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1175 states and 1744 transitions. [2022-10-17 10:24:29,004 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1175 states and 1744 transitions. [2022-10-17 10:24:29,021 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1175 to 1175. [2022-10-17 10:24:29,025 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1175 states, 1175 states have (on average 1.4842553191489363) internal successors, (1744), 1174 states have internal predecessors, (1744), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:24:29,031 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1175 states to 1175 states and 1744 transitions. [2022-10-17 10:24:29,031 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1175 states and 1744 transitions. [2022-10-17 10:24:29,032 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:24:29,033 INFO L428 stractBuchiCegarLoop]: Abstraction has 1175 states and 1744 transitions. [2022-10-17 10:24:29,033 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-10-17 10:24:29,033 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1175 states and 1744 transitions. [2022-10-17 10:24:29,039 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1048 [2022-10-17 10:24:29,039 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:24:29,039 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:24:29,041 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:24:29,042 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:24:29,042 INFO L748 eck$LassoCheckResult]: Stem: 19774#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 19775#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 20034#L1403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19793#L663 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19694#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 19444#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19445#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19952#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 19984#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19976#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 19977#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 19557#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 19547#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 19548#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 19368#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19369#L951 assume !(0 == ~M_E~0); 19107#L951-2 assume !(0 == ~T1_E~0); 19108#L956-1 assume !(0 == ~T2_E~0); 19268#L961-1 assume !(0 == ~T3_E~0); 19709#L966-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 19710#L971-1 assume !(0 == ~T5_E~0); 19849#L976-1 assume !(0 == ~T6_E~0); 19820#L981-1 assume !(0 == ~T7_E~0); 19593#L986-1 assume !(0 == ~T8_E~0); 19321#L991-1 assume !(0 == ~T9_E~0); 19322#L996-1 assume !(0 == ~E_M~0); 20016#L1001-1 assume !(0 == ~E_1~0); 19772#L1006-1 assume 0 == ~E_2~0;~E_2~0 := 1; 19773#L1011-1 assume !(0 == ~E_3~0); 19986#L1016-1 assume !(0 == ~E_4~0); 19998#L1021-1 assume !(0 == ~E_5~0); 18914#L1026-1 assume !(0 == ~E_6~0); 18915#L1031-1 assume !(0 == ~E_7~0); 19723#L1036-1 assume !(0 == ~E_8~0); 19717#L1041-1 assume !(0 == ~E_9~0); 19718#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19959#L472 assume 1 == ~m_pc~0; 20033#L473 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 19752#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19753#L484 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19760#L1179 assume !(0 != activate_threads_~tmp~1#1); 18922#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18923#L491 assume 1 == ~t1_pc~0; 19769#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19419#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19715#L503 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18894#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 18895#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18918#L510 assume !(1 == ~t2_pc~0); 18881#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 18882#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19962#L522 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19963#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19163#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19164#L529 assume 1 == ~t3_pc~0; 19514#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19515#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19926#L541 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20008#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 19084#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19085#L548 assume !(1 == ~t4_pc~0); 18982#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 18981#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19276#L560 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19026#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 19027#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18969#L567 assume 1 == ~t5_pc~0; 18970#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19028#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19209#L579 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19210#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 19947#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19095#L586 assume !(1 == ~t6_pc~0); 19096#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 19169#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20030#L598 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 20046#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 19943#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19944#L605 assume 1 == ~t7_pc~0; 19923#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19577#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19713#L617 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19714#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 20042#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19689#L624 assume !(1 == ~t8_pc~0); 19157#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 19156#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19745#L636 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19746#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 19931#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 18937#L643 assume 1 == ~t9_pc~0; 18938#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 19888#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19822#L655 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19328#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 19329#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19139#L1059 assume !(1 == ~M_E~0); 19140#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19296#L1064-1 assume !(1 == ~T2_E~0); 19297#L1069-1 assume !(1 == ~T3_E~0); 19895#L1074-1 assume !(1 == ~T4_E~0); 19929#L1079-1 assume !(1 == ~T5_E~0); 19921#L1084-1 assume !(1 == ~T6_E~0); 19922#L1089-1 assume !(1 == ~T7_E~0); 19939#L1094-1 assume !(1 == ~T8_E~0); 19622#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19623#L1104-1 assume !(1 == ~E_M~0); 19808#L1109-1 assume !(1 == ~E_1~0); 19437#L1114-1 assume !(1 == ~E_2~0); 19438#L1119-1 assume !(1 == ~E_3~0); 19490#L1124-1 assume !(1 == ~E_4~0); 18933#L1129-1 assume !(1 == ~E_5~0); 18934#L1134-1 assume !(1 == ~E_6~0); 19264#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 19265#L1144-1 assume !(1 == ~E_8~0); 19452#L1149-1 assume !(1 == ~E_9~0); 19101#L1154-1 assume { :end_inline_reset_delta_events } true; 19102#L1440-2 [2022-10-17 10:24:29,043 INFO L750 eck$LassoCheckResult]: Loop: 19102#L1440-2 assume !false; 19231#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 18873#L926 assume !false; 19492#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 19493#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 19191#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 19192#L781 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 19197#L795 assume !(0 != eval_~tmp~0#1); 19198#L941 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19617#L663-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19353#L951-3 assume !(0 == ~M_E~0); 19354#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19857#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19693#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19477#L966-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 19478#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 19747#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 18955#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 18956#L986-3 assume !(0 == ~T8_E~0); 18935#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 18936#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 19843#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 19448#L1006-3 assume 0 == ~E_2~0;~E_2~0 := 1; 19449#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 19865#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 19900#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 19641#L1026-3 assume !(0 == ~E_6~0); 19642#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 19837#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 19838#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 19893#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19855#L472-33 assume 1 == ~m_pc~0; 19856#L473-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 19055#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18890#L484-11 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18891#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19481#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19482#L491-33 assume 1 == ~t1_pc~0; 19761#L492-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18989#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20007#L503-11 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 20025#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20026#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19814#L510-33 assume !(1 == ~t2_pc~0); 19809#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 19810#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19711#L522-11 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19712#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18874#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18875#L529-33 assume 1 == ~t3_pc~0; 18902#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18903#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19176#L541-11 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20002#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 19005#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19006#L548-33 assume 1 == ~t4_pc~0; 19249#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 19370#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19408#L560-11 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19409#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 19186#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19187#L567-33 assume 1 == ~t5_pc~0; 19606#L568-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19289#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19524#L579-11 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20006#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 20037#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19708#L586-33 assume 1 == ~t6_pc~0; 19681#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19310#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19634#L598-11 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19635#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 19203#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19204#L605-33 assume !(1 == ~t7_pc~0); 19380#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 19124#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19125#L617-11 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19529#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19017#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19018#L624-33 assume 1 == ~t8_pc~0; 19174#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 19183#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19151#L636-11 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19152#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 19393#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19126#L643-33 assume 1 == ~t9_pc~0; 19127#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 19219#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19665#L655-11 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19618#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 19619#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19007#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 19008#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19504#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19554#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 19555#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19821#L1079-3 assume !(1 == ~T5_E~0); 19724#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 19663#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19664#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19586#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19587#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19844#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19825#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19826#L1119-3 assume !(1 == ~E_3~0); 20038#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20041#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 19304#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19305#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19463#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 19464#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 19624#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 20044#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 19010#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 18892#L781-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 18893#L1459 assume !(0 == start_simulation_~tmp~3#1); 18901#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 19901#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 19189#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 19732#L781-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 19351#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19352#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19505#L1422 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 19685#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 19102#L1440-2 [2022-10-17 10:24:29,044 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:24:29,044 INFO L85 PathProgramCache]: Analyzing trace with hash -1866337081, now seen corresponding path program 1 times [2022-10-17 10:24:29,044 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:24:29,044 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1013899684] [2022-10-17 10:24:29,044 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:24:29,045 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:24:29,063 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:24:29,171 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:24:29,171 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:24:29,172 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1013899684] [2022-10-17 10:24:29,172 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1013899684] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:24:29,172 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:24:29,172 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:24:29,172 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1576997929] [2022-10-17 10:24:29,173 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:24:29,173 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:24:29,174 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:24:29,174 INFO L85 PathProgramCache]: Analyzing trace with hash -2072306300, now seen corresponding path program 1 times [2022-10-17 10:24:29,174 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:24:29,174 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1754605905] [2022-10-17 10:24:29,175 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:24:29,175 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:24:29,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:24:29,250 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:24:29,250 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:24:29,251 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1754605905] [2022-10-17 10:24:29,251 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1754605905] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:24:29,251 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:24:29,251 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:24:29,251 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1051099550] [2022-10-17 10:24:29,252 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:24:29,252 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:24:29,252 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:24:29,253 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-10-17 10:24:29,253 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-10-17 10:24:29,253 INFO L87 Difference]: Start difference. First operand 1175 states and 1744 transitions. cyclomatic complexity: 570 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:24:29,424 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:24:29,425 INFO L93 Difference]: Finished difference Result 2151 states and 3181 transitions. [2022-10-17 10:24:29,425 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2151 states and 3181 transitions. [2022-10-17 10:24:29,460 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2004 [2022-10-17 10:24:29,487 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2151 states to 2151 states and 3181 transitions. [2022-10-17 10:24:29,487 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2151 [2022-10-17 10:24:29,493 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2151 [2022-10-17 10:24:29,494 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2151 states and 3181 transitions. [2022-10-17 10:24:29,498 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:24:29,498 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2151 states and 3181 transitions. [2022-10-17 10:24:29,503 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2151 states and 3181 transitions. [2022-10-17 10:24:29,566 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2151 to 2151. [2022-10-17 10:24:29,572 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2151 states, 2151 states have (on average 1.478847047884705) internal successors, (3181), 2150 states have internal predecessors, (3181), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:24:29,583 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2151 states to 2151 states and 3181 transitions. [2022-10-17 10:24:29,583 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2151 states and 3181 transitions. [2022-10-17 10:24:29,584 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-10-17 10:24:29,585 INFO L428 stractBuchiCegarLoop]: Abstraction has 2151 states and 3181 transitions. [2022-10-17 10:24:29,585 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-10-17 10:24:29,585 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2151 states and 3181 transitions. [2022-10-17 10:24:29,596 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2004 [2022-10-17 10:24:29,597 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:24:29,597 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:24:29,599 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:24:29,600 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:24:29,600 INFO L748 eck$LassoCheckResult]: Stem: 23135#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 23136#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 23423#L1403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 23156#L663 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 23052#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 22792#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 22793#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23332#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23368#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 23359#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 23360#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 22907#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 22896#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 22897#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 22714#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22715#L951 assume !(0 == ~M_E~0); 22450#L951-2 assume !(0 == ~T1_E~0); 22451#L956-1 assume !(0 == ~T2_E~0); 22612#L961-1 assume !(0 == ~T3_E~0); 23069#L966-1 assume !(0 == ~T4_E~0); 23070#L971-1 assume !(0 == ~T5_E~0); 23211#L976-1 assume !(0 == ~T6_E~0); 23181#L981-1 assume !(0 == ~T7_E~0); 22946#L986-1 assume !(0 == ~T8_E~0); 22665#L991-1 assume !(0 == ~T9_E~0); 22666#L996-1 assume !(0 == ~E_M~0); 23403#L1001-1 assume !(0 == ~E_1~0); 23132#L1006-1 assume 0 == ~E_2~0;~E_2~0 := 1; 23133#L1011-1 assume !(0 == ~E_3~0); 23371#L1016-1 assume !(0 == ~E_4~0); 23383#L1021-1 assume !(0 == ~E_5~0); 22250#L1026-1 assume !(0 == ~E_6~0); 22251#L1031-1 assume !(0 == ~E_7~0); 23083#L1036-1 assume !(0 == ~E_8~0); 23079#L1041-1 assume !(0 == ~E_9~0); 23080#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23339#L472 assume 1 == ~m_pc~0; 23421#L473 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 23112#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23113#L484 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 23120#L1179 assume !(0 != activate_threads_~tmp~1#1); 22258#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22259#L491 assume 1 == ~t1_pc~0; 23131#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 22767#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23075#L503 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22230#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 22231#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22254#L510 assume !(1 == ~t2_pc~0); 22217#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 22218#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23344#L522 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23345#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22503#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22504#L529 assume 1 == ~t3_pc~0; 22861#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 22862#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23304#L541 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 23393#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 22423#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22424#L548 assume !(1 == ~t4_pc~0); 22318#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 22317#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22622#L560 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22363#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 22364#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22310#L567 assume 1 == ~t5_pc~0; 22311#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22365#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22553#L579 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22554#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 23327#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22434#L586 assume !(1 == ~t6_pc~0); 22435#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 22511#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 23418#L598 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 23442#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 23323#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23324#L605 assume 1 == ~t7_pc~0; 23302#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 22931#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23073#L617 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 23074#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 23435#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 23047#L624 assume !(1 == ~t8_pc~0); 22497#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 22496#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23105#L636 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 23106#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 23311#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22275#L643 assume 1 == ~t9_pc~0; 22276#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 23259#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 23185#L655 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22672#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 22673#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22478#L1059 assume 1 == ~M_E~0;~M_E~0 := 2; 22479#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 24028#L1064-1 assume !(1 == ~T2_E~0); 24027#L1069-1 assume !(1 == ~T3_E~0); 24026#L1074-1 assume !(1 == ~T4_E~0); 23434#L1079-1 assume !(1 == ~T5_E~0); 24025#L1084-1 assume !(1 == ~T6_E~0); 24024#L1089-1 assume !(1 == ~T7_E~0); 24023#L1094-1 assume !(1 == ~T8_E~0); 24022#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 24021#L1104-1 assume !(1 == ~E_M~0); 24020#L1109-1 assume !(1 == ~E_1~0); 24019#L1114-1 assume !(1 == ~E_2~0); 24018#L1119-1 assume !(1 == ~E_3~0); 24017#L1124-1 assume !(1 == ~E_4~0); 24016#L1129-1 assume !(1 == ~E_5~0); 23057#L1134-1 assume !(1 == ~E_6~0); 23058#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 22798#L1144-1 assume !(1 == ~E_8~0); 22799#L1149-1 assume !(1 == ~E_9~0); 22440#L1154-1 assume { :end_inline_reset_delta_events } true; 22441#L1440-2 [2022-10-17 10:24:29,602 INFO L750 eck$LassoCheckResult]: Loop: 22441#L1440-2 assume !false; 23397#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 22209#L926 assume !false; 22839#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 22840#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 22532#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 22533#L781 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 22538#L795 assume !(0 != eval_~tmp~0#1); 22539#L941 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 23309#L663-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 23310#L951-3 assume !(0 == ~M_E~0); 23443#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 24226#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 24225#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 24224#L966-3 assume !(0 == ~T4_E~0); 24223#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 24222#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 24221#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 24220#L986-3 assume !(0 == ~T8_E~0); 24219#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 24218#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 24217#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 24216#L1006-3 assume 0 == ~E_2~0;~E_2~0 := 1; 24215#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 24214#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 24213#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 24212#L1026-3 assume !(0 == ~E_6~0); 24211#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 24210#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 24209#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 24208#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24207#L472-33 assume !(1 == ~m_pc~0); 24205#L472-35 is_master_triggered_~__retres1~0#1 := 0; 24204#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24203#L484-11 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 24202#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 24201#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24200#L491-33 assume 1 == ~t1_pc~0; 24198#L492-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24197#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24196#L503-11 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 24195#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 24194#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24193#L510-33 assume 1 == ~t2_pc~0; 24192#L511-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 24190#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24189#L522-11 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 24188#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 24187#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24186#L529-33 assume 1 == ~t3_pc~0; 24184#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 24183#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24182#L541-11 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24181#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 24180#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24179#L548-33 assume 1 == ~t4_pc~0; 24177#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 24176#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24175#L560-11 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24174#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 24173#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24172#L567-33 assume !(1 == ~t5_pc~0); 24170#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 24169#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24168#L579-11 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24167#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 24163#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 24161#L586-33 assume 1 == ~t6_pc~0; 24158#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 24157#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24156#L598-11 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24155#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 24154#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22725#L605-33 assume !(1 == ~t7_pc~0); 22726#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 22470#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22471#L617-11 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 22878#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 22354#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22355#L624-33 assume 1 == ~t8_pc~0; 22514#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 24058#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24057#L636-11 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 24056#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 24055#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24054#L643-33 assume !(1 == ~t9_pc~0); 24052#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 24051#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 24050#L655-11 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 24049#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 24048#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24047#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 22344#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 24046#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 24045#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 24044#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 23182#L1079-3 assume !(1 == ~T5_E~0); 24043#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 24042#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 24041#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 24040#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 24039#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 24038#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 24037#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 24036#L1119-3 assume !(1 == ~E_3~0); 24035#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 24034#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 24033#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 24032#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 24031#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 24030#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 24029#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 23798#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 23789#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 23788#L781-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 23787#L1459 assume !(0 == start_simulation_~tmp~3#1); 23274#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 23275#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 23482#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 23481#L781-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 23480#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 23479#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 23478#L1422 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 23271#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 22441#L1440-2 [2022-10-17 10:24:29,603 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:24:29,603 INFO L85 PathProgramCache]: Analyzing trace with hash 99525123, now seen corresponding path program 1 times [2022-10-17 10:24:29,603 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:24:29,603 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1291970934] [2022-10-17 10:24:29,604 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:24:29,604 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:24:29,620 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:24:29,680 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:24:29,681 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:24:29,681 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1291970934] [2022-10-17 10:24:29,681 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1291970934] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:24:29,681 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:24:29,682 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-10-17 10:24:29,682 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [131370262] [2022-10-17 10:24:29,682 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:24:29,684 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:24:29,684 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:24:29,685 INFO L85 PathProgramCache]: Analyzing trace with hash -631498428, now seen corresponding path program 1 times [2022-10-17 10:24:29,685 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:24:29,685 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1419957701] [2022-10-17 10:24:29,685 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:24:29,686 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:24:29,704 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:24:29,754 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:24:29,754 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:24:29,755 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1419957701] [2022-10-17 10:24:29,755 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1419957701] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:24:29,755 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:24:29,755 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:24:29,755 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1197706613] [2022-10-17 10:24:29,756 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:24:29,756 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:24:29,756 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:24:29,757 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:24:29,758 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:24:29,758 INFO L87 Difference]: Start difference. First operand 2151 states and 3181 transitions. cyclomatic complexity: 1032 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:24:29,854 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:24:29,854 INFO L93 Difference]: Finished difference Result 2151 states and 3151 transitions. [2022-10-17 10:24:29,854 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2151 states and 3151 transitions. [2022-10-17 10:24:29,873 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2004 [2022-10-17 10:24:29,895 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2151 states to 2151 states and 3151 transitions. [2022-10-17 10:24:29,895 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2151 [2022-10-17 10:24:29,898 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2151 [2022-10-17 10:24:29,899 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2151 states and 3151 transitions. [2022-10-17 10:24:29,902 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:24:29,902 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2151 states and 3151 transitions. [2022-10-17 10:24:29,906 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2151 states and 3151 transitions. [2022-10-17 10:24:29,949 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2151 to 2151. [2022-10-17 10:24:29,955 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2151 states, 2151 states have (on average 1.4649000464900046) internal successors, (3151), 2150 states have internal predecessors, (3151), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:24:29,966 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2151 states to 2151 states and 3151 transitions. [2022-10-17 10:24:29,966 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2151 states and 3151 transitions. [2022-10-17 10:24:29,967 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:24:29,968 INFO L428 stractBuchiCegarLoop]: Abstraction has 2151 states and 3151 transitions. [2022-10-17 10:24:29,968 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-10-17 10:24:29,968 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2151 states and 3151 transitions. [2022-10-17 10:24:29,997 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2004 [2022-10-17 10:24:29,998 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:24:29,998 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:24:30,000 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:24:30,001 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:24:30,001 INFO L748 eck$LassoCheckResult]: Stem: 27434#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 27435#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 27724#L1403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 27456#L663 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 27353#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 27096#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 27097#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 27631#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 27669#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 27660#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 27661#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 27209#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 27199#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 27200#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 27017#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 27018#L951 assume !(0 == ~M_E~0); 26755#L951-2 assume !(0 == ~T1_E~0); 26756#L956-1 assume !(0 == ~T2_E~0); 26916#L961-1 assume !(0 == ~T3_E~0); 27369#L966-1 assume !(0 == ~T4_E~0); 27370#L971-1 assume !(0 == ~T5_E~0); 27510#L976-1 assume !(0 == ~T6_E~0); 27481#L981-1 assume !(0 == ~T7_E~0); 27250#L986-1 assume !(0 == ~T8_E~0); 26969#L991-1 assume !(0 == ~T9_E~0); 26970#L996-1 assume !(0 == ~E_M~0); 27705#L1001-1 assume !(0 == ~E_1~0); 27432#L1006-1 assume !(0 == ~E_2~0); 27433#L1011-1 assume !(0 == ~E_3~0); 27672#L1016-1 assume !(0 == ~E_4~0); 27685#L1021-1 assume !(0 == ~E_5~0); 26558#L1026-1 assume !(0 == ~E_6~0); 26559#L1031-1 assume !(0 == ~E_7~0); 27383#L1036-1 assume !(0 == ~E_8~0); 27379#L1041-1 assume !(0 == ~E_9~0); 27380#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27638#L472 assume 1 == ~m_pc~0; 27722#L473 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 27412#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27413#L484 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 27420#L1179 assume !(0 != activate_threads_~tmp~1#1); 26566#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26567#L491 assume 1 == ~t1_pc~0; 27431#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27069#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27375#L503 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 26539#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 26540#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26562#L510 assume !(1 == ~t2_pc~0); 26526#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 26527#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27644#L522 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 27645#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 26808#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26809#L529 assume 1 == ~t3_pc~0; 27164#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27165#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 27600#L541 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 27696#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 26728#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26729#L548 assume !(1 == ~t4_pc~0); 26627#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 26626#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26926#L560 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26671#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 26672#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26619#L567 assume 1 == ~t5_pc~0; 26620#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 26673#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26857#L579 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 26858#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 27626#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26739#L586 assume !(1 == ~t6_pc~0); 26740#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 26816#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27719#L598 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 27748#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 27622#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 27623#L605 assume 1 == ~t7_pc~0; 27598#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 27233#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 27373#L617 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 27374#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 27738#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 27348#L624 assume !(1 == ~t8_pc~0); 26802#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 26801#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27406#L636 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 27407#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 27607#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 26583#L643 assume 1 == ~t9_pc~0; 26584#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 27556#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 27484#L655 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26976#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 26977#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26783#L1059 assume 1 == ~M_E~0;~M_E~0 := 2; 26784#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27887#L1064-1 assume !(1 == ~T2_E~0); 27886#L1069-1 assume !(1 == ~T3_E~0); 27885#L1074-1 assume !(1 == ~T4_E~0); 27735#L1079-1 assume !(1 == ~T5_E~0); 27884#L1084-1 assume !(1 == ~T6_E~0); 27883#L1089-1 assume !(1 == ~T7_E~0); 27882#L1094-1 assume !(1 == ~T8_E~0); 27881#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 27880#L1104-1 assume !(1 == ~E_M~0); 27471#L1109-1 assume !(1 == ~E_1~0); 27085#L1114-1 assume !(1 == ~E_2~0); 27086#L1119-1 assume !(1 == ~E_3~0); 27141#L1124-1 assume !(1 == ~E_4~0); 26579#L1129-1 assume !(1 == ~E_5~0); 26580#L1134-1 assume !(1 == ~E_6~0); 27358#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 27863#L1144-1 assume !(1 == ~E_8~0); 27861#L1149-1 assume !(1 == ~E_9~0); 26745#L1154-1 assume { :end_inline_reset_delta_events } true; 26746#L1440-2 [2022-10-17 10:24:30,002 INFO L750 eck$LassoCheckResult]: Loop: 26746#L1440-2 assume !false; 27700#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 26518#L926 assume !false; 27142#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 27143#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 26836#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 26837#L781 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 26842#L795 assume !(0 != eval_~tmp~0#1); 26843#L941 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 27605#L663-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 27606#L951-3 assume !(0 == ~M_E~0); 27744#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 27520#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 27352#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 27123#L966-3 assume !(0 == ~T4_E~0); 27124#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 27405#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 26598#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 26599#L986-3 assume !(0 == ~T8_E~0); 26577#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 26578#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 27504#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 27098#L1006-3 assume !(0 == ~E_2~0); 27099#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 27528#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 27571#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 27294#L1026-3 assume !(0 == ~E_6~0); 27295#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 27498#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 27499#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 27560#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27518#L472-33 assume !(1 == ~m_pc~0); 26699#L472-35 is_master_triggered_~__retres1~0#1 := 0; 26700#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26535#L484-11 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 26536#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 27131#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27132#L491-33 assume !(1 == ~t1_pc~0); 26633#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 26634#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27694#L503-11 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 27714#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 27715#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27475#L510-33 assume !(1 == ~t2_pc~0); 27469#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 27470#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27371#L522-11 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 27372#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 26519#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26520#L529-33 assume 1 == ~t3_pc~0; 26547#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 26548#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26821#L541-11 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 27690#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 26650#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26651#L548-33 assume !(1 == ~t4_pc~0); 26896#L548-35 is_transmit4_triggered_~__retres1~4#1 := 0; 27016#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 27056#L560-11 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27057#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 26831#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26832#L567-33 assume !(1 == ~t5_pc~0); 26939#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 26940#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 27176#L579-11 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27695#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 27726#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 27368#L586-33 assume 1 == ~t6_pc~0; 27338#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 26959#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27290#L598-11 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 27291#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 26848#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26849#L605-33 assume !(1 == ~t7_pc~0); 27028#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 26774#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26775#L617-11 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 27181#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 26662#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 26663#L624-33 assume 1 == ~t8_pc~0; 26819#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 26828#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26796#L636-11 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 26797#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 27041#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 26776#L643-33 assume 1 == ~t9_pc~0; 26777#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 26864#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 27321#L655-11 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 27272#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 27273#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26652#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 26653#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27154#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 27207#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 27208#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 27482#L1079-3 assume !(1 == ~T5_E~0); 27384#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 27319#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 27320#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 27238#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 27239#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 27505#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 27487#L1114-3 assume !(1 == ~E_2~0); 27488#L1119-3 assume !(1 == ~E_3~0); 27727#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 27734#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 26952#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 26953#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 27118#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 27119#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 27278#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 27740#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 26657#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 26537#L781-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 26538#L1459 assume !(0 == start_simulation_~tmp~3#1); 26546#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 27573#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 26834#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 27392#L781-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 26999#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 27000#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 27156#L1422 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 27570#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 26746#L1440-2 [2022-10-17 10:24:30,003 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:24:30,003 INFO L85 PathProgramCache]: Analyzing trace with hash 1976588353, now seen corresponding path program 1 times [2022-10-17 10:24:30,003 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:24:30,003 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1073155814] [2022-10-17 10:24:30,004 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:24:30,004 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:24:30,023 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:24:30,075 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:24:30,075 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:24:30,075 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1073155814] [2022-10-17 10:24:30,075 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1073155814] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:24:30,076 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:24:30,076 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-10-17 10:24:30,076 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [962247856] [2022-10-17 10:24:30,076 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:24:30,077 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:24:30,077 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:24:30,078 INFO L85 PathProgramCache]: Analyzing trace with hash -6194298, now seen corresponding path program 1 times [2022-10-17 10:24:30,078 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:24:30,078 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [10262400] [2022-10-17 10:24:30,079 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:24:30,079 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:24:30,101 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:24:30,150 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:24:30,151 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:24:30,151 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [10262400] [2022-10-17 10:24:30,151 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [10262400] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:24:30,151 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:24:30,151 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:24:30,152 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [705562255] [2022-10-17 10:24:30,152 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:24:30,152 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:24:30,153 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:24:30,153 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:24:30,154 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:24:30,154 INFO L87 Difference]: Start difference. First operand 2151 states and 3151 transitions. cyclomatic complexity: 1002 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:24:30,333 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:24:30,333 INFO L93 Difference]: Finished difference Result 4115 states and 5970 transitions. [2022-10-17 10:24:30,334 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4115 states and 5970 transitions. [2022-10-17 10:24:30,363 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3967 [2022-10-17 10:24:30,410 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4115 states to 4115 states and 5970 transitions. [2022-10-17 10:24:30,410 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4115 [2022-10-17 10:24:30,416 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4115 [2022-10-17 10:24:30,416 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4115 states and 5970 transitions. [2022-10-17 10:24:30,423 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:24:30,424 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4115 states and 5970 transitions. [2022-10-17 10:24:30,430 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4115 states and 5970 transitions. [2022-10-17 10:24:30,519 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4115 to 3977. [2022-10-17 10:24:30,530 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3977 states, 3977 states have (on average 1.4528539099823987) internal successors, (5778), 3976 states have internal predecessors, (5778), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:24:30,548 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3977 states to 3977 states and 5778 transitions. [2022-10-17 10:24:30,548 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3977 states and 5778 transitions. [2022-10-17 10:24:30,549 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:24:30,549 INFO L428 stractBuchiCegarLoop]: Abstraction has 3977 states and 5778 transitions. [2022-10-17 10:24:30,549 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-10-17 10:24:30,550 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3977 states and 5778 transitions. [2022-10-17 10:24:30,571 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3829 [2022-10-17 10:24:30,572 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:24:30,572 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:24:30,574 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:24:30,575 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:24:30,575 INFO L748 eck$LassoCheckResult]: Stem: 33720#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 33721#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 34035#L1403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 33741#L663 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 33640#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 33374#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33375#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 33929#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 33976#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 33963#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 33964#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 33492#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 33481#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 33482#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 33294#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33295#L951 assume !(0 == ~M_E~0); 33023#L951-2 assume !(0 == ~T1_E~0); 33024#L956-1 assume !(0 == ~T2_E~0); 33189#L961-1 assume !(0 == ~T3_E~0); 33655#L966-1 assume !(0 == ~T4_E~0); 33656#L971-1 assume !(0 == ~T5_E~0); 33797#L976-1 assume !(0 == ~T6_E~0); 33768#L981-1 assume !(0 == ~T7_E~0); 33531#L986-1 assume !(0 == ~T8_E~0); 33242#L991-1 assume !(0 == ~T9_E~0); 33243#L996-1 assume !(0 == ~E_M~0); 34012#L1001-1 assume !(0 == ~E_1~0); 33718#L1006-1 assume !(0 == ~E_2~0); 33719#L1011-1 assume !(0 == ~E_3~0); 33977#L1016-1 assume !(0 == ~E_4~0); 33991#L1021-1 assume !(0 == ~E_5~0); 32831#L1026-1 assume !(0 == ~E_6~0); 32832#L1031-1 assume !(0 == ~E_7~0); 33667#L1036-1 assume !(0 == ~E_8~0); 33663#L1041-1 assume !(0 == ~E_9~0); 33664#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33939#L472 assume !(1 == ~m_pc~0); 33898#L472-2 is_master_triggered_~__retres1~0#1 := 0; 33698#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33699#L484 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 33706#L1179 assume !(0 != activate_threads_~tmp~1#1); 32839#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32840#L491 assume 1 == ~t1_pc~0; 33715#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 33346#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33661#L503 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 32810#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 32811#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 32833#L510 assume !(1 == ~t2_pc~0); 32799#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 32800#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33944#L522 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 33945#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 33080#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33081#L529 assume 1 == ~t3_pc~0; 33447#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 33448#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33893#L541 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 34001#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 33000#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33001#L548 assume !(1 == ~t4_pc~0); 32899#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 32898#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33197#L560 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 32941#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 32942#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 32886#L567 assume 1 == ~t5_pc~0; 32887#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 32943#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33126#L579 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33127#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 33924#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33011#L586 assume !(1 == ~t6_pc~0); 33012#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 33086#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 34032#L598 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 34071#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 33919#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33920#L605 assume 1 == ~t7_pc~0; 33890#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 33508#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33659#L617 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 33660#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 34053#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33635#L624 assume !(1 == ~t8_pc~0); 33074#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 33073#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33691#L636 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33692#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 33902#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 32854#L643 assume 1 == ~t9_pc~0; 32855#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 33845#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33770#L655 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 33247#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 33248#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33055#L1059 assume 1 == ~M_E~0;~M_E~0 := 2; 33056#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 33217#L1064-1 assume !(1 == ~T2_E~0); 33218#L1069-1 assume !(1 == ~T3_E~0); 33854#L1074-1 assume !(1 == ~T4_E~0); 33899#L1079-1 assume !(1 == ~T5_E~0); 33888#L1084-1 assume !(1 == ~T6_E~0); 33889#L1089-1 assume !(1 == ~T7_E~0); 33915#L1094-1 assume !(1 == ~T8_E~0); 33560#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 33561#L1104-1 assume !(1 == ~E_M~0); 33756#L1109-1 assume !(1 == ~E_1~0); 33364#L1114-1 assume !(1 == ~E_2~0); 33365#L1119-1 assume !(1 == ~E_3~0); 34059#L1124-1 assume !(1 == ~E_4~0); 36405#L1129-1 assume !(1 == ~E_5~0); 36403#L1134-1 assume !(1 == ~E_6~0); 36402#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 33380#L1144-1 assume !(1 == ~E_8~0); 33381#L1149-1 assume !(1 == ~E_9~0); 35883#L1154-1 assume { :end_inline_reset_delta_events } true; 35881#L1440-2 [2022-10-17 10:24:30,576 INFO L750 eck$LassoCheckResult]: Loop: 35881#L1440-2 assume !false; 34005#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 32791#L926 assume !false; 33424#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 33425#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 35867#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 33835#L781 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 33114#L795 assume !(0 != eval_~tmp~0#1); 33115#L941 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 33554#L663-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 33901#L951-3 assume !(0 == ~M_E~0); 36566#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 36697#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 36696#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 36695#L966-3 assume !(0 == ~T4_E~0); 36694#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 36693#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 36692#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 36691#L986-3 assume !(0 == ~T8_E~0); 36690#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 36689#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 36688#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 36687#L1006-3 assume !(0 == ~E_2~0); 36686#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 36685#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 36684#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 36683#L1026-3 assume !(0 == ~E_6~0); 36682#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 36681#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 36680#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 36679#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36678#L472-33 assume !(1 == ~m_pc~0); 36677#L472-35 is_master_triggered_~__retres1~0#1 := 0; 36676#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36675#L484-11 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 36674#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 36673#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36672#L491-33 assume 1 == ~t1_pc~0; 36670#L492-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 36669#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36668#L503-11 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 36667#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 36666#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33762#L510-33 assume !(1 == ~t2_pc~0); 33757#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 33758#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33657#L522-11 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 33658#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 32792#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 32793#L529-33 assume 1 == ~t3_pc~0; 32820#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 32821#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33093#L541-11 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33995#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 32922#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32923#L548-33 assume 1 == ~t4_pc~0; 33166#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 33296#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33335#L560-11 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33336#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 33103#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33104#L567-33 assume 1 == ~t5_pc~0; 33545#L568-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 33213#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33457#L579-11 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 34000#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 34039#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33654#L586-33 assume 1 == ~t6_pc~0; 33624#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33232#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33574#L598-11 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 33575#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 33120#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33121#L605-33 assume !(1 == ~t7_pc~0); 33306#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 33046#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33047#L617-11 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 33464#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 32934#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32935#L624-33 assume 1 == ~t8_pc~0; 33091#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 33100#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33068#L636-11 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33069#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 33320#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33048#L643-33 assume 1 == ~t9_pc~0; 33049#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 33138#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33606#L655-11 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 33556#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 33557#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32924#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 32925#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 33436#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 33490#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 33491#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 33769#L1079-3 assume !(1 == ~T5_E~0); 33670#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 33604#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 33605#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 33521#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 33522#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 33792#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 33775#L1114-3 assume !(1 == ~E_2~0); 33776#L1119-3 assume !(1 == ~E_3~0); 34040#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 34047#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 33225#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 33226#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 33399#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 33400#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 33562#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 34069#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 36580#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 36579#L781-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 36578#L1459 assume !(0 == start_simulation_~tmp~3#1); 33946#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 36576#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 36404#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 34064#L781-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 33272#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 33273#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 35885#L1422 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 35882#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 35881#L1440-2 [2022-10-17 10:24:30,577 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:24:30,577 INFO L85 PathProgramCache]: Analyzing trace with hash -858385022, now seen corresponding path program 1 times [2022-10-17 10:24:30,577 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:24:30,580 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1225095860] [2022-10-17 10:24:30,580 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:24:30,580 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:24:30,598 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:24:30,690 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:24:30,690 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:24:30,690 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1225095860] [2022-10-17 10:24:30,691 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1225095860] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:24:30,691 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:24:30,691 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:24:30,691 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1538856404] [2022-10-17 10:24:30,692 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:24:30,692 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:24:30,693 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:24:30,693 INFO L85 PathProgramCache]: Analyzing trace with hash -235511613, now seen corresponding path program 1 times [2022-10-17 10:24:30,693 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:24:30,693 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [421693460] [2022-10-17 10:24:30,693 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:24:30,694 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:24:30,712 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:24:30,787 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:24:30,787 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:24:30,788 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [421693460] [2022-10-17 10:24:30,788 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [421693460] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:24:30,788 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:24:30,788 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:24:30,789 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1784420058] [2022-10-17 10:24:30,789 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:24:30,789 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:24:30,789 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:24:30,790 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-10-17 10:24:30,790 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-10-17 10:24:30,790 INFO L87 Difference]: Start difference. First operand 3977 states and 5778 transitions. cyclomatic complexity: 1805 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:24:31,125 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:24:31,125 INFO L93 Difference]: Finished difference Result 9525 states and 13699 transitions. [2022-10-17 10:24:31,125 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9525 states and 13699 transitions. [2022-10-17 10:24:31,196 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 9224 [2022-10-17 10:24:31,257 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9525 states to 9525 states and 13699 transitions. [2022-10-17 10:24:31,258 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9525 [2022-10-17 10:24:31,270 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9525 [2022-10-17 10:24:31,270 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9525 states and 13699 transitions. [2022-10-17 10:24:31,285 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:24:31,285 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9525 states and 13699 transitions. [2022-10-17 10:24:31,298 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9525 states and 13699 transitions. [2022-10-17 10:24:31,440 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9525 to 7469. [2022-10-17 10:24:31,458 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7469 states, 7469 states have (on average 1.4441022894631141) internal successors, (10786), 7468 states have internal predecessors, (10786), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:24:31,483 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7469 states to 7469 states and 10786 transitions. [2022-10-17 10:24:31,484 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7469 states and 10786 transitions. [2022-10-17 10:24:31,484 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-10-17 10:24:31,485 INFO L428 stractBuchiCegarLoop]: Abstraction has 7469 states and 10786 transitions. [2022-10-17 10:24:31,485 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-10-17 10:24:31,485 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7469 states and 10786 transitions. [2022-10-17 10:24:31,556 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 7320 [2022-10-17 10:24:31,556 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:24:31,556 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:24:31,559 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:24:31,559 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:24:31,560 INFO L748 eck$LassoCheckResult]: Stem: 47226#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 47227#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 47553#L1403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 47245#L663 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 47139#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 46884#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 46885#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 47437#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 47485#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 47473#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 47474#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 47001#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 46990#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 46991#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 46803#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 46804#L951 assume !(0 == ~M_E~0); 46536#L951-2 assume !(0 == ~T1_E~0); 46537#L956-1 assume !(0 == ~T2_E~0); 46701#L961-1 assume !(0 == ~T3_E~0); 47157#L966-1 assume !(0 == ~T4_E~0); 47158#L971-1 assume !(0 == ~T5_E~0); 47304#L976-1 assume !(0 == ~T6_E~0); 47273#L981-1 assume !(0 == ~T7_E~0); 47038#L986-1 assume !(0 == ~T8_E~0); 46754#L991-1 assume !(0 == ~T9_E~0); 46755#L996-1 assume !(0 == ~E_M~0); 47532#L1001-1 assume !(0 == ~E_1~0); 47224#L1006-1 assume !(0 == ~E_2~0); 47225#L1011-1 assume !(0 == ~E_3~0); 47486#L1016-1 assume !(0 == ~E_4~0); 47509#L1021-1 assume !(0 == ~E_5~0); 46343#L1026-1 assume !(0 == ~E_6~0); 46344#L1031-1 assume !(0 == ~E_7~0); 47169#L1036-1 assume !(0 == ~E_8~0); 47165#L1041-1 assume !(0 == ~E_9~0); 47166#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47446#L472 assume !(1 == ~m_pc~0); 47404#L472-2 is_master_triggered_~__retres1~0#1 := 0; 47202#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47203#L484 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 47211#L1179 assume !(0 != activate_threads_~tmp~1#1); 46351#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 46352#L491 assume !(1 == ~t1_pc~0); 46853#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 46854#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47163#L503 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 46322#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 46323#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46345#L510 assume !(1 == ~t2_pc~0); 46311#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 46312#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47448#L522 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 47449#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 46592#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46593#L529 assume 1 == ~t3_pc~0; 46957#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 46958#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 47399#L541 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 47521#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 46513#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46514#L548 assume !(1 == ~t4_pc~0); 46411#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 46410#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46709#L560 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 46454#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 46455#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 46398#L567 assume 1 == ~t5_pc~0; 46399#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 46456#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 46638#L579 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 46639#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 47432#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46524#L586 assume !(1 == ~t6_pc~0); 46525#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 46598#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 47549#L598 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 47580#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 47425#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 47426#L605 assume 1 == ~t7_pc~0; 47396#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 47017#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 47161#L617 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 47162#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 47565#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 47134#L624 assume !(1 == ~t8_pc~0); 46586#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 46585#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 47196#L636 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 47197#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 47408#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 46366#L643 assume 1 == ~t9_pc~0; 46367#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 47352#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 47276#L655 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 46759#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 46760#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46568#L1059 assume 1 == ~M_E~0;~M_E~0 := 2; 46569#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 47581#L1064-1 assume !(1 == ~T2_E~0); 47362#L1069-1 assume !(1 == ~T3_E~0); 47363#L1074-1 assume !(1 == ~T4_E~0); 47405#L1079-1 assume !(1 == ~T5_E~0); 47406#L1084-1 assume !(1 == ~T6_E~0); 47492#L1089-1 assume !(1 == ~T7_E~0); 47493#L1094-1 assume !(1 == ~T8_E~0); 47067#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 47068#L1104-1 assume !(1 == ~E_M~0); 47260#L1109-1 assume !(1 == ~E_1~0); 47261#L1114-1 assume !(1 == ~E_2~0); 47571#L1119-1 assume !(1 == ~E_3~0); 47572#L1124-1 assume !(1 == ~E_4~0); 46362#L1129-1 assume !(1 == ~E_5~0); 46363#L1134-1 assume !(1 == ~E_6~0); 46697#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 46698#L1144-1 assume !(1 == ~E_8~0); 47577#L1149-1 assume !(1 == ~E_9~0); 47578#L1154-1 assume { :end_inline_reset_delta_events } true; 52983#L1440-2 [2022-10-17 10:24:31,560 INFO L750 eck$LassoCheckResult]: Loop: 52983#L1440-2 assume !false; 52977#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 52973#L926 assume !false; 52972#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 52970#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 52961#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 52960#L781 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 52958#L795 assume !(0 != eval_~tmp~0#1); 52959#L941 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 53678#L663-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 53677#L951-3 assume !(0 == ~M_E~0); 47575#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 47319#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 47138#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 46914#L966-3 assume !(0 == ~T4_E~0); 46915#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 47198#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 46383#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 46384#L986-3 assume !(0 == ~T8_E~0); 46364#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 46365#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 47297#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 46888#L1006-3 assume !(0 == ~E_2~0); 46889#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 47327#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 47369#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 47085#L1026-3 assume !(0 == ~E_6~0); 47086#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 47292#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 47293#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 47574#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 53659#L472-33 assume !(1 == ~m_pc~0); 53658#L472-35 is_master_triggered_~__retres1~0#1 := 0; 53657#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 53656#L484-11 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 53655#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 53654#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 53653#L491-33 assume !(1 == ~t1_pc~0); 51074#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 47518#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47519#L503-11 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 47544#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 47545#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47264#L510-33 assume !(1 == ~t2_pc~0); 47262#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 47263#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47159#L522-11 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 47160#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 46304#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46305#L529-33 assume 1 == ~t3_pc~0; 46332#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 46333#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46605#L541-11 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 47514#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 46434#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46435#L548-33 assume 1 == ~t4_pc~0; 46677#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 46805#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46843#L560-11 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 46844#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 46615#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 46616#L567-33 assume !(1 == ~t5_pc~0); 46724#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 46725#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 46967#L579-11 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47520#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 47556#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 47156#L586-33 assume 1 == ~t6_pc~0; 47126#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 46744#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 47081#L598-11 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 47082#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 46632#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 46633#L605-33 assume !(1 == ~t7_pc~0); 46812#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 46556#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 46557#L617-11 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 46972#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 46447#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 46448#L624-33 assume 1 == ~t8_pc~0; 46601#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 46612#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 46580#L636-11 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 46581#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 46828#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 47579#L643-33 assume !(1 == ~t9_pc~0); 53185#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 53183#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 53181#L655-11 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 53179#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 53177#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 53174#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 46437#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 53166#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 53161#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 53157#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 47274#L1079-3 assume !(1 == ~T5_E~0); 53149#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 53145#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 53140#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 53135#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 53131#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 53116#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 53115#L1114-3 assume !(1 == ~E_2~0); 53114#L1119-3 assume !(1 == ~E_3~0); 53113#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 53112#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 53111#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 53110#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 53109#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 53108#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 53107#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 53105#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 53096#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 53095#L781-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 53094#L1459 assume !(0 == start_simulation_~tmp~3#1); 47453#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 53091#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 53081#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 53079#L781-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 53077#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 53013#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 52997#L1422 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 52990#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 52983#L1440-2 [2022-10-17 10:24:31,561 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:24:31,562 INFO L85 PathProgramCache]: Analyzing trace with hash -717285501, now seen corresponding path program 1 times [2022-10-17 10:24:31,562 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:24:31,562 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [564650559] [2022-10-17 10:24:31,562 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:24:31,562 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:24:31,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:24:31,650 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:24:31,650 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:24:31,650 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [564650559] [2022-10-17 10:24:31,651 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [564650559] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:24:31,651 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:24:31,651 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-10-17 10:24:31,651 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1813274050] [2022-10-17 10:24:31,651 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:24:31,652 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:24:31,652 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:24:31,653 INFO L85 PathProgramCache]: Analyzing trace with hash -2100751546, now seen corresponding path program 1 times [2022-10-17 10:24:31,653 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:24:31,653 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1664652435] [2022-10-17 10:24:31,653 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:24:31,653 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:24:31,671 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:24:31,719 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:24:31,719 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:24:31,719 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1664652435] [2022-10-17 10:24:31,719 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1664652435] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:24:31,720 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:24:31,720 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:24:31,720 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [809490469] [2022-10-17 10:24:31,720 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:24:31,721 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:24:31,721 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:24:31,721 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-10-17 10:24:31,722 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-10-17 10:24:31,722 INFO L87 Difference]: Start difference. First operand 7469 states and 10786 transitions. cyclomatic complexity: 3321 Second operand has 5 states, 5 states have (on average 23.4) internal successors, (117), 5 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:24:31,997 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:24:31,997 INFO L93 Difference]: Finished difference Result 9597 states and 13807 transitions. [2022-10-17 10:24:31,998 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9597 states and 13807 transitions. [2022-10-17 10:24:32,061 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 9444 [2022-10-17 10:24:32,107 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9597 states to 9597 states and 13807 transitions. [2022-10-17 10:24:32,108 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9597 [2022-10-17 10:24:32,122 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9597 [2022-10-17 10:24:32,122 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9597 states and 13807 transitions. [2022-10-17 10:24:32,136 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:24:32,136 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9597 states and 13807 transitions. [2022-10-17 10:24:32,151 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9597 states and 13807 transitions. [2022-10-17 10:24:32,402 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9597 to 7481. [2022-10-17 10:24:32,419 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7481 states, 7481 states have (on average 1.432562491645502) internal successors, (10717), 7480 states have internal predecessors, (10717), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:24:32,449 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7481 states to 7481 states and 10717 transitions. [2022-10-17 10:24:32,450 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7481 states and 10717 transitions. [2022-10-17 10:24:32,450 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-10-17 10:24:32,451 INFO L428 stractBuchiCegarLoop]: Abstraction has 7481 states and 10717 transitions. [2022-10-17 10:24:32,451 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-10-17 10:24:32,451 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7481 states and 10717 transitions. [2022-10-17 10:24:32,490 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 7332 [2022-10-17 10:24:32,491 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:24:32,491 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:24:32,494 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:24:32,494 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:24:32,495 INFO L748 eck$LassoCheckResult]: Stem: 64436#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 64437#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 65014#L1403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 64467#L663 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 64327#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 63993#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 63994#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 64777#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 64874#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 64848#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 64849#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 64144#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 64128#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 64129#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 63904#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 63905#L951 assume !(0 == ~M_E~0); 63619#L951-2 assume !(0 == ~T1_E~0); 63620#L956-1 assume !(0 == ~T2_E~0); 63794#L961-1 assume !(0 == ~T3_E~0); 64350#L966-1 assume !(0 == ~T4_E~0); 64351#L971-1 assume !(0 == ~T5_E~0); 64543#L976-1 assume !(0 == ~T6_E~0); 64505#L981-1 assume !(0 == ~T7_E~0); 64192#L986-1 assume !(0 == ~T8_E~0); 63851#L991-1 assume !(0 == ~T9_E~0); 63852#L996-1 assume !(0 == ~E_M~0); 64971#L1001-1 assume !(0 == ~E_1~0); 64434#L1006-1 assume !(0 == ~E_2~0); 64435#L1011-1 assume !(0 == ~E_3~0); 64875#L1016-1 assume !(0 == ~E_4~0); 64919#L1021-1 assume !(0 == ~E_5~0); 63423#L1026-1 assume !(0 == ~E_6~0); 63424#L1031-1 assume !(0 == ~E_7~0); 64364#L1036-1 assume !(0 == ~E_8~0); 64359#L1041-1 assume !(0 == ~E_9~0); 64360#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 64792#L472 assume !(1 == ~m_pc~0); 64707#L472-2 is_master_triggered_~__retres1~0#1 := 0; 64411#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 64412#L484 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 64422#L1179 assume !(0 != activate_threads_~tmp~1#1); 63431#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 63432#L491 assume !(1 == ~t1_pc~0); 63964#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 63965#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 64356#L503 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 63401#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 63402#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 63425#L510 assume !(1 == ~t2_pc~0); 63390#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 63391#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 64794#L522 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 64795#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 63677#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 63678#L529 assume 1 == ~t3_pc~0; 64081#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 64082#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 64694#L541 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 64944#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 63596#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 63597#L548 assume !(1 == ~t4_pc~0); 63491#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 63490#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 63804#L560 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 63533#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 63534#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 63478#L567 assume 1 == ~t5_pc~0; 63479#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 63535#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 63730#L579 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 63731#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 64765#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 63607#L586 assume !(1 == ~t6_pc~0); 63608#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 63683#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 65002#L598 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 65162#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 64757#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 64758#L605 assume 1 == ~t7_pc~0; 64683#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 64161#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 64354#L617 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 64355#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 65078#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 64321#L624 assume !(1 == ~t8_pc~0); 63669#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 63668#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 64399#L636 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 64400#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 64718#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 63446#L643 assume 1 == ~t9_pc~0; 63447#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 64618#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 64508#L655 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 63856#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 63857#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 63651#L1059 assume 1 == ~M_E~0;~M_E~0 := 2; 63652#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 63825#L1064-1 assume !(1 == ~T2_E~0); 63826#L1069-1 assume !(1 == ~T3_E~0); 64629#L1074-1 assume !(1 == ~T4_E~0); 64713#L1079-1 assume !(1 == ~T5_E~0); 64681#L1084-1 assume !(1 == ~T6_E~0); 64682#L1089-1 assume !(1 == ~T7_E~0); 64741#L1094-1 assume !(1 == ~T8_E~0); 64227#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 64228#L1104-1 assume !(1 == ~E_M~0); 64490#L1109-1 assume !(1 == ~E_1~0); 63984#L1114-1 assume !(1 == ~E_2~0); 63985#L1119-1 assume !(1 == ~E_3~0); 64050#L1124-1 assume !(1 == ~E_4~0); 63442#L1129-1 assume !(1 == ~E_5~0); 63443#L1134-1 assume !(1 == ~E_6~0); 63790#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 63791#L1144-1 assume !(1 == ~E_8~0); 67348#L1149-1 assume !(1 == ~E_9~0); 63613#L1154-1 assume { :end_inline_reset_delta_events } true; 63614#L1440-2 [2022-10-17 10:24:32,496 INFO L750 eck$LassoCheckResult]: Loop: 63614#L1440-2 assume !false; 65838#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 65835#L926 assume !false; 65830#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 65831#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 65784#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 65785#L781 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 65771#L795 assume !(0 != eval_~tmp~0#1); 65772#L941 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 68635#L663-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 68634#L951-3 assume !(0 == ~M_E~0); 68633#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 68632#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 68631#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 68630#L966-3 assume !(0 == ~T4_E~0); 68629#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 68628#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 68627#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 68626#L986-3 assume !(0 == ~T8_E~0); 68625#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 68624#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 68623#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 68622#L1006-3 assume !(0 == ~E_2~0); 68621#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 68620#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 68619#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 68618#L1026-3 assume !(0 == ~E_6~0); 68617#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 68616#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 68615#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 68614#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 68613#L472-33 assume !(1 == ~m_pc~0); 68612#L472-35 is_master_triggered_~__retres1~0#1 := 0; 68611#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 68610#L484-11 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 68609#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 68608#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 65039#L491-33 assume !(1 == ~t1_pc~0); 65040#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 64940#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 64941#L503-11 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 64995#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 64996#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 64493#L510-33 assume !(1 == ~t2_pc~0); 64491#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 64492#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 67727#L522-11 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 67726#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 67724#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 63710#L529-33 assume 1 == ~t3_pc~0; 63712#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 63691#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 63692#L541-11 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 65003#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 65004#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 67715#L548-33 assume 1 == ~t4_pc~0; 63906#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 63907#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 64448#L560-11 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 67708#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 67706#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 64886#L567-33 assume !(1 == ~t5_pc~0); 64887#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 64095#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 64096#L579-11 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 65025#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 65026#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 65112#L586-33 assume 1 == ~t6_pc~0; 64312#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 63840#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 64245#L598-11 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 64246#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 65136#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 65548#L605-33 assume !(1 == ~t7_pc~0); 65549#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 63639#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 63640#L617-11 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 64102#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 65520#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 65521#L624-33 assume 1 == ~t8_pc~0; 65507#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 65508#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 65496#L636-11 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 65497#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 65151#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 63641#L643-33 assume 1 == ~t9_pc~0; 63642#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 63741#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 65098#L655-11 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 64223#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 64224#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 63516#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 63517#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 64065#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 67656#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 67653#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 64506#L1079-3 assume !(1 == ~T5_E~0); 64367#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 64368#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 64450#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 64180#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 64181#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 64534#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 67642#L1114-3 assume !(1 == ~E_2~0); 65027#L1119-3 assume !(1 == ~E_3~0); 65028#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 65161#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 63833#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 63834#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 64023#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 64024#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 65157#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 65091#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 63521#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 63403#L781-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 63404#L1459 assume !(0 == start_simulation_~tmp~3#1); 67600#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 67596#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 67586#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 67584#L781-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 67582#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 67580#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 67578#L1422 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 67575#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 63614#L1440-2 [2022-10-17 10:24:32,497 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:24:32,497 INFO L85 PathProgramCache]: Analyzing trace with hash 1891501957, now seen corresponding path program 1 times [2022-10-17 10:24:32,497 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:24:32,497 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [770664884] [2022-10-17 10:24:32,498 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:24:32,498 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:24:32,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:24:32,599 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:24:32,600 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:24:32,600 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [770664884] [2022-10-17 10:24:32,600 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [770664884] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:24:32,601 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:24:32,601 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:24:32,601 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1688462662] [2022-10-17 10:24:32,601 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:24:32,602 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:24:32,602 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:24:32,603 INFO L85 PathProgramCache]: Analyzing trace with hash -1116757561, now seen corresponding path program 1 times [2022-10-17 10:24:32,603 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:24:32,603 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [124758697] [2022-10-17 10:24:32,603 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:24:32,603 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:24:32,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:24:32,675 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:24:32,675 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:24:32,675 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [124758697] [2022-10-17 10:24:32,675 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [124758697] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:24:32,676 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:24:32,676 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:24:32,676 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [648054736] [2022-10-17 10:24:32,676 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:24:32,677 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:24:32,677 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:24:32,678 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-10-17 10:24:32,678 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-10-17 10:24:32,679 INFO L87 Difference]: Start difference. First operand 7481 states and 10717 transitions. cyclomatic complexity: 3240 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:24:33,044 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:24:33,044 INFO L93 Difference]: Finished difference Result 17989 states and 25551 transitions. [2022-10-17 10:24:33,045 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17989 states and 25551 transitions. [2022-10-17 10:24:33,298 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 17535 [2022-10-17 10:24:33,367 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17989 states to 17989 states and 25551 transitions. [2022-10-17 10:24:33,367 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17989 [2022-10-17 10:24:33,390 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17989 [2022-10-17 10:24:33,390 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17989 states and 25551 transitions. [2022-10-17 10:24:33,409 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:24:33,409 INFO L218 hiAutomatonCegarLoop]: Abstraction has 17989 states and 25551 transitions. [2022-10-17 10:24:33,433 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17989 states and 25551 transitions. [2022-10-17 10:24:33,646 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17989 to 14148. [2022-10-17 10:24:33,671 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14148 states, 14148 states have (on average 1.4256432004523607) internal successors, (20170), 14147 states have internal predecessors, (20170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:24:33,838 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14148 states to 14148 states and 20170 transitions. [2022-10-17 10:24:33,838 INFO L240 hiAutomatonCegarLoop]: Abstraction has 14148 states and 20170 transitions. [2022-10-17 10:24:33,839 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-10-17 10:24:33,839 INFO L428 stractBuchiCegarLoop]: Abstraction has 14148 states and 20170 transitions. [2022-10-17 10:24:33,839 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-10-17 10:24:33,839 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14148 states and 20170 transitions. [2022-10-17 10:24:33,899 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 13996 [2022-10-17 10:24:33,900 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:24:33,900 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:24:33,903 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:24:33,903 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:24:33,904 INFO L748 eck$LassoCheckResult]: Stem: 89793#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 89794#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 90130#L1403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 89816#L663 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 89709#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 89442#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 89443#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 90012#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 90062#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 90048#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 90049#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 89562#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 89551#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 89552#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 89361#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 89362#L951 assume !(0 == ~M_E~0); 89094#L951-2 assume !(0 == ~T1_E~0); 89095#L956-1 assume !(0 == ~T2_E~0); 89260#L961-1 assume !(0 == ~T3_E~0); 89727#L966-1 assume !(0 == ~T4_E~0); 89728#L971-1 assume !(0 == ~T5_E~0); 89873#L976-1 assume !(0 == ~T6_E~0); 89843#L981-1 assume !(0 == ~T7_E~0); 89599#L986-1 assume !(0 == ~T8_E~0); 89313#L991-1 assume !(0 == ~T9_E~0); 89314#L996-1 assume !(0 == ~E_M~0); 90109#L1001-1 assume !(0 == ~E_1~0); 89791#L1006-1 assume !(0 == ~E_2~0); 89792#L1011-1 assume !(0 == ~E_3~0); 90063#L1016-1 assume !(0 == ~E_4~0); 90087#L1021-1 assume !(0 == ~E_5~0); 88902#L1026-1 assume !(0 == ~E_6~0); 88903#L1031-1 assume !(0 == ~E_7~0); 89739#L1036-1 assume !(0 == ~E_8~0); 89735#L1041-1 assume !(0 == ~E_9~0); 89736#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 90022#L472 assume !(1 == ~m_pc~0); 89975#L472-2 is_master_triggered_~__retres1~0#1 := 0; 89770#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 89771#L484 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 89778#L1179 assume !(0 != activate_threads_~tmp~1#1); 88910#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 88911#L491 assume !(1 == ~t1_pc~0); 89411#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 89412#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 89733#L503 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 88881#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 88882#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 88904#L510 assume !(1 == ~t2_pc~0); 88870#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 88871#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 90024#L522 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 90025#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 89151#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 89152#L529 assume !(1 == ~t3_pc~0); 89604#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 89899#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 89970#L541 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 90098#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 89071#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 89072#L548 assume !(1 == ~t4_pc~0); 88970#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 88969#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 89268#L560 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 89012#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 89013#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 88957#L567 assume 1 == ~t5_pc~0; 88958#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 89014#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 89199#L579 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 89200#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 90007#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 89082#L586 assume !(1 == ~t6_pc~0); 89083#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 89157#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 90124#L598 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 90162#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 89998#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 89999#L605 assume 1 == ~t7_pc~0; 89966#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 89578#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 89731#L617 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 89732#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 90152#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 89703#L624 assume !(1 == ~t8_pc~0); 89144#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 89143#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 89764#L636 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 89765#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 89980#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 88925#L643 assume 1 == ~t9_pc~0; 88926#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 89925#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 89846#L655 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 89318#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 89319#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 89126#L1059 assume 1 == ~M_E~0;~M_E~0 := 2; 89127#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 89288#L1064-1 assume !(1 == ~T2_E~0); 89289#L1069-1 assume !(1 == ~T3_E~0); 90146#L1074-1 assume !(1 == ~T4_E~0); 90147#L1079-1 assume !(1 == ~T5_E~0); 89964#L1084-1 assume !(1 == ~T6_E~0); 89965#L1089-1 assume !(1 == ~T7_E~0); 89993#L1094-1 assume !(1 == ~T8_E~0); 89994#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 90077#L1104-1 assume !(1 == ~E_M~0); 90078#L1109-1 assume !(1 == ~E_1~0); 89430#L1114-1 assume !(1 == ~E_2~0); 89431#L1119-1 assume !(1 == ~E_3~0); 89493#L1124-1 assume !(1 == ~E_4~0); 89494#L1129-1 assume !(1 == ~E_5~0); 89714#L1134-1 assume !(1 == ~E_6~0); 89715#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 89451#L1144-1 assume !(1 == ~E_8~0); 89452#L1149-1 assume !(1 == ~E_9~0); 89088#L1154-1 assume { :end_inline_reset_delta_events } true; 89089#L1440-2 [2022-10-17 10:24:33,905 INFO L750 eck$LassoCheckResult]: Loop: 89089#L1440-2 assume !false; 89221#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 88862#L926 assume !false; 89497#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 89498#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 89177#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 89178#L781 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 89915#L795 assume !(0 != eval_~tmp~0#1); 89624#L941 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 89625#L663-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 89979#L951-3 assume !(0 == ~M_E~0); 102981#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 103008#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 103007#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 103006#L966-3 assume !(0 == ~T4_E~0); 103005#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 103004#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 103003#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 103002#L986-3 assume !(0 == ~T8_E~0); 103001#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 103000#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 102999#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 102998#L1006-3 assume !(0 == ~E_2~0); 102997#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 102996#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 102995#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 102994#L1026-3 assume !(0 == ~E_6~0); 102993#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 102992#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 102991#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 89931#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 89882#L472-33 assume !(1 == ~m_pc~0); 89038#L472-35 is_master_triggered_~__retres1~0#1 := 0; 89039#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 88876#L484-11 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 88877#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 102986#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 102985#L491-33 assume !(1 == ~t1_pc~0); 88973#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 88974#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 90096#L503-11 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 90119#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 90120#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 102979#L510-33 assume !(1 == ~t2_pc~0); 102977#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 102968#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 102967#L522-11 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 102966#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 102965#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 102963#L529-33 assume !(1 == ~t3_pc~0); 97987#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 102960#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 102958#L541-11 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 102918#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 102886#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 102885#L548-33 assume 1 == ~t4_pc~0; 102883#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 102882#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 102881#L560-11 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 102880#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 102879#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 102878#L567-33 assume 1 == ~t5_pc~0; 102877#L568-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 102875#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 102874#L579-11 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 102873#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 102872#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 102871#L586-33 assume 1 == ~t6_pc~0; 102869#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 102868#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 102866#L598-11 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 102864#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 102862#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 102860#L605-33 assume !(1 == ~t7_pc~0); 102857#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 102855#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 102852#L617-11 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 102851#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 102850#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 102849#L624-33 assume !(1 == ~t8_pc~0); 102848#L624-35 is_transmit8_triggered_~__retres1~8#1 := 0; 102846#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 102845#L636-11 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 102844#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 102843#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 102842#L643-33 assume 1 == ~t9_pc~0; 102841#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 102839#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 102838#L655-11 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 102837#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 102727#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 102726#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 88996#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 102725#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 102724#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 102723#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 89844#L1079-3 assume !(1 == ~T5_E~0); 102722#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 102721#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 102720#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 102719#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 102718#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 102717#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 102716#L1114-3 assume !(1 == ~E_2~0); 102715#L1119-3 assume !(1 == ~E_3~0); 102714#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 102713#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 102712#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 102711#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 102710#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 102709#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 102708#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 102704#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 102694#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 102692#L781-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 102690#L1459 assume !(0 == start_simulation_~tmp~3#1); 90029#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 102682#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 102672#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 102670#L781-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 102668#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 102667#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 102665#L1422 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 89941#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 89089#L1440-2 [2022-10-17 10:24:33,906 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:24:33,906 INFO L85 PathProgramCache]: Analyzing trace with hash -1826536698, now seen corresponding path program 1 times [2022-10-17 10:24:33,907 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:24:33,907 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [939236840] [2022-10-17 10:24:33,907 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:24:33,907 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:24:33,926 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:24:33,988 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:24:33,988 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:24:33,989 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [939236840] [2022-10-17 10:24:33,989 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [939236840] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:24:33,989 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:24:33,989 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-10-17 10:24:33,990 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [116753857] [2022-10-17 10:24:33,990 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:24:33,990 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:24:33,991 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:24:33,991 INFO L85 PathProgramCache]: Analyzing trace with hash 1868902920, now seen corresponding path program 1 times [2022-10-17 10:24:33,991 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:24:33,991 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [199436618] [2022-10-17 10:24:33,992 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:24:33,992 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:24:34,010 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:24:34,061 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:24:34,061 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:24:34,061 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [199436618] [2022-10-17 10:24:34,061 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [199436618] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:24:34,062 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:24:34,062 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:24:34,062 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1046173832] [2022-10-17 10:24:34,062 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:24:34,063 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:24:34,063 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:24:34,064 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:24:34,064 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:24:34,064 INFO L87 Difference]: Start difference. First operand 14148 states and 20170 transitions. cyclomatic complexity: 6026 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:24:34,389 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:24:34,389 INFO L93 Difference]: Finished difference Result 26863 states and 38123 transitions. [2022-10-17 10:24:34,389 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 26863 states and 38123 transitions. [2022-10-17 10:24:34,670 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 26672 [2022-10-17 10:24:34,962 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 26863 states to 26863 states and 38123 transitions. [2022-10-17 10:24:34,963 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 26863 [2022-10-17 10:24:35,002 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 26863 [2022-10-17 10:24:35,002 INFO L73 IsDeterministic]: Start isDeterministic. Operand 26863 states and 38123 transitions. [2022-10-17 10:24:35,036 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:24:35,036 INFO L218 hiAutomatonCegarLoop]: Abstraction has 26863 states and 38123 transitions. [2022-10-17 10:24:35,069 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26863 states and 38123 transitions. [2022-10-17 10:24:35,566 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26863 to 26831. [2022-10-17 10:24:35,604 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 26831 states, 26831 states have (on average 1.4196638216987814) internal successors, (38091), 26830 states have internal predecessors, (38091), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:24:35,726 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26831 states to 26831 states and 38091 transitions. [2022-10-17 10:24:35,726 INFO L240 hiAutomatonCegarLoop]: Abstraction has 26831 states and 38091 transitions. [2022-10-17 10:24:35,727 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:24:35,727 INFO L428 stractBuchiCegarLoop]: Abstraction has 26831 states and 38091 transitions. [2022-10-17 10:24:35,728 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-10-17 10:24:35,728 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 26831 states and 38091 transitions. [2022-10-17 10:24:36,034 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 26640 [2022-10-17 10:24:36,035 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:24:36,035 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:24:36,038 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:24:36,038 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:24:36,047 INFO L748 eck$LassoCheckResult]: Stem: 130824#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 130825#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 131186#L1403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 130845#L663 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 130739#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 130460#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 130461#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 131057#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 131110#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 131097#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 131098#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 130582#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 130569#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 130570#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 130382#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 130383#L951 assume !(0 == ~M_E~0); 130112#L951-2 assume !(0 == ~T1_E~0); 130113#L956-1 assume !(0 == ~T2_E~0); 130281#L961-1 assume !(0 == ~T3_E~0); 130756#L966-1 assume !(0 == ~T4_E~0); 130757#L971-1 assume !(0 == ~T5_E~0); 130904#L976-1 assume !(0 == ~T6_E~0); 130873#L981-1 assume !(0 == ~T7_E~0); 130620#L986-1 assume !(0 == ~T8_E~0); 130336#L991-1 assume !(0 == ~T9_E~0); 130337#L996-1 assume !(0 == ~E_M~0); 131162#L1001-1 assume !(0 == ~E_1~0); 130822#L1006-1 assume !(0 == ~E_2~0); 130823#L1011-1 assume !(0 == ~E_3~0); 131111#L1016-1 assume !(0 == ~E_4~0); 131138#L1021-1 assume !(0 == ~E_5~0); 129921#L1026-1 assume !(0 == ~E_6~0); 129922#L1031-1 assume !(0 == ~E_7~0); 130768#L1036-1 assume !(0 == ~E_8~0); 130764#L1041-1 assume !(0 == ~E_9~0); 130765#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 131070#L472 assume !(1 == ~m_pc~0); 131019#L472-2 is_master_triggered_~__retres1~0#1 := 0; 130799#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 130800#L484 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 130809#L1179 assume !(0 != activate_threads_~tmp~1#1); 129929#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 129930#L491 assume !(1 == ~t1_pc~0); 130432#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 130433#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 130762#L503 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 129899#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 129900#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 129923#L510 assume !(1 == ~t2_pc~0); 129888#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 129889#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 131072#L522 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 131073#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 130171#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 130172#L529 assume !(1 == ~t3_pc~0); 130625#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 130934#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 131015#L541 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 131151#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 130089#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 130090#L548 assume !(1 == ~t4_pc~0); 129986#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 129985#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 130289#L560 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 130027#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 130028#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 129974#L567 assume !(1 == ~t5_pc~0); 129975#L567-2 is_transmit5_triggered_~__retres1~5#1 := 0; 130029#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 130220#L579 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 130221#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 131051#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 130100#L586 assume !(1 == ~t6_pc~0); 130101#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 130177#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 131179#L598 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 131225#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 131045#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 131046#L605 assume 1 == ~t7_pc~0; 131010#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 130598#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 130760#L617 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 130761#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 131207#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 130733#L624 assume !(1 == ~t8_pc~0); 130163#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 130162#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 130791#L636 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 130792#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 131023#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 129943#L643 assume 1 == ~t9_pc~0; 129944#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 130966#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 130875#L655 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 130341#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 130342#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 130144#L1059 assume 1 == ~M_E~0;~M_E~0 := 2; 130145#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 141325#L1064-1 assume !(1 == ~T2_E~0); 141324#L1069-1 assume !(1 == ~T3_E~0); 141323#L1074-1 assume !(1 == ~T4_E~0); 131204#L1079-1 assume !(1 == ~T5_E~0); 131008#L1084-1 assume !(1 == ~T6_E~0); 131009#L1089-1 assume !(1 == ~T7_E~0); 131035#L1094-1 assume !(1 == ~T8_E~0); 131036#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 141312#L1104-1 assume !(1 == ~E_M~0); 130861#L1109-1 assume !(1 == ~E_1~0); 130452#L1114-1 assume !(1 == ~E_2~0); 130453#L1119-1 assume !(1 == ~E_3~0); 131210#L1124-1 assume !(1 == ~E_4~0); 141301#L1129-1 assume !(1 == ~E_5~0); 130744#L1134-1 assume !(1 == ~E_6~0); 130277#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 130278#L1144-1 assume !(1 == ~E_8~0); 130470#L1149-1 assume !(1 == ~E_9~0); 130106#L1154-1 assume { :end_inline_reset_delta_events } true; 130107#L1440-2 [2022-10-17 10:24:36,048 INFO L750 eck$LassoCheckResult]: Loop: 130107#L1440-2 assume !false; 142994#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 142989#L926 assume !false; 142987#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 142979#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 142969#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 142967#L781 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 142964#L795 assume !(0 != eval_~tmp~0#1); 142965#L941 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 150261#L663-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 150256#L951-3 assume !(0 == ~M_E~0); 150250#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 150245#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 150241#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 150236#L966-3 assume !(0 == ~T4_E~0); 149943#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 149942#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 149938#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 149932#L986-3 assume !(0 == ~T8_E~0); 149925#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 149919#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 149913#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 149907#L1006-3 assume !(0 == ~E_2~0); 149902#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 149894#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 149887#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 149881#L1026-3 assume !(0 == ~E_6~0); 149875#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 149869#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 149862#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 149854#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 149848#L472-33 assume !(1 == ~m_pc~0); 149842#L472-35 is_master_triggered_~__retres1~0#1 := 0; 149836#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 149830#L484-11 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 149814#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 149807#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 143538#L491-33 assume !(1 == ~t1_pc~0); 143536#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 143533#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 143531#L503-11 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 143529#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 143527#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 143525#L510-33 assume !(1 == ~t2_pc~0); 143522#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 143519#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 143517#L522-11 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 143515#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 143513#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 143511#L529-33 assume !(1 == ~t3_pc~0); 143259#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 143507#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 143505#L541-11 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 143503#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 143501#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 143499#L548-33 assume 1 == ~t4_pc~0; 143496#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 143493#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 143491#L560-11 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 143489#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 143487#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 143485#L567-33 assume !(1 == ~t5_pc~0); 143483#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 143481#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 143479#L579-11 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 143477#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 143475#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 143473#L586-33 assume 1 == ~t6_pc~0; 143470#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 143468#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 143466#L598-11 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 143464#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 143462#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 143460#L605-33 assume 1 == ~t7_pc~0; 143458#L606-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 143455#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 143453#L617-11 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 143451#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 143449#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 143447#L624-33 assume 1 == ~t8_pc~0; 143444#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 143442#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 143441#L636-11 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 143440#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 143439#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 143438#L643-33 assume !(1 == ~t9_pc~0); 143436#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 143435#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 143434#L655-11 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 143433#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 143432#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 143431#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 141488#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 143429#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 143427#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 143425#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 141479#L1079-3 assume !(1 == ~T5_E~0); 143422#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 143420#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 143417#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 143415#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 143413#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 143411#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 143409#L1114-3 assume !(1 == ~E_2~0); 143407#L1119-3 assume !(1 == ~E_3~0); 143404#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 143401#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 143399#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 143397#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 143395#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 143393#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 143391#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 143384#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 143374#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 143372#L781-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 143370#L1459 assume !(0 == start_simulation_~tmp~3#1); 143367#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 143361#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 143350#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 143348#L781-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 143346#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 143344#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 143342#L1422 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 143340#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 130107#L1440-2 [2022-10-17 10:24:36,049 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:24:36,050 INFO L85 PathProgramCache]: Analyzing trace with hash 367589383, now seen corresponding path program 1 times [2022-10-17 10:24:36,050 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:24:36,050 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [925825927] [2022-10-17 10:24:36,050 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:24:36,051 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:24:36,073 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:24:36,155 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:24:36,156 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:24:36,156 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [925825927] [2022-10-17 10:24:36,156 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [925825927] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:24:36,156 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:24:36,157 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:24:36,157 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [113681722] [2022-10-17 10:24:36,157 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:24:36,158 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:24:36,158 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:24:36,158 INFO L85 PathProgramCache]: Analyzing trace with hash 168254792, now seen corresponding path program 1 times [2022-10-17 10:24:36,159 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:24:36,159 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1444687614] [2022-10-17 10:24:36,159 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:24:36,159 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:24:36,178 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:24:36,226 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:24:36,227 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:24:36,227 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1444687614] [2022-10-17 10:24:36,227 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1444687614] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:24:36,228 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:24:36,228 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:24:36,228 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [320682252] [2022-10-17 10:24:36,228 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:24:36,229 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:24:36,229 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:24:36,229 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-10-17 10:24:36,230 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-10-17 10:24:36,230 INFO L87 Difference]: Start difference. First operand 26831 states and 38091 transitions. cyclomatic complexity: 11268 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:24:37,100 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:24:37,101 INFO L93 Difference]: Finished difference Result 64082 states and 90300 transitions. [2022-10-17 10:24:37,101 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 64082 states and 90300 transitions. [2022-10-17 10:24:37,691 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 62636 [2022-10-17 10:24:38,109 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 64082 states to 64082 states and 90300 transitions. [2022-10-17 10:24:38,109 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 64082 [2022-10-17 10:24:38,145 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 64082 [2022-10-17 10:24:38,145 INFO L73 IsDeterministic]: Start isDeterministic. Operand 64082 states and 90300 transitions. [2022-10-17 10:24:38,215 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:24:38,215 INFO L218 hiAutomatonCegarLoop]: Abstraction has 64082 states and 90300 transitions. [2022-10-17 10:24:38,278 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 64082 states and 90300 transitions. [2022-10-17 10:24:39,241 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 64082 to 50910. [2022-10-17 10:24:39,320 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 50910 states, 50910 states have (on average 1.41441759968572) internal successors, (72008), 50909 states have internal predecessors, (72008), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:24:39,511 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50910 states to 50910 states and 72008 transitions. [2022-10-17 10:24:39,512 INFO L240 hiAutomatonCegarLoop]: Abstraction has 50910 states and 72008 transitions. [2022-10-17 10:24:39,512 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-10-17 10:24:39,513 INFO L428 stractBuchiCegarLoop]: Abstraction has 50910 states and 72008 transitions. [2022-10-17 10:24:39,513 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-10-17 10:24:39,513 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 50910 states and 72008 transitions. [2022-10-17 10:24:39,987 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 50672 [2022-10-17 10:24:40,000 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:24:40,001 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:24:40,009 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:24:40,010 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:24:40,010 INFO L748 eck$LassoCheckResult]: Stem: 221746#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 221747#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 222113#L1403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 221770#L663 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 221661#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 221384#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 221385#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 221979#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 222043#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 222029#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 222030#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 221505#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 221494#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 221495#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 221302#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 221303#L951 assume !(0 == ~M_E~0); 221031#L951-2 assume !(0 == ~T1_E~0); 221032#L956-1 assume !(0 == ~T2_E~0); 221200#L961-1 assume !(0 == ~T3_E~0); 221678#L966-1 assume !(0 == ~T4_E~0); 221679#L971-1 assume !(0 == ~T5_E~0); 221830#L976-1 assume !(0 == ~T6_E~0); 221799#L981-1 assume !(0 == ~T7_E~0); 221543#L986-1 assume !(0 == ~T8_E~0); 221254#L991-1 assume !(0 == ~T9_E~0); 221255#L996-1 assume !(0 == ~E_M~0); 222089#L1001-1 assume !(0 == ~E_1~0); 221744#L1006-1 assume !(0 == ~E_2~0); 221745#L1011-1 assume !(0 == ~E_3~0); 222044#L1016-1 assume !(0 == ~E_4~0); 222069#L1021-1 assume !(0 == ~E_5~0); 220843#L1026-1 assume !(0 == ~E_6~0); 220844#L1031-1 assume !(0 == ~E_7~0); 221690#L1036-1 assume !(0 == ~E_8~0); 221686#L1041-1 assume !(0 == ~E_9~0); 221687#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 221995#L472 assume !(1 == ~m_pc~0); 221938#L472-2 is_master_triggered_~__retres1~0#1 := 0; 221721#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 221722#L484 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 221731#L1179 assume !(0 != activate_threads_~tmp~1#1); 220851#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 220852#L491 assume !(1 == ~t1_pc~0); 221353#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 221354#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 221684#L503 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 220822#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 220823#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 220845#L510 assume !(1 == ~t2_pc~0); 220811#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 220812#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 221997#L522 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 221998#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 221087#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 221088#L529 assume !(1 == ~t3_pc~0); 221548#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 221856#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 221932#L541 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 222080#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 221008#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 221009#L548 assume !(1 == ~t4_pc~0); 220908#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 220907#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 221208#L560 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 220948#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 220949#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 220896#L567 assume !(1 == ~t5_pc~0); 220897#L567-2 is_transmit5_triggered_~__retres1~5#1 := 0; 220950#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 221136#L579 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 221137#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 221973#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 221019#L586 assume !(1 == ~t6_pc~0); 221020#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 221093#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 222109#L598 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 222159#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 221966#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 221967#L605 assume !(1 == ~t7_pc~0); 221519#L605-2 is_transmit7_triggered_~__retres1~7#1 := 0; 221520#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 221682#L617 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 221683#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 222134#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 221655#L624 assume !(1 == ~t8_pc~0); 221081#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 221080#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 221715#L636 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 221716#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 221942#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 220865#L643 assume 1 == ~t9_pc~0; 220866#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 221881#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 221801#L655 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 221259#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 221260#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 221063#L1059 assume 1 == ~M_E~0;~M_E~0 := 2; 221064#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 221229#L1064-1 assume !(1 == ~T2_E~0); 221230#L1069-1 assume !(1 == ~T3_E~0); 222130#L1074-1 assume !(1 == ~T4_E~0); 222131#L1079-1 assume !(1 == ~T5_E~0); 221927#L1084-1 assume !(1 == ~T6_E~0); 221928#L1089-1 assume !(1 == ~T7_E~0); 221959#L1094-1 assume !(1 == ~T8_E~0); 221960#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 222060#L1104-1 assume !(1 == ~E_M~0); 222061#L1109-1 assume !(1 == ~E_1~0); 221372#L1114-1 assume !(1 == ~E_2~0); 221373#L1119-1 assume !(1 == ~E_3~0); 221436#L1124-1 assume !(1 == ~E_4~0); 221437#L1129-1 assume !(1 == ~E_5~0); 221666#L1134-1 assume !(1 == ~E_6~0); 221667#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 221393#L1144-1 assume !(1 == ~E_8~0); 221394#L1149-1 assume !(1 == ~E_9~0); 221025#L1154-1 assume { :end_inline_reset_delta_events } true; 221026#L1440-2 [2022-10-17 10:24:40,011 INFO L750 eck$LassoCheckResult]: Loop: 221026#L1440-2 assume !false; 221159#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 220803#L926 assume !false; 221440#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 221441#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 221113#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 221114#L781 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 221123#L795 assume !(0 != eval_~tmp~0#1); 221124#L941 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 269488#L663-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 269486#L951-3 assume !(0 == ~M_E~0); 269483#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 269481#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 269479#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 269477#L966-3 assume !(0 == ~T4_E~0); 269475#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 269473#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 269472#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 269470#L986-3 assume !(0 == ~T8_E~0); 269468#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 269466#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 269464#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 269462#L1006-3 assume !(0 == ~E_2~0); 269459#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 269457#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 269455#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 269453#L1026-3 assume !(0 == ~E_6~0); 269451#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 269449#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 269446#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 269444#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 269442#L472-33 assume !(1 == ~m_pc~0); 269440#L472-35 is_master_triggered_~__retres1~0#1 := 0; 269439#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 269438#L484-11 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 269437#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 269435#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 269433#L491-33 assume !(1 == ~t1_pc~0); 266023#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 269430#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 269428#L503-11 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 269426#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 269424#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 269422#L510-33 assume !(1 == ~t2_pc~0); 269411#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 269410#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 269409#L522-11 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 269371#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 269242#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 221118#L529-33 assume !(1 == ~t3_pc~0); 221119#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 221100#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 221101#L541-11 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 222074#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 220930#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 220931#L548-33 assume !(1 == ~t4_pc~0); 221175#L548-35 is_transmit4_triggered_~__retres1~4#1 := 0; 221304#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 221343#L560-11 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 221344#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 221111#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 221112#L567-33 assume !(1 == ~t5_pc~0); 221221#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 221222#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 221470#L579-11 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 222079#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 222118#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 221677#L586-33 assume !(1 == ~t6_pc~0); 221239#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 221240#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 221589#L598-11 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 221590#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 222152#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 221312#L605-33 assume !(1 == ~t7_pc~0); 221313#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 221051#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 221052#L617-11 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 221475#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 220942#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 220943#L624-33 assume !(1 == ~t8_pc~0); 221097#L624-35 is_transmit8_triggered_~__retres1~8#1 := 0; 221105#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 221075#L636-11 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 221076#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 221328#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 221053#L643-33 assume !(1 == ~t9_pc~0); 221055#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 221144#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 221627#L655-11 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 221571#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 221572#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 220932#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 220933#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 221452#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 221503#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 221504#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 221800#L1079-3 assume !(1 == ~T5_E~0); 221693#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 221625#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 221626#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 221534#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 221535#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 221823#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 221806#L1114-3 assume !(1 == ~E_2~0); 221807#L1119-3 assume !(1 == ~E_3~0); 222119#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 222127#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 221237#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 221238#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 221411#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 221412#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 221577#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 222138#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 220937#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 220824#L781-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 220825#L1459 assume !(0 == start_simulation_~tmp~3#1); 220831#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 221901#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 221116#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 221701#L781-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 221283#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 221284#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 221456#L1422 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 221651#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 221026#L1440-2 [2022-10-17 10:24:40,012 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:24:40,012 INFO L85 PathProgramCache]: Analyzing trace with hash -589339000, now seen corresponding path program 1 times [2022-10-17 10:24:40,012 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:24:40,028 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [139606563] [2022-10-17 10:24:40,029 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:24:40,029 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:24:40,055 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:24:40,145 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:24:40,146 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:24:40,146 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [139606563] [2022-10-17 10:24:40,146 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [139606563] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:24:40,146 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:24:40,147 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:24:40,147 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [254988788] [2022-10-17 10:24:40,147 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:24:40,148 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:24:40,148 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:24:40,148 INFO L85 PathProgramCache]: Analyzing trace with hash -1428167924, now seen corresponding path program 1 times [2022-10-17 10:24:40,149 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:24:40,149 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [604734685] [2022-10-17 10:24:40,149 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:24:40,149 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:24:40,167 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:24:40,212 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:24:40,212 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:24:40,213 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [604734685] [2022-10-17 10:24:40,213 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [604734685] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:24:40,213 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:24:40,213 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:24:40,213 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1401803734] [2022-10-17 10:24:40,214 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:24:40,214 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:24:40,214 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:24:40,215 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-10-17 10:24:40,215 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-10-17 10:24:40,215 INFO L87 Difference]: Start difference. First operand 50910 states and 72008 transitions. cyclomatic complexity: 21106 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:24:41,300 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:24:41,300 INFO L93 Difference]: Finished difference Result 120701 states and 169509 transitions. [2022-10-17 10:24:41,300 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 120701 states and 169509 transitions. [2022-10-17 10:24:42,293 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 117968 [2022-10-17 10:24:42,989 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 120701 states to 120701 states and 169509 transitions. [2022-10-17 10:24:42,990 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 120701 [2022-10-17 10:24:43,072 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 120701 [2022-10-17 10:24:43,072 INFO L73 IsDeterministic]: Start isDeterministic. Operand 120701 states and 169509 transitions. [2022-10-17 10:24:43,194 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:24:43,195 INFO L218 hiAutomatonCegarLoop]: Abstraction has 120701 states and 169509 transitions. [2022-10-17 10:24:43,303 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 120701 states and 169509 transitions. [2022-10-17 10:24:44,657 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 120701 to 96525. [2022-10-17 10:24:44,751 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 96525 states, 96525 states have (on average 1.40984200984201) internal successors, (136085), 96524 states have internal predecessors, (136085), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:24:44,996 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 96525 states to 96525 states and 136085 transitions. [2022-10-17 10:24:44,996 INFO L240 hiAutomatonCegarLoop]: Abstraction has 96525 states and 136085 transitions. [2022-10-17 10:24:44,996 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-10-17 10:24:44,998 INFO L428 stractBuchiCegarLoop]: Abstraction has 96525 states and 136085 transitions. [2022-10-17 10:24:44,998 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2022-10-17 10:24:44,998 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 96525 states and 136085 transitions. [2022-10-17 10:24:45,265 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 96192 [2022-10-17 10:24:45,266 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:24:45,266 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:24:45,271 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:24:45,271 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:24:45,272 INFO L748 eck$LassoCheckResult]: Stem: 393374#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 393375#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 393757#L1403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 393400#L663 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 393284#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 393003#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 393004#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 393615#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 393680#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 393665#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 393666#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 393126#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 393113#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 393114#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 392921#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 392922#L951 assume !(0 == ~M_E~0); 392652#L951-2 assume !(0 == ~T1_E~0); 392653#L956-1 assume !(0 == ~T2_E~0); 392818#L961-1 assume !(0 == ~T3_E~0); 393303#L966-1 assume !(0 == ~T4_E~0); 393304#L971-1 assume !(0 == ~T5_E~0); 393458#L976-1 assume !(0 == ~T6_E~0); 393429#L981-1 assume !(0 == ~T7_E~0); 393167#L986-1 assume !(0 == ~T8_E~0); 392871#L991-1 assume !(0 == ~T9_E~0); 392872#L996-1 assume !(0 == ~E_M~0); 393727#L1001-1 assume !(0 == ~E_1~0); 393372#L1006-1 assume !(0 == ~E_2~0); 393373#L1011-1 assume !(0 == ~E_3~0); 393681#L1016-1 assume !(0 == ~E_4~0); 393706#L1021-1 assume !(0 == ~E_5~0); 392465#L1026-1 assume !(0 == ~E_6~0); 392466#L1031-1 assume !(0 == ~E_7~0); 393318#L1036-1 assume !(0 == ~E_8~0); 393314#L1041-1 assume !(0 == ~E_9~0); 393315#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 393628#L472 assume !(1 == ~m_pc~0); 393567#L472-2 is_master_triggered_~__retres1~0#1 := 0; 393351#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 393352#L484 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 393361#L1179 assume !(0 != activate_threads_~tmp~1#1); 392473#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 392474#L491 assume !(1 == ~t1_pc~0); 392972#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 392973#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 393312#L503 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 392443#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 392444#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 392467#L510 assume !(1 == ~t2_pc~0); 392432#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 392433#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 393630#L522 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 393631#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 392707#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 392708#L529 assume !(1 == ~t3_pc~0); 393172#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 393486#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 393563#L541 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 393718#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 392629#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 392630#L548 assume !(1 == ~t4_pc~0); 392529#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 392528#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 392826#L560 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 392569#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 392570#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 392517#L567 assume !(1 == ~t5_pc~0); 392518#L567-2 is_transmit5_triggered_~__retres1~5#1 := 0; 392571#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 392754#L579 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 392755#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 393609#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 392640#L586 assume !(1 == ~t6_pc~0); 392641#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 392713#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 393748#L598 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 393809#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 393600#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 393601#L605 assume !(1 == ~t7_pc~0); 393141#L605-2 is_transmit7_triggered_~__retres1~7#1 := 0; 393142#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 393307#L617 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 393308#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 393780#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 393279#L624 assume !(1 == ~t8_pc~0); 392701#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 392700#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 393344#L636 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 393345#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 393572#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 392487#L643 assume !(1 == ~t9_pc~0); 392488#L643-2 is_transmit9_triggered_~__retres1~9#1 := 0; 393512#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 393431#L655 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 392876#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 392877#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 392683#L1059 assume 1 == ~M_E~0;~M_E~0 := 2; 392684#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 392847#L1064-1 assume !(1 == ~T2_E~0); 392848#L1069-1 assume !(1 == ~T3_E~0); 393775#L1074-1 assume !(1 == ~T4_E~0); 393776#L1079-1 assume !(1 == ~T5_E~0); 393557#L1084-1 assume !(1 == ~T6_E~0); 393558#L1089-1 assume !(1 == ~T7_E~0); 393591#L1094-1 assume !(1 == ~T8_E~0); 393592#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 393697#L1104-1 assume !(1 == ~E_M~0); 393698#L1109-1 assume !(1 == ~E_1~0); 392991#L1114-1 assume !(1 == ~E_2~0); 392992#L1119-1 assume !(1 == ~E_3~0); 393054#L1124-1 assume !(1 == ~E_4~0); 393055#L1129-1 assume !(1 == ~E_5~0); 393289#L1134-1 assume !(1 == ~E_6~0); 393290#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 393011#L1144-1 assume !(1 == ~E_8~0); 393012#L1149-1 assume !(1 == ~E_9~0); 392646#L1154-1 assume { :end_inline_reset_delta_events } true; 392647#L1440-2 [2022-10-17 10:24:45,273 INFO L750 eck$LassoCheckResult]: Loop: 392647#L1440-2 assume !false; 479463#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 479458#L926 assume !false; 479456#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 479410#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 479397#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 479393#L781 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 479387#L795 assume !(0 != eval_~tmp~0#1); 479388#L941 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 486527#L663-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 486525#L951-3 assume !(0 == ~M_E~0); 486523#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 486521#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 486519#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 486517#L966-3 assume !(0 == ~T4_E~0); 486514#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 486512#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 486510#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 486508#L986-3 assume !(0 == ~T8_E~0); 486506#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 486504#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 486502#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 486500#L1006-3 assume !(0 == ~E_2~0); 486498#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 486496#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 486494#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 486492#L1026-3 assume !(0 == ~E_6~0); 486434#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 486388#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 486382#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 486377#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 486283#L472-33 assume !(1 == ~m_pc~0); 486280#L472-35 is_master_triggered_~__retres1~0#1 := 0; 486277#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 486276#L484-11 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 486271#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 486270#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 393765#L491-33 assume !(1 == ~t1_pc~0); 393766#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 486453#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 486451#L503-11 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 486449#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 486448#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 486445#L510-33 assume !(1 == ~t2_pc~0); 486442#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 486440#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 486438#L522-11 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 486436#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 486435#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 480225#L529-33 assume !(1 == ~t3_pc~0); 480222#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 480219#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 480216#L541-11 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 480213#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 480211#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 480209#L548-33 assume !(1 == ~t4_pc~0); 480206#L548-35 is_transmit4_triggered_~__retres1~4#1 := 0; 480202#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 480199#L560-11 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 480196#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 480192#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 480189#L567-33 assume !(1 == ~t5_pc~0); 480186#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 480183#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 480181#L579-11 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 480179#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 480177#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 480175#L586-33 assume !(1 == ~t6_pc~0); 480173#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 480170#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 480168#L598-11 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 480165#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 480163#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 480161#L605-33 assume !(1 == ~t7_pc~0); 478160#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 480158#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 480156#L617-11 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 480155#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 480153#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 480151#L624-33 assume !(1 == ~t8_pc~0); 480149#L624-35 is_transmit8_triggered_~__retres1~8#1 := 0; 480147#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 480146#L636-11 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 480144#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 480142#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 480140#L643-33 assume !(1 == ~t9_pc~0); 429713#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 480137#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 480133#L655-11 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 480128#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 480123#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 480119#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 468772#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 480112#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 480108#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 480101#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 468752#L1079-3 assume !(1 == ~T5_E~0); 480092#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 480087#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 480082#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 480077#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 480072#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 480065#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 480061#L1114-3 assume !(1 == ~E_2~0); 480057#L1119-3 assume !(1 == ~E_3~0); 480052#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 480047#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 480042#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 480037#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 480033#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 480029#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 480027#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 479911#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 479898#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 479892#L781-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 479886#L1459 assume !(0 == start_simulation_~tmp~3#1); 479880#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 479487#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 479477#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 479475#L781-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 479473#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 479471#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 479468#L1422 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 479466#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 392647#L1440-2 [2022-10-17 10:24:45,273 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:24:45,274 INFO L85 PathProgramCache]: Analyzing trace with hash 2033110665, now seen corresponding path program 1 times [2022-10-17 10:24:45,274 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:24:45,274 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [658175549] [2022-10-17 10:24:45,274 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:24:45,275 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:24:45,294 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:24:45,353 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:24:45,353 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:24:45,353 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [658175549] [2022-10-17 10:24:45,354 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [658175549] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:24:45,354 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:24:45,354 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-10-17 10:24:45,354 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1614545710] [2022-10-17 10:24:45,354 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:24:45,355 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:24:45,355 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:24:45,355 INFO L85 PathProgramCache]: Analyzing trace with hash -1428167924, now seen corresponding path program 2 times [2022-10-17 10:24:45,356 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:24:45,356 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2138607426] [2022-10-17 10:24:45,356 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:24:45,356 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:24:45,372 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:24:45,962 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:24:45,962 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:24:45,963 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2138607426] [2022-10-17 10:24:45,963 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2138607426] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:24:45,963 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:24:45,963 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:24:45,964 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1916159575] [2022-10-17 10:24:45,964 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:24:45,965 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:24:45,965 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:24:45,966 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:24:45,966 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:24:45,966 INFO L87 Difference]: Start difference. First operand 96525 states and 136085 transitions. cyclomatic complexity: 39568 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:24:46,691 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:24:46,691 INFO L93 Difference]: Finished difference Result 143145 states and 202124 transitions. [2022-10-17 10:24:46,692 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 143145 states and 202124 transitions. [2022-10-17 10:24:48,090 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 142720