./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.07.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version dbf71c69 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6458d27-bfd4-4e1c-9152-86f12a566835/bin/uautomizer-J5u9QxTXDZ/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6458d27-bfd4-4e1c-9152-86f12a566835/bin/uautomizer-J5u9QxTXDZ/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6458d27-bfd4-4e1c-9152-86f12a566835/bin/uautomizer-J5u9QxTXDZ/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6458d27-bfd4-4e1c-9152-86f12a566835/bin/uautomizer-J5u9QxTXDZ/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.07.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6458d27-bfd4-4e1c-9152-86f12a566835/bin/uautomizer-J5u9QxTXDZ/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6458d27-bfd4-4e1c-9152-86f12a566835/bin/uautomizer-J5u9QxTXDZ --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 022987cd4c8c671e376c5c3e5a08e2f1b98444b4d5d48bc73787bff74aa0de0f --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-dbf71c6-m [2022-10-17 10:15:55,725 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-10-17 10:15:55,727 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-10-17 10:15:55,768 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-10-17 10:15:55,769 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-10-17 10:15:55,774 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-10-17 10:15:55,777 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-10-17 10:15:55,784 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-10-17 10:15:55,786 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-10-17 10:15:55,794 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-10-17 10:15:55,795 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-10-17 10:15:55,796 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-10-17 10:15:55,797 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-10-17 10:15:55,798 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-10-17 10:15:55,799 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-10-17 10:15:55,801 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-10-17 10:15:55,802 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-10-17 10:15:55,803 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-10-17 10:15:55,805 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-10-17 10:15:55,812 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-10-17 10:15:55,815 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-10-17 10:15:55,821 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-10-17 10:15:55,826 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-10-17 10:15:55,827 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-10-17 10:15:55,837 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-10-17 10:15:55,837 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-10-17 10:15:55,838 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-10-17 10:15:55,840 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-10-17 10:15:55,840 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-10-17 10:15:55,841 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-10-17 10:15:55,842 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-10-17 10:15:55,844 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-10-17 10:15:55,846 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-10-17 10:15:55,847 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-10-17 10:15:55,848 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-10-17 10:15:55,849 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-10-17 10:15:55,849 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-10-17 10:15:55,849 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-10-17 10:15:55,850 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-10-17 10:15:55,851 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-10-17 10:15:55,851 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-10-17 10:15:55,852 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6458d27-bfd4-4e1c-9152-86f12a566835/bin/uautomizer-J5u9QxTXDZ/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-10-17 10:15:55,893 INFO L113 SettingsManager]: Loading preferences was successful [2022-10-17 10:15:55,893 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-10-17 10:15:55,893 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-10-17 10:15:55,893 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-10-17 10:15:55,894 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-10-17 10:15:55,895 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-10-17 10:15:55,895 INFO L138 SettingsManager]: * Use SBE=true [2022-10-17 10:15:55,895 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-10-17 10:15:55,895 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-10-17 10:15:55,895 INFO L138 SettingsManager]: * Use old map elimination=false [2022-10-17 10:15:55,896 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-10-17 10:15:55,896 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-10-17 10:15:55,896 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-10-17 10:15:55,896 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-10-17 10:15:55,896 INFO L138 SettingsManager]: * sizeof long=4 [2022-10-17 10:15:55,897 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-10-17 10:15:55,897 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-10-17 10:15:55,897 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-10-17 10:15:55,897 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-10-17 10:15:55,897 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-10-17 10:15:55,898 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-10-17 10:15:55,898 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-10-17 10:15:55,898 INFO L138 SettingsManager]: * sizeof long double=12 [2022-10-17 10:15:55,898 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-10-17 10:15:55,898 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-10-17 10:15:55,899 INFO L138 SettingsManager]: * Use constant arrays=true [2022-10-17 10:15:55,899 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-10-17 10:15:55,899 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-10-17 10:15:55,899 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-10-17 10:15:55,899 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-10-17 10:15:55,900 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-10-17 10:15:55,901 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-10-17 10:15:55,901 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6458d27-bfd4-4e1c-9152-86f12a566835/bin/uautomizer-J5u9QxTXDZ/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6458d27-bfd4-4e1c-9152-86f12a566835/bin/uautomizer-J5u9QxTXDZ Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 022987cd4c8c671e376c5c3e5a08e2f1b98444b4d5d48bc73787bff74aa0de0f [2022-10-17 10:15:56,199 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-10-17 10:15:56,240 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-10-17 10:15:56,242 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-10-17 10:15:56,243 INFO L271 PluginConnector]: Initializing CDTParser... [2022-10-17 10:15:56,244 INFO L275 PluginConnector]: CDTParser initialized [2022-10-17 10:15:56,245 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6458d27-bfd4-4e1c-9152-86f12a566835/bin/uautomizer-J5u9QxTXDZ/../../sv-benchmarks/c/systemc/transmitter.07.cil.c [2022-10-17 10:15:56,318 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6458d27-bfd4-4e1c-9152-86f12a566835/bin/uautomizer-J5u9QxTXDZ/data/35e282745/24620c444c8f436da2360445abc8009d/FLAGc0f16decf [2022-10-17 10:15:56,834 INFO L306 CDTParser]: Found 1 translation units. [2022-10-17 10:15:56,839 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6458d27-bfd4-4e1c-9152-86f12a566835/sv-benchmarks/c/systemc/transmitter.07.cil.c [2022-10-17 10:15:56,859 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6458d27-bfd4-4e1c-9152-86f12a566835/bin/uautomizer-J5u9QxTXDZ/data/35e282745/24620c444c8f436da2360445abc8009d/FLAGc0f16decf [2022-10-17 10:15:57,140 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6458d27-bfd4-4e1c-9152-86f12a566835/bin/uautomizer-J5u9QxTXDZ/data/35e282745/24620c444c8f436da2360445abc8009d [2022-10-17 10:15:57,145 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-10-17 10:15:57,146 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-10-17 10:15:57,149 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-10-17 10:15:57,149 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-10-17 10:15:57,152 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-10-17 10:15:57,153 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.10 10:15:57" (1/1) ... [2022-10-17 10:15:57,154 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@71f0d992 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:15:57, skipping insertion in model container [2022-10-17 10:15:57,155 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.10 10:15:57" (1/1) ... [2022-10-17 10:15:57,162 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-10-17 10:15:57,199 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-10-17 10:15:57,400 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6458d27-bfd4-4e1c-9152-86f12a566835/sv-benchmarks/c/systemc/transmitter.07.cil.c[706,719] [2022-10-17 10:15:57,563 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-10-17 10:15:57,573 INFO L203 MainTranslator]: Completed pre-run [2022-10-17 10:15:57,585 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6458d27-bfd4-4e1c-9152-86f12a566835/sv-benchmarks/c/systemc/transmitter.07.cil.c[706,719] [2022-10-17 10:15:57,629 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-10-17 10:15:57,648 INFO L208 MainTranslator]: Completed translation [2022-10-17 10:15:57,648 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:15:57 WrapperNode [2022-10-17 10:15:57,648 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-10-17 10:15:57,650 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-10-17 10:15:57,650 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-10-17 10:15:57,650 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-10-17 10:15:57,657 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:15:57" (1/1) ... [2022-10-17 10:15:57,669 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:15:57" (1/1) ... [2022-10-17 10:15:57,781 INFO L138 Inliner]: procedures = 42, calls = 51, calls flagged for inlining = 46, calls inlined = 124, statements flattened = 1845 [2022-10-17 10:15:57,781 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-10-17 10:15:57,782 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-10-17 10:15:57,782 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-10-17 10:15:57,782 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-10-17 10:15:57,798 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:15:57" (1/1) ... [2022-10-17 10:15:57,799 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:15:57" (1/1) ... [2022-10-17 10:15:57,808 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:15:57" (1/1) ... [2022-10-17 10:15:57,808 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:15:57" (1/1) ... [2022-10-17 10:15:57,834 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:15:57" (1/1) ... [2022-10-17 10:15:57,875 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:15:57" (1/1) ... [2022-10-17 10:15:57,884 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:15:57" (1/1) ... [2022-10-17 10:15:57,893 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:15:57" (1/1) ... [2022-10-17 10:15:57,900 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-10-17 10:15:57,902 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-10-17 10:15:57,902 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-10-17 10:15:57,902 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-10-17 10:15:57,903 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:15:57" (1/1) ... [2022-10-17 10:15:57,908 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:15:57,919 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6458d27-bfd4-4e1c-9152-86f12a566835/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:15:57,932 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6458d27-bfd4-4e1c-9152-86f12a566835/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:15:57,951 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6458d27-bfd4-4e1c-9152-86f12a566835/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-10-17 10:15:57,984 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-10-17 10:15:57,984 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-10-17 10:15:57,984 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-10-17 10:15:57,984 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-10-17 10:15:58,086 INFO L235 CfgBuilder]: Building ICFG [2022-10-17 10:15:58,088 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-10-17 10:15:59,614 INFO L276 CfgBuilder]: Performing block encoding [2022-10-17 10:15:59,629 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-10-17 10:15:59,629 INFO L300 CfgBuilder]: Removed 11 assume(true) statements. [2022-10-17 10:15:59,633 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 17.10 10:15:59 BoogieIcfgContainer [2022-10-17 10:15:59,633 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-10-17 10:15:59,634 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-10-17 10:15:59,634 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-10-17 10:15:59,638 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-10-17 10:15:59,639 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-10-17 10:15:59,639 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 17.10 10:15:57" (1/3) ... [2022-10-17 10:15:59,640 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@401bdfcc and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.10 10:15:59, skipping insertion in model container [2022-10-17 10:15:59,640 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-10-17 10:15:59,640 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:15:57" (2/3) ... [2022-10-17 10:15:59,641 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@401bdfcc and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.10 10:15:59, skipping insertion in model container [2022-10-17 10:15:59,641 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-10-17 10:15:59,641 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 17.10 10:15:59" (3/3) ... [2022-10-17 10:15:59,642 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.07.cil.c [2022-10-17 10:15:59,716 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-10-17 10:15:59,716 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-10-17 10:15:59,716 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-10-17 10:15:59,716 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-10-17 10:15:59,717 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-10-17 10:15:59,717 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-10-17 10:15:59,717 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-10-17 10:15:59,717 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-10-17 10:15:59,726 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 775 states, 774 states have (on average 1.5232558139534884) internal successors, (1179), 774 states have internal predecessors, (1179), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:15:59,794 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 670 [2022-10-17 10:15:59,795 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:15:59,795 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:15:59,818 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:15:59,820 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:15:59,821 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-10-17 10:15:59,823 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 775 states, 774 states have (on average 1.5232558139534884) internal successors, (1179), 774 states have internal predecessors, (1179), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:15:59,840 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 670 [2022-10-17 10:15:59,841 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:15:59,841 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:15:59,846 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:15:59,846 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:15:59,857 INFO L748 eck$LassoCheckResult]: Stem: 385#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 710#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 716#L1111true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 452#L514true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 640#L521true assume !(1 == ~m_i~0);~m_st~0 := 2; 605#L521-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 634#L526-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 191#L531-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 551#L536-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 237#L541-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 141#L546-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 598#L551-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 124#L556-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 682#L754true assume !(0 == ~M_E~0); 727#L754-2true assume !(0 == ~T1_E~0); 511#L759-1true assume !(0 == ~T2_E~0); 379#L764-1true assume !(0 == ~T3_E~0); 341#L769-1true assume !(0 == ~T4_E~0); 380#L774-1true assume !(0 == ~T5_E~0); 624#L779-1true assume 0 == ~T6_E~0;~T6_E~0 := 1; 523#L784-1true assume !(0 == ~T7_E~0); 339#L789-1true assume !(0 == ~E_1~0); 423#L794-1true assume !(0 == ~E_2~0); 754#L799-1true assume !(0 == ~E_3~0); 348#L804-1true assume !(0 == ~E_4~0); 376#L809-1true assume !(0 == ~E_5~0); 552#L814-1true assume !(0 == ~E_6~0); 10#L819-1true assume 0 == ~E_7~0;~E_7~0 := 1; 169#L824-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 140#L361true assume 1 == ~m_pc~0; 665#L362true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 707#L372true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 76#L373true activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 623#L930true assume !(0 != activate_threads_~tmp~1#1); 268#L930-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 136#L380true assume !(1 == ~t1_pc~0); 755#L380-2true is_transmit1_triggered_~__retres1~1#1 := 0; 635#L391true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 324#L392true activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 759#L938true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 461#L938-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 439#L399true assume 1 == ~t2_pc~0; 627#L400true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 644#L410true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 343#L411true activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 173#L946true assume !(0 != activate_threads_~tmp___1~0#1); 415#L946-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14#L418true assume !(1 == ~t3_pc~0); 691#L418-2true is_transmit3_triggered_~__retres1~3#1 := 0; 554#L429true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 695#L430true activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 767#L954true assume !(0 != activate_threads_~tmp___2~0#1); 363#L954-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 684#L437true assume 1 == ~t4_pc~0; 746#L438true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 494#L448true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 440#L449true activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 203#L962true assume !(0 != activate_threads_~tmp___3~0#1); 590#L962-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 477#L456true assume !(1 == ~t5_pc~0); 332#L456-2true is_transmit5_triggered_~__retres1~5#1 := 0; 672#L467true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 273#L468true activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 411#L970true assume !(0 != activate_threads_~tmp___4~0#1); 725#L970-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 43#L475true assume 1 == ~t6_pc~0; 220#L476true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 62#L486true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 693#L487true activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 402#L978true assume !(0 != activate_threads_~tmp___5~0#1); 354#L978-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 550#L494true assume 1 == ~t7_pc~0; 300#L495true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 314#L505true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 264#L506true activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 382#L986true assume !(0 != activate_threads_~tmp___6~0#1); 751#L986-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 658#L837true assume !(1 == ~M_E~0); 570#L837-2true assume !(1 == ~T1_E~0); 434#L842-1true assume !(1 == ~T2_E~0); 211#L847-1true assume !(1 == ~T3_E~0); 261#L852-1true assume !(1 == ~T4_E~0); 771#L857-1true assume 1 == ~T5_E~0;~T5_E~0 := 2; 178#L862-1true assume !(1 == ~T6_E~0); 187#L867-1true assume !(1 == ~T7_E~0); 236#L872-1true assume !(1 == ~E_1~0); 393#L877-1true assume !(1 == ~E_2~0); 580#L882-1true assume !(1 == ~E_3~0); 702#L887-1true assume !(1 == ~E_4~0); 455#L892-1true assume !(1 == ~E_5~0); 650#L897-1true assume 1 == ~E_6~0;~E_6~0 := 2; 196#L902-1true assume !(1 == ~E_7~0); 476#L907-1true assume { :end_inline_reset_delta_events } true; 228#L1148-2true [2022-10-17 10:15:59,860 INFO L750 eck$LassoCheckResult]: Loop: 228#L1148-2true assume !false; 11#L1149true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 111#L729true assume !true; 213#L744true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 214#L514-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 150#L754-3true assume 0 == ~M_E~0;~M_E~0 := 1; 17#L754-5true assume !(0 == ~T1_E~0); 533#L759-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 223#L764-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 608#L769-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 364#L774-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 92#L779-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 15#L784-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 764#L789-3true assume 0 == ~E_1~0;~E_1~0 := 1; 12#L794-3true assume !(0 == ~E_2~0); 34#L799-3true assume 0 == ~E_3~0;~E_3~0 := 1; 153#L804-3true assume 0 == ~E_4~0;~E_4~0 := 1; 290#L809-3true assume 0 == ~E_5~0;~E_5~0 := 1; 33#L814-3true assume 0 == ~E_6~0;~E_6~0 := 1; 528#L819-3true assume 0 == ~E_7~0;~E_7~0 := 1; 486#L824-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 233#L361-24true assume !(1 == ~m_pc~0); 537#L361-26true is_master_triggered_~__retres1~0#1 := 0; 299#L372-8true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 405#L373-8true activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 555#L930-24true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 583#L930-26true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 346#L380-24true assume !(1 == ~t1_pc~0); 47#L380-26true is_transmit1_triggered_~__retres1~1#1 := 0; 617#L391-8true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 252#L392-8true activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 148#L938-24true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 441#L938-26true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 507#L399-24true assume !(1 == ~t2_pc~0); 156#L399-26true is_transmit2_triggered_~__retres1~2#1 := 0; 113#L410-8true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 48#L411-8true activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 260#L946-24true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 145#L946-26true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 615#L418-24true assume 1 == ~t3_pc~0; 553#L419-8true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 182#L429-8true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 146#L430-8true activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 94#L954-24true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 413#L954-26true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 559#L437-24true assume 1 == ~t4_pc~0; 490#L438-8true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 732#L448-8true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 456#L449-8true activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 85#L962-24true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 353#L962-26true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 636#L456-24true assume !(1 == ~t5_pc~0); 729#L456-26true is_transmit5_triggered_~__retres1~5#1 := 0; 303#L467-8true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 109#L468-8true activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 575#L970-24true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 270#L970-26true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 758#L475-24true assume !(1 == ~t6_pc~0); 585#L475-26true is_transmit6_triggered_~__retres1~6#1 := 0; 312#L486-8true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 669#L487-8true activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 349#L978-24true assume !(0 != activate_threads_~tmp___5~0#1); 6#L978-26true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 307#L494-24true assume !(1 == ~t7_pc~0); 183#L494-26true is_transmit7_triggered_~__retres1~7#1 := 0; 172#L505-8true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 531#L506-8true activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 143#L986-24true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 489#L986-26true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 518#L837-3true assume !(1 == ~M_E~0); 660#L837-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 266#L842-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 602#L847-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 408#L852-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 311#L857-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 738#L862-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 698#L867-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 244#L872-3true assume !(1 == ~E_1~0); 302#L877-3true assume 1 == ~E_2~0;~E_2~0 := 2; 720#L882-3true assume 1 == ~E_3~0;~E_3~0 := 2; 357#L887-3true assume 1 == ~E_4~0;~E_4~0 := 2; 105#L892-3true assume 1 == ~E_5~0;~E_5~0 := 2; 517#L897-3true assume 1 == ~E_6~0;~E_6~0 := 2; 762#L902-3true assume 1 == ~E_7~0;~E_7~0 := 2; 193#L907-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 582#L569-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 369#L611-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 381#L612-1true start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 678#L1167true assume !(0 == start_simulation_~tmp~3#1); 231#L1167-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 737#L569-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 254#L611-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 673#L612-2true stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 305#L1122true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 221#L1129true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7#L1130true start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 123#L1180true assume !(0 != start_simulation_~tmp___0~1#1); 228#L1148-2true [2022-10-17 10:15:59,866 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:15:59,867 INFO L85 PathProgramCache]: Analyzing trace with hash -171938705, now seen corresponding path program 1 times [2022-10-17 10:15:59,876 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:15:59,876 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1247060167] [2022-10-17 10:15:59,877 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:15:59,877 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:15:59,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:16:00,205 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:16:00,205 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:16:00,207 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1247060167] [2022-10-17 10:16:00,208 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1247060167] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:16:00,208 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:16:00,209 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:16:00,211 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1803172214] [2022-10-17 10:16:00,212 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:16:00,218 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:16:00,220 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:16:00,220 INFO L85 PathProgramCache]: Analyzing trace with hash -571863600, now seen corresponding path program 1 times [2022-10-17 10:16:00,220 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:16:00,221 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [134580728] [2022-10-17 10:16:00,222 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:16:00,222 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:16:00,255 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:16:00,323 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:16:00,324 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:16:00,324 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [134580728] [2022-10-17 10:16:00,325 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [134580728] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:16:00,325 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:16:00,325 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-10-17 10:16:00,326 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [211916373] [2022-10-17 10:16:00,326 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:16:00,328 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:16:00,329 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:16:00,379 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:16:00,380 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:16:00,384 INFO L87 Difference]: Start difference. First operand has 775 states, 774 states have (on average 1.5232558139534884) internal successors, (1179), 774 states have internal predecessors, (1179), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:16:00,475 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:16:00,476 INFO L93 Difference]: Finished difference Result 774 states and 1154 transitions. [2022-10-17 10:16:00,477 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 774 states and 1154 transitions. [2022-10-17 10:16:00,488 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 667 [2022-10-17 10:16:00,514 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 774 states to 768 states and 1148 transitions. [2022-10-17 10:16:00,515 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 768 [2022-10-17 10:16:00,518 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 768 [2022-10-17 10:16:00,519 INFO L73 IsDeterministic]: Start isDeterministic. Operand 768 states and 1148 transitions. [2022-10-17 10:16:00,530 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:16:00,530 INFO L218 hiAutomatonCegarLoop]: Abstraction has 768 states and 1148 transitions. [2022-10-17 10:16:00,553 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 768 states and 1148 transitions. [2022-10-17 10:16:00,605 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 768 to 768. [2022-10-17 10:16:00,608 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 768 states, 768 states have (on average 1.4947916666666667) internal successors, (1148), 767 states have internal predecessors, (1148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:16:00,612 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 768 states to 768 states and 1148 transitions. [2022-10-17 10:16:00,614 INFO L240 hiAutomatonCegarLoop]: Abstraction has 768 states and 1148 transitions. [2022-10-17 10:16:00,615 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:16:00,620 INFO L428 stractBuchiCegarLoop]: Abstraction has 768 states and 1148 transitions. [2022-10-17 10:16:00,620 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-10-17 10:16:00,621 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 768 states and 1148 transitions. [2022-10-17 10:16:00,627 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 667 [2022-10-17 10:16:00,628 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:16:00,628 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:16:00,632 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:16:00,632 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:16:00,633 INFO L748 eck$LassoCheckResult]: Stem: 2325#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 2304#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 2305#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1765#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1766#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 2182#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2183#L526-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 2151#L531-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2074#L536-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2075#L541-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2064#L546-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 2065#L551-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 2024#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2025#L754 assume !(0 == ~M_E~0); 2283#L754-2 assume !(0 == ~T1_E~0); 1967#L759-1 assume !(0 == ~T2_E~0); 1968#L764-1 assume !(0 == ~T3_E~0); 2312#L769-1 assume !(0 == ~T4_E~0); 2313#L774-1 assume !(0 == ~T5_E~0); 2213#L779-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1998#L784-1 assume !(0 == ~T7_E~0); 1999#L789-1 assume !(0 == ~E_1~0); 1678#L794-1 assume !(0 == ~E_2~0); 1679#L799-1 assume !(0 == ~E_3~0); 2314#L804-1 assume !(0 == ~E_4~0); 2315#L809-1 assume !(0 == ~E_5~0); 2078#L814-1 assume !(0 == ~E_6~0); 1594#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 1595#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2060#L361 assume 1 == ~m_pc~0; 2061#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2102#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1883#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1884#L930 assume !(0 != activate_threads_~tmp~1#1); 2208#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2054#L380 assume !(1 == ~t1_pc~0); 1728#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1727#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2233#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2308#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1804#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1729#L399 assume 1 == ~t2_pc~0; 1730#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1936#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2243#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2122#L946 assume !(0 != activate_threads_~tmp___1~0#1); 1634#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1602#L418 assume !(1 == ~t3_pc~0); 1563#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1564#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2082#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2290#L954 assume !(0 != activate_threads_~tmp___2~0#1); 2320#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2285#L437 assume 1 == ~t4_pc~0; 2286#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1904#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1732#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1733#L962 assume !(0 != activate_threads_~tmp___3~0#1); 2161#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1860#L456 assume !(1 == ~t5_pc~0); 1861#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1964#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2264#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1624#L970 assume !(0 != activate_threads_~tmp___4~0#1); 1625#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1748#L475 assume 1 == ~t6_pc~0; 1749#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1824#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1825#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1584#L978 assume !(0 != activate_threads_~tmp___5~0#1); 1585#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2067#L494 assume 1 == ~t7_pc~0; 2068#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2108#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2260#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2261#L986 assume !(0 != activate_threads_~tmp___6~0#1); 2323#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2262#L837 assume !(1 == ~M_E~0); 2125#L837-2 assume !(1 == ~T1_E~0); 1711#L842-1 assume !(1 == ~T2_E~0); 1712#L847-1 assume !(1 == ~T3_E~0); 2178#L852-1 assume !(1 == ~T4_E~0); 2255#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2134#L862-1 assume !(1 == ~T6_E~0); 2135#L867-1 assume !(1 == ~T7_E~0); 2144#L872-1 assume !(1 == ~E_1~0); 2210#L877-1 assume !(1 == ~E_2~0); 2140#L882-1 assume !(1 == ~E_3~0); 2141#L887-1 assume !(1 == ~E_4~0); 1771#L892-1 assume !(1 == ~E_5~0); 1772#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 2158#L902-1 assume !(1 == ~E_7~0); 1852#L907-1 assume { :end_inline_reset_delta_events } true; 1853#L1148-2 [2022-10-17 10:16:00,634 INFO L750 eck$LassoCheckResult]: Loop: 1853#L1148-2 assume !false; 1596#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1597#L729 assume !false; 1995#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1991#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1942#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2011#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2049#L626 assume !(0 != eval_~tmp~0#1); 2050#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2180#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2084#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1637#L754-5 assume !(0 == ~T1_E~0); 1638#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2020#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2188#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2189#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1952#L779-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1613#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1614#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1598#L794-3 assume !(0 == ~E_2~0); 1599#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1693#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2090#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1686#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1687#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1886#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1887#L361-24 assume 1 == ~m_pc~0; 1923#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1924#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1606#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1607#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2083#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2147#L380-24 assume 1 == ~t1_pc~0; 2148#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1774#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2206#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2079#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1734#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1735#L399-24 assume 1 == ~t2_pc~0; 1947#L400-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1997#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1775#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1776#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2071#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2072#L418-24 assume !(1 == ~t3_pc~0); 1682#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 1683#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2073#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1951#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1626#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1627#L437-24 assume 1 == ~t4_pc~0; 1898#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1899#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1777#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1778#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1926#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2235#L456-24 assume 1 == ~t5_pc~0; 2236#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2296#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1989#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1990#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2129#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2263#L475-24 assume 1 == ~t6_pc~0; 1628#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1629#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2272#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2273#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 1571#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1572#L494-24 assume 1 == ~t7_pc~0; 2229#L495-8 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2119#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2016#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2017#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1896#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1897#L837-3 assume !(1 == ~M_E~0); 1979#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2259#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2175#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1615#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1616#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2300#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2292#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2226#L872-3 assume !(1 == ~E_1~0); 2227#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2295#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2310#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1982#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1975#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1976#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2152#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2145#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1601#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2321#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 2281#L1167 assume !(0 == start_simulation_~tmp~3#1); 2176#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2203#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 2008#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2242#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 2275#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2190#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1577#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1578#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 1853#L1148-2 [2022-10-17 10:16:00,634 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:16:00,635 INFO L85 PathProgramCache]: Analyzing trace with hash 598794861, now seen corresponding path program 1 times [2022-10-17 10:16:00,635 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:16:00,635 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [159764666] [2022-10-17 10:16:00,636 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:16:00,636 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:16:00,659 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:16:00,758 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:16:00,758 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:16:00,759 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [159764666] [2022-10-17 10:16:00,759 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [159764666] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:16:00,759 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:16:00,760 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:16:00,760 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [848495536] [2022-10-17 10:16:00,760 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:16:00,761 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:16:00,761 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:16:00,762 INFO L85 PathProgramCache]: Analyzing trace with hash 1141273896, now seen corresponding path program 1 times [2022-10-17 10:16:00,762 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:16:00,767 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1800233484] [2022-10-17 10:16:00,767 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:16:00,767 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:16:00,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:16:00,950 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:16:00,950 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:16:00,951 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1800233484] [2022-10-17 10:16:00,952 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1800233484] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:16:00,952 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:16:00,952 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:16:00,952 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [619832766] [2022-10-17 10:16:00,953 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:16:00,954 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:16:00,955 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:16:00,956 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:16:00,956 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:16:00,957 INFO L87 Difference]: Start difference. First operand 768 states and 1148 transitions. cyclomatic complexity: 381 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:16:00,995 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:16:00,996 INFO L93 Difference]: Finished difference Result 768 states and 1147 transitions. [2022-10-17 10:16:00,996 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 768 states and 1147 transitions. [2022-10-17 10:16:01,004 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 667 [2022-10-17 10:16:01,012 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 768 states to 768 states and 1147 transitions. [2022-10-17 10:16:01,012 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 768 [2022-10-17 10:16:01,013 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 768 [2022-10-17 10:16:01,014 INFO L73 IsDeterministic]: Start isDeterministic. Operand 768 states and 1147 transitions. [2022-10-17 10:16:01,016 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:16:01,016 INFO L218 hiAutomatonCegarLoop]: Abstraction has 768 states and 1147 transitions. [2022-10-17 10:16:01,018 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 768 states and 1147 transitions. [2022-10-17 10:16:01,042 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 768 to 768. [2022-10-17 10:16:01,044 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 768 states, 768 states have (on average 1.4934895833333333) internal successors, (1147), 767 states have internal predecessors, (1147), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:16:01,048 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 768 states to 768 states and 1147 transitions. [2022-10-17 10:16:01,048 INFO L240 hiAutomatonCegarLoop]: Abstraction has 768 states and 1147 transitions. [2022-10-17 10:16:01,050 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:16:01,051 INFO L428 stractBuchiCegarLoop]: Abstraction has 768 states and 1147 transitions. [2022-10-17 10:16:01,051 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-10-17 10:16:01,051 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 768 states and 1147 transitions. [2022-10-17 10:16:01,058 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 667 [2022-10-17 10:16:01,058 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:16:01,058 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:16:01,065 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:16:01,065 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:16:01,066 INFO L748 eck$LassoCheckResult]: Stem: 3868#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 3846#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 3847#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3308#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3309#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 3725#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3726#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3694#L531-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3614#L536-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3615#L541-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3607#L546-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3608#L551-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3567#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3568#L754 assume !(0 == ~M_E~0); 3826#L754-2 assume !(0 == ~T1_E~0); 3510#L759-1 assume !(0 == ~T2_E~0); 3511#L764-1 assume !(0 == ~T3_E~0); 3855#L769-1 assume !(0 == ~T4_E~0); 3856#L774-1 assume !(0 == ~T5_E~0); 3754#L779-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3541#L784-1 assume !(0 == ~T7_E~0); 3542#L789-1 assume !(0 == ~E_1~0); 3217#L794-1 assume !(0 == ~E_2~0); 3218#L799-1 assume !(0 == ~E_3~0); 3857#L804-1 assume !(0 == ~E_4~0); 3858#L809-1 assume !(0 == ~E_5~0); 3619#L814-1 assume !(0 == ~E_6~0); 3137#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 3138#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3603#L361 assume 1 == ~m_pc~0; 3604#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3645#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3426#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3427#L930 assume !(0 != activate_threads_~tmp~1#1); 3751#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3597#L380 assume !(1 == ~t1_pc~0); 3271#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3270#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3774#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3851#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3347#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3272#L399 assume 1 == ~t2_pc~0; 3273#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3479#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3786#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3665#L946 assume !(0 != activate_threads_~tmp___1~0#1); 3177#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3145#L418 assume !(1 == ~t3_pc~0); 3106#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3107#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3625#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3833#L954 assume !(0 != activate_threads_~tmp___2~0#1); 3863#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3827#L437 assume 1 == ~t4_pc~0; 3828#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3447#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3275#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3276#L962 assume !(0 != activate_threads_~tmp___3~0#1); 3704#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3398#L456 assume !(1 == ~t5_pc~0); 3399#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3507#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3807#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3164#L970 assume !(0 != activate_threads_~tmp___4~0#1); 3165#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3288#L475 assume 1 == ~t6_pc~0; 3289#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3367#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3368#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3127#L978 assume !(0 != activate_threads_~tmp___5~0#1); 3128#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3610#L494 assume 1 == ~t7_pc~0; 3611#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3651#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3801#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3802#L986 assume !(0 != activate_threads_~tmp___6~0#1); 3866#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3803#L837 assume !(1 == ~M_E~0); 3668#L837-2 assume !(1 == ~T1_E~0); 3254#L842-1 assume !(1 == ~T2_E~0); 3255#L847-1 assume !(1 == ~T3_E~0); 3721#L852-1 assume !(1 == ~T4_E~0); 3796#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3676#L862-1 assume !(1 == ~T6_E~0); 3677#L867-1 assume !(1 == ~T7_E~0); 3685#L872-1 assume !(1 == ~E_1~0); 3753#L877-1 assume !(1 == ~E_2~0); 3683#L882-1 assume !(1 == ~E_3~0); 3684#L887-1 assume !(1 == ~E_4~0); 3314#L892-1 assume !(1 == ~E_5~0); 3315#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 3699#L902-1 assume !(1 == ~E_7~0); 3395#L907-1 assume { :end_inline_reset_delta_events } true; 3396#L1148-2 [2022-10-17 10:16:01,066 INFO L750 eck$LassoCheckResult]: Loop: 3396#L1148-2 assume !false; 3139#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3140#L729 assume !false; 3538#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 3534#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3485#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3554#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3591#L626 assume !(0 != eval_~tmp~0#1); 3592#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3722#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3627#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3178#L754-5 assume !(0 == ~T1_E~0); 3179#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3563#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3731#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3732#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3490#L779-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3154#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3155#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3141#L794-3 assume !(0 == ~E_2~0); 3142#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3236#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3633#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3231#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3232#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3429#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3430#L361-24 assume 1 == ~m_pc~0; 3466#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3467#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3149#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3150#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3626#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3690#L380-24 assume !(1 == ~t1_pc~0); 3316#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 3317#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3749#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3622#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3277#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3278#L399-24 assume 1 == ~t2_pc~0; 3491#L400-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3540#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3318#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3319#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3616#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3617#L418-24 assume 1 == ~t3_pc~0; 3620#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3226#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3618#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3495#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3169#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3170#L437-24 assume 1 == ~t4_pc~0; 3441#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3442#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3320#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3321#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3469#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3778#L456-24 assume 1 == ~t5_pc~0; 3779#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3839#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3532#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3533#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3674#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3806#L475-24 assume 1 == ~t6_pc~0; 3171#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3172#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3815#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3816#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 3114#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3115#L494-24 assume !(1 == ~t7_pc~0); 3682#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 3663#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3559#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3560#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3439#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3440#L837-3 assume !(1 == ~M_E~0); 3522#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3805#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3719#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3158#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3159#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3843#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3835#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3770#L872-3 assume !(1 == ~E_1~0); 3771#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3838#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3853#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3527#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3520#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3521#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3695#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 3688#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3144#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3864#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 3824#L1167 assume !(0 == start_simulation_~tmp~3#1); 3718#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 3746#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3552#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3785#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 3818#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3733#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3120#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 3121#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 3396#L1148-2 [2022-10-17 10:16:01,067 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:16:01,067 INFO L85 PathProgramCache]: Analyzing trace with hash 1185071083, now seen corresponding path program 1 times [2022-10-17 10:16:01,067 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:16:01,067 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [282621889] [2022-10-17 10:16:01,068 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:16:01,068 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:16:01,083 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:16:01,137 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:16:01,137 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:16:01,137 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [282621889] [2022-10-17 10:16:01,138 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [282621889] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:16:01,138 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:16:01,138 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:16:01,138 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1788504822] [2022-10-17 10:16:01,139 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:16:01,139 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:16:01,140 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:16:01,140 INFO L85 PathProgramCache]: Analyzing trace with hash 1561027463, now seen corresponding path program 1 times [2022-10-17 10:16:01,140 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:16:01,140 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1572064656] [2022-10-17 10:16:01,141 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:16:01,141 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:16:01,159 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:16:01,243 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:16:01,244 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:16:01,244 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1572064656] [2022-10-17 10:16:01,245 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1572064656] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:16:01,245 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:16:01,245 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:16:01,245 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [114000506] [2022-10-17 10:16:01,246 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:16:01,247 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:16:01,247 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:16:01,248 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:16:01,248 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:16:01,248 INFO L87 Difference]: Start difference. First operand 768 states and 1147 transitions. cyclomatic complexity: 380 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:16:01,272 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:16:01,273 INFO L93 Difference]: Finished difference Result 768 states and 1146 transitions. [2022-10-17 10:16:01,273 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 768 states and 1146 transitions. [2022-10-17 10:16:01,280 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 667 [2022-10-17 10:16:01,288 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 768 states to 768 states and 1146 transitions. [2022-10-17 10:16:01,288 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 768 [2022-10-17 10:16:01,289 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 768 [2022-10-17 10:16:01,289 INFO L73 IsDeterministic]: Start isDeterministic. Operand 768 states and 1146 transitions. [2022-10-17 10:16:01,291 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:16:01,291 INFO L218 hiAutomatonCegarLoop]: Abstraction has 768 states and 1146 transitions. [2022-10-17 10:16:01,293 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 768 states and 1146 transitions. [2022-10-17 10:16:01,305 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 768 to 768. [2022-10-17 10:16:01,307 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 768 states, 768 states have (on average 1.4921875) internal successors, (1146), 767 states have internal predecessors, (1146), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:16:01,310 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 768 states to 768 states and 1146 transitions. [2022-10-17 10:16:01,310 INFO L240 hiAutomatonCegarLoop]: Abstraction has 768 states and 1146 transitions. [2022-10-17 10:16:01,311 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:16:01,313 INFO L428 stractBuchiCegarLoop]: Abstraction has 768 states and 1146 transitions. [2022-10-17 10:16:01,314 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-10-17 10:16:01,314 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 768 states and 1146 transitions. [2022-10-17 10:16:01,319 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 667 [2022-10-17 10:16:01,319 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:16:01,319 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:16:01,324 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:16:01,324 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:16:01,324 INFO L748 eck$LassoCheckResult]: Stem: 5411#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 5390#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 5391#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4851#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4852#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 5268#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5269#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5237#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5160#L536-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5161#L541-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5150#L546-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5151#L551-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5110#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5111#L754 assume !(0 == ~M_E~0); 5369#L754-2 assume !(0 == ~T1_E~0); 5053#L759-1 assume !(0 == ~T2_E~0); 5054#L764-1 assume !(0 == ~T3_E~0); 5398#L769-1 assume !(0 == ~T4_E~0); 5399#L774-1 assume !(0 == ~T5_E~0); 5299#L779-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5084#L784-1 assume !(0 == ~T7_E~0); 5085#L789-1 assume !(0 == ~E_1~0); 4764#L794-1 assume !(0 == ~E_2~0); 4765#L799-1 assume !(0 == ~E_3~0); 5400#L804-1 assume !(0 == ~E_4~0); 5401#L809-1 assume !(0 == ~E_5~0); 5164#L814-1 assume !(0 == ~E_6~0); 4680#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 4681#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5146#L361 assume 1 == ~m_pc~0; 5147#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5188#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4969#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4970#L930 assume !(0 != activate_threads_~tmp~1#1); 5294#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5140#L380 assume !(1 == ~t1_pc~0); 4814#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4813#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5319#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5394#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4890#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4815#L399 assume 1 == ~t2_pc~0; 4816#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5022#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5329#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5208#L946 assume !(0 != activate_threads_~tmp___1~0#1); 4720#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4688#L418 assume !(1 == ~t3_pc~0); 4649#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4650#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5168#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5376#L954 assume !(0 != activate_threads_~tmp___2~0#1); 5406#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5371#L437 assume 1 == ~t4_pc~0; 5372#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4991#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4818#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4819#L962 assume !(0 != activate_threads_~tmp___3~0#1); 5247#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4946#L456 assume !(1 == ~t5_pc~0); 4947#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 5050#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5350#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4710#L970 assume !(0 != activate_threads_~tmp___4~0#1); 4711#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4834#L475 assume 1 == ~t6_pc~0; 4835#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4910#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4911#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4670#L978 assume !(0 != activate_threads_~tmp___5~0#1); 4671#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5153#L494 assume 1 == ~t7_pc~0; 5154#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5194#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5346#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5347#L986 assume !(0 != activate_threads_~tmp___6~0#1); 5409#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5348#L837 assume !(1 == ~M_E~0); 5211#L837-2 assume !(1 == ~T1_E~0); 4797#L842-1 assume !(1 == ~T2_E~0); 4798#L847-1 assume !(1 == ~T3_E~0); 5264#L852-1 assume !(1 == ~T4_E~0); 5341#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5220#L862-1 assume !(1 == ~T6_E~0); 5221#L867-1 assume !(1 == ~T7_E~0); 5230#L872-1 assume !(1 == ~E_1~0); 5296#L877-1 assume !(1 == ~E_2~0); 5226#L882-1 assume !(1 == ~E_3~0); 5227#L887-1 assume !(1 == ~E_4~0); 4857#L892-1 assume !(1 == ~E_5~0); 4858#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 5244#L902-1 assume !(1 == ~E_7~0); 4938#L907-1 assume { :end_inline_reset_delta_events } true; 4939#L1148-2 [2022-10-17 10:16:01,325 INFO L750 eck$LassoCheckResult]: Loop: 4939#L1148-2 assume !false; 4682#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4683#L729 assume !false; 5081#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5077#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 5028#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5097#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 5135#L626 assume !(0 != eval_~tmp~0#1); 5136#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5266#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5170#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4723#L754-5 assume !(0 == ~T1_E~0); 4724#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5106#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5274#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5275#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5038#L779-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4699#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4700#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4684#L794-3 assume !(0 == ~E_2~0); 4685#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4776#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5176#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4772#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4773#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4972#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4973#L361-24 assume 1 == ~m_pc~0; 5009#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5010#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4692#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4693#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5169#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5233#L380-24 assume 1 == ~t1_pc~0; 5234#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4860#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5292#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5165#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4820#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4821#L399-24 assume 1 == ~t2_pc~0; 5033#L400-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5083#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4861#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4862#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5157#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5158#L418-24 assume !(1 == ~t3_pc~0); 4768#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 4769#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5159#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5037#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4712#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4713#L437-24 assume 1 == ~t4_pc~0; 4984#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4985#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4863#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4864#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5012#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5321#L456-24 assume 1 == ~t5_pc~0; 5322#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5382#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5075#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5076#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5215#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5349#L475-24 assume 1 == ~t6_pc~0; 4714#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4715#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5358#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5359#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 4657#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4658#L494-24 assume 1 == ~t7_pc~0; 5315#L495-8 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5205#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5102#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5103#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4982#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4983#L837-3 assume !(1 == ~M_E~0); 5065#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5345#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5261#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4701#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4702#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5386#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5378#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5312#L872-3 assume !(1 == ~E_1~0); 5313#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5381#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5396#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5068#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5061#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5062#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5238#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5231#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 4687#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5407#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 5367#L1167 assume !(0 == start_simulation_~tmp~3#1); 5262#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5289#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 5094#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5328#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 5361#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5276#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4663#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 4664#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 4939#L1148-2 [2022-10-17 10:16:01,326 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:16:01,326 INFO L85 PathProgramCache]: Analyzing trace with hash -1151321427, now seen corresponding path program 1 times [2022-10-17 10:16:01,326 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:16:01,327 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [547699237] [2022-10-17 10:16:01,327 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:16:01,328 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:16:01,359 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:16:01,405 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:16:01,406 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:16:01,406 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [547699237] [2022-10-17 10:16:01,406 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [547699237] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:16:01,406 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:16:01,407 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:16:01,407 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [310832378] [2022-10-17 10:16:01,407 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:16:01,408 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:16:01,408 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:16:01,408 INFO L85 PathProgramCache]: Analyzing trace with hash 1141273896, now seen corresponding path program 2 times [2022-10-17 10:16:01,409 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:16:01,409 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [346674327] [2022-10-17 10:16:01,409 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:16:01,409 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:16:01,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:16:01,467 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:16:01,467 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:16:01,468 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [346674327] [2022-10-17 10:16:01,468 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [346674327] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:16:01,468 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:16:01,468 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:16:01,469 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [4690366] [2022-10-17 10:16:01,469 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:16:01,469 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:16:01,470 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:16:01,470 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:16:01,470 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:16:01,471 INFO L87 Difference]: Start difference. First operand 768 states and 1146 transitions. cyclomatic complexity: 379 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:16:01,494 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:16:01,494 INFO L93 Difference]: Finished difference Result 768 states and 1145 transitions. [2022-10-17 10:16:01,494 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 768 states and 1145 transitions. [2022-10-17 10:16:01,501 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 667 [2022-10-17 10:16:01,508 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 768 states to 768 states and 1145 transitions. [2022-10-17 10:16:01,509 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 768 [2022-10-17 10:16:01,510 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 768 [2022-10-17 10:16:01,510 INFO L73 IsDeterministic]: Start isDeterministic. Operand 768 states and 1145 transitions. [2022-10-17 10:16:01,512 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:16:01,512 INFO L218 hiAutomatonCegarLoop]: Abstraction has 768 states and 1145 transitions. [2022-10-17 10:16:01,514 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 768 states and 1145 transitions. [2022-10-17 10:16:01,526 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 768 to 768. [2022-10-17 10:16:01,528 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 768 states, 768 states have (on average 1.4908854166666667) internal successors, (1145), 767 states have internal predecessors, (1145), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:16:01,532 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 768 states to 768 states and 1145 transitions. [2022-10-17 10:16:01,532 INFO L240 hiAutomatonCegarLoop]: Abstraction has 768 states and 1145 transitions. [2022-10-17 10:16:01,533 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:16:01,533 INFO L428 stractBuchiCegarLoop]: Abstraction has 768 states and 1145 transitions. [2022-10-17 10:16:01,534 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-10-17 10:16:01,534 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 768 states and 1145 transitions. [2022-10-17 10:16:01,539 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 667 [2022-10-17 10:16:01,539 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:16:01,539 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:16:01,541 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:16:01,541 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:16:01,542 INFO L748 eck$LassoCheckResult]: Stem: 6954#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 6932#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 6933#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6394#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6395#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 6811#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6812#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6780#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6700#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6701#L541-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6693#L546-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6694#L551-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6653#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6654#L754 assume !(0 == ~M_E~0); 6912#L754-2 assume !(0 == ~T1_E~0); 6596#L759-1 assume !(0 == ~T2_E~0); 6597#L764-1 assume !(0 == ~T3_E~0); 6941#L769-1 assume !(0 == ~T4_E~0); 6942#L774-1 assume !(0 == ~T5_E~0); 6840#L779-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6627#L784-1 assume !(0 == ~T7_E~0); 6628#L789-1 assume !(0 == ~E_1~0); 6303#L794-1 assume !(0 == ~E_2~0); 6304#L799-1 assume !(0 == ~E_3~0); 6943#L804-1 assume !(0 == ~E_4~0); 6944#L809-1 assume !(0 == ~E_5~0); 6705#L814-1 assume !(0 == ~E_6~0); 6223#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 6224#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6689#L361 assume 1 == ~m_pc~0; 6690#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 6731#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6512#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6513#L930 assume !(0 != activate_threads_~tmp~1#1); 6837#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6683#L380 assume !(1 == ~t1_pc~0); 6357#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6356#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6860#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6937#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6433#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6358#L399 assume 1 == ~t2_pc~0; 6359#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6565#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6872#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6751#L946 assume !(0 != activate_threads_~tmp___1~0#1); 6263#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6231#L418 assume !(1 == ~t3_pc~0); 6192#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 6193#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6711#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6919#L954 assume !(0 != activate_threads_~tmp___2~0#1); 6949#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6913#L437 assume 1 == ~t4_pc~0; 6914#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6533#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6361#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6362#L962 assume !(0 != activate_threads_~tmp___3~0#1); 6790#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6484#L456 assume !(1 == ~t5_pc~0); 6485#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 6593#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6893#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6250#L970 assume !(0 != activate_threads_~tmp___4~0#1); 6251#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6374#L475 assume 1 == ~t6_pc~0; 6375#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6453#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6454#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6213#L978 assume !(0 != activate_threads_~tmp___5~0#1); 6214#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6696#L494 assume 1 == ~t7_pc~0; 6697#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6737#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6887#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6888#L986 assume !(0 != activate_threads_~tmp___6~0#1); 6952#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6889#L837 assume !(1 == ~M_E~0); 6754#L837-2 assume !(1 == ~T1_E~0); 6340#L842-1 assume !(1 == ~T2_E~0); 6341#L847-1 assume !(1 == ~T3_E~0); 6807#L852-1 assume !(1 == ~T4_E~0); 6882#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6762#L862-1 assume !(1 == ~T6_E~0); 6763#L867-1 assume !(1 == ~T7_E~0); 6771#L872-1 assume !(1 == ~E_1~0); 6839#L877-1 assume !(1 == ~E_2~0); 6769#L882-1 assume !(1 == ~E_3~0); 6770#L887-1 assume !(1 == ~E_4~0); 6400#L892-1 assume !(1 == ~E_5~0); 6401#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 6785#L902-1 assume !(1 == ~E_7~0); 6481#L907-1 assume { :end_inline_reset_delta_events } true; 6482#L1148-2 [2022-10-17 10:16:01,543 INFO L750 eck$LassoCheckResult]: Loop: 6482#L1148-2 assume !false; 6225#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6226#L729 assume !false; 6624#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 6620#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 6571#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 6640#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 6677#L626 assume !(0 != eval_~tmp~0#1); 6678#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6808#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6713#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6264#L754-5 assume !(0 == ~T1_E~0); 6265#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6649#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6817#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6818#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6576#L779-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6242#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 6243#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6227#L794-3 assume !(0 == ~E_2~0); 6228#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6322#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6719#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6317#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6318#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 6515#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6516#L361-24 assume 1 == ~m_pc~0; 6552#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 6553#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6235#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6236#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6712#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6776#L380-24 assume !(1 == ~t1_pc~0); 6402#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 6403#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6835#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6708#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6363#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6364#L399-24 assume 1 == ~t2_pc~0; 6577#L400-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6626#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6404#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6405#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6702#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6703#L418-24 assume 1 == ~t3_pc~0; 6706#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6312#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6704#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6581#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6255#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6256#L437-24 assume !(1 == ~t4_pc~0); 6529#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 6528#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6406#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6407#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6555#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6864#L456-24 assume 1 == ~t5_pc~0; 6865#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6925#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6618#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6619#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6760#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6892#L475-24 assume 1 == ~t6_pc~0; 6257#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6258#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6901#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6902#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 6200#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6201#L494-24 assume !(1 == ~t7_pc~0); 6768#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 6749#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6645#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6646#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 6525#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6526#L837-3 assume !(1 == ~M_E~0); 6608#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6891#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6805#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6244#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6245#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6929#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6921#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6856#L872-3 assume !(1 == ~E_1~0); 6857#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6924#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6939#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6613#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6606#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6607#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 6781#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 6774#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 6230#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 6950#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 6910#L1167 assume !(0 == start_simulation_~tmp~3#1); 6804#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 6832#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 6638#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 6871#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 6904#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6819#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6206#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 6207#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 6482#L1148-2 [2022-10-17 10:16:01,543 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:16:01,544 INFO L85 PathProgramCache]: Analyzing trace with hash 1267163051, now seen corresponding path program 1 times [2022-10-17 10:16:01,544 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:16:01,544 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1903923130] [2022-10-17 10:16:01,544 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:16:01,545 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:16:01,556 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:16:01,584 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:16:01,584 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:16:01,584 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1903923130] [2022-10-17 10:16:01,585 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1903923130] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:16:01,585 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:16:01,585 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:16:01,585 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1419349842] [2022-10-17 10:16:01,586 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:16:01,586 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:16:01,587 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:16:01,587 INFO L85 PathProgramCache]: Analyzing trace with hash 859459238, now seen corresponding path program 1 times [2022-10-17 10:16:01,587 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:16:01,587 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1852638914] [2022-10-17 10:16:01,588 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:16:01,588 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:16:01,612 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:16:01,669 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:16:01,671 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:16:01,671 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1852638914] [2022-10-17 10:16:01,671 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1852638914] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:16:01,671 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:16:01,672 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:16:01,672 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [137407951] [2022-10-17 10:16:01,672 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:16:01,672 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:16:01,673 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:16:01,673 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:16:01,673 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:16:01,674 INFO L87 Difference]: Start difference. First operand 768 states and 1145 transitions. cyclomatic complexity: 378 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:16:01,713 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:16:01,714 INFO L93 Difference]: Finished difference Result 768 states and 1144 transitions. [2022-10-17 10:16:01,714 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 768 states and 1144 transitions. [2022-10-17 10:16:01,721 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 667 [2022-10-17 10:16:01,728 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 768 states to 768 states and 1144 transitions. [2022-10-17 10:16:01,728 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 768 [2022-10-17 10:16:01,729 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 768 [2022-10-17 10:16:01,729 INFO L73 IsDeterministic]: Start isDeterministic. Operand 768 states and 1144 transitions. [2022-10-17 10:16:01,731 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:16:01,731 INFO L218 hiAutomatonCegarLoop]: Abstraction has 768 states and 1144 transitions. [2022-10-17 10:16:01,733 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 768 states and 1144 transitions. [2022-10-17 10:16:01,746 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 768 to 768. [2022-10-17 10:16:01,748 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 768 states, 768 states have (on average 1.4895833333333333) internal successors, (1144), 767 states have internal predecessors, (1144), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:16:01,751 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 768 states to 768 states and 1144 transitions. [2022-10-17 10:16:01,752 INFO L240 hiAutomatonCegarLoop]: Abstraction has 768 states and 1144 transitions. [2022-10-17 10:16:01,752 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:16:01,753 INFO L428 stractBuchiCegarLoop]: Abstraction has 768 states and 1144 transitions. [2022-10-17 10:16:01,753 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-10-17 10:16:01,753 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 768 states and 1144 transitions. [2022-10-17 10:16:01,758 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 667 [2022-10-17 10:16:01,758 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:16:01,759 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:16:01,760 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:16:01,761 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:16:01,761 INFO L748 eck$LassoCheckResult]: Stem: 8497#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 8476#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 8477#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7937#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7938#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 8354#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8355#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8323#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8246#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8247#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 8236#L546-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8237#L551-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8196#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8197#L754 assume !(0 == ~M_E~0); 8455#L754-2 assume !(0 == ~T1_E~0); 8139#L759-1 assume !(0 == ~T2_E~0); 8140#L764-1 assume !(0 == ~T3_E~0); 8484#L769-1 assume !(0 == ~T4_E~0); 8485#L774-1 assume !(0 == ~T5_E~0); 8385#L779-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8170#L784-1 assume !(0 == ~T7_E~0); 8171#L789-1 assume !(0 == ~E_1~0); 7850#L794-1 assume !(0 == ~E_2~0); 7851#L799-1 assume !(0 == ~E_3~0); 8486#L804-1 assume !(0 == ~E_4~0); 8487#L809-1 assume !(0 == ~E_5~0); 8250#L814-1 assume !(0 == ~E_6~0); 7768#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 7769#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8232#L361 assume 1 == ~m_pc~0; 8233#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 8274#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8055#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 8056#L930 assume !(0 != activate_threads_~tmp~1#1); 8380#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8226#L380 assume !(1 == ~t1_pc~0); 7900#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7899#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8405#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8481#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7976#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7901#L399 assume 1 == ~t2_pc~0; 7902#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8108#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8415#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8294#L946 assume !(0 != activate_threads_~tmp___1~0#1); 7806#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7774#L418 assume !(1 == ~t3_pc~0); 7735#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 7736#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8254#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8462#L954 assume !(0 != activate_threads_~tmp___2~0#1); 8492#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8457#L437 assume 1 == ~t4_pc~0; 8458#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8077#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7904#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7905#L962 assume !(0 != activate_threads_~tmp___3~0#1); 8333#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8032#L456 assume !(1 == ~t5_pc~0); 8033#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 8136#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8436#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7796#L970 assume !(0 != activate_threads_~tmp___4~0#1); 7797#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7920#L475 assume 1 == ~t6_pc~0; 7921#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7996#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7997#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7756#L978 assume !(0 != activate_threads_~tmp___5~0#1); 7757#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8239#L494 assume 1 == ~t7_pc~0; 8240#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8280#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8432#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8433#L986 assume !(0 != activate_threads_~tmp___6~0#1); 8495#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8434#L837 assume !(1 == ~M_E~0); 8297#L837-2 assume !(1 == ~T1_E~0); 7883#L842-1 assume !(1 == ~T2_E~0); 7884#L847-1 assume !(1 == ~T3_E~0); 8350#L852-1 assume !(1 == ~T4_E~0); 8427#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8306#L862-1 assume !(1 == ~T6_E~0); 8307#L867-1 assume !(1 == ~T7_E~0); 8316#L872-1 assume !(1 == ~E_1~0); 8382#L877-1 assume !(1 == ~E_2~0); 8312#L882-1 assume !(1 == ~E_3~0); 8313#L887-1 assume !(1 == ~E_4~0); 7943#L892-1 assume !(1 == ~E_5~0); 7944#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 8330#L902-1 assume !(1 == ~E_7~0); 8024#L907-1 assume { :end_inline_reset_delta_events } true; 8025#L1148-2 [2022-10-17 10:16:01,762 INFO L750 eck$LassoCheckResult]: Loop: 8025#L1148-2 assume !false; 7770#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7771#L729 assume !false; 8167#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 8163#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8114#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 8183#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 8221#L626 assume !(0 != eval_~tmp~0#1); 8222#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8352#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8256#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7809#L754-5 assume !(0 == ~T1_E~0); 7810#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8192#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8360#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8361#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8124#L779-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7785#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7786#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7766#L794-3 assume !(0 == ~E_2~0); 7767#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7862#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8262#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7858#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7859#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 8058#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8059#L361-24 assume !(1 == ~m_pc~0); 8097#L361-26 is_master_triggered_~__retres1~0#1 := 0; 8096#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7778#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7779#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8255#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8319#L380-24 assume 1 == ~t1_pc~0; 8320#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7946#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8378#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8251#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7906#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7907#L399-24 assume 1 == ~t2_pc~0; 8119#L400-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8169#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7947#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7948#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8243#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8244#L418-24 assume 1 == ~t3_pc~0; 8248#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7855#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8245#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8123#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7798#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7799#L437-24 assume 1 == ~t4_pc~0; 8070#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8071#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7949#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7950#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8098#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8407#L456-24 assume 1 == ~t5_pc~0; 8408#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8468#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8161#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8162#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8301#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8435#L475-24 assume 1 == ~t6_pc~0; 7800#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7801#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8444#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8445#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 7743#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7744#L494-24 assume 1 == ~t7_pc~0; 8401#L495-8 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8291#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8188#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8189#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8068#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8069#L837-3 assume !(1 == ~M_E~0); 8151#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8431#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8347#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7787#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7788#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8472#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8464#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8398#L872-3 assume !(1 == ~E_1~0); 8399#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8467#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8482#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8154#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8147#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8148#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8324#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 8317#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 7773#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 8493#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 8453#L1167 assume !(0 == start_simulation_~tmp~3#1); 8348#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 8375#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8180#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 8414#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 8447#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8362#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7749#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 7750#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 8025#L1148-2 [2022-10-17 10:16:01,762 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:16:01,763 INFO L85 PathProgramCache]: Analyzing trace with hash -1148673299, now seen corresponding path program 1 times [2022-10-17 10:16:01,763 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:16:01,763 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [789414532] [2022-10-17 10:16:01,763 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:16:01,764 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:16:01,774 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:16:01,801 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:16:01,802 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:16:01,802 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [789414532] [2022-10-17 10:16:01,802 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [789414532] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:16:01,802 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:16:01,802 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:16:01,803 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2035470943] [2022-10-17 10:16:01,803 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:16:01,803 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:16:01,804 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:16:01,804 INFO L85 PathProgramCache]: Analyzing trace with hash -1932928152, now seen corresponding path program 1 times [2022-10-17 10:16:01,804 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:16:01,805 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1826512052] [2022-10-17 10:16:01,805 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:16:01,805 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:16:01,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:16:01,856 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:16:01,857 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:16:01,857 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1826512052] [2022-10-17 10:16:01,857 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1826512052] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:16:01,858 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:16:01,858 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:16:01,858 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [816862059] [2022-10-17 10:16:01,858 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:16:01,859 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:16:01,859 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:16:01,859 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:16:01,860 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:16:01,860 INFO L87 Difference]: Start difference. First operand 768 states and 1144 transitions. cyclomatic complexity: 377 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:16:01,883 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:16:01,883 INFO L93 Difference]: Finished difference Result 768 states and 1143 transitions. [2022-10-17 10:16:01,883 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 768 states and 1143 transitions. [2022-10-17 10:16:01,891 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 667 [2022-10-17 10:16:01,898 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 768 states to 768 states and 1143 transitions. [2022-10-17 10:16:01,898 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 768 [2022-10-17 10:16:01,899 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 768 [2022-10-17 10:16:01,899 INFO L73 IsDeterministic]: Start isDeterministic. Operand 768 states and 1143 transitions. [2022-10-17 10:16:01,901 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:16:01,901 INFO L218 hiAutomatonCegarLoop]: Abstraction has 768 states and 1143 transitions. [2022-10-17 10:16:01,903 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 768 states and 1143 transitions. [2022-10-17 10:16:01,915 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 768 to 768. [2022-10-17 10:16:01,917 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 768 states, 768 states have (on average 1.48828125) internal successors, (1143), 767 states have internal predecessors, (1143), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:16:01,921 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 768 states to 768 states and 1143 transitions. [2022-10-17 10:16:01,921 INFO L240 hiAutomatonCegarLoop]: Abstraction has 768 states and 1143 transitions. [2022-10-17 10:16:01,922 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:16:01,923 INFO L428 stractBuchiCegarLoop]: Abstraction has 768 states and 1143 transitions. [2022-10-17 10:16:01,923 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-10-17 10:16:01,923 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 768 states and 1143 transitions. [2022-10-17 10:16:01,928 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 667 [2022-10-17 10:16:01,928 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:16:01,929 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:16:01,930 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:16:01,930 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:16:01,931 INFO L748 eck$LassoCheckResult]: Stem: 10040#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 10018#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 10019#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9480#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9481#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 9897#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9898#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9866#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9786#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9787#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9779#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 9780#L551-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 9739#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9740#L754 assume !(0 == ~M_E~0); 9998#L754-2 assume !(0 == ~T1_E~0); 9682#L759-1 assume !(0 == ~T2_E~0); 9683#L764-1 assume !(0 == ~T3_E~0); 10027#L769-1 assume !(0 == ~T4_E~0); 10028#L774-1 assume !(0 == ~T5_E~0); 9926#L779-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9713#L784-1 assume !(0 == ~T7_E~0); 9714#L789-1 assume !(0 == ~E_1~0); 9389#L794-1 assume !(0 == ~E_2~0); 9390#L799-1 assume !(0 == ~E_3~0); 10029#L804-1 assume !(0 == ~E_4~0); 10030#L809-1 assume !(0 == ~E_5~0); 9791#L814-1 assume !(0 == ~E_6~0); 9309#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 9310#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9775#L361 assume 1 == ~m_pc~0; 9776#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 9817#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9598#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 9599#L930 assume !(0 != activate_threads_~tmp~1#1); 9923#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9769#L380 assume !(1 == ~t1_pc~0); 9443#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 9442#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9946#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 10023#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9519#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9444#L399 assume 1 == ~t2_pc~0; 9445#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9651#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9958#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9837#L946 assume !(0 != activate_threads_~tmp___1~0#1); 9349#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9317#L418 assume !(1 == ~t3_pc~0); 9278#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 9279#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9797#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10005#L954 assume !(0 != activate_threads_~tmp___2~0#1); 10035#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9999#L437 assume 1 == ~t4_pc~0; 10000#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9619#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9447#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9448#L962 assume !(0 != activate_threads_~tmp___3~0#1); 9876#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9570#L456 assume !(1 == ~t5_pc~0); 9571#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 9679#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9979#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9336#L970 assume !(0 != activate_threads_~tmp___4~0#1); 9337#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9460#L475 assume 1 == ~t6_pc~0; 9461#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 9539#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9540#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9299#L978 assume !(0 != activate_threads_~tmp___5~0#1); 9300#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9782#L494 assume 1 == ~t7_pc~0; 9783#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 9823#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9973#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9974#L986 assume !(0 != activate_threads_~tmp___6~0#1); 10038#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9975#L837 assume !(1 == ~M_E~0); 9840#L837-2 assume !(1 == ~T1_E~0); 9426#L842-1 assume !(1 == ~T2_E~0); 9427#L847-1 assume !(1 == ~T3_E~0); 9893#L852-1 assume !(1 == ~T4_E~0); 9968#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9848#L862-1 assume !(1 == ~T6_E~0); 9849#L867-1 assume !(1 == ~T7_E~0); 9857#L872-1 assume !(1 == ~E_1~0); 9925#L877-1 assume !(1 == ~E_2~0); 9855#L882-1 assume !(1 == ~E_3~0); 9856#L887-1 assume !(1 == ~E_4~0); 9486#L892-1 assume !(1 == ~E_5~0); 9487#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 9871#L902-1 assume !(1 == ~E_7~0); 9567#L907-1 assume { :end_inline_reset_delta_events } true; 9568#L1148-2 [2022-10-17 10:16:01,931 INFO L750 eck$LassoCheckResult]: Loop: 9568#L1148-2 assume !false; 9311#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9312#L729 assume !false; 9710#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 9706#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 9657#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 9726#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 9763#L626 assume !(0 != eval_~tmp~0#1); 9764#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9894#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9799#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9350#L754-5 assume !(0 == ~T1_E~0); 9351#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9735#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9903#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9904#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9662#L779-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9328#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 9329#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9313#L794-3 assume !(0 == ~E_2~0); 9314#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9408#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9805#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9403#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9404#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9601#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9602#L361-24 assume 1 == ~m_pc~0; 9638#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 9639#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9321#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 9322#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9798#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9862#L380-24 assume !(1 == ~t1_pc~0); 9488#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 9489#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9921#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9794#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9449#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9450#L399-24 assume !(1 == ~t2_pc~0); 9664#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 9712#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9490#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9491#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9788#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9789#L418-24 assume 1 == ~t3_pc~0; 9792#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9398#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9790#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9667#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9341#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9342#L437-24 assume 1 == ~t4_pc~0; 9613#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9614#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9492#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9493#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9641#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9950#L456-24 assume !(1 == ~t5_pc~0); 9952#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 10011#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9704#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9705#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9846#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9978#L475-24 assume !(1 == ~t6_pc~0); 9345#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 9344#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9987#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9988#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 9286#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9287#L494-24 assume 1 == ~t7_pc~0; 9944#L495-8 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 9835#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9731#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9732#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9611#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9612#L837-3 assume !(1 == ~M_E~0); 9694#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9977#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9891#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9330#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9331#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10015#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10007#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9942#L872-3 assume !(1 == ~E_1~0); 9943#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10010#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10025#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9699#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9692#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 9693#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 9867#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 9860#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 9316#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 10036#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 9996#L1167 assume !(0 == start_simulation_~tmp~3#1); 9890#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 9918#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 9724#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 9957#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 9990#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9905#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9292#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 9293#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 9568#L1148-2 [2022-10-17 10:16:01,932 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:16:01,933 INFO L85 PathProgramCache]: Analyzing trace with hash 1821437803, now seen corresponding path program 1 times [2022-10-17 10:16:01,933 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:16:01,933 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [634035853] [2022-10-17 10:16:01,933 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:16:01,934 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:16:01,945 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:16:01,974 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:16:01,974 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:16:01,974 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [634035853] [2022-10-17 10:16:01,975 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [634035853] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:16:01,975 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:16:01,975 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:16:01,975 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1612243133] [2022-10-17 10:16:01,975 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:16:01,976 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:16:01,976 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:16:01,976 INFO L85 PathProgramCache]: Analyzing trace with hash -1308384443, now seen corresponding path program 1 times [2022-10-17 10:16:01,977 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:16:01,977 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [872869930] [2022-10-17 10:16:01,977 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:16:01,977 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:16:01,991 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:16:02,026 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:16:02,026 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:16:02,026 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [872869930] [2022-10-17 10:16:02,027 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [872869930] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:16:02,027 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:16:02,027 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:16:02,027 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2017556487] [2022-10-17 10:16:02,028 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:16:02,028 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:16:02,028 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:16:02,029 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:16:02,029 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:16:02,029 INFO L87 Difference]: Start difference. First operand 768 states and 1143 transitions. cyclomatic complexity: 376 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:16:02,051 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:16:02,052 INFO L93 Difference]: Finished difference Result 768 states and 1142 transitions. [2022-10-17 10:16:02,052 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 768 states and 1142 transitions. [2022-10-17 10:16:02,060 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 667 [2022-10-17 10:16:02,067 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 768 states to 768 states and 1142 transitions. [2022-10-17 10:16:02,067 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 768 [2022-10-17 10:16:02,068 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 768 [2022-10-17 10:16:02,068 INFO L73 IsDeterministic]: Start isDeterministic. Operand 768 states and 1142 transitions. [2022-10-17 10:16:02,070 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:16:02,070 INFO L218 hiAutomatonCegarLoop]: Abstraction has 768 states and 1142 transitions. [2022-10-17 10:16:02,072 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 768 states and 1142 transitions. [2022-10-17 10:16:02,084 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 768 to 768. [2022-10-17 10:16:02,086 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 768 states, 768 states have (on average 1.4869791666666667) internal successors, (1142), 767 states have internal predecessors, (1142), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:16:02,090 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 768 states to 768 states and 1142 transitions. [2022-10-17 10:16:02,090 INFO L240 hiAutomatonCegarLoop]: Abstraction has 768 states and 1142 transitions. [2022-10-17 10:16:02,090 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:16:02,091 INFO L428 stractBuchiCegarLoop]: Abstraction has 768 states and 1142 transitions. [2022-10-17 10:16:02,091 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-10-17 10:16:02,092 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 768 states and 1142 transitions. [2022-10-17 10:16:02,097 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 667 [2022-10-17 10:16:02,097 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:16:02,097 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:16:02,099 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:16:02,099 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:16:02,100 INFO L748 eck$LassoCheckResult]: Stem: 11583#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 11562#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 11563#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11023#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11024#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 11440#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11441#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11409#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 11332#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11333#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 11322#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 11323#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 11282#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11283#L754 assume !(0 == ~M_E~0); 11541#L754-2 assume !(0 == ~T1_E~0); 11225#L759-1 assume !(0 == ~T2_E~0); 11226#L764-1 assume !(0 == ~T3_E~0); 11570#L769-1 assume !(0 == ~T4_E~0); 11571#L774-1 assume !(0 == ~T5_E~0); 11471#L779-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11256#L784-1 assume !(0 == ~T7_E~0); 11257#L789-1 assume !(0 == ~E_1~0); 10936#L794-1 assume !(0 == ~E_2~0); 10937#L799-1 assume !(0 == ~E_3~0); 11572#L804-1 assume !(0 == ~E_4~0); 11573#L809-1 assume !(0 == ~E_5~0); 11336#L814-1 assume !(0 == ~E_6~0); 10854#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 10855#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11318#L361 assume 1 == ~m_pc~0; 11319#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 11360#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11141#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 11142#L930 assume !(0 != activate_threads_~tmp~1#1); 11466#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11312#L380 assume !(1 == ~t1_pc~0); 10986#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 10985#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11491#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11567#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11062#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10987#L399 assume 1 == ~t2_pc~0; 10988#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11194#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11501#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11380#L946 assume !(0 != activate_threads_~tmp___1~0#1); 10892#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10860#L418 assume !(1 == ~t3_pc~0); 10821#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 10822#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11340#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11548#L954 assume !(0 != activate_threads_~tmp___2~0#1); 11578#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11543#L437 assume 1 == ~t4_pc~0; 11544#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11163#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10990#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10991#L962 assume !(0 != activate_threads_~tmp___3~0#1); 11419#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11118#L456 assume !(1 == ~t5_pc~0); 11119#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 11222#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11522#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10882#L970 assume !(0 != activate_threads_~tmp___4~0#1); 10883#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11006#L475 assume 1 == ~t6_pc~0; 11007#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11082#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11083#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10842#L978 assume !(0 != activate_threads_~tmp___5~0#1); 10843#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11325#L494 assume 1 == ~t7_pc~0; 11326#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11366#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11518#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11519#L986 assume !(0 != activate_threads_~tmp___6~0#1); 11581#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11520#L837 assume !(1 == ~M_E~0); 11383#L837-2 assume !(1 == ~T1_E~0); 10969#L842-1 assume !(1 == ~T2_E~0); 10970#L847-1 assume !(1 == ~T3_E~0); 11436#L852-1 assume !(1 == ~T4_E~0); 11513#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11392#L862-1 assume !(1 == ~T6_E~0); 11393#L867-1 assume !(1 == ~T7_E~0); 11402#L872-1 assume !(1 == ~E_1~0); 11468#L877-1 assume !(1 == ~E_2~0); 11398#L882-1 assume !(1 == ~E_3~0); 11399#L887-1 assume !(1 == ~E_4~0); 11029#L892-1 assume !(1 == ~E_5~0); 11030#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 11416#L902-1 assume !(1 == ~E_7~0); 11111#L907-1 assume { :end_inline_reset_delta_events } true; 11112#L1148-2 [2022-10-17 10:16:02,100 INFO L750 eck$LassoCheckResult]: Loop: 11112#L1148-2 assume !false; 10856#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10857#L729 assume !false; 11253#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 11249#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 11200#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 11269#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 11307#L626 assume !(0 != eval_~tmp~0#1); 11308#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11438#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11342#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10895#L754-5 assume !(0 == ~T1_E~0); 10896#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11278#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11446#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11447#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11210#L779-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10871#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 10872#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10852#L794-3 assume !(0 == ~E_2~0); 10853#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10948#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11348#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10946#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 10947#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 11144#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11145#L361-24 assume 1 == ~m_pc~0; 11181#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 11182#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10864#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 10865#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11341#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11405#L380-24 assume !(1 == ~t1_pc~0); 11031#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 11032#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11464#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11337#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10992#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10993#L399-24 assume 1 == ~t2_pc~0; 11205#L400-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11255#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11033#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11034#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11329#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11330#L418-24 assume 1 == ~t3_pc~0; 11334#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10941#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11331#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11209#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10884#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10885#L437-24 assume 1 == ~t4_pc~0; 11156#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11157#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11035#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11036#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11184#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11493#L456-24 assume 1 == ~t5_pc~0; 11494#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11554#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11247#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11248#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11387#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11521#L475-24 assume 1 == ~t6_pc~0; 10886#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10887#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11530#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11531#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 10829#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10830#L494-24 assume !(1 == ~t7_pc~0); 11397#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 11377#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11274#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11275#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11154#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11155#L837-3 assume !(1 == ~M_E~0); 11237#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11517#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11433#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10873#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10874#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11558#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 11550#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11484#L872-3 assume !(1 == ~E_1~0); 11485#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11553#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11568#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 11240#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 11233#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11234#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 11410#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 11403#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 10859#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 11579#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 11539#L1167 assume !(0 == start_simulation_~tmp~3#1); 11434#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 11461#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 11266#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 11500#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 11533#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11448#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10835#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 10836#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 11112#L1148-2 [2022-10-17 10:16:02,101 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:16:02,101 INFO L85 PathProgramCache]: Analyzing trace with hash 254679853, now seen corresponding path program 1 times [2022-10-17 10:16:02,102 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:16:02,102 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [882884597] [2022-10-17 10:16:02,102 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:16:02,102 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:16:02,115 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:16:02,208 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:16:02,208 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:16:02,209 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [882884597] [2022-10-17 10:16:02,209 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [882884597] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:16:02,209 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:16:02,209 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:16:02,210 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [343445208] [2022-10-17 10:16:02,210 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:16:02,210 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:16:02,210 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:16:02,211 INFO L85 PathProgramCache]: Analyzing trace with hash 1561027463, now seen corresponding path program 2 times [2022-10-17 10:16:02,211 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:16:02,215 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [459831487] [2022-10-17 10:16:02,215 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:16:02,216 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:16:02,228 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:16:02,266 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:16:02,266 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:16:02,266 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [459831487] [2022-10-17 10:16:02,269 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [459831487] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:16:02,269 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:16:02,269 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:16:02,269 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [901666737] [2022-10-17 10:16:02,269 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:16:02,270 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:16:02,270 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:16:02,270 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-10-17 10:16:02,271 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-10-17 10:16:02,271 INFO L87 Difference]: Start difference. First operand 768 states and 1142 transitions. cyclomatic complexity: 375 Second operand has 4 states, 4 states have (on average 23.25) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:16:02,407 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:16:02,407 INFO L93 Difference]: Finished difference Result 1448 states and 2148 transitions. [2022-10-17 10:16:02,408 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1448 states and 2148 transitions. [2022-10-17 10:16:02,423 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1334 [2022-10-17 10:16:02,435 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1448 states to 1448 states and 2148 transitions. [2022-10-17 10:16:02,436 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1448 [2022-10-17 10:16:02,437 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1448 [2022-10-17 10:16:02,437 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1448 states and 2148 transitions. [2022-10-17 10:16:02,440 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:16:02,440 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1448 states and 2148 transitions. [2022-10-17 10:16:02,443 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1448 states and 2148 transitions. [2022-10-17 10:16:02,473 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1448 to 1448. [2022-10-17 10:16:02,477 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1448 states, 1448 states have (on average 1.4834254143646408) internal successors, (2148), 1447 states have internal predecessors, (2148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:16:02,484 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1448 states to 1448 states and 2148 transitions. [2022-10-17 10:16:02,484 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1448 states and 2148 transitions. [2022-10-17 10:16:02,484 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-10-17 10:16:02,488 INFO L428 stractBuchiCegarLoop]: Abstraction has 1448 states and 2148 transitions. [2022-10-17 10:16:02,488 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-10-17 10:16:02,488 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1448 states and 2148 transitions. [2022-10-17 10:16:02,497 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1334 [2022-10-17 10:16:02,498 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:16:02,498 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:16:02,499 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:16:02,499 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:16:02,500 INFO L748 eck$LassoCheckResult]: Stem: 13864#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 13825#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 13826#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13252#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13253#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 13676#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13677#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13643#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 13565#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 13566#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 13555#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 13556#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 13513#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13514#L754 assume !(0 == ~M_E~0); 13798#L754-2 assume !(0 == ~T1_E~0); 13454#L759-1 assume !(0 == ~T2_E~0); 13455#L764-1 assume !(0 == ~T3_E~0); 13840#L769-1 assume !(0 == ~T4_E~0); 13841#L774-1 assume !(0 == ~T5_E~0); 13711#L779-1 assume !(0 == ~T6_E~0); 13485#L784-1 assume !(0 == ~T7_E~0); 13486#L789-1 assume !(0 == ~E_1~0); 13162#L794-1 assume !(0 == ~E_2~0); 13163#L799-1 assume !(0 == ~E_3~0); 13842#L804-1 assume !(0 == ~E_4~0); 13843#L809-1 assume !(0 == ~E_5~0); 13569#L814-1 assume !(0 == ~E_6~0); 13078#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 13079#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13551#L361 assume 1 == ~m_pc~0; 13552#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 13594#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13370#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 13371#L930 assume !(0 != activate_threads_~tmp~1#1); 13706#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13544#L380 assume !(1 == ~t1_pc~0); 13213#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 13212#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13732#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 13831#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13291#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13214#L399 assume 1 == ~t2_pc~0; 13215#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13423#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13743#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13614#L946 assume !(0 != activate_threads_~tmp___1~0#1); 13118#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13086#L418 assume !(1 == ~t3_pc~0); 13047#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 13048#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13573#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13806#L954 assume !(0 != activate_threads_~tmp___2~0#1); 13856#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13799#L437 assume 1 == ~t4_pc~0; 13800#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13391#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13217#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13218#L962 assume !(0 != activate_threads_~tmp___3~0#1); 13654#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13347#L456 assume !(1 == ~t5_pc~0); 13348#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 13451#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13773#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13108#L970 assume !(0 != activate_threads_~tmp___4~0#1); 13109#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13233#L475 assume 1 == ~t6_pc~0; 13234#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13311#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13312#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13068#L978 assume !(0 != activate_threads_~tmp___5~0#1); 13069#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13558#L494 assume 1 == ~t7_pc~0; 13559#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 13600#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13767#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13768#L986 assume !(0 != activate_threads_~tmp___6~0#1); 13861#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13769#L837 assume !(1 == ~M_E~0); 13617#L837-2 assume !(1 == ~T1_E~0); 13195#L842-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13196#L847-1 assume !(1 == ~T3_E~0); 13671#L852-1 assume !(1 == ~T4_E~0); 13761#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 13626#L862-1 assume !(1 == ~T6_E~0); 13627#L867-1 assume !(1 == ~T7_E~0); 13636#L872-1 assume !(1 == ~E_1~0); 13708#L877-1 assume !(1 == ~E_2~0); 13632#L882-1 assume !(1 == ~E_3~0); 13633#L887-1 assume !(1 == ~E_4~0); 13258#L892-1 assume !(1 == ~E_5~0); 13259#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 13954#L902-1 assume !(1 == ~E_7~0); 13892#L907-1 assume { :end_inline_reset_delta_events } true; 13698#L1148-2 [2022-10-17 10:16:02,500 INFO L750 eck$LassoCheckResult]: Loop: 13698#L1148-2 assume !false; 13080#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13081#L729 assume !false; 13482#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 13478#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 13429#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 13873#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 13871#L626 assume !(0 != eval_~tmp~0#1); 13870#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13869#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13868#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13867#L754-5 assume !(0 == ~T1_E~0); 13865#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13866#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14489#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14488#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14487#L779-3 assume !(0 == ~T6_E~0); 14486#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 14485#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14484#L794-3 assume !(0 == ~E_2~0); 14483#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14482#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14481#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14480#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 14479#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 14478#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14477#L361-24 assume 1 == ~m_pc~0; 14475#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 14474#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14473#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 14472#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14471#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14470#L380-24 assume !(1 == ~t1_pc~0); 14468#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 14467#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13741#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 13570#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13221#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13222#L399-24 assume 1 == ~t2_pc~0; 13434#L400-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13484#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13262#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13263#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 13562#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13563#L418-24 assume !(1 == ~t3_pc~0); 13166#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 13167#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13564#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13438#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13110#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13111#L437-24 assume 1 == ~t4_pc~0; 13385#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13386#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13264#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13265#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13413#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13734#L456-24 assume 1 == ~t5_pc~0; 13735#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13813#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13476#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13477#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 13621#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14401#L475-24 assume 1 == ~t6_pc~0; 14395#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 14393#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14391#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14389#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 14388#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14387#L494-24 assume 1 == ~t7_pc~0; 14384#L495-8 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14382#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14380#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14378#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 14376#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14373#L837-3 assume !(1 == ~M_E~0); 14371#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14369#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13766#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14366#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14364#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14363#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13849#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14362#L872-3 assume !(1 == ~E_1~0); 14360#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14359#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14357#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14355#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14353#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14352#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 14350#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 14343#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 14335#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 14334#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 14332#L1167 assume !(0 == start_simulation_~tmp~3#1); 13700#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 13701#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 13494#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 13742#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 13788#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13686#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13061#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 13062#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 13698#L1148-2 [2022-10-17 10:16:02,501 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:16:02,501 INFO L85 PathProgramCache]: Analyzing trace with hash -2141947347, now seen corresponding path program 1 times [2022-10-17 10:16:02,502 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:16:02,502 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1868356543] [2022-10-17 10:16:02,502 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:16:02,502 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:16:02,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:16:02,566 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:16:02,566 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:16:02,567 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1868356543] [2022-10-17 10:16:02,567 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1868356543] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:16:02,567 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:16:02,567 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-10-17 10:16:02,567 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1004767016] [2022-10-17 10:16:02,567 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:16:02,568 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:16:02,568 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:16:02,568 INFO L85 PathProgramCache]: Analyzing trace with hash 89455557, now seen corresponding path program 1 times [2022-10-17 10:16:02,569 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:16:02,569 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1536728529] [2022-10-17 10:16:02,569 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:16:02,569 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:16:02,584 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:16:02,628 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:16:02,628 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:16:02,628 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1536728529] [2022-10-17 10:16:02,628 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1536728529] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:16:02,629 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:16:02,629 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:16:02,629 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [495789914] [2022-10-17 10:16:02,629 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:16:02,630 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:16:02,630 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:16:02,630 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:16:02,631 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:16:02,631 INFO L87 Difference]: Start difference. First operand 1448 states and 2148 transitions. cyclomatic complexity: 702 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 2 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:16:02,688 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:16:02,688 INFO L93 Difference]: Finished difference Result 1448 states and 2122 transitions. [2022-10-17 10:16:02,689 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1448 states and 2122 transitions. [2022-10-17 10:16:02,702 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1334 [2022-10-17 10:16:02,714 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1448 states to 1448 states and 2122 transitions. [2022-10-17 10:16:02,714 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1448 [2022-10-17 10:16:02,716 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1448 [2022-10-17 10:16:02,716 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1448 states and 2122 transitions. [2022-10-17 10:16:02,718 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:16:02,718 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1448 states and 2122 transitions. [2022-10-17 10:16:02,721 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1448 states and 2122 transitions. [2022-10-17 10:16:02,772 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1448 to 1448. [2022-10-17 10:16:02,776 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1448 states, 1448 states have (on average 1.4654696132596685) internal successors, (2122), 1447 states have internal predecessors, (2122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:16:02,784 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1448 states to 1448 states and 2122 transitions. [2022-10-17 10:16:02,784 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1448 states and 2122 transitions. [2022-10-17 10:16:02,784 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:16:02,785 INFO L428 stractBuchiCegarLoop]: Abstraction has 1448 states and 2122 transitions. [2022-10-17 10:16:02,785 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-10-17 10:16:02,786 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1448 states and 2122 transitions. [2022-10-17 10:16:02,796 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1334 [2022-10-17 10:16:02,796 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:16:02,796 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:16:02,798 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:16:02,798 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:16:02,799 INFO L748 eck$LassoCheckResult]: Stem: 16744#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 16716#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 16717#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16153#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16154#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 16578#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16579#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16546#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16465#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16466#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 16458#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 16459#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 16417#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16418#L754 assume !(0 == ~M_E~0); 16690#L754-2 assume !(0 == ~T1_E~0); 16355#L759-1 assume !(0 == ~T2_E~0); 16356#L764-1 assume !(0 == ~T3_E~0); 16725#L769-1 assume !(0 == ~T4_E~0); 16726#L774-1 assume !(0 == ~T5_E~0); 16609#L779-1 assume !(0 == ~T6_E~0); 16389#L784-1 assume !(0 == ~T7_E~0); 16390#L789-1 assume !(0 == ~E_1~0); 16061#L794-1 assume !(0 == ~E_2~0); 16062#L799-1 assume !(0 == ~E_3~0); 16729#L804-1 assume !(0 == ~E_4~0); 16730#L809-1 assume !(0 == ~E_5~0); 16470#L814-1 assume !(0 == ~E_6~0); 15981#L819-1 assume !(0 == ~E_7~0); 15982#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16454#L361 assume 1 == ~m_pc~0; 16455#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 16497#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16272#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 16273#L930 assume !(0 != activate_threads_~tmp~1#1); 16606#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16448#L380 assume !(1 == ~t1_pc~0); 16117#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 16116#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16630#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 16721#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 16192#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16118#L399 assume 1 == ~t2_pc~0; 16119#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 16324#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16642#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 16517#L946 assume !(0 != activate_threads_~tmp___1~0#1); 16021#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15989#L418 assume !(1 == ~t3_pc~0); 15950#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 15951#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16474#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16699#L954 assume !(0 != activate_threads_~tmp___2~0#1); 16737#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16691#L437 assume 1 == ~t4_pc~0; 16692#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 16293#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16121#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16122#L962 assume !(0 != activate_threads_~tmp___3~0#1); 16556#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16244#L456 assume !(1 == ~t5_pc~0); 16245#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 16352#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16666#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16008#L970 assume !(0 != activate_threads_~tmp___4~0#1); 16009#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16134#L475 assume 1 == ~t6_pc~0; 16135#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 16213#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16214#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15971#L978 assume !(0 != activate_threads_~tmp___5~0#1); 15972#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16461#L494 assume !(1 == ~t7_pc~0); 16463#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 16503#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16659#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16660#L986 assume !(0 != activate_threads_~tmp___6~0#1); 16741#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16661#L837 assume !(1 == ~M_E~0); 16520#L837-2 assume !(1 == ~T1_E~0); 16099#L842-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16100#L847-1 assume !(1 == ~T3_E~0); 16574#L852-1 assume !(1 == ~T4_E~0); 16653#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16528#L862-1 assume !(1 == ~T6_E~0); 16529#L867-1 assume !(1 == ~T7_E~0); 16537#L872-1 assume !(1 == ~E_1~0); 16608#L877-1 assume !(1 == ~E_2~0); 16535#L882-1 assume !(1 == ~E_3~0); 16536#L887-1 assume !(1 == ~E_4~0); 16777#L892-1 assume !(1 == ~E_5~0); 16776#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 16774#L902-1 assume !(1 == ~E_7~0); 16771#L907-1 assume { :end_inline_reset_delta_events } true; 16598#L1148-2 [2022-10-17 10:16:02,800 INFO L750 eck$LassoCheckResult]: Loop: 16598#L1148-2 assume !false; 15983#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 15984#L729 assume !false; 16386#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 16380#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 16330#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 16752#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 16751#L626 assume !(0 != eval_~tmp~0#1); 16750#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16749#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16748#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 16747#L754-5 assume !(0 == ~T1_E~0); 16745#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16746#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17392#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17391#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17390#L779-3 assume !(0 == ~T6_E~0); 17389#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 17388#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 17387#L794-3 assume !(0 == ~E_2~0); 17386#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17385#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 17384#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 17383#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 17382#L819-3 assume !(0 == ~E_7~0); 17381#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17380#L361-24 assume 1 == ~m_pc~0; 17378#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 17377#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17376#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 17375#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 17374#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17373#L380-24 assume !(1 == ~t1_pc~0); 17371#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 17370#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17369#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 17368#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17367#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17366#L399-24 assume 1 == ~t2_pc~0; 17364#L400-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17363#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17362#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 17361#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 17360#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17359#L418-24 assume !(1 == ~t3_pc~0); 17357#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 17356#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17355#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 17354#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17353#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17352#L437-24 assume 1 == ~t4_pc~0; 17350#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17349#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17348#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 17347#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17346#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17345#L456-24 assume 1 == ~t5_pc~0; 17344#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17342#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17341#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17340#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 17339#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17338#L475-24 assume 1 == ~t6_pc~0; 17336#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17335#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17334#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17333#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 17332#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17331#L494-24 assume !(1 == ~t7_pc~0); 17329#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 17328#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17327#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17326#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 17325#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17324#L837-3 assume !(1 == ~M_E~0); 17323#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17322#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16664#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17321#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 17320#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 17319#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16735#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 17318#L872-3 assume !(1 == ~E_1~0); 17317#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 17316#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 17315#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17314#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 17313#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 17312#L902-3 assume !(1 == ~E_7~0); 17311#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 16929#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 16921#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 16920#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 16918#L1167 assume !(0 == start_simulation_~tmp~3#1); 16916#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 16734#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 16400#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 16641#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 16679#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16775#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16773#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 16772#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 16598#L1148-2 [2022-10-17 10:16:02,801 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:16:02,801 INFO L85 PathProgramCache]: Analyzing trace with hash 1307665866, now seen corresponding path program 1 times [2022-10-17 10:16:02,801 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:16:02,801 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2038922646] [2022-10-17 10:16:02,802 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:16:02,802 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:16:02,815 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:16:02,853 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:16:02,853 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:16:02,853 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2038922646] [2022-10-17 10:16:02,854 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2038922646] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:16:02,854 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:16:02,854 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-10-17 10:16:02,854 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1199241015] [2022-10-17 10:16:02,854 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:16:02,855 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:16:02,855 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:16:02,856 INFO L85 PathProgramCache]: Analyzing trace with hash -1711278304, now seen corresponding path program 1 times [2022-10-17 10:16:02,856 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:16:02,856 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [431588549] [2022-10-17 10:16:02,856 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:16:02,856 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:16:02,870 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:16:02,908 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:16:02,909 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:16:02,909 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [431588549] [2022-10-17 10:16:02,909 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [431588549] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:16:02,909 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:16:02,910 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:16:02,910 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1657828440] [2022-10-17 10:16:02,910 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:16:02,911 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:16:02,911 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:16:02,911 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:16:02,911 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:16:02,912 INFO L87 Difference]: Start difference. First operand 1448 states and 2122 transitions. cyclomatic complexity: 676 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 2 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:16:03,002 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:16:03,003 INFO L93 Difference]: Finished difference Result 2759 states and 4004 transitions. [2022-10-17 10:16:03,003 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2759 states and 4004 transitions. [2022-10-17 10:16:03,030 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2644 [2022-10-17 10:16:03,055 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2759 states to 2759 states and 4004 transitions. [2022-10-17 10:16:03,055 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2759 [2022-10-17 10:16:03,058 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2759 [2022-10-17 10:16:03,058 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2759 states and 4004 transitions. [2022-10-17 10:16:03,063 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:16:03,063 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2759 states and 4004 transitions. [2022-10-17 10:16:03,067 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2759 states and 4004 transitions. [2022-10-17 10:16:03,117 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2759 to 2645. [2022-10-17 10:16:03,123 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2645 states, 2645 states have (on average 1.454820415879017) internal successors, (3848), 2644 states have internal predecessors, (3848), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:16:03,136 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2645 states to 2645 states and 3848 transitions. [2022-10-17 10:16:03,136 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2645 states and 3848 transitions. [2022-10-17 10:16:03,136 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:16:03,137 INFO L428 stractBuchiCegarLoop]: Abstraction has 2645 states and 3848 transitions. [2022-10-17 10:16:03,137 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-10-17 10:16:03,137 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2645 states and 3848 transitions. [2022-10-17 10:16:03,151 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2530 [2022-10-17 10:16:03,151 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:16:03,151 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:16:03,152 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:16:03,153 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:16:03,153 INFO L748 eck$LassoCheckResult]: Stem: 21016#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 20972#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 20973#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20366#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 20367#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 20819#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20820#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20781#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20687#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20688#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 20679#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 20680#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 20636#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20637#L754 assume !(0 == ~M_E~0); 20944#L754-2 assume !(0 == ~T1_E~0); 20574#L759-1 assume !(0 == ~T2_E~0); 20575#L764-1 assume !(0 == ~T3_E~0); 20991#L769-1 assume !(0 == ~T4_E~0); 20992#L774-1 assume !(0 == ~T5_E~0); 20856#L779-1 assume !(0 == ~T6_E~0); 20606#L784-1 assume !(0 == ~T7_E~0); 20607#L789-1 assume !(0 == ~E_1~0); 20275#L794-1 assume !(0 == ~E_2~0); 20276#L799-1 assume !(0 == ~E_3~0); 20995#L804-1 assume !(0 == ~E_4~0); 20996#L809-1 assume !(0 == ~E_5~0); 20692#L814-1 assume !(0 == ~E_6~0); 20195#L819-1 assume !(0 == ~E_7~0); 20196#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20676#L361 assume !(1 == ~m_pc~0); 20677#L361-2 is_master_triggered_~__retres1~0#1 := 0; 20723#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20485#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 20486#L930 assume !(0 != activate_threads_~tmp~1#1); 20851#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20669#L380 assume !(1 == ~t1_pc~0); 20330#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 20329#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20877#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 20979#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20405#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20331#L399 assume 1 == ~t2_pc~0; 20332#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 20540#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20894#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 20747#L946 assume !(0 != activate_threads_~tmp___1~0#1); 20235#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20203#L418 assume !(1 == ~t3_pc~0); 20164#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 20165#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20696#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 20954#L954 assume !(0 != activate_threads_~tmp___2~0#1); 21004#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20945#L437 assume 1 == ~t4_pc~0; 20946#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 20506#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20334#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 20335#L962 assume !(0 != activate_threads_~tmp___3~0#1); 20792#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20457#L456 assume !(1 == ~t5_pc~0); 20458#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 20571#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20921#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 20222#L970 assume !(0 != activate_threads_~tmp___4~0#1); 20223#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20347#L475 assume 1 == ~t6_pc~0; 20348#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 20426#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20427#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20185#L978 assume !(0 != activate_threads_~tmp___5~0#1); 20186#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20683#L494 assume !(1 == ~t7_pc~0); 20685#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 20731#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20914#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20915#L986 assume !(0 != activate_threads_~tmp___6~0#1); 21011#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20916#L837 assume !(1 == ~M_E~0); 20751#L837-2 assume !(1 == ~T1_E~0); 20312#L842-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20313#L847-1 assume !(1 == ~T3_E~0); 20907#L852-1 assume !(1 == ~T4_E~0); 20908#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20761#L862-1 assume !(1 == ~T6_E~0); 20762#L867-1 assume !(1 == ~T7_E~0); 20772#L872-1 assume !(1 == ~E_1~0); 20855#L877-1 assume !(1 == ~E_2~0); 20768#L882-1 assume !(1 == ~E_3~0); 20769#L887-1 assume !(1 == ~E_4~0); 20372#L892-1 assume !(1 == ~E_5~0); 20373#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 20786#L902-1 assume !(1 == ~E_7~0); 20787#L907-1 assume { :end_inline_reset_delta_events } true; 21237#L1148-2 [2022-10-17 10:16:03,153 INFO L750 eck$LassoCheckResult]: Loop: 21237#L1148-2 assume !false; 21238#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21226#L729 assume !false; 21227#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 21109#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 21105#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 21090#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 21091#L626 assume !(0 != eval_~tmp~0#1); 21470#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21468#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21466#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 21464#L754-5 assume !(0 == ~T1_E~0); 21461#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 21462#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21971#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21970#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 21969#L779-3 assume !(0 == ~T6_E~0); 21968#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 21967#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 21966#L794-3 assume !(0 == ~E_2~0); 21965#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 21964#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 21963#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 21962#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 21961#L819-3 assume !(0 == ~E_7~0); 21960#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21959#L361-24 assume !(1 == ~m_pc~0); 21958#L361-26 is_master_triggered_~__retres1~0#1 := 0; 21957#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21956#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 21955#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 21954#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21433#L380-24 assume !(1 == ~t1_pc~0); 21434#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 21943#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21942#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 21941#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 21940#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21939#L399-24 assume 1 == ~t2_pc~0; 21937#L400-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 21936#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21935#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 21934#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 21406#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21407#L418-24 assume !(1 == ~t3_pc~0); 21927#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 21926#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21925#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 21924#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 21923#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21387#L437-24 assume 1 == ~t4_pc~0; 21384#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21383#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21380#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 21378#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 21375#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21376#L456-24 assume !(1 == ~t5_pc~0); 21368#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 21366#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21362#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 21363#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 21903#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21353#L475-24 assume !(1 == ~t6_pc~0); 21354#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 21345#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21343#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 21340#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 21341#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21335#L494-24 assume !(1 == ~t7_pc~0); 21332#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 21329#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21327#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 21325#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 21323#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21321#L837-3 assume !(1 == ~M_E~0); 21318#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21316#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 21314#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21312#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 21310#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 21308#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 21306#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 21304#L872-3 assume !(1 == ~E_1~0); 21301#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 21302#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 21294#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 21295#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 21287#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 21288#L902-3 assume !(1 == ~E_7~0); 21281#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 21282#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 21548#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 21547#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 21545#L1167 assume !(0 == start_simulation_~tmp~3#1); 21544#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 21540#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 21535#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 21534#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 21533#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 21532#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 21243#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 21244#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 21237#L1148-2 [2022-10-17 10:16:03,154 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:16:03,154 INFO L85 PathProgramCache]: Analyzing trace with hash 2012584553, now seen corresponding path program 1 times [2022-10-17 10:16:03,154 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:16:03,155 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1153926962] [2022-10-17 10:16:03,155 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:16:03,155 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:16:03,168 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:16:03,220 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:16:03,220 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:16:03,220 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1153926962] [2022-10-17 10:16:03,220 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1153926962] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:16:03,220 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:16:03,220 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-10-17 10:16:03,221 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [541956609] [2022-10-17 10:16:03,221 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:16:03,221 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:16:03,221 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:16:03,221 INFO L85 PathProgramCache]: Analyzing trace with hash 1754793277, now seen corresponding path program 1 times [2022-10-17 10:16:03,222 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:16:03,222 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [504002452] [2022-10-17 10:16:03,222 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:16:03,222 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:16:03,234 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:16:03,269 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:16:03,270 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:16:03,270 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [504002452] [2022-10-17 10:16:03,270 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [504002452] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:16:03,270 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:16:03,270 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:16:03,270 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [708262818] [2022-10-17 10:16:03,270 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:16:03,271 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:16:03,271 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:16:03,272 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-10-17 10:16:03,272 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-10-17 10:16:03,272 INFO L87 Difference]: Start difference. First operand 2645 states and 3848 transitions. cyclomatic complexity: 1207 Second operand has 5 states, 5 states have (on average 18.6) internal successors, (93), 5 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:16:03,601 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:16:03,601 INFO L93 Difference]: Finished difference Result 7326 states and 10627 transitions. [2022-10-17 10:16:03,602 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7326 states and 10627 transitions. [2022-10-17 10:16:03,658 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 7060 [2022-10-17 10:16:03,731 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7326 states to 7326 states and 10627 transitions. [2022-10-17 10:16:03,731 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7326 [2022-10-17 10:16:03,743 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7326 [2022-10-17 10:16:03,743 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7326 states and 10627 transitions. [2022-10-17 10:16:03,755 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:16:03,755 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7326 states and 10627 transitions. [2022-10-17 10:16:03,765 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7326 states and 10627 transitions. [2022-10-17 10:16:03,860 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7326 to 2750. [2022-10-17 10:16:03,866 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2750 states, 2750 states have (on average 1.4374545454545455) internal successors, (3953), 2749 states have internal predecessors, (3953), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:16:03,876 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2750 states to 2750 states and 3953 transitions. [2022-10-17 10:16:03,877 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2750 states and 3953 transitions. [2022-10-17 10:16:03,877 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-10-17 10:16:03,878 INFO L428 stractBuchiCegarLoop]: Abstraction has 2750 states and 3953 transitions. [2022-10-17 10:16:03,878 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-10-17 10:16:03,878 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2750 states and 3953 transitions. [2022-10-17 10:16:03,904 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2632 [2022-10-17 10:16:03,905 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:16:03,905 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:16:03,906 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:16:03,906 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:16:03,907 INFO L748 eck$LassoCheckResult]: Stem: 31067#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 31006#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 31007#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 30353#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 30354#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 30833#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 30834#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 30789#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 30691#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 30692#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 30683#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 30684#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 30638#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 30639#L754 assume !(0 == ~M_E~0); 30966#L754-2 assume !(0 == ~T1_E~0); 30567#L759-1 assume !(0 == ~T2_E~0); 30568#L764-1 assume !(0 == ~T3_E~0); 31030#L769-1 assume !(0 == ~T4_E~0); 31031#L774-1 assume !(0 == ~T5_E~0); 30872#L779-1 assume !(0 == ~T6_E~0); 30604#L784-1 assume !(0 == ~T7_E~0); 30605#L789-1 assume !(0 == ~E_1~0); 30260#L794-1 assume !(0 == ~E_2~0); 30261#L799-1 assume !(0 == ~E_3~0); 31036#L804-1 assume !(0 == ~E_4~0); 31037#L809-1 assume !(0 == ~E_5~0); 30696#L814-1 assume !(0 == ~E_6~0); 30179#L819-1 assume !(0 == ~E_7~0); 30180#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30679#L361 assume !(1 == ~m_pc~0); 30680#L361-2 is_master_triggered_~__retres1~0#1 := 0; 30726#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30477#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 30478#L930 assume !(0 != activate_threads_~tmp~1#1); 30867#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30673#L380 assume !(1 == ~t1_pc~0); 30317#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 30894#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30895#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 31066#L938 assume !(0 != activate_threads_~tmp___0~0#1); 30395#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30318#L399 assume 1 == ~t2_pc~0; 30319#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 30533#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30912#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 30750#L946 assume !(0 != activate_threads_~tmp___1~0#1); 30219#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30187#L418 assume !(1 == ~t3_pc~0); 30148#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 30149#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30700#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 30987#L954 assume !(0 != activate_threads_~tmp___2~0#1); 31052#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30968#L437 assume 1 == ~t4_pc~0; 30969#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 30500#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30321#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 30322#L962 assume !(0 != activate_threads_~tmp___3~0#1); 30800#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30449#L456 assume !(1 == ~t5_pc~0); 30450#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 30564#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30939#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 30206#L970 assume !(0 != activate_threads_~tmp___4~0#1); 30207#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 30334#L475 assume 1 == ~t6_pc~0; 30335#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 30416#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 30417#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 30169#L978 assume !(0 != activate_threads_~tmp___5~0#1); 30170#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 30687#L494 assume !(1 == ~t7_pc~0); 30689#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 30732#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30932#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 30933#L986 assume !(0 != activate_threads_~tmp___6~0#1); 31063#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30934#L837 assume !(1 == ~M_E~0); 30753#L837-2 assume !(1 == ~T1_E~0); 30298#L842-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30299#L847-1 assume !(1 == ~T3_E~0); 30824#L852-1 assume !(1 == ~T4_E~0); 30927#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 30763#L862-1 assume !(1 == ~T6_E~0); 30764#L867-1 assume !(1 == ~T7_E~0); 30775#L872-1 assume !(1 == ~E_1~0); 30871#L877-1 assume !(1 == ~E_2~0); 30771#L882-1 assume !(1 == ~E_3~0); 30772#L887-1 assume !(1 == ~E_4~0); 30360#L892-1 assume !(1 == ~E_5~0); 30361#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 30793#L902-1 assume !(1 == ~E_7~0); 30794#L907-1 assume { :end_inline_reset_delta_events } true; 31482#L1148-2 [2022-10-17 10:16:03,907 INFO L750 eck$LassoCheckResult]: Loop: 31482#L1148-2 assume !false; 31483#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 31816#L729 assume !false; 31815#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 31145#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 31141#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 31134#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 31135#L626 assume !(0 != eval_~tmp~0#1); 31806#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 31804#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 31802#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 31800#L754-5 assume !(0 == ~T1_E~0); 31797#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 31798#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 32236#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 32235#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 32234#L779-3 assume !(0 == ~T6_E~0); 32233#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 32232#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 32231#L794-3 assume !(0 == ~E_2~0); 32230#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 32229#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 32228#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 32227#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 32226#L819-3 assume !(0 == ~E_7~0); 32225#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30868#L361-24 assume !(1 == ~m_pc~0); 30869#L361-26 is_master_triggered_~__retres1~0#1 := 0; 30990#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30191#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 30192#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 32223#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31668#L380-24 assume !(1 == ~t1_pc~0); 31669#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 30863#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30864#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 30699#L938-24 assume !(0 != activate_threads_~tmp___0~0#1); 30323#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30324#L399-24 assume 1 == ~t2_pc~0; 30547#L400-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 30603#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30364#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 30365#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 30693#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30694#L418-24 assume 1 == ~t3_pc~0; 30697#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30269#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30695#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 30551#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30211#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30212#L437-24 assume 1 == ~t4_pc~0; 30493#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 30494#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30366#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 30367#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 30524#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30899#L456-24 assume 1 == ~t5_pc~0; 30900#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 32199#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 32198#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 32197#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 32196#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 32195#L475-24 assume 1 == ~t6_pc~0; 32193#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 32192#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 32191#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 32190#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 32189#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 32188#L494-24 assume !(1 == ~t7_pc~0); 32186#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 32185#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 32184#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 32183#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 32182#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32181#L837-3 assume !(1 == ~M_E~0); 32180#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 32179#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30937#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 32178#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 32177#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 32176#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 31045#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 32175#L872-3 assume !(1 == ~E_1~0); 32174#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 32173#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 32172#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 32171#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 32170#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 32169#L902-3 assume !(1 == ~E_7~0); 32168#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 32166#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 32159#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 32158#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 32156#L1167 assume !(0 == start_simulation_~tmp~3#1); 32154#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 32148#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 32143#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 32142#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 32141#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 31490#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 31487#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 31488#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 31482#L1148-2 [2022-10-17 10:16:03,908 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:16:03,908 INFO L85 PathProgramCache]: Analyzing trace with hash -1406363737, now seen corresponding path program 1 times [2022-10-17 10:16:03,908 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:16:03,909 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1860510530] [2022-10-17 10:16:03,909 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:16:03,909 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:16:03,920 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:16:03,976 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:16:03,976 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:16:03,976 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1860510530] [2022-10-17 10:16:03,979 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1860510530] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:16:03,979 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:16:03,979 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:16:03,980 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [495900870] [2022-10-17 10:16:03,981 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:16:03,981 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:16:03,981 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:16:03,982 INFO L85 PathProgramCache]: Analyzing trace with hash -1222480482, now seen corresponding path program 1 times [2022-10-17 10:16:03,982 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:16:03,982 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1869799371] [2022-10-17 10:16:03,982 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:16:03,982 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:16:04,001 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:16:04,038 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:16:04,038 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:16:04,038 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1869799371] [2022-10-17 10:16:04,038 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1869799371] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:16:04,038 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:16:04,039 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:16:04,039 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [319161910] [2022-10-17 10:16:04,039 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:16:04,040 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:16:04,040 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:16:04,057 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-10-17 10:16:04,057 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-10-17 10:16:04,057 INFO L87 Difference]: Start difference. First operand 2750 states and 3953 transitions. cyclomatic complexity: 1207 Second operand has 4 states, 4 states have (on average 23.25) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:16:04,285 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:16:04,285 INFO L93 Difference]: Finished difference Result 6499 states and 9249 transitions. [2022-10-17 10:16:04,285 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6499 states and 9249 transitions. [2022-10-17 10:16:04,332 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 6246 [2022-10-17 10:16:04,384 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6499 states to 6499 states and 9249 transitions. [2022-10-17 10:16:04,384 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6499 [2022-10-17 10:16:04,391 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6499 [2022-10-17 10:16:04,392 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6499 states and 9249 transitions. [2022-10-17 10:16:04,402 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:16:04,402 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6499 states and 9249 transitions. [2022-10-17 10:16:04,411 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6499 states and 9249 transitions. [2022-10-17 10:16:04,529 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6499 to 5099. [2022-10-17 10:16:04,540 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5099 states, 5099 states have (on average 1.4300843302608355) internal successors, (7292), 5098 states have internal predecessors, (7292), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:16:04,571 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5099 states to 5099 states and 7292 transitions. [2022-10-17 10:16:04,572 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5099 states and 7292 transitions. [2022-10-17 10:16:04,572 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-10-17 10:16:04,573 INFO L428 stractBuchiCegarLoop]: Abstraction has 5099 states and 7292 transitions. [2022-10-17 10:16:04,573 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-10-17 10:16:04,573 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5099 states and 7292 transitions. [2022-10-17 10:16:04,597 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4980 [2022-10-17 10:16:04,598 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:16:04,598 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:16:04,599 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:16:04,600 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:16:04,600 INFO L748 eck$LassoCheckResult]: Stem: 40277#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 40230#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 40231#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 39611#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 39612#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 40067#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 40068#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 40030#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 39939#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 39940#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 39931#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 39932#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 39890#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 39891#L754 assume !(0 == ~M_E~0); 40191#L754-2 assume !(0 == ~T1_E~0); 39819#L759-1 assume !(0 == ~T2_E~0); 39820#L764-1 assume !(0 == ~T3_E~0); 40245#L769-1 assume !(0 == ~T4_E~0); 40246#L774-1 assume !(0 == ~T5_E~0); 40100#L779-1 assume !(0 == ~T6_E~0); 39857#L784-1 assume !(0 == ~T7_E~0); 39858#L789-1 assume !(0 == ~E_1~0); 39519#L794-1 assume !(0 == ~E_2~0); 39520#L799-1 assume !(0 == ~E_3~0); 40248#L804-1 assume !(0 == ~E_4~0); 40249#L809-1 assume !(0 == ~E_5~0); 39944#L814-1 assume !(0 == ~E_6~0); 39438#L819-1 assume !(0 == ~E_7~0); 39439#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 39928#L361 assume !(1 == ~m_pc~0); 39929#L361-2 is_master_triggered_~__retres1~0#1 := 0; 39969#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39734#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 39735#L930 assume !(0 != activate_threads_~tmp~1#1); 40096#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 39922#L380 assume !(1 == ~t1_pc~0); 39575#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 40121#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40122#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 40238#L938 assume !(0 != activate_threads_~tmp___0~0#1); 39652#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 39576#L399 assume !(1 == ~t2_pc~0); 39577#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 39790#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40134#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 39993#L946 assume !(0 != activate_threads_~tmp___1~0#1); 39478#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39446#L418 assume !(1 == ~t3_pc~0); 39407#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 39408#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 39948#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 40207#L954 assume !(0 != activate_threads_~tmp___2~0#1); 40264#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40193#L437 assume 1 == ~t4_pc~0; 40194#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 39755#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39578#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 39579#L962 assume !(0 != activate_threads_~tmp___3~0#1); 40040#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 39704#L456 assume !(1 == ~t5_pc~0); 39705#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 39816#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 40169#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 39465#L970 assume !(0 != activate_threads_~tmp___4~0#1); 39466#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 39591#L475 assume 1 == ~t6_pc~0; 39592#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 39671#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 39672#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 39428#L978 assume !(0 != activate_threads_~tmp___5~0#1); 39429#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 39935#L494 assume !(1 == ~t7_pc~0); 39937#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 39977#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 40159#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 40160#L986 assume !(0 != activate_threads_~tmp___6~0#1); 40273#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40161#L837 assume !(1 == ~M_E~0); 39996#L837-2 assume !(1 == ~T1_E~0); 39557#L842-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 39558#L847-1 assume !(1 == ~T3_E~0); 40064#L852-1 assume !(1 == ~T4_E~0); 40285#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 40286#L862-1 assume !(1 == ~T6_E~0); 40006#L867-1 assume !(1 == ~T7_E~0); 40020#L872-1 assume !(1 == ~E_1~0); 40283#L877-1 assume !(1 == ~E_2~0); 40284#L882-1 assume !(1 == ~E_3~0); 40219#L887-1 assume !(1 == ~E_4~0); 40220#L892-1 assume !(1 == ~E_5~0); 40147#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 40148#L902-1 assume !(1 == ~E_7~0); 39700#L907-1 assume { :end_inline_reset_delta_events } true; 39701#L1148-2 [2022-10-17 10:16:04,601 INFO L750 eck$LassoCheckResult]: Loop: 39701#L1148-2 assume !false; 39440#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 39441#L729 assume !false; 39852#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 39846#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 39796#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 39872#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 39915#L626 assume !(0 != eval_~tmp~0#1); 39916#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 40065#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 39952#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 39479#L754-5 assume !(0 == ~T1_E~0); 39480#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 44120#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 44202#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 44201#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 44200#L779-3 assume !(0 == ~T6_E~0); 44199#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 44198#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 44197#L794-3 assume !(0 == ~E_2~0); 44196#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 44195#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 44194#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 44193#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 44192#L819-3 assume !(0 == ~E_7~0); 44191#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 44190#L361-24 assume !(1 == ~m_pc~0); 44189#L361-26 is_master_triggered_~__retres1~0#1 := 0; 44188#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 44187#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 44186#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 44185#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44184#L380-24 assume !(1 == ~t1_pc~0); 44181#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 44179#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44178#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 44177#L938-24 assume !(0 != activate_threads_~tmp___0~0#1); 44175#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 44174#L399-24 assume !(1 == ~t2_pc~0); 42405#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 44173#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 44172#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 44171#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 44170#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 44169#L418-24 assume !(1 == ~t3_pc~0); 44167#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 44166#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 44165#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 44164#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 44163#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44162#L437-24 assume 1 == ~t4_pc~0; 44160#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 44159#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 44158#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 44157#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 44156#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 44155#L456-24 assume !(1 == ~t5_pc~0); 44153#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 44152#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 44151#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 44150#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 44149#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 44148#L475-24 assume 1 == ~t6_pc~0; 44146#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 44145#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 44144#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 44143#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 44142#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 44141#L494-24 assume !(1 == ~t7_pc~0); 44139#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 44138#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 44137#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 44136#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 44135#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44134#L837-3 assume !(1 == ~M_E~0); 44133#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 44132#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 40164#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 44131#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 44130#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 44092#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 40211#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 40117#L872-3 assume !(1 == ~E_1~0); 40118#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 40216#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 40242#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 39837#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 39832#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 39833#L902-3 assume !(1 == ~E_7~0); 40031#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 40023#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 39445#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 40267#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 40189#L1167 assume !(0 == start_simulation_~tmp~3#1); 40062#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 40089#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 39868#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 40133#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 40182#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 40075#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 39421#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 39422#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 39701#L1148-2 [2022-10-17 10:16:04,602 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:16:04,602 INFO L85 PathProgramCache]: Analyzing trace with hash -2107931962, now seen corresponding path program 1 times [2022-10-17 10:16:04,602 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:16:04,602 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1510171012] [2022-10-17 10:16:04,602 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:16:04,603 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:16:04,624 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:16:04,670 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:16:04,671 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:16:04,671 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1510171012] [2022-10-17 10:16:04,671 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1510171012] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:16:04,671 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:16:04,671 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-10-17 10:16:04,672 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2075376251] [2022-10-17 10:16:04,672 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:16:04,673 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:16:04,673 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:16:04,674 INFO L85 PathProgramCache]: Analyzing trace with hash 1327753339, now seen corresponding path program 1 times [2022-10-17 10:16:04,674 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:16:04,674 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1778680008] [2022-10-17 10:16:04,674 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:16:04,674 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:16:04,686 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:16:04,718 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:16:04,718 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:16:04,718 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1778680008] [2022-10-17 10:16:04,718 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1778680008] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:16:04,718 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:16:04,719 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:16:04,719 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [17063502] [2022-10-17 10:16:04,719 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:16:04,720 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:16:04,720 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:16:04,720 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:16:04,721 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:16:04,721 INFO L87 Difference]: Start difference. First operand 5099 states and 7292 transitions. cyclomatic complexity: 2197 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 2 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:16:04,913 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:16:04,913 INFO L93 Difference]: Finished difference Result 9538 states and 13577 transitions. [2022-10-17 10:16:04,914 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9538 states and 13577 transitions. [2022-10-17 10:16:04,998 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 9400 [2022-10-17 10:16:05,072 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9538 states to 9538 states and 13577 transitions. [2022-10-17 10:16:05,073 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9538 [2022-10-17 10:16:05,084 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9538 [2022-10-17 10:16:05,084 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9538 states and 13577 transitions. [2022-10-17 10:16:05,100 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:16:05,100 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9538 states and 13577 transitions. [2022-10-17 10:16:05,115 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9538 states and 13577 transitions. [2022-10-17 10:16:05,277 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9538 to 9522. [2022-10-17 10:16:05,309 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9522 states, 9522 states have (on average 1.424175593362739) internal successors, (13561), 9521 states have internal predecessors, (13561), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:16:05,363 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9522 states to 9522 states and 13561 transitions. [2022-10-17 10:16:05,364 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9522 states and 13561 transitions. [2022-10-17 10:16:05,364 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:16:05,365 INFO L428 stractBuchiCegarLoop]: Abstraction has 9522 states and 13561 transitions. [2022-10-17 10:16:05,365 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-10-17 10:16:05,365 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9522 states and 13561 transitions. [2022-10-17 10:16:05,437 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 9384 [2022-10-17 10:16:05,438 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:16:05,438 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:16:05,440 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:16:05,440 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:16:05,440 INFO L748 eck$LassoCheckResult]: Stem: 54938#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 54883#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 54884#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 54250#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 54251#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 54718#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 54719#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 54679#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 54586#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 54587#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 54577#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 54578#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 54533#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 54534#L754 assume !(0 == ~M_E~0); 54844#L754-2 assume !(0 == ~T1_E~0); 54462#L759-1 assume !(0 == ~T2_E~0); 54463#L764-1 assume !(0 == ~T3_E~0); 54905#L769-1 assume !(0 == ~T4_E~0); 54906#L774-1 assume !(0 == ~T5_E~0); 54754#L779-1 assume !(0 == ~T6_E~0); 54499#L784-1 assume !(0 == ~T7_E~0); 54500#L789-1 assume !(0 == ~E_1~0); 54164#L794-1 assume !(0 == ~E_2~0); 54165#L799-1 assume !(0 == ~E_3~0); 54907#L804-1 assume !(0 == ~E_4~0); 54908#L809-1 assume !(0 == ~E_5~0); 54590#L814-1 assume !(0 == ~E_6~0); 54084#L819-1 assume !(0 == ~E_7~0); 54085#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 54572#L361 assume !(1 == ~m_pc~0); 54573#L361-2 is_master_triggered_~__retres1~0#1 := 0; 54618#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 54376#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 54377#L930 assume !(0 != activate_threads_~tmp~1#1); 54749#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 54565#L380 assume !(1 == ~t1_pc~0); 54215#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 54777#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 54778#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 54896#L938 assume !(0 != activate_threads_~tmp___0~0#1); 54293#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 54216#L399 assume !(1 == ~t2_pc~0); 54217#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 54433#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 54791#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 54642#L946 assume !(0 != activate_threads_~tmp___1~0#1); 54120#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 54091#L418 assume !(1 == ~t3_pc~0); 54051#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 54052#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 54595#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 54859#L954 assume !(0 != activate_threads_~tmp___2~0#1); 54923#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 54847#L437 assume !(1 == ~t4_pc~0); 54721#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 54400#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 54218#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 54219#L962 assume !(0 != activate_threads_~tmp___3~0#1); 54688#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 54351#L456 assume !(1 == ~t5_pc~0); 54352#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 54459#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 54821#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 54110#L970 assume !(0 != activate_threads_~tmp___4~0#1); 54111#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 54234#L475 assume 1 == ~t6_pc~0; 54235#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 54314#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 54315#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 54072#L978 assume !(0 != activate_threads_~tmp___5~0#1); 54073#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 54579#L494 assume !(1 == ~t7_pc~0); 54581#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 54626#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 54813#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 54814#L986 assume !(0 != activate_threads_~tmp___6~0#1); 54932#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54815#L837 assume !(1 == ~M_E~0); 54645#L837-2 assume !(1 == ~T1_E~0); 54197#L842-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 54198#L847-1 assume !(1 == ~T3_E~0); 56920#L852-1 assume !(1 == ~T4_E~0); 56919#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 56918#L862-1 assume !(1 == ~T6_E~0); 54656#L867-1 assume !(1 == ~T7_E~0); 56917#L872-1 assume !(1 == ~E_1~0); 56916#L877-1 assume !(1 == ~E_2~0); 56915#L882-1 assume !(1 == ~E_3~0); 56914#L887-1 assume !(1 == ~E_4~0); 54258#L892-1 assume !(1 == ~E_5~0); 54259#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 54685#L902-1 assume !(1 == ~E_7~0); 54342#L907-1 assume { :end_inline_reset_delta_events } true; 54343#L1148-2 [2022-10-17 10:16:05,441 INFO L750 eck$LassoCheckResult]: Loop: 54343#L1148-2 assume !false; 54082#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 54083#L729 assume !false; 54496#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 54490#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 54439#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 54514#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 54559#L626 assume !(0 != eval_~tmp~0#1); 54560#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 54716#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 54598#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 54121#L754-5 assume !(0 == ~T1_E~0); 54122#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 54525#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 54725#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 54726#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 54444#L779-3 assume !(0 == ~T6_E~0); 54097#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 54098#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 54080#L794-3 assume !(0 == ~E_2~0); 54081#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 54176#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 54604#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 54172#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 54173#L819-3 assume !(0 == ~E_7~0); 54380#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 54381#L361-24 assume !(1 == ~m_pc~0); 54531#L361-26 is_master_triggered_~__retres1~0#1 := 0; 54532#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 54092#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 54093#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 54672#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 54673#L380-24 assume 1 == ~t1_pc~0; 54674#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 54676#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 54745#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 62947#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 54220#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 54221#L399-24 assume !(1 == ~t2_pc~0); 54445#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 54498#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 54262#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 54263#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 54583#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 54584#L418-24 assume !(1 == ~t3_pc~0); 54168#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 54169#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 54585#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 54447#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 54112#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 54113#L437-24 assume !(1 == ~t4_pc~0); 54612#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 54915#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 54264#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 54265#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 54426#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 54780#L456-24 assume 1 == ~t5_pc~0; 54781#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 54867#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 54488#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 54489#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 54653#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 54819#L475-24 assume 1 == ~t6_pc~0; 54114#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 54115#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 54874#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 63344#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 63343#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 54868#L494-24 assume !(1 == ~t7_pc~0); 54663#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 54639#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 54520#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 54521#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 54388#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54389#L837-3 assume !(1 == ~M_E~0); 54478#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 54810#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 54709#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 54101#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 54102#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 54873#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 54861#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 54771#L872-3 assume !(1 == ~E_1~0); 54772#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 54865#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 54900#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 54481#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 54474#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 54475#L902-3 assume !(1 == ~E_7~0); 54680#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 54670#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 54087#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 54929#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 54841#L1167 assume !(0 == start_simulation_~tmp~3#1); 54710#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 54742#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 54504#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 54790#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 54834#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 54727#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 54065#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 54066#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 54343#L1148-2 [2022-10-17 10:16:05,442 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:16:05,442 INFO L85 PathProgramCache]: Analyzing trace with hash -1707940763, now seen corresponding path program 1 times [2022-10-17 10:16:05,443 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:16:05,443 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [833616284] [2022-10-17 10:16:05,443 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:16:05,443 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:16:05,460 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:16:05,527 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:16:05,527 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:16:05,528 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [833616284] [2022-10-17 10:16:05,528 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [833616284] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:16:05,528 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:16:05,528 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:16:05,528 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1859618136] [2022-10-17 10:16:05,528 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:16:05,529 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:16:05,529 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:16:05,529 INFO L85 PathProgramCache]: Analyzing trace with hash 1759400862, now seen corresponding path program 1 times [2022-10-17 10:16:05,530 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:16:05,530 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1285541911] [2022-10-17 10:16:05,530 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:16:05,530 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:16:05,543 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:16:05,579 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:16:05,580 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:16:05,580 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1285541911] [2022-10-17 10:16:05,580 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1285541911] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:16:05,580 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:16:05,580 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:16:05,581 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1607518842] [2022-10-17 10:16:05,581 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:16:05,581 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:16:05,581 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:16:05,582 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-10-17 10:16:05,582 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-10-17 10:16:05,583 INFO L87 Difference]: Start difference. First operand 9522 states and 13561 transitions. cyclomatic complexity: 4047 Second operand has 4 states, 4 states have (on average 23.25) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:16:05,867 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:16:05,867 INFO L93 Difference]: Finished difference Result 22429 states and 31670 transitions. [2022-10-17 10:16:05,867 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22429 states and 31670 transitions. [2022-10-17 10:16:06,008 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 21732 [2022-10-17 10:16:06,104 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22429 states to 22429 states and 31670 transitions. [2022-10-17 10:16:06,105 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22429 [2022-10-17 10:16:06,130 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22429 [2022-10-17 10:16:06,131 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22429 states and 31670 transitions. [2022-10-17 10:16:06,158 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:16:06,158 INFO L218 hiAutomatonCegarLoop]: Abstraction has 22429 states and 31670 transitions. [2022-10-17 10:16:06,277 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22429 states and 31670 transitions. [2022-10-17 10:16:06,547 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22429 to 17825. [2022-10-17 10:16:06,709 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17825 states, 17825 states have (on average 1.418569424964937) internal successors, (25286), 17824 states have internal predecessors, (25286), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:16:06,774 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17825 states to 17825 states and 25286 transitions. [2022-10-17 10:16:06,774 INFO L240 hiAutomatonCegarLoop]: Abstraction has 17825 states and 25286 transitions. [2022-10-17 10:16:06,774 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-10-17 10:16:06,775 INFO L428 stractBuchiCegarLoop]: Abstraction has 17825 states and 25286 transitions. [2022-10-17 10:16:06,775 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-10-17 10:16:06,775 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17825 states and 25286 transitions. [2022-10-17 10:16:06,855 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 17664 [2022-10-17 10:16:06,855 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:16:06,855 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:16:06,858 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:16:06,858 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:16:06,858 INFO L748 eck$LassoCheckResult]: Stem: 86891#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 86840#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 86841#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 86213#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 86214#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 86675#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 86676#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 86631#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 86544#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 86545#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 86535#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 86536#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 86492#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 86493#L754 assume !(0 == ~M_E~0); 86806#L754-2 assume !(0 == ~T1_E~0); 86416#L759-1 assume !(0 == ~T2_E~0); 86417#L764-1 assume !(0 == ~T3_E~0); 86858#L769-1 assume !(0 == ~T4_E~0); 86859#L774-1 assume !(0 == ~T5_E~0); 86714#L779-1 assume !(0 == ~T6_E~0); 86458#L784-1 assume !(0 == ~T7_E~0); 86459#L789-1 assume !(0 == ~E_1~0); 86126#L794-1 assume !(0 == ~E_2~0); 86127#L799-1 assume !(0 == ~E_3~0); 86860#L804-1 assume !(0 == ~E_4~0); 86861#L809-1 assume !(0 == ~E_5~0); 86548#L814-1 assume !(0 == ~E_6~0); 86046#L819-1 assume !(0 == ~E_7~0); 86047#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 86530#L361 assume !(1 == ~m_pc~0); 86531#L361-2 is_master_triggered_~__retres1~0#1 := 0; 86573#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 86329#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 86330#L930 assume !(0 != activate_threads_~tmp~1#1); 86708#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 86523#L380 assume !(1 == ~t1_pc~0); 86179#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 86735#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 86736#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 86848#L938 assume !(0 != activate_threads_~tmp___0~0#1); 86252#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 86180#L399 assume !(1 == ~t2_pc~0); 86181#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 86386#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 86749#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 86597#L946 assume !(0 != activate_threads_~tmp___1~0#1); 86082#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 86053#L418 assume !(1 == ~t3_pc~0); 86012#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 86013#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 86552#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 86819#L954 assume !(0 != activate_threads_~tmp___2~0#1); 86876#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 86812#L437 assume !(1 == ~t4_pc~0); 86679#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 86352#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 86182#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 86183#L962 assume !(0 != activate_threads_~tmp___3~0#1); 86643#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 86306#L456 assume !(1 == ~t5_pc~0); 86307#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 86413#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 86779#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 86072#L970 assume !(0 != activate_threads_~tmp___4~0#1); 86073#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 86198#L475 assume !(1 == ~t6_pc~0); 86199#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 86271#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 86272#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 86033#L978 assume !(0 != activate_threads_~tmp___5~0#1); 86034#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 86537#L494 assume !(1 == ~t7_pc~0); 86539#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 86581#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 86774#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 86775#L986 assume !(0 != activate_threads_~tmp___6~0#1); 86886#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 86776#L837 assume !(1 == ~M_E~0); 86600#L837-2 assume !(1 == ~T1_E~0); 86160#L842-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 86161#L847-1 assume !(1 == ~T3_E~0); 86669#L852-1 assume !(1 == ~T4_E~0); 86767#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 86609#L862-1 assume !(1 == ~T6_E~0); 86610#L867-1 assume !(1 == ~T7_E~0); 86621#L872-1 assume !(1 == ~E_1~0); 86711#L877-1 assume !(1 == ~E_2~0); 86617#L882-1 assume !(1 == ~E_3~0); 86618#L887-1 assume !(1 == ~E_4~0); 86219#L892-1 assume !(1 == ~E_5~0); 86220#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 86764#L902-1 assume !(1 == ~E_7~0); 86299#L907-1 assume { :end_inline_reset_delta_events } true; 86300#L1148-2 [2022-10-17 10:16:06,859 INFO L750 eck$LassoCheckResult]: Loop: 86300#L1148-2 assume !false; 95745#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 95743#L729 assume !false; 95740#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 95731#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 95725#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 95723#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 95720#L626 assume !(0 != eval_~tmp~0#1); 95721#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 103808#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 103806#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 103804#L754-5 assume !(0 == ~T1_E~0); 103802#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 103800#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 103796#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 103794#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 103793#L779-3 assume !(0 == ~T6_E~0); 103792#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 103759#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 86042#L794-3 assume !(0 == ~E_2~0); 86043#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 86141#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 86560#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 86136#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 86137#L819-3 assume !(0 == ~E_7~0); 86332#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 86333#L361-24 assume !(1 == ~m_pc~0); 86489#L361-26 is_master_triggered_~__retres1~0#1 := 0; 86490#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 86054#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 86055#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 86553#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 86624#L380-24 assume 1 == ~t1_pc~0; 86625#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 86626#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 103696#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 103695#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 86184#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 86185#L399-24 assume !(1 == ~t2_pc~0); 86399#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 86457#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 86223#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 86224#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 102118#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 101989#L418-24 assume !(1 == ~t3_pc~0); 101987#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 101985#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 101983#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 101981#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 101979#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 101977#L437-24 assume !(1 == ~t4_pc~0); 101975#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 101972#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 101970#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 101968#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 101966#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 101964#L456-24 assume !(1 == ~t5_pc~0); 101961#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 101959#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 101957#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 101955#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 101953#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 101951#L475-24 assume !(1 == ~t6_pc~0); 90832#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 101947#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 101945#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 101943#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 101941#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 101939#L494-24 assume !(1 == ~t7_pc~0); 101936#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 101935#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 101933#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 101931#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 101929#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 101927#L837-3 assume !(1 == ~M_E~0); 101924#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 101922#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 95864#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 101919#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 101917#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 101915#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 95855#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 101912#L872-3 assume !(1 == ~E_1~0); 101910#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 101909#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 101907#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 101905#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 101903#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 101902#L902-3 assume !(1 == ~E_7~0); 101900#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 101894#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 101886#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 101884#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 101883#L1167 assume !(0 == start_simulation_~tmp~3#1); 101881#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 101873#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 101867#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 101866#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 101865#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 101864#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 101863#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 101862#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 86300#L1148-2 [2022-10-17 10:16:06,860 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:16:06,860 INFO L85 PathProgramCache]: Analyzing trace with hash -2016379772, now seen corresponding path program 1 times [2022-10-17 10:16:06,860 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:16:06,860 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2021442751] [2022-10-17 10:16:06,861 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:16:06,861 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:16:06,965 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:16:07,011 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:16:07,012 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:16:07,012 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2021442751] [2022-10-17 10:16:07,012 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2021442751] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:16:07,012 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:16:07,012 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-10-17 10:16:07,013 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1631539005] [2022-10-17 10:16:07,013 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:16:07,013 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:16:07,013 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:16:07,014 INFO L85 PathProgramCache]: Analyzing trace with hash 851387292, now seen corresponding path program 1 times [2022-10-17 10:16:07,014 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:16:07,014 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [734870533] [2022-10-17 10:16:07,014 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:16:07,014 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:16:07,026 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:16:07,059 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:16:07,060 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:16:07,060 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [734870533] [2022-10-17 10:16:07,060 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [734870533] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:16:07,060 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:16:07,060 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:16:07,061 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1460123308] [2022-10-17 10:16:07,061 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:16:07,061 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:16:07,061 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:16:07,062 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:16:07,062 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:16:07,062 INFO L87 Difference]: Start difference. First operand 17825 states and 25286 transitions. cyclomatic complexity: 7469 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 2 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:16:07,164 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:16:07,165 INFO L93 Difference]: Finished difference Result 17821 states and 25197 transitions. [2022-10-17 10:16:07,165 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17821 states and 25197 transitions. [2022-10-17 10:16:07,403 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 17664 [2022-10-17 10:16:07,584 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17821 states to 17821 states and 25197 transitions. [2022-10-17 10:16:07,584 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17821 [2022-10-17 10:16:07,624 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17821 [2022-10-17 10:16:07,624 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17821 states and 25197 transitions. [2022-10-17 10:16:07,646 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:16:07,646 INFO L218 hiAutomatonCegarLoop]: Abstraction has 17821 states and 25197 transitions. [2022-10-17 10:16:07,673 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17821 states and 25197 transitions. [2022-10-17 10:16:07,825 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17821 to 8956. [2022-10-17 10:16:07,840 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8956 states, 8956 states have (on average 1.4136891469405986) internal successors, (12661), 8955 states have internal predecessors, (12661), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:16:07,989 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8956 states to 8956 states and 12661 transitions. [2022-10-17 10:16:07,990 INFO L240 hiAutomatonCegarLoop]: Abstraction has 8956 states and 12661 transitions. [2022-10-17 10:16:07,990 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:16:07,991 INFO L428 stractBuchiCegarLoop]: Abstraction has 8956 states and 12661 transitions. [2022-10-17 10:16:07,991 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-10-17 10:16:07,992 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8956 states and 12661 transitions. [2022-10-17 10:16:08,037 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 8832 [2022-10-17 10:16:08,037 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:16:08,038 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:16:08,040 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:16:08,040 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:16:08,040 INFO L748 eck$LassoCheckResult]: Stem: 122545#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 122490#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 122491#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 121865#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 121866#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 122327#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 122328#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 122287#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 122193#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 122194#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 122185#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 122186#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 122144#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 122145#L754 assume !(0 == ~M_E~0); 122457#L754-2 assume !(0 == ~T1_E~0); 122071#L759-1 assume !(0 == ~T2_E~0); 122072#L764-1 assume !(0 == ~T3_E~0); 122505#L769-1 assume !(0 == ~T4_E~0); 122506#L774-1 assume !(0 == ~T5_E~0); 122370#L779-1 assume !(0 == ~T6_E~0); 122111#L784-1 assume !(0 == ~T7_E~0); 122112#L789-1 assume !(0 == ~E_1~0); 121774#L794-1 assume !(0 == ~E_2~0); 121775#L799-1 assume !(0 == ~E_3~0); 122511#L804-1 assume !(0 == ~E_4~0); 122512#L809-1 assume !(0 == ~E_5~0); 122198#L814-1 assume !(0 == ~E_6~0); 121694#L819-1 assume !(0 == ~E_7~0); 121695#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 122182#L361 assume !(1 == ~m_pc~0); 122183#L361-2 is_master_triggered_~__retres1~0#1 := 0; 122226#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 121986#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 121987#L930 assume !(0 != activate_threads_~tmp~1#1); 122367#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 122176#L380 assume !(1 == ~t1_pc~0); 121830#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 122391#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 122392#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 122497#L938 assume !(0 != activate_threads_~tmp___0~0#1); 121904#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 121831#L399 assume !(1 == ~t2_pc~0); 121832#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 122041#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 122409#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 122250#L946 assume !(0 != activate_threads_~tmp___1~0#1); 121734#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 121702#L418 assume !(1 == ~t3_pc~0); 121665#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 121666#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 122203#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 122472#L954 assume !(0 != activate_threads_~tmp___2~0#1); 122523#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 122459#L437 assume !(1 == ~t4_pc~0); 122331#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 122008#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 121833#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 121834#L962 assume !(0 != activate_threads_~tmp___3~0#1); 122300#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 121956#L456 assume !(1 == ~t5_pc~0); 121957#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 122068#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 122434#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 121721#L970 assume !(0 != activate_threads_~tmp___4~0#1); 121722#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 121846#L475 assume !(1 == ~t6_pc~0); 121847#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 121923#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 121924#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 121686#L978 assume !(0 != activate_threads_~tmp___5~0#1); 121687#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 122189#L494 assume !(1 == ~t7_pc~0); 122191#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 122234#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 122428#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 122429#L986 assume !(0 != activate_threads_~tmp___6~0#1); 122539#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 122430#L837 assume !(1 == ~M_E~0); 122253#L837-2 assume !(1 == ~T1_E~0); 121812#L842-1 assume !(1 == ~T2_E~0); 121813#L847-1 assume !(1 == ~T3_E~0); 122323#L852-1 assume !(1 == ~T4_E~0); 122422#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 122263#L862-1 assume !(1 == ~T6_E~0); 122264#L867-1 assume !(1 == ~T7_E~0); 122277#L872-1 assume !(1 == ~E_1~0); 122369#L877-1 assume !(1 == ~E_2~0); 122274#L882-1 assume !(1 == ~E_3~0); 122275#L887-1 assume !(1 == ~E_4~0); 121871#L892-1 assume !(1 == ~E_5~0); 121872#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 122294#L902-1 assume !(1 == ~E_7~0); 121952#L907-1 assume { :end_inline_reset_delta_events } true; 121953#L1148-2 [2022-10-17 10:16:08,041 INFO L750 eck$LassoCheckResult]: Loop: 121953#L1148-2 assume !false; 128054#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 128049#L729 assume !false; 128043#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 128008#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 127998#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 127990#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 127982#L626 assume !(0 != eval_~tmp~0#1); 127983#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 129396#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 129394#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 129392#L754-5 assume !(0 == ~T1_E~0); 129390#L759-3 assume !(0 == ~T2_E~0); 129388#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 129386#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 129384#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 129382#L779-3 assume !(0 == ~T6_E~0); 129380#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 129378#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 129376#L794-3 assume !(0 == ~E_2~0); 129375#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 129374#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 129373#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 129372#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 129371#L819-3 assume !(0 == ~E_7~0); 129370#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 129368#L361-24 assume !(1 == ~m_pc~0); 129367#L361-26 is_master_triggered_~__retres1~0#1 := 0; 129366#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 129364#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 129362#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 129361#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 129360#L380-24 assume !(1 == ~t1_pc~0); 129356#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 129353#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 129351#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 129349#L938-24 assume !(0 != activate_threads_~tmp___0~0#1); 129346#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 122054#L399-24 assume !(1 == ~t2_pc~0); 122055#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 128362#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 128355#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 128350#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 128345#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 128341#L418-24 assume 1 == ~t3_pc~0; 128337#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 128332#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 128327#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 128322#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 128318#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 128315#L437-24 assume !(1 == ~t4_pc~0); 128311#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 128306#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 128300#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 128295#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 128290#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 128285#L456-24 assume !(1 == ~t5_pc~0); 128279#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 128272#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 128268#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 128263#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 128258#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 128253#L475-24 assume !(1 == ~t6_pc~0); 127114#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 128244#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 128239#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 128234#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 128230#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 128226#L494-24 assume !(1 == ~t7_pc~0); 128220#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 128216#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 128211#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 128206#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 128201#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 128196#L837-3 assume !(1 == ~M_E~0); 128191#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 128185#L842-3 assume !(1 == ~T2_E~0); 128179#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 128173#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 128166#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 128162#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 128158#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 128154#L872-3 assume !(1 == ~E_1~0); 128150#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 128146#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 128145#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 128144#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 128143#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 128142#L902-3 assume !(1 == ~E_7~0); 128141#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 128137#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 128128#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 128126#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 128123#L1167 assume !(0 == start_simulation_~tmp~3#1); 128120#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 128106#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 128100#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 128098#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 128095#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 128093#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 128091#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 128089#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 121953#L1148-2 [2022-10-17 10:16:08,042 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:16:08,042 INFO L85 PathProgramCache]: Analyzing trace with hash 1267470274, now seen corresponding path program 1 times [2022-10-17 10:16:08,043 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:16:08,043 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [479336065] [2022-10-17 10:16:08,043 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:16:08,043 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:16:08,060 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:16:08,147 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:16:08,147 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:16:08,147 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [479336065] [2022-10-17 10:16:08,148 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [479336065] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:16:08,148 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:16:08,148 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-10-17 10:16:08,148 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [226231804] [2022-10-17 10:16:08,148 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:16:08,149 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:16:08,149 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:16:08,149 INFO L85 PathProgramCache]: Analyzing trace with hash -188040746, now seen corresponding path program 1 times [2022-10-17 10:16:08,149 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:16:08,149 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2030763789] [2022-10-17 10:16:08,150 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:16:08,150 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:16:08,164 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:16:08,197 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:16:08,197 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:16:08,197 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2030763789] [2022-10-17 10:16:08,197 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2030763789] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:16:08,197 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:16:08,198 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:16:08,198 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1111244737] [2022-10-17 10:16:08,198 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:16:08,198 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:16:08,199 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:16:08,199 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:16:08,199 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:16:08,199 INFO L87 Difference]: Start difference. First operand 8956 states and 12661 transitions. cyclomatic complexity: 3709 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 2 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:16:08,251 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:16:08,251 INFO L93 Difference]: Finished difference Result 8956 states and 12611 transitions. [2022-10-17 10:16:08,252 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8956 states and 12611 transitions. [2022-10-17 10:16:08,318 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 8832 [2022-10-17 10:16:08,355 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8956 states to 8956 states and 12611 transitions. [2022-10-17 10:16:08,355 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8956 [2022-10-17 10:16:08,364 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8956 [2022-10-17 10:16:08,364 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8956 states and 12611 transitions. [2022-10-17 10:16:08,373 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:16:08,374 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8956 states and 12611 transitions. [2022-10-17 10:16:08,383 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8956 states and 12611 transitions. [2022-10-17 10:16:08,573 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8956 to 8956. [2022-10-17 10:16:08,587 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8956 states, 8956 states have (on average 1.4081062974542207) internal successors, (12611), 8955 states have internal predecessors, (12611), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:16:08,617 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8956 states to 8956 states and 12611 transitions. [2022-10-17 10:16:08,618 INFO L240 hiAutomatonCegarLoop]: Abstraction has 8956 states and 12611 transitions. [2022-10-17 10:16:08,618 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:16:08,619 INFO L428 stractBuchiCegarLoop]: Abstraction has 8956 states and 12611 transitions. [2022-10-17 10:16:08,619 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-10-17 10:16:08,619 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8956 states and 12611 transitions. [2022-10-17 10:16:08,653 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 8832 [2022-10-17 10:16:08,653 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:16:08,653 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:16:08,655 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:16:08,655 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:16:08,656 INFO L748 eck$LassoCheckResult]: Stem: 140456#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 140410#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 140411#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 139783#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 139784#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 140245#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 140246#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 140203#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 140115#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 140116#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 140106#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 140107#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 140064#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 140065#L754 assume !(0 == ~M_E~0); 140376#L754-2 assume !(0 == ~T1_E~0); 139987#L759-1 assume !(0 == ~T2_E~0); 139988#L764-1 assume !(0 == ~T3_E~0); 140424#L769-1 assume !(0 == ~T4_E~0); 140425#L774-1 assume !(0 == ~T5_E~0); 140288#L779-1 assume !(0 == ~T6_E~0); 140030#L784-1 assume !(0 == ~T7_E~0); 140031#L789-1 assume !(0 == ~E_1~0); 139697#L794-1 assume !(0 == ~E_2~0); 139698#L799-1 assume !(0 == ~E_3~0); 140426#L804-1 assume !(0 == ~E_4~0); 140427#L809-1 assume !(0 == ~E_5~0); 140120#L814-1 assume !(0 == ~E_6~0); 139618#L819-1 assume !(0 == ~E_7~0); 139619#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 140101#L361 assume !(1 == ~m_pc~0); 140102#L361-2 is_master_triggered_~__retres1~0#1 := 0; 140145#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 139901#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 139902#L930 assume !(0 != activate_threads_~tmp~1#1); 140282#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 140094#L380 assume !(1 == ~t1_pc~0); 139748#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 140308#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 140309#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 140455#L938 assume !(0 != activate_threads_~tmp___0~0#1); 139823#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 139749#L399 assume !(1 == ~t2_pc~0); 139750#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 139957#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 140322#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 140168#L946 assume !(0 != activate_threads_~tmp___1~0#1); 139654#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 139625#L418 assume !(1 == ~t3_pc~0); 139584#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 139585#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 140124#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 140386#L954 assume !(0 != activate_threads_~tmp___2~0#1); 140437#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 140380#L437 assume !(1 == ~t4_pc~0); 140249#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 139925#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 139751#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 139752#L962 assume !(0 != activate_threads_~tmp___3~0#1); 140216#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 139878#L456 assume !(1 == ~t5_pc~0); 139879#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 139984#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 140351#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 139644#L970 assume !(0 != activate_threads_~tmp___4~0#1); 139645#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 139767#L475 assume !(1 == ~t6_pc~0); 139768#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 139842#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 139843#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 139605#L978 assume !(0 != activate_threads_~tmp___5~0#1); 139606#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 140108#L494 assume !(1 == ~t7_pc~0); 140110#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 140151#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 140345#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 140346#L986 assume !(0 != activate_threads_~tmp___6~0#1); 140451#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 140347#L837 assume !(1 == ~M_E~0); 140171#L837-2 assume !(1 == ~T1_E~0); 139731#L842-1 assume !(1 == ~T2_E~0); 139732#L847-1 assume !(1 == ~T3_E~0); 140239#L852-1 assume !(1 == ~T4_E~0); 140340#L857-1 assume !(1 == ~T5_E~0); 140181#L862-1 assume !(1 == ~T6_E~0); 140182#L867-1 assume !(1 == ~T7_E~0); 140193#L872-1 assume !(1 == ~E_1~0); 140285#L877-1 assume !(1 == ~E_2~0); 140189#L882-1 assume !(1 == ~E_3~0); 140190#L887-1 assume !(1 == ~E_4~0); 139790#L892-1 assume !(1 == ~E_5~0); 139791#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 140210#L902-1 assume !(1 == ~E_7~0); 139871#L907-1 assume { :end_inline_reset_delta_events } true; 139872#L1148-2 [2022-10-17 10:16:08,656 INFO L750 eck$LassoCheckResult]: Loop: 139872#L1148-2 assume !false; 144851#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 144849#L729 assume !false; 144847#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 144835#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 144829#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 144827#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 144824#L626 assume !(0 != eval_~tmp~0#1); 144825#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 145058#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 145056#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 145054#L754-5 assume !(0 == ~T1_E~0); 145052#L759-3 assume !(0 == ~T2_E~0); 145050#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 145048#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 145047#L774-3 assume !(0 == ~T5_E~0); 145045#L779-3 assume !(0 == ~T6_E~0); 145043#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 145041#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 145039#L794-3 assume !(0 == ~E_2~0); 145036#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 145034#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 145032#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 145030#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 145028#L819-3 assume !(0 == ~E_7~0); 145026#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 145022#L361-24 assume !(1 == ~m_pc~0); 145020#L361-26 is_master_triggered_~__retres1~0#1 := 0; 145018#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 145017#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 145016#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 145015#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 145014#L380-24 assume !(1 == ~t1_pc~0); 145012#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 145010#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 145008#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 145007#L938-24 assume !(0 != activate_threads_~tmp___0~0#1); 145005#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 145004#L399-24 assume !(1 == ~t2_pc~0); 144303#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 145003#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 145002#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 145001#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 145000#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 144999#L418-24 assume !(1 == ~t3_pc~0); 144996#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 144994#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 144992#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 144990#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 144988#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 144986#L437-24 assume !(1 == ~t4_pc~0); 144984#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 144981#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 144979#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 144977#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 144975#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 144973#L456-24 assume !(1 == ~t5_pc~0); 144970#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 144968#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 144966#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 144964#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 144962#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 144960#L475-24 assume !(1 == ~t6_pc~0); 144483#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 144956#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 144954#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 144952#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 144950#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 144948#L494-24 assume !(1 == ~t7_pc~0); 144945#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 144944#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 144942#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 144940#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 144938#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 144936#L837-3 assume !(1 == ~M_E~0); 144933#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 144931#L842-3 assume !(1 == ~T2_E~0); 144929#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 144927#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 144925#L857-3 assume !(1 == ~T5_E~0); 144923#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 144921#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 144919#L872-3 assume !(1 == ~E_1~0); 144917#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 144915#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 144913#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 144911#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 144909#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 144907#L902-3 assume !(1 == ~E_7~0); 144905#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 144899#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 144891#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 144889#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 144887#L1167 assume !(0 == start_simulation_~tmp~3#1); 144885#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 144881#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 144876#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 144875#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 144874#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 144873#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 144871#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 144869#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 139872#L1148-2 [2022-10-17 10:16:08,657 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:16:08,657 INFO L85 PathProgramCache]: Analyzing trace with hash 1968534852, now seen corresponding path program 1 times [2022-10-17 10:16:08,658 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:16:08,658 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [561708989] [2022-10-17 10:16:08,658 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:16:08,658 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:16:08,670 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:16:08,736 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:16:08,737 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:16:08,737 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [561708989] [2022-10-17 10:16:08,737 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [561708989] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:16:08,737 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:16:08,737 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:16:08,738 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1908793414] [2022-10-17 10:16:08,738 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:16:08,738 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:16:08,739 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:16:08,739 INFO L85 PathProgramCache]: Analyzing trace with hash 573564601, now seen corresponding path program 1 times [2022-10-17 10:16:08,739 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:16:08,739 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1688000356] [2022-10-17 10:16:08,739 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:16:08,739 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:16:08,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:16:08,786 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:16:08,786 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:16:08,786 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1688000356] [2022-10-17 10:16:08,786 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1688000356] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:16:08,786 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:16:08,787 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:16:08,787 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [311704472] [2022-10-17 10:16:08,787 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:16:08,787 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:16:08,787 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:16:08,788 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-10-17 10:16:08,788 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-10-17 10:16:08,788 INFO L87 Difference]: Start difference. First operand 8956 states and 12611 transitions. cyclomatic complexity: 3659 Second operand has 4 states, 4 states have (on average 23.25) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:16:08,955 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:16:08,956 INFO L93 Difference]: Finished difference Result 18213 states and 25558 transitions. [2022-10-17 10:16:08,956 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18213 states and 25558 transitions. [2022-10-17 10:16:09,195 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 17976 [2022-10-17 10:16:09,267 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18213 states to 18213 states and 25558 transitions. [2022-10-17 10:16:09,267 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18213 [2022-10-17 10:16:09,284 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18213 [2022-10-17 10:16:09,285 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18213 states and 25558 transitions. [2022-10-17 10:16:09,301 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:16:09,301 INFO L218 hiAutomatonCegarLoop]: Abstraction has 18213 states and 25558 transitions. [2022-10-17 10:16:09,319 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18213 states and 25558 transitions. [2022-10-17 10:16:09,450 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18213 to 10187. [2022-10-17 10:16:09,464 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10187 states, 10187 states have (on average 1.4017865907529203) internal successors, (14280), 10186 states have internal predecessors, (14280), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:16:09,496 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10187 states to 10187 states and 14280 transitions. [2022-10-17 10:16:09,496 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10187 states and 14280 transitions. [2022-10-17 10:16:09,497 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-10-17 10:16:09,497 INFO L428 stractBuchiCegarLoop]: Abstraction has 10187 states and 14280 transitions. [2022-10-17 10:16:09,497 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2022-10-17 10:16:09,498 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10187 states and 14280 transitions. [2022-10-17 10:16:09,536 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 9992 [2022-10-17 10:16:09,537 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:16:09,537 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:16:09,539 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:16:09,539 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:16:09,540 INFO L748 eck$LassoCheckResult]: Stem: 167664#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 167597#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 167598#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 166962#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 166963#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 167431#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 167432#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 167392#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 167291#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 167292#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 167283#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 167284#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 167241#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 167242#L754 assume !(0 == ~M_E~0); 167555#L754-2 assume !(0 == ~T1_E~0); 167171#L759-1 assume !(0 == ~T2_E~0); 167172#L764-1 assume !(0 == ~T3_E~0); 167617#L769-1 assume !(0 == ~T4_E~0); 167618#L774-1 assume !(0 == ~T5_E~0); 167468#L779-1 assume !(0 == ~T6_E~0); 167212#L784-1 assume !(0 == ~T7_E~0); 167213#L789-1 assume !(0 == ~E_1~0); 166874#L794-1 assume !(0 == ~E_2~0); 166875#L799-1 assume !(0 == ~E_3~0); 167624#L804-1 assume !(0 == ~E_4~0); 167625#L809-1 assume !(0 == ~E_5~0); 167296#L814-1 assume 0 == ~E_6~0;~E_6~0 := 1; 166794#L819-1 assume !(0 == ~E_7~0); 166795#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 167280#L361 assume !(1 == ~m_pc~0); 167281#L361-2 is_master_triggered_~__retres1~0#1 := 0; 167591#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 167592#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 167693#L930 assume !(0 != activate_threads_~tmp~1#1); 167528#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 167529#L380 assume !(1 == ~t1_pc~0); 166928#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 167658#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 167690#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 167687#L938 assume !(0 != activate_threads_~tmp___0~0#1); 167686#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 166929#L399 assume !(1 == ~t2_pc~0); 166930#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 167685#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 167620#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 167621#L946 assume !(0 != activate_threads_~tmp___1~0#1); 166833#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 166834#L418 assume !(1 == ~t3_pc~0); 166763#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 166764#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 167570#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 167571#L954 assume !(0 != activate_threads_~tmp___2~0#1); 167641#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 167642#L437 assume !(1 == ~t4_pc~0); 167684#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 167106#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 167107#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 167683#L962 assume !(0 != activate_threads_~tmp___3~0#1); 167402#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 167403#L456 assume !(1 == ~t5_pc~0); 167168#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 167167#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 167531#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 166824#L970 assume !(0 != activate_threads_~tmp___4~0#1); 166825#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 166944#L475 assume !(1 == ~t6_pc~0); 166945#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 167022#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 167023#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 166784#L978 assume !(0 != activate_threads_~tmp___5~0#1); 166785#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 167287#L494 assume !(1 == ~t7_pc~0); 167289#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 167593#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 167594#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 167660#L986 assume !(0 != activate_threads_~tmp___6~0#1); 167661#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 167525#L837 assume !(1 == ~M_E~0); 167526#L837-2 assume !(1 == ~T1_E~0); 166911#L842-1 assume !(1 == ~T2_E~0); 166912#L847-1 assume !(1 == ~T3_E~0); 167428#L852-1 assume !(1 == ~T4_E~0); 167674#L857-1 assume !(1 == ~T5_E~0); 167675#L862-1 assume !(1 == ~T6_E~0); 167381#L867-1 assume !(1 == ~T7_E~0); 167382#L872-1 assume !(1 == ~E_1~0); 167467#L877-1 assume !(1 == ~E_2~0); 167376#L882-1 assume !(1 == ~E_3~0); 167377#L887-1 assume !(1 == ~E_4~0); 167678#L892-1 assume !(1 == ~E_5~0); 167677#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 167396#L902-1 assume !(1 == ~E_7~0); 167050#L907-1 assume { :end_inline_reset_delta_events } true; 167051#L1148-2 [2022-10-17 10:16:09,541 INFO L750 eck$LassoCheckResult]: Loop: 167051#L1148-2 assume !false; 166792#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 166793#L729 assume !false; 167207#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 167201#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 167147#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 167225#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 167266#L626 assume !(0 != eval_~tmp~0#1); 167267#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 167429#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 167306#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 166835#L754-5 assume !(0 == ~T1_E~0); 166836#L759-3 assume !(0 == ~T2_E~0); 167234#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 167439#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 167440#L774-3 assume !(0 == ~T5_E~0); 167152#L779-3 assume !(0 == ~T6_E~0); 166813#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 166814#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 167668#L794-3 assume !(0 == ~E_2~0); 176159#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 176158#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 167565#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 166886#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 166887#L819-3 assume !(0 == ~E_7~0); 176545#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 176544#L361-24 assume !(1 == ~m_pc~0); 176543#L361-26 is_master_triggered_~__retres1~0#1 := 0; 176542#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 176541#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 176540#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 176539#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 176538#L380-24 assume 1 == ~t1_pc~0; 176536#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 176534#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 176532#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 176530#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 176529#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 176528#L399-24 assume !(1 == ~t2_pc~0); 175272#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 176527#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 176526#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 176525#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 176524#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 176523#L418-24 assume 1 == ~t3_pc~0; 176522#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 176520#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 176519#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 176518#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 176517#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 176516#L437-24 assume !(1 == ~t4_pc~0); 176515#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 176514#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 176513#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 176512#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 176511#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 176510#L456-24 assume !(1 == ~t5_pc~0); 176508#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 176507#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 176506#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 176505#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 176504#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 176503#L475-24 assume !(1 == ~t6_pc~0); 172777#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 176502#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 176501#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 176500#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 176499#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 176498#L494-24 assume !(1 == ~t7_pc~0); 176496#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 176495#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 176494#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 176493#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 176492#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 176491#L837-3 assume !(1 == ~M_E~0); 176490#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 176489#L842-3 assume !(1 == ~T2_E~0); 176488#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 176487#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 176486#L857-3 assume !(1 == ~T5_E~0); 176485#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 176484#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 176483#L872-3 assume !(1 == ~E_1~0); 176482#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 176481#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 176480#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 176479#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 176478#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 167186#L902-3 assume !(1 == ~E_7~0); 167393#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 167383#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 166799#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 167645#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 167553#L1167 assume !(0 == start_simulation_~tmp~3#1); 167426#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 167457#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 167218#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 167502#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 167544#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 167441#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 166777#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 166778#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 167051#L1148-2 [2022-10-17 10:16:09,542 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:16:09,543 INFO L85 PathProgramCache]: Analyzing trace with hash -1110278718, now seen corresponding path program 1 times [2022-10-17 10:16:09,543 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:16:09,543 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [275961579] [2022-10-17 10:16:09,543 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:16:09,543 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:16:09,553 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:16:09,699 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:16:09,700 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:16:09,700 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [275961579] [2022-10-17 10:16:09,700 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [275961579] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:16:09,700 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:16:09,700 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:16:09,701 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2131670727] [2022-10-17 10:16:09,701 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:16:09,701 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:16:09,702 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:16:09,702 INFO L85 PathProgramCache]: Analyzing trace with hash 1540422973, now seen corresponding path program 1 times [2022-10-17 10:16:09,702 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:16:09,702 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1061580251] [2022-10-17 10:16:09,702 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:16:09,703 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:16:09,717 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:16:09,757 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:16:09,757 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:16:09,757 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1061580251] [2022-10-17 10:16:09,757 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1061580251] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:16:09,758 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:16:09,758 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:16:09,758 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1963373067] [2022-10-17 10:16:09,758 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:16:09,759 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:16:09,759 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:16:09,760 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-10-17 10:16:09,760 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-10-17 10:16:09,760 INFO L87 Difference]: Start difference. First operand 10187 states and 14280 transitions. cyclomatic complexity: 4097 Second operand has 4 states, 4 states have (on average 23.25) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:16:09,925 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:16:09,925 INFO L93 Difference]: Finished difference Result 16884 states and 23649 transitions. [2022-10-17 10:16:09,925 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 16884 states and 23649 transitions. [2022-10-17 10:16:10,028 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 16720 [2022-10-17 10:16:10,102 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 16884 states to 16884 states and 23649 transitions. [2022-10-17 10:16:10,102 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16884 [2022-10-17 10:16:10,119 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16884 [2022-10-17 10:16:10,120 INFO L73 IsDeterministic]: Start isDeterministic. Operand 16884 states and 23649 transitions. [2022-10-17 10:16:10,138 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:16:10,138 INFO L218 hiAutomatonCegarLoop]: Abstraction has 16884 states and 23649 transitions. [2022-10-17 10:16:10,158 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16884 states and 23649 transitions. [2022-10-17 10:16:10,426 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16884 to 8956. [2022-10-17 10:16:10,438 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8956 states, 8956 states have (on average 1.3967172845020097) internal successors, (12509), 8955 states have internal predecessors, (12509), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:16:10,475 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8956 states to 8956 states and 12509 transitions. [2022-10-17 10:16:10,475 INFO L240 hiAutomatonCegarLoop]: Abstraction has 8956 states and 12509 transitions. [2022-10-17 10:16:10,476 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-10-17 10:16:10,477 INFO L428 stractBuchiCegarLoop]: Abstraction has 8956 states and 12509 transitions. [2022-10-17 10:16:10,477 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2022-10-17 10:16:10,478 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8956 states and 12509 transitions. [2022-10-17 10:16:10,515 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 8832 [2022-10-17 10:16:10,515 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:16:10,515 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:16:10,518 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:16:10,518 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:16:10,518 INFO L748 eck$LassoCheckResult]: Stem: 194718#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 194672#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 194673#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 194038#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 194039#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 194504#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 194505#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 194463#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 194372#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 194373#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 194363#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 194364#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 194321#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 194322#L754 assume !(0 == ~M_E~0); 194638#L754-2 assume !(0 == ~T1_E~0); 194248#L759-1 assume !(0 == ~T2_E~0); 194249#L764-1 assume !(0 == ~T3_E~0); 194688#L769-1 assume !(0 == ~T4_E~0); 194689#L774-1 assume !(0 == ~T5_E~0); 194546#L779-1 assume !(0 == ~T6_E~0); 194289#L784-1 assume !(0 == ~T7_E~0); 194290#L789-1 assume !(0 == ~E_1~0); 193950#L794-1 assume !(0 == ~E_2~0); 193951#L799-1 assume !(0 == ~E_3~0); 194690#L804-1 assume !(0 == ~E_4~0); 194691#L809-1 assume !(0 == ~E_5~0); 194377#L814-1 assume !(0 == ~E_6~0); 193873#L819-1 assume !(0 == ~E_7~0); 193874#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 194360#L361 assume !(1 == ~m_pc~0); 194361#L361-2 is_master_triggered_~__retres1~0#1 := 0; 194405#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 194162#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 194163#L930 assume !(0 != activate_threads_~tmp~1#1); 194543#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 194354#L380 assume !(1 == ~t1_pc~0); 194005#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 194568#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 194569#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 194717#L938 assume !(0 != activate_threads_~tmp___0~0#1); 194078#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 194006#L399 assume !(1 == ~t2_pc~0); 194007#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 194217#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 194584#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 194427#L946 assume !(0 != activate_threads_~tmp___1~0#1); 193912#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 193881#L418 assume !(1 == ~t3_pc~0); 193844#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 193845#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 194381#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 194653#L954 assume !(0 != activate_threads_~tmp___2~0#1); 194701#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 194640#L437 assume !(1 == ~t4_pc~0); 194508#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 194184#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 194008#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 194009#L962 assume !(0 != activate_threads_~tmp___3~0#1); 194476#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 194132#L456 assume !(1 == ~t5_pc~0); 194133#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 194245#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 194613#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 193900#L970 assume !(0 != activate_threads_~tmp___4~0#1); 193901#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 194021#L475 assume !(1 == ~t6_pc~0); 194022#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 194098#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 194099#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 193865#L978 assume !(0 != activate_threads_~tmp___5~0#1); 193866#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 194368#L494 assume !(1 == ~t7_pc~0); 194370#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 194411#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 194606#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 194607#L986 assume !(0 != activate_threads_~tmp___6~0#1); 194712#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 194605#L837 assume !(1 == ~M_E~0); 194430#L837-2 assume !(1 == ~T1_E~0); 193988#L842-1 assume !(1 == ~T2_E~0); 193989#L847-1 assume !(1 == ~T3_E~0); 194500#L852-1 assume !(1 == ~T4_E~0); 194599#L857-1 assume !(1 == ~T5_E~0); 194440#L862-1 assume !(1 == ~T6_E~0); 194441#L867-1 assume !(1 == ~T7_E~0); 194452#L872-1 assume !(1 == ~E_1~0); 194545#L877-1 assume !(1 == ~E_2~0); 194449#L882-1 assume !(1 == ~E_3~0); 194450#L887-1 assume !(1 == ~E_4~0); 194045#L892-1 assume !(1 == ~E_5~0); 194046#L897-1 assume !(1 == ~E_6~0); 194470#L902-1 assume !(1 == ~E_7~0); 194128#L907-1 assume { :end_inline_reset_delta_events } true; 194129#L1148-2 [2022-10-17 10:16:10,519 INFO L750 eck$LassoCheckResult]: Loop: 194129#L1148-2 assume !false; 197890#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 197886#L729 assume !false; 197881#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 197870#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 197861#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 197857#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 197850#L626 assume !(0 != eval_~tmp~0#1); 197851#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 199225#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 199223#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 199221#L754-5 assume !(0 == ~T1_E~0); 199219#L759-3 assume !(0 == ~T2_E~0); 199217#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 199215#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 199214#L774-3 assume !(0 == ~T5_E~0); 199211#L779-3 assume !(0 == ~T6_E~0); 199209#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 199207#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 199205#L794-3 assume !(0 == ~E_2~0); 199203#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 199201#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 199199#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 199197#L814-3 assume !(0 == ~E_6~0); 199195#L819-3 assume !(0 == ~E_7~0); 199193#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 199191#L361-24 assume !(1 == ~m_pc~0); 199189#L361-26 is_master_triggered_~__retres1~0#1 := 0; 199186#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 199138#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 199116#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 199110#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 199103#L380-24 assume 1 == ~t1_pc~0; 199095#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 199081#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 199072#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 199065#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 199060#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 198209#L399-24 assume !(1 == ~t2_pc~0); 198207#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 198205#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 198203#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 198201#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 198199#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 198198#L418-24 assume 1 == ~t3_pc~0; 198192#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 198189#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 198187#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 198185#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 198183#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 198181#L437-24 assume !(1 == ~t4_pc~0); 198179#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 198177#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 198175#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 198173#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 198171#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 198169#L456-24 assume 1 == ~t5_pc~0; 198167#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 198164#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 198162#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 198160#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 198158#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 198155#L475-24 assume !(1 == ~t6_pc~0); 197370#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 198152#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 198148#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 198138#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 198130#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 198121#L494-24 assume !(1 == ~t7_pc~0); 198119#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 198117#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 198115#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 198113#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 198111#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 198109#L837-3 assume !(1 == ~M_E~0); 198106#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 198104#L842-3 assume !(1 == ~T2_E~0); 198102#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 198100#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 198098#L857-3 assume !(1 == ~T5_E~0); 198096#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 198093#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 198091#L872-3 assume !(1 == ~E_1~0); 198089#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 198087#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 198085#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 198083#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 198075#L897-3 assume !(1 == ~E_6~0); 198031#L902-3 assume !(1 == ~E_7~0); 198026#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 197968#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 197957#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 197952#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 197946#L1167 assume !(0 == start_simulation_~tmp~3#1); 197939#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 197930#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 197924#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 197922#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 197919#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 197915#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 197909#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 197903#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 194129#L1148-2 [2022-10-17 10:16:10,520 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:16:10,520 INFO L85 PathProgramCache]: Analyzing trace with hash 1968536774, now seen corresponding path program 1 times [2022-10-17 10:16:10,521 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:16:10,521 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1607616476] [2022-10-17 10:16:10,521 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:16:10,521 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:16:10,543 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:16:10,544 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:16:10,558 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:16:10,613 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:16:10,613 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:16:10,614 INFO L85 PathProgramCache]: Analyzing trace with hash 1808803810, now seen corresponding path program 1 times [2022-10-17 10:16:10,614 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:16:10,614 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1394130960] [2022-10-17 10:16:10,614 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:16:10,614 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:16:10,629 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:16:10,667 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:16:10,667 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:16:10,667 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1394130960] [2022-10-17 10:16:10,667 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1394130960] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:16:10,668 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:16:10,668 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:16:10,668 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [681499133] [2022-10-17 10:16:10,668 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:16:10,669 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:16:10,669 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:16:10,669 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:16:10,670 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:16:10,670 INFO L87 Difference]: Start difference. First operand 8956 states and 12509 transitions. cyclomatic complexity: 3557 Second operand has 3 states, 3 states have (on average 34.0) internal successors, (102), 3 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:16:10,796 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:16:10,796 INFO L93 Difference]: Finished difference Result 13391 states and 18516 transitions. [2022-10-17 10:16:10,796 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13391 states and 18516 transitions. [2022-10-17 10:16:10,982 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 13188 [2022-10-17 10:16:11,041 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13391 states to 13391 states and 18516 transitions. [2022-10-17 10:16:11,041 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13391 [2022-10-17 10:16:11,069 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13391 [2022-10-17 10:16:11,069 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13391 states and 18516 transitions. [2022-10-17 10:16:11,079 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:16:11,079 INFO L218 hiAutomatonCegarLoop]: Abstraction has 13391 states and 18516 transitions. [2022-10-17 10:16:11,091 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13391 states and 18516 transitions. [2022-10-17 10:16:11,226 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13391 to 13391. [2022-10-17 10:16:11,247 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13391 states, 13391 states have (on average 1.382719737136883) internal successors, (18516), 13390 states have internal predecessors, (18516), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:16:11,291 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13391 states to 13391 states and 18516 transitions. [2022-10-17 10:16:11,292 INFO L240 hiAutomatonCegarLoop]: Abstraction has 13391 states and 18516 transitions. [2022-10-17 10:16:11,292 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:16:11,293 INFO L428 stractBuchiCegarLoop]: Abstraction has 13391 states and 18516 transitions. [2022-10-17 10:16:11,293 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2022-10-17 10:16:11,293 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13391 states and 18516 transitions. [2022-10-17 10:16:11,347 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 13188 [2022-10-17 10:16:11,347 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:16:11,348 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:16:11,350 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:16:11,350 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:16:11,351 INFO L748 eck$LassoCheckResult]: Stem: 217123#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 217053#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 217054#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 216394#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 216395#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 216875#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 216876#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 216834#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 216730#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 216731#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 216722#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 216723#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 216679#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 216680#L754 assume 0 == ~M_E~0;~M_E~0 := 1; 217010#L754-2 assume !(0 == ~T1_E~0); 217077#L759-1 assume !(0 == ~T2_E~0); 217115#L764-1 assume !(0 == ~T3_E~0); 217116#L769-1 assume !(0 == ~T4_E~0); 217119#L774-1 assume !(0 == ~T5_E~0); 216919#L779-1 assume !(0 == ~T6_E~0); 216647#L784-1 assume !(0 == ~T7_E~0); 216648#L789-1 assume !(0 == ~E_1~0); 217152#L794-1 assume !(0 == ~E_2~0); 217117#L799-1 assume !(0 == ~E_3~0); 217118#L804-1 assume !(0 == ~E_4~0); 217109#L809-1 assume !(0 == ~E_5~0); 217110#L814-1 assume !(0 == ~E_6~0); 216226#L819-1 assume !(0 == ~E_7~0); 216227#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 216719#L361 assume !(1 == ~m_pc~0); 216720#L361-2 is_master_triggered_~__retres1~0#1 := 0; 217046#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 217047#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 217151#L930 assume !(0 != activate_threads_~tmp~1#1); 216979#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 216980#L380 assume !(1 == ~t1_pc~0); 216361#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 217120#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 217061#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 217062#L938 assume !(0 != activate_threads_~tmp___0~0#1); 216434#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 216435#L399 assume !(1 == ~t2_pc~0); 217142#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 217141#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 217071#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 217072#L946 assume !(0 != activate_threads_~tmp___1~0#1); 216266#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 216234#L418 assume !(1 == ~t3_pc~0); 216235#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 216743#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 216744#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 217139#L954 assume !(0 != activate_threads_~tmp___2~0#1); 217093#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 217094#L437 assume !(1 == ~t4_pc~0); 217138#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 216540#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 216541#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 217137#L962 assume !(0 != activate_threads_~tmp___3~0#1); 217136#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 216487#L456 assume !(1 == ~t5_pc~0); 216488#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 216999#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 217000#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 217135#L970 assume !(0 != activate_threads_~tmp___4~0#1); 217073#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 217074#L475 assume !(1 == ~t6_pc~0); 217040#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 216455#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 216456#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 217133#L978 assume !(0 != activate_threads_~tmp___5~0#1); 217082#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 217083#L494 assume !(1 == ~t7_pc~0); 216778#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 216779#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 216973#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 216974#L986 assume !(0 != activate_threads_~tmp___6~0#1); 217111#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 216975#L837 assume 1 == ~M_E~0;~M_E~0 := 2; 216801#L837-2 assume !(1 == ~T1_E~0); 216343#L842-1 assume !(1 == ~T2_E~0); 216344#L847-1 assume !(1 == ~T3_E~0); 216869#L852-1 assume !(1 == ~T4_E~0); 216967#L857-1 assume !(1 == ~T5_E~0); 216811#L862-1 assume !(1 == ~T6_E~0); 216812#L867-1 assume !(1 == ~T7_E~0); 216824#L872-1 assume !(1 == ~E_1~0); 216918#L877-1 assume !(1 == ~E_2~0); 216821#L882-1 assume !(1 == ~E_3~0); 216822#L887-1 assume !(1 == ~E_4~0); 216402#L892-1 assume !(1 == ~E_5~0); 216403#L897-1 assume !(1 == ~E_6~0); 216839#L902-1 assume !(1 == ~E_7~0); 216483#L907-1 assume { :end_inline_reset_delta_events } true; 216484#L1148-2 [2022-10-17 10:16:11,351 INFO L750 eck$LassoCheckResult]: Loop: 216484#L1148-2 assume !false; 216228#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 216229#L729 assume !false; 216642#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 217098#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 228536#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 216823#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 216704#L626 assume !(0 != eval_~tmp~0#1); 216705#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 228901#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 228900#L754-3 assume !(0 == ~M_E~0); 228898#L754-5 assume !(0 == ~T1_E~0); 228897#L759-3 assume !(0 == ~T2_E~0); 228896#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 228895#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 228894#L774-3 assume !(0 == ~T5_E~0); 228892#L779-3 assume !(0 == ~T6_E~0); 228891#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 228890#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 228889#L794-3 assume !(0 == ~E_2~0); 228887#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 228884#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 228882#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 228880#L814-3 assume !(0 == ~E_6~0); 228878#L819-3 assume !(0 == ~E_7~0); 228876#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 228874#L361-24 assume !(1 == ~m_pc~0); 228872#L361-26 is_master_triggered_~__retres1~0#1 := 0; 228870#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 228868#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 228866#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 228864#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 228862#L380-24 assume !(1 == ~t1_pc~0); 228858#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 228856#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 228854#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 228852#L938-24 assume !(0 != activate_threads_~tmp___0~0#1); 228849#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 228847#L399-24 assume !(1 == ~t2_pc~0); 227890#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 228844#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 228842#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 228840#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 228836#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 228834#L418-24 assume 1 == ~t3_pc~0; 228832#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 228829#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 228826#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 228824#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 228822#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 228821#L437-24 assume !(1 == ~t4_pc~0); 228819#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 228817#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 228815#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 228813#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 228811#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 228808#L456-24 assume 1 == ~t5_pc~0; 228806#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 228804#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 228803#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 228602#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 228591#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 217121#L475-24 assume !(1 == ~t6_pc~0); 217122#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 229006#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 229005#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 229004#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 229003#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 229002#L494-24 assume !(1 == ~t7_pc~0); 228999#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 228997#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 228995#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 228993#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 228990#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 228980#L837-3 assume !(1 == ~M_E~0); 228978#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 228976#L842-3 assume !(1 == ~T2_E~0); 216866#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 216248#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 216249#L857-3 assume !(1 == ~T5_E~0); 217045#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 217033#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 216936#L872-3 assume !(1 == ~E_1~0); 216937#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 217037#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 217065#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 216627#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 216622#L897-3 assume !(1 == ~E_6~0); 216623#L902-3 assume !(1 == ~E_7~0); 216836#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 216827#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 216233#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 217097#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 217008#L1167 assume !(0 == start_simulation_~tmp~3#1); 216867#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 216907#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 216658#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 216954#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 217001#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 216886#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 216211#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 216212#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 216484#L1148-2 [2022-10-17 10:16:11,355 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:16:11,355 INFO L85 PathProgramCache]: Analyzing trace with hash -162859702, now seen corresponding path program 1 times [2022-10-17 10:16:11,356 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:16:11,356 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [41081900] [2022-10-17 10:16:11,356 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:16:11,356 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:16:11,367 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:16:11,400 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:16:11,400 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:16:11,401 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [41081900] [2022-10-17 10:16:11,401 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [41081900] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:16:11,401 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:16:11,401 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-10-17 10:16:11,401 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [158197197] [2022-10-17 10:16:11,402 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:16:11,402 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:16:11,402 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:16:11,402 INFO L85 PathProgramCache]: Analyzing trace with hash 1955092541, now seen corresponding path program 1 times [2022-10-17 10:16:11,403 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:16:11,403 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [267288222] [2022-10-17 10:16:11,403 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:16:11,403 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:16:11,414 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:16:11,526 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:16:11,527 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:16:11,527 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [267288222] [2022-10-17 10:16:11,527 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [267288222] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:16:11,527 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:16:11,527 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:16:11,528 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1757545739] [2022-10-17 10:16:11,528 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:16:11,528 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:16:11,528 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:16:11,529 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:16:11,529 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:16:11,530 INFO L87 Difference]: Start difference. First operand 13391 states and 18516 transitions. cyclomatic complexity: 5129 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 2 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:16:11,604 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:16:11,604 INFO L93 Difference]: Finished difference Result 8956 states and 12399 transitions. [2022-10-17 10:16:11,604 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8956 states and 12399 transitions. [2022-10-17 10:16:11,652 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 8832 [2022-10-17 10:16:11,688 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8956 states to 8956 states and 12399 transitions. [2022-10-17 10:16:11,688 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8956 [2022-10-17 10:16:11,694 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8956 [2022-10-17 10:16:11,694 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8956 states and 12399 transitions. [2022-10-17 10:16:11,702 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:16:11,702 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8956 states and 12399 transitions. [2022-10-17 10:16:11,709 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8956 states and 12399 transitions. [2022-10-17 10:16:11,788 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8956 to 8956. [2022-10-17 10:16:11,800 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8956 states, 8956 states have (on average 1.3844350156319785) internal successors, (12399), 8955 states have internal predecessors, (12399), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:16:11,826 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8956 states to 8956 states and 12399 transitions. [2022-10-17 10:16:11,826 INFO L240 hiAutomatonCegarLoop]: Abstraction has 8956 states and 12399 transitions. [2022-10-17 10:16:11,827 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:16:11,827 INFO L428 stractBuchiCegarLoop]: Abstraction has 8956 states and 12399 transitions. [2022-10-17 10:16:11,827 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2022-10-17 10:16:11,827 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8956 states and 12399 transitions. [2022-10-17 10:16:11,861 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 8832 [2022-10-17 10:16:11,861 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:16:11,862 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:16:11,864 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:16:11,864 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:16:11,864 INFO L748 eck$LassoCheckResult]: Stem: 239425#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 239372#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 239373#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 238745#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 238746#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 239212#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 239213#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 239173#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 239079#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 239080#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 239071#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 239072#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 239030#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 239031#L754 assume !(0 == ~M_E~0); 239342#L754-2 assume !(0 == ~T1_E~0); 238954#L759-1 assume !(0 == ~T2_E~0); 238955#L764-1 assume !(0 == ~T3_E~0); 239390#L769-1 assume !(0 == ~T4_E~0); 239391#L774-1 assume !(0 == ~T5_E~0); 239255#L779-1 assume !(0 == ~T6_E~0); 238998#L784-1 assume !(0 == ~T7_E~0); 238999#L789-1 assume !(0 == ~E_1~0); 238657#L794-1 assume !(0 == ~E_2~0); 238658#L799-1 assume !(0 == ~E_3~0); 239392#L804-1 assume !(0 == ~E_4~0); 239393#L809-1 assume !(0 == ~E_5~0); 239084#L814-1 assume !(0 == ~E_6~0); 238581#L819-1 assume !(0 == ~E_7~0); 238582#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 239068#L361 assume !(1 == ~m_pc~0); 239069#L361-2 is_master_triggered_~__retres1~0#1 := 0; 239115#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 238866#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 238867#L930 assume !(0 != activate_threads_~tmp~1#1); 239252#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 239062#L380 assume !(1 == ~t1_pc~0); 238712#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 239275#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 239276#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 239424#L938 assume !(0 != activate_threads_~tmp___0~0#1); 238785#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 238713#L399 assume !(1 == ~t2_pc~0); 238714#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 238923#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 239290#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 239137#L946 assume !(0 != activate_threads_~tmp___1~0#1); 238619#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 238589#L418 assume !(1 == ~t3_pc~0); 238551#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 238552#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 239090#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 239353#L954 assume !(0 != activate_threads_~tmp___2~0#1); 239408#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 239343#L437 assume !(1 == ~t4_pc~0); 239216#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 238889#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 238715#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 238716#L962 assume !(0 != activate_threads_~tmp___3~0#1); 239184#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 238836#L456 assume !(1 == ~t5_pc~0); 238837#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 238951#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 239318#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 238607#L970 assume !(0 != activate_threads_~tmp___4~0#1); 238608#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 238728#L475 assume !(1 == ~t6_pc~0); 238729#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 238805#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 238806#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 238572#L978 assume !(0 != activate_threads_~tmp___5~0#1); 238573#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 239075#L494 assume !(1 == ~t7_pc~0); 239077#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 239121#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 239309#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 239310#L986 assume !(0 != activate_threads_~tmp___6~0#1); 239418#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 239311#L837 assume !(1 == ~M_E~0); 239140#L837-2 assume !(1 == ~T1_E~0); 238695#L842-1 assume !(1 == ~T2_E~0); 238696#L847-1 assume !(1 == ~T3_E~0); 239206#L852-1 assume !(1 == ~T4_E~0); 239303#L857-1 assume !(1 == ~T5_E~0); 239150#L862-1 assume !(1 == ~T6_E~0); 239151#L867-1 assume !(1 == ~T7_E~0); 239161#L872-1 assume !(1 == ~E_1~0); 239254#L877-1 assume !(1 == ~E_2~0); 239159#L882-1 assume !(1 == ~E_3~0); 239160#L887-1 assume !(1 == ~E_4~0); 238752#L892-1 assume !(1 == ~E_5~0); 238753#L897-1 assume !(1 == ~E_6~0); 239178#L902-1 assume !(1 == ~E_7~0); 238832#L907-1 assume { :end_inline_reset_delta_events } true; 238833#L1148-2 [2022-10-17 10:16:11,865 INFO L750 eck$LassoCheckResult]: Loop: 238833#L1148-2 assume !false; 238583#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 238584#L729 assume !false; 238994#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 238987#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 238929#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 239013#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 239055#L626 assume !(0 != eval_~tmp~0#1); 239056#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 246978#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 246976#L754-3 assume !(0 == ~M_E~0); 246975#L754-5 assume !(0 == ~T1_E~0); 246974#L759-3 assume !(0 == ~T2_E~0); 246973#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 246971#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 246970#L774-3 assume !(0 == ~T5_E~0); 246969#L779-3 assume !(0 == ~T6_E~0); 246968#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 246966#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 246964#L794-3 assume !(0 == ~E_2~0); 246962#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 246960#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 246958#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 246956#L814-3 assume !(0 == ~E_6~0); 246952#L819-3 assume !(0 == ~E_7~0); 246950#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 246948#L361-24 assume !(1 == ~m_pc~0); 246946#L361-26 is_master_triggered_~__retres1~0#1 := 0; 246943#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 246941#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 246939#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 246938#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 246935#L380-24 assume !(1 == ~t1_pc~0); 246931#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 246929#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 246927#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 246925#L938-24 assume !(0 != activate_threads_~tmp___0~0#1); 246922#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 246921#L399-24 assume !(1 == ~t2_pc~0); 245026#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 246919#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 246917#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 246915#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 246914#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 246913#L418-24 assume 1 == ~t3_pc~0; 246911#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 246909#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 246908#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 246906#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 246904#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 246902#L437-24 assume !(1 == ~t4_pc~0); 246900#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 246898#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 246897#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 246896#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 239398#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 239280#L456-24 assume !(1 == ~t5_pc~0); 239282#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 239363#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 238985#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 238986#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 239148#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 239315#L475-24 assume !(1 == ~t6_pc~0); 239422#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 246773#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 246771#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 246769#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 246767#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 246765#L494-24 assume !(1 == ~t7_pc~0); 246761#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 246759#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 246757#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 246756#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 246753#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 246751#L837-3 assume !(1 == ~M_E~0); 239314#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 239313#L842-3 assume !(1 == ~T2_E~0); 239203#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 238601#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 238602#L857-3 assume !(1 == ~T5_E~0); 239369#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 239355#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 239271#L872-3 assume !(1 == ~E_1~0); 239272#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 239360#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 239387#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 238976#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 238971#L897-3 assume !(1 == ~E_6~0); 238972#L902-3 assume !(1 == ~E_7~0); 239175#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 239164#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 238588#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 239411#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 239340#L1167 assume !(0 == start_simulation_~tmp~3#1); 239204#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 239244#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 239009#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 239289#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 239364#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 239221#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 238565#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 238566#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 238833#L1148-2 [2022-10-17 10:16:11,867 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:16:11,867 INFO L85 PathProgramCache]: Analyzing trace with hash 1968536774, now seen corresponding path program 2 times [2022-10-17 10:16:11,868 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:16:11,868 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1926021750] [2022-10-17 10:16:11,868 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:16:11,868 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:16:11,883 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:16:11,883 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:16:11,892 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:16:11,936 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:16:11,936 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:16:11,936 INFO L85 PathProgramCache]: Analyzing trace with hash 647087772, now seen corresponding path program 1 times [2022-10-17 10:16:11,937 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:16:11,937 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [834411844] [2022-10-17 10:16:11,937 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:16:11,937 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:16:11,953 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:16:11,987 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:16:11,987 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:16:11,987 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [834411844] [2022-10-17 10:16:11,987 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [834411844] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:16:11,987 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:16:11,988 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:16:11,988 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1782817926] [2022-10-17 10:16:11,988 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:16:11,988 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:16:11,989 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:16:11,989 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:16:11,989 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:16:11,989 INFO L87 Difference]: Start difference. First operand 8956 states and 12399 transitions. cyclomatic complexity: 3447 Second operand has 3 states, 3 states have (on average 34.0) internal successors, (102), 3 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:16:12,216 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:16:12,216 INFO L93 Difference]: Finished difference Result 16204 states and 22209 transitions. [2022-10-17 10:16:12,216 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 16204 states and 22209 transitions. [2022-10-17 10:16:12,318 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 15988 [2022-10-17 10:16:12,393 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 16204 states to 16204 states and 22209 transitions. [2022-10-17 10:16:12,394 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16204 [2022-10-17 10:16:12,406 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16204 [2022-10-17 10:16:12,406 INFO L73 IsDeterministic]: Start isDeterministic. Operand 16204 states and 22209 transitions. [2022-10-17 10:16:12,420 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:16:12,421 INFO L218 hiAutomatonCegarLoop]: Abstraction has 16204 states and 22209 transitions. [2022-10-17 10:16:12,433 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16204 states and 22209 transitions. [2022-10-17 10:16:12,618 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16204 to 16164. [2022-10-17 10:16:12,636 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16164 states, 16164 states have (on average 1.371504578074734) internal successors, (22169), 16163 states have internal predecessors, (22169), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:16:12,682 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16164 states to 16164 states and 22169 transitions. [2022-10-17 10:16:12,682 INFO L240 hiAutomatonCegarLoop]: Abstraction has 16164 states and 22169 transitions. [2022-10-17 10:16:12,683 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:16:12,683 INFO L428 stractBuchiCegarLoop]: Abstraction has 16164 states and 22169 transitions. [2022-10-17 10:16:12,683 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2022-10-17 10:16:12,684 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16164 states and 22169 transitions. [2022-10-17 10:16:12,755 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 15956 [2022-10-17 10:16:12,756 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:16:12,756 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:16:12,759 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:16:12,759 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:16:12,760 INFO L748 eck$LassoCheckResult]: Stem: 264684#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 264608#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 264609#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 263913#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 263914#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 264409#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 264410#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 264367#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 264251#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 264252#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 264243#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 264244#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 264201#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 264202#L754 assume !(0 == ~M_E~0); 264562#L754-2 assume !(0 == ~T1_E~0); 264126#L759-1 assume !(0 == ~T2_E~0); 264127#L764-1 assume !(0 == ~T3_E~0); 264636#L769-1 assume !(0 == ~T4_E~0); 264637#L774-1 assume !(0 == ~T5_E~0); 264456#L779-1 assume !(0 == ~T6_E~0); 264168#L784-1 assume !(0 == ~T7_E~0); 264169#L789-1 assume 0 == ~E_1~0;~E_1~0 := 1; 264634#L794-1 assume !(0 == ~E_2~0); 264678#L799-1 assume !(0 == ~E_3~0); 264679#L804-1 assume !(0 == ~E_4~0); 264672#L809-1 assume !(0 == ~E_5~0); 264673#L814-1 assume !(0 == ~E_6~0); 263748#L819-1 assume !(0 == ~E_7~0); 263749#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 264240#L361 assume !(1 == ~m_pc~0); 264241#L361-2 is_master_triggered_~__retres1~0#1 := 0; 264598#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 264599#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 264699#L930 assume !(0 != activate_threads_~tmp~1#1); 264527#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 264528#L380 assume !(1 == ~t1_pc~0); 264680#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 264479#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 264480#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 264706#L938 assume !(0 != activate_threads_~tmp___0~0#1); 264705#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 263880#L399 assume !(1 == ~t2_pc~0); 263881#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 264704#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 264638#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 264639#L946 assume !(0 != activate_threads_~tmp___1~0#1); 263786#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 263787#L418 assume !(1 == ~t3_pc~0); 263717#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 263718#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 264579#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 264580#L954 assume !(0 != activate_threads_~tmp___2~0#1); 264659#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 264660#L437 assume !(1 == ~t4_pc~0); 264703#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 264056#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 264057#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 264702#L962 assume !(0 != activate_threads_~tmp___3~0#1); 264701#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 264008#L456 assume !(1 == ~t5_pc~0); 264009#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 264548#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 264549#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 264700#L970 assume !(0 != activate_threads_~tmp___4~0#1); 264640#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 264641#L475 assume !(1 == ~t6_pc~0); 264592#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 264593#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 264578#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 263738#L978 assume !(0 != activate_threads_~tmp___5~0#1); 263739#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 264247#L494 assume !(1 == ~t7_pc~0); 264249#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 264601#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 264602#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 264696#L986 assume !(0 != activate_threads_~tmp___6~0#1); 264674#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 264675#L837 assume !(1 == ~M_E~0); 264326#L837-2 assume !(1 == ~T1_E~0); 264327#L842-1 assume !(1 == ~T2_E~0); 264695#L847-1 assume !(1 == ~T3_E~0); 264515#L852-1 assume !(1 == ~T4_E~0); 264516#L857-1 assume !(1 == ~T5_E~0); 264338#L862-1 assume !(1 == ~T6_E~0); 264339#L867-1 assume !(1 == ~T7_E~0); 264355#L872-1 assume 1 == ~E_1~0;~E_1~0 := 2; 264455#L877-1 assume !(1 == ~E_2~0); 264348#L882-1 assume !(1 == ~E_3~0); 264349#L887-1 assume !(1 == ~E_4~0); 263920#L892-1 assume !(1 == ~E_5~0); 263921#L897-1 assume !(1 == ~E_6~0); 264375#L902-1 assume !(1 == ~E_7~0); 264002#L907-1 assume { :end_inline_reset_delta_events } true; 264003#L1148-2 [2022-10-17 10:16:12,760 INFO L750 eck$LassoCheckResult]: Loop: 264003#L1148-2 assume !false; 270060#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 270059#L729 assume !false; 270058#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 270054#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 270049#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 270047#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 270044#L626 assume !(0 != eval_~tmp~0#1); 270045#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 270791#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 270789#L754-3 assume !(0 == ~M_E~0); 270787#L754-5 assume !(0 == ~T1_E~0); 270785#L759-3 assume !(0 == ~T2_E~0); 270784#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 270783#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 270782#L774-3 assume !(0 == ~T5_E~0); 270780#L779-3 assume !(0 == ~T6_E~0); 270778#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 270727#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 270725#L794-3 assume !(0 == ~E_2~0); 270723#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 270720#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 270718#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 270716#L814-3 assume !(0 == ~E_6~0); 270714#L819-3 assume !(0 == ~E_7~0); 270712#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 270710#L361-24 assume !(1 == ~m_pc~0); 270708#L361-26 is_master_triggered_~__retres1~0#1 := 0; 270706#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 270704#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 270702#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 270700#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 270698#L380-24 assume !(1 == ~t1_pc~0); 270696#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 270694#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 270692#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 270691#L938-24 assume !(0 != activate_threads_~tmp___0~0#1); 270687#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 270685#L399-24 assume !(1 == ~t2_pc~0); 270271#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 270682#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 270680#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 270678#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 270675#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 270673#L418-24 assume !(1 == ~t3_pc~0); 270670#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 270668#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 270666#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 270664#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 270662#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 270660#L437-24 assume !(1 == ~t4_pc~0); 270658#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 270656#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 270654#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 270652#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 270649#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 270647#L456-24 assume !(1 == ~t5_pc~0); 270644#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 270642#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 270640#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 270638#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 270636#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 270633#L475-24 assume !(1 == ~t6_pc~0); 269349#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 270630#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 270628#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 270626#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 270624#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 270622#L494-24 assume !(1 == ~t7_pc~0); 270619#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 270617#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 270615#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 270613#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 270611#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 270609#L837-3 assume !(1 == ~M_E~0); 270607#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 270604#L842-3 assume !(1 == ~T2_E~0); 270602#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 270600#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 270598#L857-3 assume !(1 == ~T5_E~0); 270596#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 270594#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 270592#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 270590#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 270589#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 270588#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 270587#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 270586#L897-3 assume !(1 == ~E_6~0); 270585#L902-3 assume !(1 == ~E_7~0); 270583#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 270577#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 270569#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 270567#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 270564#L1167 assume !(0 == start_simulation_~tmp~3#1); 270559#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 270547#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 270539#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 270528#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 270519#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 270505#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 270501#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 270499#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 264003#L1148-2 [2022-10-17 10:16:12,761 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:16:12,761 INFO L85 PathProgramCache]: Analyzing trace with hash -1593984694, now seen corresponding path program 1 times [2022-10-17 10:16:12,761 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:16:12,762 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [682312561] [2022-10-17 10:16:12,762 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:16:12,763 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:16:12,876 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:16:12,925 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:16:12,925 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:16:12,926 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [682312561] [2022-10-17 10:16:12,926 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [682312561] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:16:12,926 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:16:12,926 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:16:12,926 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [30380422] [2022-10-17 10:16:12,927 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:16:12,927 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:16:12,927 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:16:12,928 INFO L85 PathProgramCache]: Analyzing trace with hash 323088829, now seen corresponding path program 1 times [2022-10-17 10:16:12,928 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:16:12,928 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1170591373] [2022-10-17 10:16:12,928 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:16:12,928 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:16:12,941 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:16:13,001 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:16:13,002 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:16:13,003 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1170591373] [2022-10-17 10:16:13,003 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1170591373] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:16:13,003 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:16:13,003 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-10-17 10:16:13,004 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [186710256] [2022-10-17 10:16:13,004 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:16:13,004 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:16:13,004 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:16:13,005 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-10-17 10:16:13,005 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-10-17 10:16:13,005 INFO L87 Difference]: Start difference. First operand 16164 states and 22169 transitions. cyclomatic complexity: 6009 Second operand has 4 states, 4 states have (on average 23.25) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:16:13,195 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:16:13,195 INFO L93 Difference]: Finished difference Result 23828 states and 32646 transitions. [2022-10-17 10:16:13,195 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 23828 states and 32646 transitions. [2022-10-17 10:16:13,315 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 22496 [2022-10-17 10:16:13,410 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 23828 states to 23828 states and 32646 transitions. [2022-10-17 10:16:13,411 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 23828 [2022-10-17 10:16:13,426 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23828 [2022-10-17 10:16:13,426 INFO L73 IsDeterministic]: Start isDeterministic. Operand 23828 states and 32646 transitions. [2022-10-17 10:16:13,443 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:16:13,444 INFO L218 hiAutomatonCegarLoop]: Abstraction has 23828 states and 32646 transitions. [2022-10-17 10:16:13,459 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23828 states and 32646 transitions. [2022-10-17 10:16:13,781 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23828 to 16145. [2022-10-17 10:16:13,797 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16145 states, 16145 states have (on average 1.370517187983896) internal successors, (22127), 16144 states have internal predecessors, (22127), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:16:13,837 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16145 states to 16145 states and 22127 transitions. [2022-10-17 10:16:13,838 INFO L240 hiAutomatonCegarLoop]: Abstraction has 16145 states and 22127 transitions. [2022-10-17 10:16:13,838 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-10-17 10:16:13,838 INFO L428 stractBuchiCegarLoop]: Abstraction has 16145 states and 22127 transitions. [2022-10-17 10:16:13,839 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2022-10-17 10:16:13,839 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16145 states and 22127 transitions. [2022-10-17 10:16:13,899 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 15956 [2022-10-17 10:16:13,899 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:16:13,899 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:16:13,902 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:16:13,902 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:16:13,903 INFO L748 eck$LassoCheckResult]: Stem: 304623#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 304559#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 304560#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 303917#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 303918#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 304387#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 304388#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 304346#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 304250#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 304251#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 304241#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 304242#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 304200#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 304201#L754 assume !(0 == ~M_E~0); 304516#L754-2 assume !(0 == ~T1_E~0); 304127#L759-1 assume !(0 == ~T2_E~0); 304128#L764-1 assume !(0 == ~T3_E~0); 304581#L769-1 assume !(0 == ~T4_E~0); 304582#L774-1 assume !(0 == ~T5_E~0); 304431#L779-1 assume !(0 == ~T6_E~0); 304169#L784-1 assume !(0 == ~T7_E~0); 304170#L789-1 assume !(0 == ~E_1~0); 303833#L794-1 assume !(0 == ~E_2~0); 303834#L799-1 assume !(0 == ~E_3~0); 304588#L804-1 assume !(0 == ~E_4~0); 304589#L809-1 assume !(0 == ~E_5~0); 304254#L814-1 assume !(0 == ~E_6~0); 303754#L819-1 assume !(0 == ~E_7~0); 303755#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 304236#L361 assume !(1 == ~m_pc~0); 304237#L361-2 is_master_triggered_~__retres1~0#1 := 0; 304280#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 304037#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 304038#L930 assume !(0 != activate_threads_~tmp~1#1); 304425#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 304230#L380 assume !(1 == ~t1_pc~0); 303884#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 304619#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 304569#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 304570#L938 assume !(0 != activate_threads_~tmp___0~0#1); 304644#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 303885#L399 assume !(1 == ~t2_pc~0); 303886#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 304095#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 304466#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 304304#L946 assume !(0 != activate_threads_~tmp___1~0#1); 304305#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 303760#L418 assume !(1 == ~t3_pc~0); 303761#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 304258#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 304259#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 304628#L954 assume !(0 != activate_threads_~tmp___2~0#1); 304629#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 304521#L437 assume !(1 == ~t4_pc~0); 304391#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 304392#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 303887#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 303888#L962 assume !(0 != activate_threads_~tmp___3~0#1); 304355#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 304356#L456 assume !(1 == ~t5_pc~0); 304124#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 304123#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 304492#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 303781#L970 assume !(0 != activate_threads_~tmp___4~0#1); 303782#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 303902#L475 assume !(1 == ~t6_pc~0); 303903#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 303976#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 303977#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 304637#L978 assume !(0 != activate_threads_~tmp___5~0#1); 304593#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 304594#L494 assume !(1 == ~t7_pc~0); 304287#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 304288#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 304486#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 304487#L986 assume !(0 != activate_threads_~tmp___6~0#1); 304616#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 304617#L837 assume !(1 == ~M_E~0); 304308#L837-2 assume !(1 == ~T1_E~0); 304309#L842-1 assume !(1 == ~T2_E~0); 304635#L847-1 assume !(1 == ~T3_E~0); 304480#L852-1 assume !(1 == ~T4_E~0); 304481#L857-1 assume !(1 == ~T5_E~0); 304320#L862-1 assume !(1 == ~T6_E~0); 304321#L867-1 assume !(1 == ~T7_E~0); 304634#L872-1 assume !(1 == ~E_1~0); 304428#L877-1 assume !(1 == ~E_2~0); 304327#L882-1 assume !(1 == ~E_3~0); 304328#L887-1 assume !(1 == ~E_4~0); 303924#L892-1 assume !(1 == ~E_5~0); 303925#L897-1 assume !(1 == ~E_6~0); 304352#L902-1 assume !(1 == ~E_7~0); 304005#L907-1 assume { :end_inline_reset_delta_events } true; 304006#L1148-2 [2022-10-17 10:16:13,903 INFO L750 eck$LassoCheckResult]: Loop: 304006#L1148-2 assume !false; 312950#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 312951#L729 assume !false; 317790#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 317786#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 317781#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 312907#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 312908#L626 assume !(0 != eval_~tmp~0#1); 304384#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 304385#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 304261#L754-3 assume !(0 == ~M_E~0); 303794#L754-5 assume !(0 == ~T1_E~0); 303795#L759-3 assume !(0 == ~T2_E~0); 304193#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 304396#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 304397#L774-3 assume !(0 == ~T5_E~0); 304111#L779-3 assume !(0 == ~T6_E~0); 303770#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 303771#L789-3 assume !(0 == ~E_1~0); 319371#L794-3 assume !(0 == ~E_2~0); 319370#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 319369#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 319368#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 319366#L814-3 assume !(0 == ~E_6~0); 319365#L819-3 assume !(0 == ~E_7~0); 319364#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 319363#L361-24 assume !(1 == ~m_pc~0); 319361#L361-26 is_master_triggered_~__retres1~0#1 := 0; 319359#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 319357#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 319355#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 319353#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 319351#L380-24 assume 1 == ~t1_pc~0; 319350#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 318313#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 318311#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 318308#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 318307#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 318306#L399-24 assume !(1 == ~t2_pc~0); 315218#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 318305#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 318304#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 318303#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 318302#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 318301#L418-24 assume 1 == ~t3_pc~0; 318300#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 318298#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 318297#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 318296#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 318295#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 318294#L437-24 assume !(1 == ~t4_pc~0); 318293#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 318292#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 318291#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 318290#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 318289#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 318288#L456-24 assume !(1 == ~t5_pc~0); 318286#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 318285#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 315182#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 315181#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 313792#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 313230#L475-24 assume !(1 == ~t6_pc~0); 313226#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 313143#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 313140#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 313138#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 313136#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 313134#L494-24 assume !(1 == ~t7_pc~0); 313131#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 313129#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 313127#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 313125#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 313123#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 313121#L837-3 assume !(1 == ~M_E~0); 313119#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 313117#L842-3 assume !(1 == ~T2_E~0); 313094#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 313052#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 313046#L857-3 assume !(1 == ~T5_E~0); 313040#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 313034#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 313028#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 313022#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 313017#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 313012#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 312995#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 312992#L897-3 assume !(1 == ~E_6~0); 312990#L902-3 assume !(1 == ~E_7~0); 312988#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 312985#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 312977#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 312975#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 312972#L1167 assume !(0 == start_simulation_~tmp~3#1); 312970#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 312966#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 312961#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 312960#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 312959#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 312958#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 312957#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 312956#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 304006#L1148-2 [2022-10-17 10:16:13,903 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:16:13,904 INFO L85 PathProgramCache]: Analyzing trace with hash 1968536774, now seen corresponding path program 3 times [2022-10-17 10:16:13,904 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:16:13,904 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1855990083] [2022-10-17 10:16:13,904 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:16:13,904 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:16:13,919 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:16:13,919 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:16:13,931 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:16:13,963 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:16:13,963 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:16:13,963 INFO L85 PathProgramCache]: Analyzing trace with hash -589183745, now seen corresponding path program 1 times [2022-10-17 10:16:13,964 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:16:13,964 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [668063779] [2022-10-17 10:16:13,964 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:16:13,964 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:16:13,977 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:16:14,037 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:16:14,038 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:16:14,038 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [668063779] [2022-10-17 10:16:14,038 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [668063779] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:16:14,038 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:16:14,038 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-10-17 10:16:14,038 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [280432192] [2022-10-17 10:16:14,039 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:16:14,039 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:16:14,039 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:16:14,040 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-10-17 10:16:14,040 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-10-17 10:16:14,040 INFO L87 Difference]: Start difference. First operand 16145 states and 22127 transitions. cyclomatic complexity: 5986 Second operand has 5 states, 5 states have (on average 20.4) internal successors, (102), 5 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:16:14,438 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:16:14,438 INFO L93 Difference]: Finished difference Result 29293 states and 39879 transitions. [2022-10-17 10:16:14,438 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 29293 states and 39879 transitions. [2022-10-17 10:16:14,588 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 29064 [2022-10-17 10:16:14,706 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 29293 states to 29293 states and 39879 transitions. [2022-10-17 10:16:14,706 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 29293 [2022-10-17 10:16:14,724 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 29293 [2022-10-17 10:16:14,725 INFO L73 IsDeterministic]: Start isDeterministic. Operand 29293 states and 39879 transitions. [2022-10-17 10:16:14,746 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:16:14,746 INFO L218 hiAutomatonCegarLoop]: Abstraction has 29293 states and 39879 transitions. [2022-10-17 10:16:14,767 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29293 states and 39879 transitions. [2022-10-17 10:16:15,126 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29293 to 16241. [2022-10-17 10:16:15,143 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16241 states, 16241 states have (on average 1.368327073456068) internal successors, (22223), 16240 states have internal predecessors, (22223), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:16:15,187 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16241 states to 16241 states and 22223 transitions. [2022-10-17 10:16:15,188 INFO L240 hiAutomatonCegarLoop]: Abstraction has 16241 states and 22223 transitions. [2022-10-17 10:16:15,188 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-10-17 10:16:15,189 INFO L428 stractBuchiCegarLoop]: Abstraction has 16241 states and 22223 transitions. [2022-10-17 10:16:15,189 INFO L335 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2022-10-17 10:16:15,190 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16241 states and 22223 transitions. [2022-10-17 10:16:15,256 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 16052 [2022-10-17 10:16:15,256 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:16:15,257 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:16:15,259 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:16:15,260 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:16:15,260 INFO L748 eck$LassoCheckResult]: Stem: 350135#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 350061#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 350062#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 349374#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 349375#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 349873#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 349874#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 349831#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 349722#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 349723#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 349710#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 349711#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 349667#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 349668#L754 assume !(0 == ~M_E~0); 350011#L754-2 assume !(0 == ~T1_E~0); 349585#L759-1 assume !(0 == ~T2_E~0); 349586#L764-1 assume !(0 == ~T3_E~0); 350082#L769-1 assume !(0 == ~T4_E~0); 350083#L774-1 assume !(0 == ~T5_E~0); 349918#L779-1 assume !(0 == ~T6_E~0); 349632#L784-1 assume !(0 == ~T7_E~0); 349633#L789-1 assume !(0 == ~E_1~0); 349287#L794-1 assume !(0 == ~E_2~0); 349288#L799-1 assume !(0 == ~E_3~0); 350090#L804-1 assume !(0 == ~E_4~0); 350091#L809-1 assume !(0 == ~E_5~0); 349727#L814-1 assume !(0 == ~E_6~0); 349208#L819-1 assume !(0 == ~E_7~0); 349209#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 349705#L361 assume !(1 == ~m_pc~0); 349706#L361-2 is_master_triggered_~__retres1~0#1 := 0; 349760#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 349492#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 349493#L930 assume !(0 != activate_threads_~tmp~1#1); 349912#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 349698#L380 assume !(1 == ~t1_pc~0); 349341#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 350130#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 350069#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 350070#L938 assume !(0 != activate_threads_~tmp___0~0#1); 350165#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 349342#L399 assume !(1 == ~t2_pc~0); 349343#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 350164#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 350084#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 350085#L946 assume !(0 != activate_threads_~tmp___1~0#1); 349244#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 349245#L418 assume !(1 == ~t3_pc~0); 349175#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 349176#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 350027#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 350028#L954 assume !(0 != activate_threads_~tmp___2~0#1); 350112#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 350113#L437 assume !(1 == ~t4_pc~0); 350163#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 349516#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 349517#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 350162#L962 assume !(0 != activate_threads_~tmp___3~0#1); 350161#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 349469#L456 assume !(1 == ~t5_pc~0); 349470#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 349998#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 349999#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 350160#L970 assume !(0 != activate_threads_~tmp___4~0#1); 350086#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 350087#L475 assume !(1 == ~t6_pc~0); 350046#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 350047#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 350026#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 349196#L978 assume !(0 != activate_threads_~tmp___5~0#1); 349197#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 349714#L494 assume !(1 == ~t7_pc~0); 349716#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 350055#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 350056#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 350157#L986 assume !(0 != activate_threads_~tmp___6~0#1); 350126#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 350127#L837 assume !(1 == ~M_E~0); 349791#L837-2 assume !(1 == ~T1_E~0); 349792#L842-1 assume !(1 == ~T2_E~0); 350156#L847-1 assume !(1 == ~T3_E~0); 349967#L852-1 assume !(1 == ~T4_E~0); 349968#L857-1 assume !(1 == ~T5_E~0); 350148#L862-1 assume !(1 == ~T6_E~0); 350154#L867-1 assume !(1 == ~T7_E~0); 350153#L872-1 assume !(1 == ~E_1~0); 349915#L877-1 assume !(1 == ~E_2~0); 349813#L882-1 assume !(1 == ~E_3~0); 349814#L887-1 assume !(1 == ~E_4~0); 349380#L892-1 assume !(1 == ~E_5~0); 349381#L897-1 assume !(1 == ~E_6~0); 349838#L902-1 assume !(1 == ~E_7~0); 349462#L907-1 assume { :end_inline_reset_delta_events } true; 349463#L1148-2 [2022-10-17 10:16:15,261 INFO L750 eck$LassoCheckResult]: Loop: 349463#L1148-2 assume !false; 364766#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 364750#L729 assume !false; 364654#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 364632#L569 assume !(0 == ~m_st~0); 364633#L573 assume !(0 == ~t1_st~0); 364636#L577 assume !(0 == ~t2_st~0); 364630#L581 assume !(0 == ~t3_st~0); 364631#L585 assume !(0 == ~t4_st~0); 364635#L589 assume !(0 == ~t5_st~0); 364628#L593 assume !(0 == ~t6_st~0); 364629#L597 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 364634#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 355486#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 355487#L626 assume !(0 != eval_~tmp~0#1); 364619#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 364617#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 364615#L754-3 assume !(0 == ~M_E~0); 364613#L754-5 assume !(0 == ~T1_E~0); 364611#L759-3 assume !(0 == ~T2_E~0); 364609#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 364607#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 364605#L774-3 assume !(0 == ~T5_E~0); 364603#L779-3 assume !(0 == ~T6_E~0); 364601#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 364599#L789-3 assume !(0 == ~E_1~0); 364597#L794-3 assume !(0 == ~E_2~0); 364595#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 364593#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 364591#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 364589#L814-3 assume !(0 == ~E_6~0); 364587#L819-3 assume !(0 == ~E_7~0); 364585#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 364583#L361-24 assume !(1 == ~m_pc~0); 364581#L361-26 is_master_triggered_~__retres1~0#1 := 0; 364579#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 364577#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 364573#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 364574#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 364564#L380-24 assume !(1 == ~t1_pc~0); 364565#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 364567#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 364568#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 364557#L938-24 assume !(0 != activate_threads_~tmp___0~0#1); 364558#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 349568#L399-24 assume !(1 == ~t2_pc~0); 349569#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 364969#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 364970#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 364965#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 364966#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 364960#L418-24 assume !(1 == ~t3_pc~0); 364961#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 349809#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 349810#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 349563#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 349564#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 364549#L437-24 assume !(1 == ~t4_pc~0); 364550#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 364545#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 364546#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 364541#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 364542#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 364536#L456-24 assume 1 == ~t5_pc~0; 364537#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 364531#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 364532#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 364527#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 364528#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 364524#L475-24 assume !(1 == ~t6_pc~0); 364290#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 363723#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 363724#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 363656#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 363657#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 363653#L494-24 assume !(1 == ~t7_pc~0); 363652#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 363647#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 363648#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 363641#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 363642#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 363636#L837-3 assume !(1 == ~M_E~0); 363637#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 363630#L842-3 assume !(1 == ~T2_E~0); 363631#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 350227#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 350228#L857-3 assume !(1 == ~T5_E~0); 350196#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 350197#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 350174#L872-3 assume !(1 == ~E_1~0); 349933#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 350076#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 350077#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 365188#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 349601#L897-3 assume !(1 == ~E_6~0); 349602#L902-3 assume !(1 == ~E_7~0); 349832#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 349833#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 365180#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 365179#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 365178#L1167 assume !(0 == start_simulation_~tmp~3#1); 349903#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 349904#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 349640#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 349951#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 349997#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 364775#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 364774#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 364772#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 349463#L1148-2 [2022-10-17 10:16:15,261 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:16:15,262 INFO L85 PathProgramCache]: Analyzing trace with hash 1968536774, now seen corresponding path program 4 times [2022-10-17 10:16:15,262 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:16:15,262 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1308030359] [2022-10-17 10:16:15,262 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:16:15,262 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:16:15,277 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:16:15,278 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:16:15,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:16:15,325 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:16:15,326 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:16:15,326 INFO L85 PathProgramCache]: Analyzing trace with hash -378041378, now seen corresponding path program 1 times [2022-10-17 10:16:15,326 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:16:15,326 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2088856426] [2022-10-17 10:16:15,326 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:16:15,327 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:16:15,344 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:16:15,449 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:16:15,449 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:16:15,449 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2088856426] [2022-10-17 10:16:15,449 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2088856426] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:16:15,449 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:16:15,450 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-10-17 10:16:15,450 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [83687202] [2022-10-17 10:16:15,450 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:16:15,450 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:16:15,451 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:16:15,452 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-10-17 10:16:15,452 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-10-17 10:16:15,452 INFO L87 Difference]: Start difference. First operand 16241 states and 22223 transitions. cyclomatic complexity: 5986 Second operand has 5 states, 5 states have (on average 21.8) internal successors, (109), 5 states have internal predecessors, (109), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:16:15,686 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:16:15,686 INFO L93 Difference]: Finished difference Result 19929 states and 27326 transitions. [2022-10-17 10:16:15,687 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 19929 states and 27326 transitions. [2022-10-17 10:16:15,803 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 19724 [2022-10-17 10:16:15,897 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 19929 states to 19929 states and 27326 transitions. [2022-10-17 10:16:15,898 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19929 [2022-10-17 10:16:15,912 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19929 [2022-10-17 10:16:15,912 INFO L73 IsDeterministic]: Start isDeterministic. Operand 19929 states and 27326 transitions. [2022-10-17 10:16:15,929 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:16:15,930 INFO L218 hiAutomatonCegarLoop]: Abstraction has 19929 states and 27326 transitions. [2022-10-17 10:16:15,945 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19929 states and 27326 transitions. [2022-10-17 10:16:16,144 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19929 to 16265. [2022-10-17 10:16:16,161 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16265 states, 16265 states have (on average 1.3559176145096834) internal successors, (22054), 16264 states have internal predecessors, (22054), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:16:16,418 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16265 states to 16265 states and 22054 transitions. [2022-10-17 10:16:16,418 INFO L240 hiAutomatonCegarLoop]: Abstraction has 16265 states and 22054 transitions. [2022-10-17 10:16:16,419 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-10-17 10:16:16,420 INFO L428 stractBuchiCegarLoop]: Abstraction has 16265 states and 22054 transitions. [2022-10-17 10:16:16,420 INFO L335 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2022-10-17 10:16:16,420 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16265 states and 22054 transitions. [2022-10-17 10:16:16,481 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 16076 [2022-10-17 10:16:16,481 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:16:16,481 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:16:16,487 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:16:16,487 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:16:16,487 INFO L748 eck$LassoCheckResult]: Stem: 386442#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 386336#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 386337#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 385557#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 385558#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 386102#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 386103#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 386043#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 385922#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 385923#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 385912#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 385913#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 385868#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 385869#L754 assume !(0 == ~M_E~0); 386274#L754-2 assume !(0 == ~T1_E~0); 385783#L759-1 assume !(0 == ~T2_E~0); 385784#L764-1 assume !(0 == ~T3_E~0); 386367#L769-1 assume !(0 == ~T4_E~0); 386368#L774-1 assume !(0 == ~T5_E~0); 386152#L779-1 assume !(0 == ~T6_E~0); 385831#L784-1 assume !(0 == ~T7_E~0); 385832#L789-1 assume !(0 == ~E_1~0); 385466#L794-1 assume !(0 == ~E_2~0); 385467#L799-1 assume !(0 == ~E_3~0); 386378#L804-1 assume !(0 == ~E_4~0); 386379#L809-1 assume !(0 == ~E_5~0); 385928#L814-1 assume !(0 == ~E_6~0); 385387#L819-1 assume !(0 == ~E_7~0); 385388#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 385909#L361 assume !(1 == ~m_pc~0); 385910#L361-2 is_master_triggered_~__retres1~0#1 := 0; 385963#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 385682#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 385683#L930 assume !(0 != activate_threads_~tmp~1#1); 386147#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 385901#L380 assume !(1 == ~t1_pc~0); 385523#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 386179#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 386180#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 386441#L938 assume !(0 != activate_threads_~tmp___0~0#1); 385597#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 385598#L399 assume !(1 == ~t2_pc~0); 385744#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 385745#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 386202#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 385993#L946 assume !(0 != activate_threads_~tmp___1~0#1); 385994#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 385395#L418 assume !(1 == ~t3_pc~0); 385396#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 385934#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 385935#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 386456#L954 assume !(0 != activate_threads_~tmp___2~0#1); 386457#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 386275#L437 assume !(1 == ~t4_pc~0); 386106#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 386107#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 385526#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 385527#L962 assume !(0 != activate_threads_~tmp___3~0#1); 386061#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 386062#L456 assume !(1 == ~t5_pc~0); 385780#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 385779#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 386240#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 385415#L970 assume !(0 != activate_threads_~tmp___4~0#1); 385416#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 385539#L475 assume !(1 == ~t6_pc~0); 385540#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 385619#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 385620#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 386480#L978 assume !(0 != activate_threads_~tmp___5~0#1); 386388#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 386389#L494 assume !(1 == ~t7_pc~0); 385969#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 385970#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 386226#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 386227#L986 assume !(0 != activate_threads_~tmp___6~0#1); 386438#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 386228#L837 assume !(1 == ~M_E~0); 386229#L837-2 assume !(1 == ~T1_E~0); 385505#L842-1 assume !(1 == ~T2_E~0); 385506#L847-1 assume !(1 == ~T3_E~0); 386096#L852-1 assume !(1 == ~T4_E~0); 386217#L857-1 assume !(1 == ~T5_E~0); 386465#L862-1 assume !(1 == ~T6_E~0); 386474#L867-1 assume !(1 == ~T7_E~0); 386473#L872-1 assume !(1 == ~E_1~0); 386151#L877-1 assume !(1 == ~E_2~0); 386026#L882-1 assume !(1 == ~E_3~0); 386027#L887-1 assume !(1 == ~E_4~0); 385564#L892-1 assume !(1 == ~E_5~0); 385565#L897-1 assume !(1 == ~E_6~0); 386055#L902-1 assume !(1 == ~E_7~0); 385648#L907-1 assume { :end_inline_reset_delta_events } true; 385649#L1148-2 [2022-10-17 10:16:16,488 INFO L750 eck$LassoCheckResult]: Loop: 385649#L1148-2 assume !false; 389882#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 389881#L729 assume !false; 389880#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 389875#L569 assume !(0 == ~m_st~0); 389876#L573 assume !(0 == ~t1_st~0); 389879#L577 assume !(0 == ~t2_st~0); 389873#L581 assume !(0 == ~t3_st~0); 389874#L585 assume !(0 == ~t4_st~0); 389878#L589 assume !(0 == ~t5_st~0); 389871#L593 assume !(0 == ~t6_st~0); 389872#L597 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 389877#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 389614#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 389615#L626 assume !(0 != eval_~tmp~0#1); 390218#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 390484#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 390483#L754-3 assume !(0 == ~M_E~0); 390482#L754-5 assume !(0 == ~T1_E~0); 390481#L759-3 assume !(0 == ~T2_E~0); 390480#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 390479#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 390478#L774-3 assume !(0 == ~T5_E~0); 390477#L779-3 assume !(0 == ~T6_E~0); 390476#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 390475#L789-3 assume !(0 == ~E_1~0); 390474#L794-3 assume !(0 == ~E_2~0); 390473#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 390472#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 390471#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 390470#L814-3 assume !(0 == ~E_6~0); 390469#L819-3 assume !(0 == ~E_7~0); 390468#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 390467#L361-24 assume !(1 == ~m_pc~0); 390466#L361-26 is_master_triggered_~__retres1~0#1 := 0; 390465#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 390464#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 390463#L930-24 assume !(0 != activate_threads_~tmp~1#1); 390462#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 390461#L380-24 assume 1 == ~t1_pc~0; 390459#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 390460#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 390528#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 390131#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 390128#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 390126#L399-24 assume !(1 == ~t2_pc~0); 390124#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 390122#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 390120#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 390118#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 390114#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 390110#L418-24 assume !(1 == ~t3_pc~0); 390105#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 390100#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 390096#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 390092#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 390088#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 390082#L437-24 assume !(1 == ~t4_pc~0); 390078#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 390074#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 390070#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 390066#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 390062#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 390058#L456-24 assume !(1 == ~t5_pc~0); 390053#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 390048#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 390044#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 390040#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 390036#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 390030#L475-24 assume !(1 == ~t6_pc~0); 387493#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 390024#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 390020#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 390016#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 390012#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 390010#L494-24 assume !(1 == ~t7_pc~0); 390004#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 390000#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 389996#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 389992#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 389986#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 389982#L837-3 assume !(1 == ~M_E~0); 389978#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 389974#L842-3 assume !(1 == ~T2_E~0); 389970#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 389966#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 389962#L857-3 assume !(1 == ~T5_E~0); 389958#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 389954#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 389950#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 389946#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 389943#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 389940#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 389928#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 389925#L897-3 assume !(1 == ~E_6~0); 389923#L902-3 assume !(1 == ~E_7~0); 389921#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 389918#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 389910#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 389908#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 389905#L1167 assume !(0 == start_simulation_~tmp~3#1); 389903#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 389899#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 389894#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 389893#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 389892#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 389891#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 389889#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 389887#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 385649#L1148-2 [2022-10-17 10:16:16,488 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:16:16,488 INFO L85 PathProgramCache]: Analyzing trace with hash 1968536774, now seen corresponding path program 5 times [2022-10-17 10:16:16,489 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:16:16,489 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1035812230] [2022-10-17 10:16:16,489 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:16:16,489 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:16:16,501 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:16:16,501 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:16:16,509 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:16:16,535 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:16:16,536 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:16:16,536 INFO L85 PathProgramCache]: Analyzing trace with hash -966285920, now seen corresponding path program 1 times [2022-10-17 10:16:16,536 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:16:16,537 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [635798184] [2022-10-17 10:16:16,537 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:16:16,537 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:16:16,549 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:16:16,589 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:16:16,589 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:16:16,589 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [635798184] [2022-10-17 10:16:16,589 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [635798184] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:16:16,589 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:16:16,590 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:16:16,590 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [188739759] [2022-10-17 10:16:16,590 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:16:16,590 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:16:16,591 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:16:16,591 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:16:16,592 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:16:16,592 INFO L87 Difference]: Start difference. First operand 16265 states and 22054 transitions. cyclomatic complexity: 5793 Second operand has 3 states, 3 states have (on average 36.333333333333336) internal successors, (109), 3 states have internal predecessors, (109), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:16:16,720 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:16:16,720 INFO L93 Difference]: Finished difference Result 27243 states and 36568 transitions. [2022-10-17 10:16:16,720 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27243 states and 36568 transitions. [2022-10-17 10:16:16,861 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 27020 [2022-10-17 10:16:16,950 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27243 states to 27243 states and 36568 transitions. [2022-10-17 10:16:16,951 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27243 [2022-10-17 10:16:16,972 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27243 [2022-10-17 10:16:16,973 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27243 states and 36568 transitions. [2022-10-17 10:16:16,993 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:16:16,993 INFO L218 hiAutomatonCegarLoop]: Abstraction has 27243 states and 36568 transitions. [2022-10-17 10:16:17,012 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27243 states and 36568 transitions. [2022-10-17 10:16:17,566 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27243 to 27243. [2022-10-17 10:16:17,620 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27243 states, 27243 states have (on average 1.3422897625078) internal successors, (36568), 27242 states have internal predecessors, (36568), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:16:17,741 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27243 states to 27243 states and 36568 transitions. [2022-10-17 10:16:17,741 INFO L240 hiAutomatonCegarLoop]: Abstraction has 27243 states and 36568 transitions. [2022-10-17 10:16:17,742 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:16:17,742 INFO L428 stractBuchiCegarLoop]: Abstraction has 27243 states and 36568 transitions. [2022-10-17 10:16:17,742 INFO L335 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2022-10-17 10:16:17,743 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27243 states and 36568 transitions. [2022-10-17 10:16:17,841 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 27020 [2022-10-17 10:16:17,841 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:16:17,841 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:16:17,844 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:16:17,844 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:16:17,846 INFO L748 eck$LassoCheckResult]: Stem: 429765#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 429708#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 429709#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 429069#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 429070#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 429544#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 429545#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 429500#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 429401#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 429402#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 429392#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 429393#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 429351#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 429352#L754 assume !(0 == ~M_E~0); 429668#L754-2 assume !(0 == ~T1_E~0); 429277#L759-1 assume !(0 == ~T2_E~0); 429278#L764-1 assume !(0 == ~T3_E~0); 429724#L769-1 assume !(0 == ~T4_E~0); 429725#L774-1 assume !(0 == ~T5_E~0); 429582#L779-1 assume !(0 == ~T6_E~0); 429320#L784-1 assume !(0 == ~T7_E~0); 429321#L789-1 assume !(0 == ~E_1~0); 428981#L794-1 assume !(0 == ~E_2~0); 428982#L799-1 assume !(0 == ~E_3~0); 429733#L804-1 assume !(0 == ~E_4~0); 429734#L809-1 assume !(0 == ~E_5~0); 429406#L814-1 assume !(0 == ~E_6~0); 428902#L819-1 assume !(0 == ~E_7~0); 428903#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 429389#L361 assume !(1 == ~m_pc~0); 429390#L361-2 is_master_triggered_~__retres1~0#1 := 0; 429436#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 429188#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 429189#L930 assume !(0 != activate_threads_~tmp~1#1); 429579#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 429382#L380 assume !(1 == ~t1_pc~0); 429035#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 429602#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 429603#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 429764#L938 assume !(0 != activate_threads_~tmp___0~0#1); 429109#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 429110#L399 assume !(1 == ~t2_pc~0); 429245#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 429246#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 429616#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 429463#L946 assume !(0 != activate_threads_~tmp___1~0#1); 429464#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 428910#L418 assume !(1 == ~t3_pc~0); 428911#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 429411#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 429412#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 429770#L954 assume !(0 != activate_threads_~tmp___2~0#1); 429771#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 429670#L437 assume !(1 == ~t4_pc~0); 429548#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 429549#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 429038#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 429039#L962 assume !(0 != activate_threads_~tmp___3~0#1); 429513#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 429514#L456 assume !(1 == ~t5_pc~0); 429274#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 429273#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 429644#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 428930#L970 assume !(0 != activate_threads_~tmp___4~0#1); 428931#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 429051#L475 assume !(1 == ~t6_pc~0); 429052#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 429129#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 429130#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 429782#L978 assume !(0 != activate_threads_~tmp___5~0#1); 429737#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 429738#L494 assume !(1 == ~t7_pc~0); 429443#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 429444#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 429636#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 429637#L986 assume !(0 != activate_threads_~tmp___6~0#1); 429763#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 429638#L837 assume !(1 == ~M_E~0); 429639#L837-2 assume !(1 == ~T1_E~0); 429018#L842-1 assume !(1 == ~T2_E~0); 429019#L847-1 assume !(1 == ~T3_E~0); 429540#L852-1 assume !(1 == ~T4_E~0); 429628#L857-1 assume !(1 == ~T5_E~0); 429773#L862-1 assume !(1 == ~T6_E~0); 429776#L867-1 assume !(1 == ~T7_E~0); 429775#L872-1 assume !(1 == ~E_1~0); 429581#L877-1 assume !(1 == ~E_2~0); 429485#L882-1 assume !(1 == ~E_3~0); 429486#L887-1 assume !(1 == ~E_4~0); 429076#L892-1 assume !(1 == ~E_5~0); 429077#L897-1 assume !(1 == ~E_6~0); 429507#L902-1 assume !(1 == ~E_7~0); 429157#L907-1 assume { :end_inline_reset_delta_events } true; 429158#L1148-2 assume !false; 441280#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 441278#L729 [2022-10-17 10:16:17,846 INFO L750 eck$LassoCheckResult]: Loop: 441278#L729 assume !false; 441276#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 441273#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 441271#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 441269#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 441268#L626 assume 0 != eval_~tmp~0#1; 441263#L626-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 441261#L634 assume !(0 != eval_~tmp_ndt_1~0#1); 441258#L631 assume !(0 == ~t1_st~0); 441255#L645 assume !(0 == ~t2_st~0); 441252#L659 assume !(0 == ~t3_st~0); 441248#L673 assume !(0 == ~t4_st~0); 441243#L687 assume !(0 == ~t5_st~0); 441238#L701 assume !(0 == ~t6_st~0); 441236#L715 assume !(0 == ~t7_st~0); 441278#L729 [2022-10-17 10:16:17,847 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:16:17,847 INFO L85 PathProgramCache]: Analyzing trace with hash 1978243464, now seen corresponding path program 1 times [2022-10-17 10:16:17,847 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:16:17,848 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1404585852] [2022-10-17 10:16:17,848 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:16:17,848 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:16:17,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:16:17,864 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:16:17,873 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:16:17,899 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:16:17,900 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:16:17,900 INFO L85 PathProgramCache]: Analyzing trace with hash -1503391009, now seen corresponding path program 1 times [2022-10-17 10:16:17,900 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:16:17,900 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1461594717] [2022-10-17 10:16:17,900 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:16:17,901 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:16:17,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:16:17,906 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:16:17,909 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:16:17,911 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:16:17,912 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:16:17,912 INFO L85 PathProgramCache]: Analyzing trace with hash -1562289544, now seen corresponding path program 1 times [2022-10-17 10:16:17,912 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:16:17,912 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [830129599] [2022-10-17 10:16:17,913 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:16:17,913 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:16:17,930 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:16:17,968 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:16:17,968 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:16:17,968 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [830129599] [2022-10-17 10:16:17,969 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [830129599] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:16:17,969 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:16:17,969 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:16:17,969 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2122254219] [2022-10-17 10:16:17,969 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:16:18,105 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:16:18,106 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:16:18,106 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:16:18,106 INFO L87 Difference]: Start difference. First operand 27243 states and 36568 transitions. cyclomatic complexity: 9333 Second operand has 3 states, 3 states have (on average 36.666666666666664) internal successors, (110), 3 states have internal predecessors, (110), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:16:18,335 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:16:18,335 INFO L93 Difference]: Finished difference Result 49528 states and 66201 transitions. [2022-10-17 10:16:18,335 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 49528 states and 66201 transitions. [2022-10-17 10:16:18,591 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 49088 [2022-10-17 10:16:19,002 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 49528 states to 49528 states and 66201 transitions. [2022-10-17 10:16:19,003 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 49528 [2022-10-17 10:16:19,042 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 49528 [2022-10-17 10:16:19,042 INFO L73 IsDeterministic]: Start isDeterministic. Operand 49528 states and 66201 transitions. [2022-10-17 10:16:19,098 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:16:19,098 INFO L218 hiAutomatonCegarLoop]: Abstraction has 49528 states and 66201 transitions. [2022-10-17 10:16:19,127 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49528 states and 66201 transitions. [2022-10-17 10:16:19,520 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49528 to 48104. [2022-10-17 10:16:19,557 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 48104 states, 48104 states have (on average 1.3376226509230003) internal successors, (64345), 48103 states have internal predecessors, (64345), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:16:20,021 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48104 states to 48104 states and 64345 transitions. [2022-10-17 10:16:20,027 INFO L240 hiAutomatonCegarLoop]: Abstraction has 48104 states and 64345 transitions. [2022-10-17 10:16:20,028 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:16:20,029 INFO L428 stractBuchiCegarLoop]: Abstraction has 48104 states and 64345 transitions. [2022-10-17 10:16:20,029 INFO L335 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2022-10-17 10:16:20,029 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 48104 states and 64345 transitions. [2022-10-17 10:16:20,176 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 47664 [2022-10-17 10:16:20,176 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:16:20,176 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:16:20,178 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:16:20,178 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:16:20,178 INFO L748 eck$LassoCheckResult]: Stem: 506668#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 506578#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 506579#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 505849#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 505850#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 506366#L521-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 506367#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 506437#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 506196#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 506197#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 506188#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 506189#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 506143#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 506144#L754 assume !(0 == ~M_E~0); 506614#L754-2 assume !(0 == ~T1_E~0); 506615#L759-1 assume !(0 == ~T2_E~0); 506655#L764-1 assume !(0 == ~T3_E~0); 506656#L769-1 assume !(0 == ~T4_E~0); 506659#L774-1 assume !(0 == ~T5_E~0); 506660#L779-1 assume !(0 == ~T6_E~0); 506107#L784-1 assume !(0 == ~T7_E~0); 506108#L789-1 assume !(0 == ~E_1~0); 505760#L794-1 assume !(0 == ~E_2~0); 505761#L799-1 assume !(0 == ~E_3~0); 506612#L804-1 assume !(0 == ~E_4~0); 506613#L809-1 assume !(0 == ~E_5~0); 506202#L814-1 assume !(0 == ~E_6~0); 506203#L819-1 assume !(0 == ~E_7~0); 506261#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 506262#L361 assume !(1 == ~m_pc~0); 506236#L361-2 is_master_triggered_~__retres1~0#1 := 0; 506237#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 505970#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 505971#L930 assume !(0 != activate_threads_~tmp~1#1); 506489#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 506490#L380 assume !(1 == ~t1_pc~0); 505816#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 506662#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 506587#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 506588#L938 assume !(0 != activate_threads_~tmp___0~0#1); 506780#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 506781#L399 assume !(1 == ~t2_pc~0); 506776#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 506777#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 506605#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 506606#L946 assume !(0 != activate_threads_~tmp___1~0#1); 505721#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 505722#L418 assume !(1 == ~t3_pc~0); 505651#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 505652#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 506543#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 506544#L954 assume !(0 != activate_threads_~tmp___2~0#1); 506634#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 506635#L437 assume !(1 == ~t4_pc~0); 506750#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 506751#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 506746#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 506747#L962 assume !(0 != activate_threads_~tmp___3~0#1); 506742#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 506743#L456 assume !(1 == ~t5_pc~0); 506736#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 506737#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 506732#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 506733#L970 assume !(0 != activate_threads_~tmp___4~0#1); 506608#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 506609#L475 assume !(1 == ~t6_pc~0); 506560#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 506561#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 506541#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 506542#L978 assume !(0 != activate_threads_~tmp___5~0#1); 506716#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 506717#L494 assume !(1 == ~t7_pc~0); 506711#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 506712#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 506707#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 506708#L986 assume !(0 != activate_threads_~tmp___6~0#1); 506703#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 506704#L837 assume !(1 == ~M_E~0); 506699#L837-2 assume !(1 == ~T1_E~0); 506700#L842-1 assume !(1 == ~T2_E~0); 506359#L847-1 assume !(1 == ~T3_E~0); 506360#L852-1 assume !(1 == ~T4_E~0); 506683#L857-1 assume !(1 == ~T5_E~0); 506684#L862-1 assume !(1 == ~T6_E~0); 506687#L867-1 assume !(1 == ~T7_E~0); 506688#L872-1 assume !(1 == ~E_1~0); 506681#L877-1 assume !(1 == ~E_2~0); 506682#L882-1 assume !(1 == ~E_3~0); 506562#L887-1 assume !(1 == ~E_4~0); 506563#L892-1 assume !(1 == ~E_5~0); 506472#L897-1 assume !(1 == ~E_6~0); 506473#L902-1 assume !(1 == ~E_7~0); 505936#L907-1 assume { :end_inline_reset_delta_events } true; 505937#L1148-2 assume !false; 507726#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 507727#L729 [2022-10-17 10:16:20,179 INFO L750 eck$LassoCheckResult]: Loop: 507727#L729 assume !false; 507707#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 507708#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 507693#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 507694#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 507681#L626 assume 0 != eval_~tmp~0#1; 507682#L626-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 507665#L634 assume !(0 != eval_~tmp_ndt_1~0#1); 507667#L631 assume !(0 == ~t1_st~0); 507656#L645 assume !(0 == ~t2_st~0); 507645#L659 assume !(0 == ~t3_st~0); 507642#L673 assume !(0 == ~t4_st~0); 507759#L687 assume !(0 == ~t5_st~0); 507756#L701 assume !(0 == ~t6_st~0); 507731#L715 assume !(0 == ~t7_st~0); 507727#L729 [2022-10-17 10:16:20,179 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:16:20,180 INFO L85 PathProgramCache]: Analyzing trace with hash -439660602, now seen corresponding path program 1 times [2022-10-17 10:16:20,180 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:16:20,180 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1217917684] [2022-10-17 10:16:20,180 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:16:20,180 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:16:20,192 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:16:20,214 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:16:20,214 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:16:20,214 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1217917684] [2022-10-17 10:16:20,214 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1217917684] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:16:20,215 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:16:20,215 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:16:20,215 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [868964374] [2022-10-17 10:16:20,215 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:16:20,216 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:16:20,216 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:16:20,216 INFO L85 PathProgramCache]: Analyzing trace with hash -1503391009, now seen corresponding path program 2 times [2022-10-17 10:16:20,216 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:16:20,217 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1994363750] [2022-10-17 10:16:20,217 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:16:20,217 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:16:20,221 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:16:20,221 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:16:20,224 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:16:20,226 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:16:20,364 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:16:20,364 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:16:20,365 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:16:20,365 INFO L87 Difference]: Start difference. First operand 48104 states and 64345 transitions. cyclomatic complexity: 16249 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:16:20,583 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:16:20,583 INFO L93 Difference]: Finished difference Result 47959 states and 64151 transitions. [2022-10-17 10:16:20,584 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 47959 states and 64151 transitions. [2022-10-17 10:16:20,793 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 47664 [2022-10-17 10:16:20,909 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 47959 states to 47959 states and 64151 transitions. [2022-10-17 10:16:20,909 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 47959 [2022-10-17 10:16:20,932 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 47959 [2022-10-17 10:16:20,933 INFO L73 IsDeterministic]: Start isDeterministic. Operand 47959 states and 64151 transitions. [2022-10-17 10:16:20,955 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:16:20,955 INFO L218 hiAutomatonCegarLoop]: Abstraction has 47959 states and 64151 transitions. [2022-10-17 10:16:20,989 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47959 states and 64151 transitions. [2022-10-17 10:16:21,939 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47959 to 47959. [2022-10-17 10:16:21,970 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 47959 states, 47959 states have (on average 1.3376217185512624) internal successors, (64151), 47958 states have internal predecessors, (64151), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:16:22,079 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47959 states to 47959 states and 64151 transitions. [2022-10-17 10:16:22,080 INFO L240 hiAutomatonCegarLoop]: Abstraction has 47959 states and 64151 transitions. [2022-10-17 10:16:22,080 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:16:22,081 INFO L428 stractBuchiCegarLoop]: Abstraction has 47959 states and 64151 transitions. [2022-10-17 10:16:22,081 INFO L335 stractBuchiCegarLoop]: ======== Iteration 28 ============ [2022-10-17 10:16:22,081 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 47959 states and 64151 transitions. [2022-10-17 10:16:22,236 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 47664 [2022-10-17 10:16:22,236 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:16:22,236 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:16:22,238 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:16:22,238 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:16:22,238 INFO L748 eck$LassoCheckResult]: Stem: 602648#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 602582#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 602583#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 601919#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 601920#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 602397#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 602398#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 602353#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 602252#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 602253#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 602246#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 602247#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 602203#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 602204#L754 assume !(0 == ~M_E~0); 602537#L754-2 assume !(0 == ~T1_E~0); 602128#L759-1 assume !(0 == ~T2_E~0); 602129#L764-1 assume !(0 == ~T3_E~0); 602604#L769-1 assume !(0 == ~T4_E~0); 602605#L774-1 assume !(0 == ~T5_E~0); 602443#L779-1 assume !(0 == ~T6_E~0); 602169#L784-1 assume !(0 == ~T7_E~0); 602170#L789-1 assume !(0 == ~E_1~0); 601834#L794-1 assume !(0 == ~E_2~0); 601835#L799-1 assume !(0 == ~E_3~0); 602612#L804-1 assume !(0 == ~E_4~0); 602613#L809-1 assume !(0 == ~E_5~0); 602258#L814-1 assume !(0 == ~E_6~0); 601752#L819-1 assume !(0 == ~E_7~0); 601753#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 602241#L361 assume !(1 == ~m_pc~0); 602242#L361-2 is_master_triggered_~__retres1~0#1 := 0; 602286#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 602038#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 602039#L930 assume !(0 != activate_threads_~tmp~1#1); 602437#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 602234#L380 assume !(1 == ~t1_pc~0); 601888#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 602645#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 602591#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 602592#L938 assume !(0 != activate_threads_~tmp___0~0#1); 602675#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 601884#L399 assume !(1 == ~t2_pc~0); 601885#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 602674#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 602607#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 602608#L946 assume !(0 != activate_threads_~tmp___1~0#1); 601790#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 601791#L418 assume !(1 == ~t3_pc~0); 601720#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 601721#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 602553#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 602554#L954 assume !(0 != activate_threads_~tmp___2~0#1); 602629#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 602630#L437 assume !(1 == ~t4_pc~0); 602673#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 602061#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 602062#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 602672#L962 assume !(0 != activate_threads_~tmp___3~0#1); 602671#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 602013#L456 assume !(1 == ~t5_pc~0); 602014#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 602522#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 602523#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 602670#L970 assume !(0 != activate_threads_~tmp___4~0#1); 602609#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 602610#L475 assume !(1 == ~t6_pc~0); 602569#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 602570#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 602552#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 601741#L978 assume !(0 != activate_threads_~tmp___5~0#1); 601742#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 602248#L494 assume !(1 == ~t7_pc~0); 602250#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 602577#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 602578#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 602667#L986 assume !(0 != activate_threads_~tmp___6~0#1); 602639#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 602640#L837 assume !(1 == ~M_E~0); 602316#L837-2 assume !(1 == ~T1_E~0); 602317#L842-1 assume !(1 == ~T2_E~0); 602666#L847-1 assume !(1 == ~T3_E~0); 602492#L852-1 assume !(1 == ~T4_E~0); 602493#L857-1 assume !(1 == ~T5_E~0); 602662#L862-1 assume !(1 == ~T6_E~0); 602664#L867-1 assume !(1 == ~T7_E~0); 602663#L872-1 assume !(1 == ~E_1~0); 602440#L877-1 assume !(1 == ~E_2~0); 602336#L882-1 assume !(1 == ~E_3~0); 602337#L887-1 assume !(1 == ~E_4~0); 601925#L892-1 assume !(1 == ~E_5~0); 601926#L897-1 assume !(1 == ~E_6~0); 602362#L902-1 assume !(1 == ~E_7~0); 602008#L907-1 assume { :end_inline_reset_delta_events } true; 602009#L1148-2 assume !false; 621686#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 621682#L729 [2022-10-17 10:16:22,239 INFO L750 eck$LassoCheckResult]: Loop: 621682#L729 assume !false; 621677#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 621671#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 621669#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 621667#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 621636#L626 assume 0 != eval_~tmp~0#1; 621637#L626-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 626393#L634 assume !(0 != eval_~tmp_ndt_1~0#1); 626391#L631 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 626387#L648 assume !(0 != eval_~tmp_ndt_2~0#1); 626383#L645 assume !(0 == ~t2_st~0); 626377#L659 assume !(0 == ~t3_st~0); 626370#L673 assume !(0 == ~t4_st~0); 626363#L687 assume !(0 == ~t5_st~0); 626360#L701 assume !(0 == ~t6_st~0); 621690#L715 assume !(0 == ~t7_st~0); 621682#L729 [2022-10-17 10:16:22,239 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:16:22,239 INFO L85 PathProgramCache]: Analyzing trace with hash 1978243464, now seen corresponding path program 2 times [2022-10-17 10:16:22,240 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:16:22,240 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1168336529] [2022-10-17 10:16:22,240 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:16:22,240 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:16:22,254 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:16:22,254 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:16:22,261 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:16:22,285 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:16:22,286 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:16:22,286 INFO L85 PathProgramCache]: Analyzing trace with hash -1848014684, now seen corresponding path program 1 times [2022-10-17 10:16:22,286 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:16:22,287 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1850602606] [2022-10-17 10:16:22,287 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:16:22,287 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:16:22,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:16:22,290 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:16:22,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:16:22,294 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:16:22,295 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:16:22,295 INFO L85 PathProgramCache]: Analyzing trace with hash 621098027, now seen corresponding path program 1 times [2022-10-17 10:16:22,295 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:16:22,295 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [106744237] [2022-10-17 10:16:22,296 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:16:22,296 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:16:22,307 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:16:22,346 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:16:22,346 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:16:22,346 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [106744237] [2022-10-17 10:16:22,346 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [106744237] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:16:22,347 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:16:22,347 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:16:22,347 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [863325009] [2022-10-17 10:16:22,347 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:16:22,487 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:16:22,487 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:16:22,487 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:16:22,488 INFO L87 Difference]: Start difference. First operand 47959 states and 64151 transitions. cyclomatic complexity: 16200 Second operand has 3 states, 3 states have (on average 37.0) internal successors, (111), 3 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:16:22,852 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:16:22,852 INFO L93 Difference]: Finished difference Result 92159 states and 122847 transitions. [2022-10-17 10:16:22,852 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 92159 states and 122847 transitions.