./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.09.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version dbf71c69 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18724260-ba09-40e0-ae41-b565b5500ff6/bin/uautomizer-J5u9QxTXDZ/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18724260-ba09-40e0-ae41-b565b5500ff6/bin/uautomizer-J5u9QxTXDZ/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18724260-ba09-40e0-ae41-b565b5500ff6/bin/uautomizer-J5u9QxTXDZ/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18724260-ba09-40e0-ae41-b565b5500ff6/bin/uautomizer-J5u9QxTXDZ/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.09.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18724260-ba09-40e0-ae41-b565b5500ff6/bin/uautomizer-J5u9QxTXDZ/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18724260-ba09-40e0-ae41-b565b5500ff6/bin/uautomizer-J5u9QxTXDZ --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 3945fa4b58cef50cb4b44b435a699812e99a1f6375664d08551274c6b50bee45 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-dbf71c6-m [2022-10-17 10:09:33,051 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-10-17 10:09:33,053 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-10-17 10:09:33,107 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-10-17 10:09:33,108 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-10-17 10:09:33,112 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-10-17 10:09:33,115 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-10-17 10:09:33,120 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-10-17 10:09:33,123 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-10-17 10:09:33,129 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-10-17 10:09:33,130 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-10-17 10:09:33,133 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-10-17 10:09:33,134 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-10-17 10:09:33,136 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-10-17 10:09:33,138 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-10-17 10:09:33,140 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-10-17 10:09:33,142 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-10-17 10:09:33,143 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-10-17 10:09:33,145 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-10-17 10:09:33,152 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-10-17 10:09:33,154 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-10-17 10:09:33,155 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-10-17 10:09:33,159 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-10-17 10:09:33,160 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-10-17 10:09:33,170 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-10-17 10:09:33,170 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-10-17 10:09:33,171 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-10-17 10:09:33,173 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-10-17 10:09:33,173 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-10-17 10:09:33,174 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-10-17 10:09:33,175 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-10-17 10:09:33,176 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-10-17 10:09:33,179 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-10-17 10:09:33,180 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-10-17 10:09:33,181 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-10-17 10:09:33,182 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-10-17 10:09:33,182 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-10-17 10:09:33,182 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-10-17 10:09:33,183 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-10-17 10:09:33,184 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-10-17 10:09:33,184 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-10-17 10:09:33,185 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18724260-ba09-40e0-ae41-b565b5500ff6/bin/uautomizer-J5u9QxTXDZ/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-10-17 10:09:33,231 INFO L113 SettingsManager]: Loading preferences was successful [2022-10-17 10:09:33,234 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-10-17 10:09:33,235 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-10-17 10:09:33,235 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-10-17 10:09:33,236 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-10-17 10:09:33,237 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-10-17 10:09:33,237 INFO L138 SettingsManager]: * Use SBE=true [2022-10-17 10:09:33,237 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-10-17 10:09:33,237 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-10-17 10:09:33,238 INFO L138 SettingsManager]: * Use old map elimination=false [2022-10-17 10:09:33,239 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-10-17 10:09:33,239 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-10-17 10:09:33,239 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-10-17 10:09:33,240 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-10-17 10:09:33,240 INFO L138 SettingsManager]: * sizeof long=4 [2022-10-17 10:09:33,240 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-10-17 10:09:33,240 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-10-17 10:09:33,241 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-10-17 10:09:33,241 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-10-17 10:09:33,241 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-10-17 10:09:33,241 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-10-17 10:09:33,242 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-10-17 10:09:33,242 INFO L138 SettingsManager]: * sizeof long double=12 [2022-10-17 10:09:33,242 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-10-17 10:09:33,242 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-10-17 10:09:33,242 INFO L138 SettingsManager]: * Use constant arrays=true [2022-10-17 10:09:33,243 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-10-17 10:09:33,244 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-10-17 10:09:33,245 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-10-17 10:09:33,245 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-10-17 10:09:33,245 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-10-17 10:09:33,254 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-10-17 10:09:33,254 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18724260-ba09-40e0-ae41-b565b5500ff6/bin/uautomizer-J5u9QxTXDZ/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18724260-ba09-40e0-ae41-b565b5500ff6/bin/uautomizer-J5u9QxTXDZ Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 3945fa4b58cef50cb4b44b435a699812e99a1f6375664d08551274c6b50bee45 [2022-10-17 10:09:33,572 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-10-17 10:09:33,600 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-10-17 10:09:33,605 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-10-17 10:09:33,606 INFO L271 PluginConnector]: Initializing CDTParser... [2022-10-17 10:09:33,607 INFO L275 PluginConnector]: CDTParser initialized [2022-10-17 10:09:33,608 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18724260-ba09-40e0-ae41-b565b5500ff6/bin/uautomizer-J5u9QxTXDZ/../../sv-benchmarks/c/systemc/transmitter.09.cil.c [2022-10-17 10:09:33,674 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18724260-ba09-40e0-ae41-b565b5500ff6/bin/uautomizer-J5u9QxTXDZ/data/7e122564c/56870bebdaad45e484facf8aab94763f/FLAG358760536 [2022-10-17 10:09:34,165 INFO L306 CDTParser]: Found 1 translation units. [2022-10-17 10:09:34,165 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18724260-ba09-40e0-ae41-b565b5500ff6/sv-benchmarks/c/systemc/transmitter.09.cil.c [2022-10-17 10:09:34,193 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18724260-ba09-40e0-ae41-b565b5500ff6/bin/uautomizer-J5u9QxTXDZ/data/7e122564c/56870bebdaad45e484facf8aab94763f/FLAG358760536 [2022-10-17 10:09:34,506 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18724260-ba09-40e0-ae41-b565b5500ff6/bin/uautomizer-J5u9QxTXDZ/data/7e122564c/56870bebdaad45e484facf8aab94763f [2022-10-17 10:09:34,509 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-10-17 10:09:34,510 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-10-17 10:09:34,512 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-10-17 10:09:34,512 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-10-17 10:09:34,518 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-10-17 10:09:34,519 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.10 10:09:34" (1/1) ... [2022-10-17 10:09:34,520 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5ec46c29 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:09:34, skipping insertion in model container [2022-10-17 10:09:34,520 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.10 10:09:34" (1/1) ... [2022-10-17 10:09:34,527 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-10-17 10:09:34,567 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-10-17 10:09:34,776 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18724260-ba09-40e0-ae41-b565b5500ff6/sv-benchmarks/c/systemc/transmitter.09.cil.c[706,719] [2022-10-17 10:09:34,897 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-10-17 10:09:34,911 INFO L203 MainTranslator]: Completed pre-run [2022-10-17 10:09:34,922 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18724260-ba09-40e0-ae41-b565b5500ff6/sv-benchmarks/c/systemc/transmitter.09.cil.c[706,719] [2022-10-17 10:09:34,983 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-10-17 10:09:35,025 INFO L208 MainTranslator]: Completed translation [2022-10-17 10:09:35,026 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:09:35 WrapperNode [2022-10-17 10:09:35,027 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-10-17 10:09:35,028 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-10-17 10:09:35,028 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-10-17 10:09:35,029 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-10-17 10:09:35,037 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:09:35" (1/1) ... [2022-10-17 10:09:35,060 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:09:35" (1/1) ... [2022-10-17 10:09:35,172 INFO L138 Inliner]: procedures = 46, calls = 57, calls flagged for inlining = 52, calls inlined = 170, statements flattened = 2581 [2022-10-17 10:09:35,173 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-10-17 10:09:35,173 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-10-17 10:09:35,174 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-10-17 10:09:35,174 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-10-17 10:09:35,189 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:09:35" (1/1) ... [2022-10-17 10:09:35,190 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:09:35" (1/1) ... [2022-10-17 10:09:35,198 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:09:35" (1/1) ... [2022-10-17 10:09:35,199 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:09:35" (1/1) ... [2022-10-17 10:09:35,247 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:09:35" (1/1) ... [2022-10-17 10:09:35,355 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:09:35" (1/1) ... [2022-10-17 10:09:35,360 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:09:35" (1/1) ... [2022-10-17 10:09:35,373 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:09:35" (1/1) ... [2022-10-17 10:09:35,406 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-10-17 10:09:35,407 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-10-17 10:09:35,407 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-10-17 10:09:35,407 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-10-17 10:09:35,411 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:09:35" (1/1) ... [2022-10-17 10:09:35,418 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:09:35,433 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18724260-ba09-40e0-ae41-b565b5500ff6/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:09:35,463 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18724260-ba09-40e0-ae41-b565b5500ff6/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:09:35,491 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18724260-ba09-40e0-ae41-b565b5500ff6/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-10-17 10:09:35,520 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-10-17 10:09:35,520 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-10-17 10:09:35,520 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-10-17 10:09:35,521 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-10-17 10:09:35,688 INFO L235 CfgBuilder]: Building ICFG [2022-10-17 10:09:35,690 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-10-17 10:09:37,324 INFO L276 CfgBuilder]: Performing block encoding [2022-10-17 10:09:37,351 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-10-17 10:09:37,351 INFO L300 CfgBuilder]: Removed 13 assume(true) statements. [2022-10-17 10:09:37,355 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 17.10 10:09:37 BoogieIcfgContainer [2022-10-17 10:09:37,355 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-10-17 10:09:37,357 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-10-17 10:09:37,357 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-10-17 10:09:37,361 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-10-17 10:09:37,362 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-10-17 10:09:37,362 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 17.10 10:09:34" (1/3) ... [2022-10-17 10:09:37,364 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1cff2c4b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.10 10:09:37, skipping insertion in model container [2022-10-17 10:09:37,364 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-10-17 10:09:37,364 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:09:35" (2/3) ... [2022-10-17 10:09:37,364 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1cff2c4b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.10 10:09:37, skipping insertion in model container [2022-10-17 10:09:37,365 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-10-17 10:09:37,365 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 17.10 10:09:37" (3/3) ... [2022-10-17 10:09:37,367 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.09.cil.c [2022-10-17 10:09:37,463 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-10-17 10:09:37,463 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-10-17 10:09:37,463 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-10-17 10:09:37,463 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-10-17 10:09:37,464 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-10-17 10:09:37,464 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-10-17 10:09:37,464 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-10-17 10:09:37,464 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-10-17 10:09:37,483 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1101 states, 1100 states have (on average 1.5136363636363637) internal successors, (1665), 1100 states have internal predecessors, (1665), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:09:37,597 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 972 [2022-10-17 10:09:37,598 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:09:37,598 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:09:37,613 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:09:37,613 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:09:37,613 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-10-17 10:09:37,616 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1101 states, 1100 states have (on average 1.5136363636363637) internal successors, (1665), 1100 states have internal predecessors, (1665), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:09:37,634 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 972 [2022-10-17 10:09:37,634 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:09:37,635 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:09:37,640 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:09:37,640 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:09:37,651 INFO L748 eck$LassoCheckResult]: Stem: 530#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 998#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 219#L1359true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1058#L634true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 720#L641true assume !(1 == ~m_i~0);~m_st~0 := 2; 768#L641-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 694#L646-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 482#L651-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 971#L656-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 326#L661-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 929#L666-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 848#L671-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 672#L676-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 373#L681-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 223#L686-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1089#L922true assume !(0 == ~M_E~0); 1026#L922-2true assume !(0 == ~T1_E~0); 1046#L927-1true assume !(0 == ~T2_E~0); 538#L932-1true assume !(0 == ~T3_E~0); 427#L937-1true assume 0 == ~T4_E~0;~T4_E~0 := 1; 481#L942-1true assume !(0 == ~T5_E~0); 724#L947-1true assume !(0 == ~T6_E~0); 542#L952-1true assume !(0 == ~T7_E~0); 619#L957-1true assume !(0 == ~T8_E~0); 968#L962-1true assume !(0 == ~T9_E~0); 408#L967-1true assume !(0 == ~E_1~0); 935#L972-1true assume !(0 == ~E_2~0); 703#L977-1true assume 0 == ~E_3~0;~E_3~0 := 1; 1037#L982-1true assume !(0 == ~E_4~0); 104#L987-1true assume !(0 == ~E_5~0); 108#L992-1true assume !(0 == ~E_6~0); 355#L997-1true assume !(0 == ~E_7~0); 879#L1002-1true assume !(0 == ~E_8~0); 345#L1007-1true assume !(0 == ~E_9~0); 7#L1012-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 871#L443true assume !(1 == ~m_pc~0); 556#L443-2true is_master_triggered_~__retres1~0#1 := 0; 547#L454true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 961#L455true activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 189#L1140true assume !(0 != activate_threads_~tmp~1#1); 62#L1140-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 895#L462true assume 1 == ~t1_pc~0; 449#L463true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 941#L473true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47#L474true activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 567#L1148true assume !(0 != activate_threads_~tmp___0~0#1); 314#L1148-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 979#L481true assume !(1 == ~t2_pc~0); 773#L481-2true is_transmit2_triggered_~__retres1~2#1 := 0; 528#L492true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 425#L493true activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 236#L1156true assume !(0 != activate_threads_~tmp___1~0#1); 298#L1156-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1081#L500true assume 1 == ~t3_pc~0; 461#L501true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 737#L511true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 687#L512true activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 764#L1164true assume !(0 != activate_threads_~tmp___2~0#1); 8#L1164-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 749#L519true assume 1 == ~t4_pc~0; 155#L520true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 297#L530true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 577#L531true activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 209#L1172true assume !(0 != activate_threads_~tmp___3~0#1); 503#L1172-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 89#L538true assume !(1 == ~t5_pc~0); 826#L538-2true is_transmit5_triggered_~__retres1~5#1 := 0; 42#L549true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 953#L550true activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 177#L1180true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 601#L1180-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1102#L557true assume 1 == ~t6_pc~0; 400#L558true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 808#L568true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 145#L569true activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 210#L1188true assume !(0 != activate_threads_~tmp___5~0#1); 930#L1188-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1051#L576true assume !(1 == ~t7_pc~0); 302#L576-2true is_transmit7_triggered_~__retres1~7#1 := 0; 399#L587true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 348#L588true activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1047#L1196true assume !(0 != activate_threads_~tmp___6~0#1); 656#L1196-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 257#L595true assume 1 == ~t8_pc~0; 1001#L596true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 688#L606true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 844#L607true activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 505#L1204true assume !(0 != activate_threads_~tmp___7~0#1); 933#L1204-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 152#L614true assume !(1 == ~t9_pc~0); 450#L614-2true is_transmit9_triggered_~__retres1~9#1 := 0; 100#L625true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 194#L626true activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 670#L1212true assume !(0 != activate_threads_~tmp___8~0#1); 237#L1212-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 414#L1025true assume !(1 == ~M_E~0); 460#L1025-2true assume !(1 == ~T1_E~0); 594#L1030-1true assume 1 == ~T2_E~0;~T2_E~0 := 2; 744#L1035-1true assume !(1 == ~T3_E~0); 233#L1040-1true assume !(1 == ~T4_E~0); 728#L1045-1true assume !(1 == ~T5_E~0); 183#L1050-1true assume !(1 == ~T6_E~0); 292#L1055-1true assume !(1 == ~T7_E~0); 93#L1060-1true assume !(1 == ~T8_E~0); 124#L1065-1true assume !(1 == ~T9_E~0); 948#L1070-1true assume 1 == ~E_1~0;~E_1~0 := 2; 543#L1075-1true assume !(1 == ~E_2~0); 1085#L1080-1true assume !(1 == ~E_3~0); 535#L1085-1true assume !(1 == ~E_4~0); 838#L1090-1true assume !(1 == ~E_5~0); 966#L1095-1true assume !(1 == ~E_6~0); 575#L1100-1true assume !(1 == ~E_7~0); 582#L1105-1true assume !(1 == ~E_8~0); 81#L1110-1true assume 1 == ~E_9~0;~E_9~0 := 2; 264#L1115-1true assume { :end_inline_reset_delta_events } true; 205#L1396-2true [2022-10-17 10:09:37,654 INFO L750 eck$LassoCheckResult]: Loop: 205#L1396-2true assume !false; 949#L1397true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 965#L897true assume false; 785#L912true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 50#L634-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 341#L922-3true assume 0 == ~M_E~0;~M_E~0 := 1; 970#L922-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 173#L927-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 277#L932-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 533#L937-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 76#L942-3true assume !(0 == ~T5_E~0); 623#L947-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 278#L952-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 810#L957-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 832#L962-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 632#L967-3true assume 0 == ~E_1~0;~E_1~0 := 1; 854#L972-3true assume 0 == ~E_2~0;~E_2~0 := 1; 537#L977-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1088#L982-3true assume !(0 == ~E_4~0); 1060#L987-3true assume 0 == ~E_5~0;~E_5~0 := 1; 243#L992-3true assume 0 == ~E_6~0;~E_6~0 := 1; 359#L997-3true assume 0 == ~E_7~0;~E_7~0 := 1; 241#L1002-3true assume 0 == ~E_8~0;~E_8~0 := 1; 493#L1007-3true assume 0 == ~E_9~0;~E_9~0 := 1; 94#L1012-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 271#L443-30true assume 1 == ~m_pc~0; 110#L444-10true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 261#L454-10true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 883#L455-10true activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 945#L1140-30true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 710#L1140-32true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 331#L462-30true assume !(1 == ~t1_pc~0); 800#L462-32true is_transmit1_triggered_~__retres1~1#1 := 0; 700#L473-10true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 685#L474-10true activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 740#L1148-30true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1066#L1148-32true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 322#L481-30true assume 1 == ~t2_pc~0; 156#L482-10true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 665#L492-10true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 184#L493-10true activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 140#L1156-30true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 301#L1156-32true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 551#L500-30true assume !(1 == ~t3_pc~0); 1067#L500-32true is_transmit3_triggered_~__retres1~3#1 := 0; 361#L511-10true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 193#L512-10true activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1025#L1164-30true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 290#L1164-32true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 637#L519-30true assume 1 == ~t4_pc~0; 585#L520-10true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 403#L530-10true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29#L531-10true activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 410#L1172-30true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 518#L1172-32true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 925#L538-30true assume 1 == ~t5_pc~0; 99#L539-10true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 280#L549-10true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 256#L550-10true activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 660#L1180-30true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 137#L1180-32true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 143#L557-30true assume 1 == ~t6_pc~0; 2#L558-10true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 388#L568-10true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 429#L569-10true activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1044#L1188-30true assume !(0 != activate_threads_~tmp___5~0#1); 151#L1188-32true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 510#L576-30true assume 1 == ~t7_pc~0; 1028#L577-10true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 383#L587-10true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1073#L588-10true activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 835#L1196-30true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 234#L1196-32true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 214#L595-30true assume 1 == ~t8_pc~0; 255#L596-10true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 180#L606-10true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 46#L607-10true activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 836#L1204-30true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1092#L1204-32true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 938#L614-30true assume 1 == ~t9_pc~0; 182#L615-10true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 639#L625-10true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 254#L626-10true activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 95#L1212-30true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 617#L1212-32true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 494#L1025-3true assume 1 == ~M_E~0;~M_E~0 := 2; 316#L1025-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 463#L1030-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 855#L1035-3true assume !(1 == ~T3_E~0); 1017#L1040-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 1039#L1045-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 845#L1050-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 686#L1055-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 45#L1060-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 719#L1065-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 712#L1070-3true assume 1 == ~E_1~0;~E_1~0 := 2; 521#L1075-3true assume !(1 == ~E_2~0); 856#L1080-3true assume 1 == ~E_3~0;~E_3~0 := 2; 939#L1085-3true assume 1 == ~E_4~0;~E_4~0 := 2; 697#L1090-3true assume 1 == ~E_5~0;~E_5~0 := 2; 1005#L1095-3true assume 1 == ~E_6~0;~E_6~0 := 2; 727#L1100-3true assume 1 == ~E_7~0;~E_7~0 := 2; 914#L1105-3true assume 1 == ~E_8~0;~E_8~0 := 2; 118#L1110-3true assume 1 == ~E_9~0;~E_9~0 := 2; 776#L1115-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 752#L699-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 121#L751-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 49#L752-1true start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 709#L1415true assume !(0 == start_simulation_~tmp~3#1); 407#L1415-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 969#L699-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 412#L751-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 597#L752-2true stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 1076#L1370true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1061#L1377true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 457#L1378true start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 160#L1428true assume !(0 != start_simulation_~tmp___0~1#1); 205#L1396-2true [2022-10-17 10:09:37,661 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:09:37,662 INFO L85 PathProgramCache]: Analyzing trace with hash 1400170149, now seen corresponding path program 1 times [2022-10-17 10:09:37,676 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:09:37,677 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [257438286] [2022-10-17 10:09:37,678 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:09:37,678 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:09:37,841 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:09:38,080 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:09:38,081 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:09:38,081 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [257438286] [2022-10-17 10:09:38,082 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [257438286] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:09:38,082 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:09:38,082 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:09:38,084 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2112324520] [2022-10-17 10:09:38,085 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:09:38,090 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:09:38,090 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:09:38,091 INFO L85 PathProgramCache]: Analyzing trace with hash -887452230, now seen corresponding path program 1 times [2022-10-17 10:09:38,091 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:09:38,091 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1382880872] [2022-10-17 10:09:38,092 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:09:38,092 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:09:38,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:09:38,154 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:09:38,155 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:09:38,155 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1382880872] [2022-10-17 10:09:38,155 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1382880872] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:09:38,156 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:09:38,156 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-10-17 10:09:38,156 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [46609303] [2022-10-17 10:09:38,156 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:09:38,158 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:09:38,159 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:09:38,194 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:09:38,195 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:09:38,200 INFO L87 Difference]: Start difference. First operand has 1101 states, 1100 states have (on average 1.5136363636363637) internal successors, (1665), 1100 states have internal predecessors, (1665), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:09:38,281 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:09:38,281 INFO L93 Difference]: Finished difference Result 1100 states and 1636 transitions. [2022-10-17 10:09:38,282 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1100 states and 1636 transitions. [2022-10-17 10:09:38,297 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 969 [2022-10-17 10:09:38,313 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1100 states to 1094 states and 1630 transitions. [2022-10-17 10:09:38,314 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1094 [2022-10-17 10:09:38,316 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1094 [2022-10-17 10:09:38,317 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1094 states and 1630 transitions. [2022-10-17 10:09:38,323 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:09:38,323 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1094 states and 1630 transitions. [2022-10-17 10:09:38,345 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1094 states and 1630 transitions. [2022-10-17 10:09:38,409 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1094 to 1094. [2022-10-17 10:09:38,413 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1094 states, 1094 states have (on average 1.489945155393053) internal successors, (1630), 1093 states have internal predecessors, (1630), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:09:38,419 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1094 states to 1094 states and 1630 transitions. [2022-10-17 10:09:38,421 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1094 states and 1630 transitions. [2022-10-17 10:09:38,422 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:09:38,426 INFO L428 stractBuchiCegarLoop]: Abstraction has 1094 states and 1630 transitions. [2022-10-17 10:09:38,426 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-10-17 10:09:38,427 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1094 states and 1630 transitions. [2022-10-17 10:09:38,448 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 969 [2022-10-17 10:09:38,448 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:09:38,448 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:09:38,453 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:09:38,453 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:09:38,454 INFO L748 eck$LassoCheckResult]: Stem: 3047#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 3048#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 2648#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2649#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3195#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 3196#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3178#L646-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 2998#L651-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2999#L656-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2815#L661-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2816#L666-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3255#L671-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3162#L676-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 2870#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2654#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2655#L922 assume !(0 == ~M_E~0); 3300#L922-2 assume !(0 == ~T1_E~0); 3301#L927-1 assume !(0 == ~T2_E~0); 3055#L932-1 assume !(0 == ~T3_E~0); 2940#L937-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2941#L942-1 assume !(0 == ~T5_E~0); 2997#L947-1 assume !(0 == ~T6_E~0); 3059#L952-1 assume !(0 == ~T7_E~0); 3060#L957-1 assume !(0 == ~T8_E~0); 3120#L962-1 assume !(0 == ~T9_E~0); 2916#L967-1 assume !(0 == ~E_1~0); 2917#L972-1 assume !(0 == ~E_2~0); 3183#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 3184#L982-1 assume !(0 == ~E_4~0); 2424#L987-1 assume !(0 == ~E_5~0); 2425#L992-1 assume !(0 == ~E_6~0); 2433#L997-1 assume !(0 == ~E_7~0); 2847#L1002-1 assume !(0 == ~E_8~0); 2834#L1007-1 assume !(0 == ~E_9~0); 2222#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2223#L443 assume !(1 == ~m_pc~0); 3075#L443-2 is_master_triggered_~__retres1~0#1 := 0; 3066#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3067#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2588#L1140 assume !(0 != activate_threads_~tmp~1#1); 2337#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2338#L462 assume 1 == ~t1_pc~0; 2966#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2933#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2308#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2309#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 2796#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2797#L481 assume !(1 == ~t2_pc~0); 2583#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2582#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2937#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2676#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 2677#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2769#L500 assume 1 == ~t3_pc~0; 2979#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2980#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3170#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3171#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 2224#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2225#L519 assume 1 == ~t4_pc~0; 2523#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2524#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2768#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2628#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 2629#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2391#L538 assume !(1 == ~t5_pc~0); 2392#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2298#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2299#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2567#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2568#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3105#L557 assume 1 == ~t6_pc~0; 2904#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2605#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2505#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2506#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 2630#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3283#L576 assume !(1 == ~t7_pc~0); 2592#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2593#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2837#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2838#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 3154#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2713#L595 assume 1 == ~t8_pc~0; 2714#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3172#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3173#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3022#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 3023#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2516#L614 assume !(1 == ~t9_pc~0); 2517#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 2416#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2417#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2596#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 2678#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2679#L1025 assume !(1 == ~M_E~0); 2925#L1025-2 assume !(1 == ~T1_E~0); 2978#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3100#L1035-1 assume !(1 == ~T3_E~0); 2672#L1040-1 assume !(1 == ~T4_E~0); 2673#L1045-1 assume !(1 == ~T5_E~0); 2578#L1050-1 assume !(1 == ~T6_E~0); 2579#L1055-1 assume !(1 == ~T7_E~0); 2400#L1060-1 assume !(1 == ~T8_E~0); 2401#L1065-1 assume !(1 == ~T9_E~0); 2464#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 3061#L1075-1 assume !(1 == ~E_2~0); 3062#L1080-1 assume !(1 == ~E_3~0); 3050#L1085-1 assume !(1 == ~E_4~0); 3051#L1090-1 assume !(1 == ~E_5~0); 3250#L1095-1 assume !(1 == ~E_6~0); 3084#L1100-1 assume !(1 == ~E_7~0); 3085#L1105-1 assume !(1 == ~E_8~0); 2373#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 2374#L1115-1 assume { :end_inline_reset_delta_events } true; 2535#L1396-2 [2022-10-17 10:09:38,455 INFO L750 eck$LassoCheckResult]: Loop: 2535#L1396-2 assume !false; 2618#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2647#L897 assume !false; 3290#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3197#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2245#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2246#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3245#L766 assume !(0 != eval_~tmp~0#1); 3231#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2315#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2316#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2830#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2559#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2560#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2738#L937-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2365#L942-3 assume !(0 == ~T5_E~0); 2366#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2739#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2740#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 3241#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3132#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3133#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3053#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3054#L982-3 assume !(0 == ~E_4~0); 3302#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2689#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2690#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2684#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2685#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 2402#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2403#L443-30 assume 1 == ~m_pc~0; 2436#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2437#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2720#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3268#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3187#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2820#L462-30 assume 1 == ~t1_pc~0; 2664#L463-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2666#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3168#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3169#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3209#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2807#L481-30 assume !(1 == ~t2_pc~0); 2528#L481-32 is_transmit2_triggered_~__retres1~2#1 := 0; 2527#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2580#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2493#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2494#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2774#L500-30 assume 1 == ~t3_pc~0; 2531#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2532#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2594#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2595#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2757#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2758#L519-30 assume 1 == ~t4_pc~0; 3093#L520-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2909#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2271#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2272#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2921#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3034#L538-30 assume 1 == ~t5_pc~0; 2412#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2413#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2711#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2712#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2489#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2490#L557-30 assume 1 == ~t6_pc~0; 2210#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2211#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2888#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2948#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 2514#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2515#L576-30 assume 1 == ~t7_pc~0; 3027#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2297#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2882#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3248#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2674#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2637#L595-30 assume !(1 == ~t8_pc~0); 2638#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 2569#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2306#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2307#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3249#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3285#L614-30 assume !(1 == ~t9_pc~0); 2576#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 2575#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2710#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2404#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2405#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3013#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2798#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2799#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2983#L1035-3 assume !(1 == ~T3_E~0); 3258#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3298#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3254#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3167#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2304#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2305#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3189#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3035#L1075-3 assume !(1 == ~E_2~0); 3036#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3259#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3180#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3181#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3200#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3201#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2452#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 2453#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3212#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2321#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2310#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 2311#L1415 assume !(0 == start_simulation_~tmp~3#1); 2912#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2913#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2361#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2923#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 3102#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3303#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2971#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 2534#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 2535#L1396-2 [2022-10-17 10:09:38,456 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:09:38,456 INFO L85 PathProgramCache]: Analyzing trace with hash -1247434205, now seen corresponding path program 1 times [2022-10-17 10:09:38,456 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:09:38,456 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [517784312] [2022-10-17 10:09:38,457 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:09:38,457 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:09:38,501 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:09:38,599 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:09:38,599 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:09:38,600 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [517784312] [2022-10-17 10:09:38,600 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [517784312] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:09:38,600 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:09:38,600 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:09:38,601 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1052667555] [2022-10-17 10:09:38,601 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:09:38,601 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:09:38,602 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:09:38,602 INFO L85 PathProgramCache]: Analyzing trace with hash -1392985774, now seen corresponding path program 1 times [2022-10-17 10:09:38,602 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:09:38,603 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1093898914] [2022-10-17 10:09:38,603 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:09:38,603 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:09:38,633 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:09:38,712 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:09:38,713 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:09:38,713 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1093898914] [2022-10-17 10:09:38,713 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1093898914] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:09:38,714 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:09:38,714 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:09:38,714 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1905582158] [2022-10-17 10:09:38,714 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:09:38,715 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:09:38,715 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:09:38,716 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:09:38,716 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:09:38,716 INFO L87 Difference]: Start difference. First operand 1094 states and 1630 transitions. cyclomatic complexity: 537 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:09:38,744 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:09:38,744 INFO L93 Difference]: Finished difference Result 1094 states and 1629 transitions. [2022-10-17 10:09:38,744 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1094 states and 1629 transitions. [2022-10-17 10:09:38,754 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 969 [2022-10-17 10:09:38,764 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1094 states to 1094 states and 1629 transitions. [2022-10-17 10:09:38,764 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1094 [2022-10-17 10:09:38,765 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1094 [2022-10-17 10:09:38,766 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1094 states and 1629 transitions. [2022-10-17 10:09:38,767 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:09:38,767 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1094 states and 1629 transitions. [2022-10-17 10:09:38,770 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1094 states and 1629 transitions. [2022-10-17 10:09:38,784 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1094 to 1094. [2022-10-17 10:09:38,787 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1094 states, 1094 states have (on average 1.4890310786106034) internal successors, (1629), 1093 states have internal predecessors, (1629), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:09:38,792 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1094 states to 1094 states and 1629 transitions. [2022-10-17 10:09:38,793 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1094 states and 1629 transitions. [2022-10-17 10:09:38,793 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:09:38,794 INFO L428 stractBuchiCegarLoop]: Abstraction has 1094 states and 1629 transitions. [2022-10-17 10:09:38,794 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-10-17 10:09:38,794 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1094 states and 1629 transitions. [2022-10-17 10:09:38,802 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 969 [2022-10-17 10:09:38,802 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:09:38,802 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:09:38,810 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:09:38,810 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:09:38,812 INFO L748 eck$LassoCheckResult]: Stem: 5242#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 5243#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 4843#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4844#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5390#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 5391#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5373#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5193#L651-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 5194#L656-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5010#L661-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5011#L666-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5450#L671-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5357#L676-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 5065#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4849#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4850#L922 assume !(0 == ~M_E~0); 5495#L922-2 assume !(0 == ~T1_E~0); 5496#L927-1 assume !(0 == ~T2_E~0); 5250#L932-1 assume !(0 == ~T3_E~0); 5135#L937-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5136#L942-1 assume !(0 == ~T5_E~0); 5192#L947-1 assume !(0 == ~T6_E~0); 5254#L952-1 assume !(0 == ~T7_E~0); 5255#L957-1 assume !(0 == ~T8_E~0); 5317#L962-1 assume !(0 == ~T9_E~0); 5111#L967-1 assume !(0 == ~E_1~0); 5112#L972-1 assume !(0 == ~E_2~0); 5378#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 5379#L982-1 assume !(0 == ~E_4~0); 4619#L987-1 assume !(0 == ~E_5~0); 4620#L992-1 assume !(0 == ~E_6~0); 4628#L997-1 assume !(0 == ~E_7~0); 5042#L1002-1 assume !(0 == ~E_8~0); 5029#L1007-1 assume !(0 == ~E_9~0); 4417#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4418#L443 assume !(1 == ~m_pc~0); 5270#L443-2 is_master_triggered_~__retres1~0#1 := 0; 5261#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5262#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4783#L1140 assume !(0 != activate_threads_~tmp~1#1); 4532#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4533#L462 assume 1 == ~t1_pc~0; 5161#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5128#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4503#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4504#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 4991#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4992#L481 assume !(1 == ~t2_pc~0); 4778#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4777#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5132#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4871#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 4872#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4964#L500 assume 1 == ~t3_pc~0; 5174#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5175#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5365#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5366#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 4419#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4420#L519 assume 1 == ~t4_pc~0; 4718#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4719#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4963#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4825#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 4826#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4586#L538 assume !(1 == ~t5_pc~0); 4587#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4493#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4494#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4762#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4763#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5302#L557 assume 1 == ~t6_pc~0; 5099#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4800#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4700#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4701#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 4827#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5478#L576 assume !(1 == ~t7_pc~0); 4787#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 4788#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5032#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5033#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 5349#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4908#L595 assume 1 == ~t8_pc~0; 4909#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 5367#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5368#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5217#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 5218#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4711#L614 assume !(1 == ~t9_pc~0); 4712#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 4611#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4612#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4791#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 4873#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4874#L1025 assume !(1 == ~M_E~0); 5120#L1025-2 assume !(1 == ~T1_E~0); 5173#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5295#L1035-1 assume !(1 == ~T3_E~0); 4868#L1040-1 assume !(1 == ~T4_E~0); 4869#L1045-1 assume !(1 == ~T5_E~0); 4773#L1050-1 assume !(1 == ~T6_E~0); 4774#L1055-1 assume !(1 == ~T7_E~0); 4595#L1060-1 assume !(1 == ~T8_E~0); 4596#L1065-1 assume !(1 == ~T9_E~0); 4659#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 5256#L1075-1 assume !(1 == ~E_2~0); 5257#L1080-1 assume !(1 == ~E_3~0); 5245#L1085-1 assume !(1 == ~E_4~0); 5246#L1090-1 assume !(1 == ~E_5~0); 5445#L1095-1 assume !(1 == ~E_6~0); 5279#L1100-1 assume !(1 == ~E_7~0); 5280#L1105-1 assume !(1 == ~E_8~0); 4568#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 4569#L1115-1 assume { :end_inline_reset_delta_events } true; 4730#L1396-2 [2022-10-17 10:09:38,813 INFO L750 eck$LassoCheckResult]: Loop: 4730#L1396-2 assume !false; 4813#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4842#L897 assume !false; 5485#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 5392#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 4442#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 4443#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 5440#L766 assume !(0 != eval_~tmp~0#1); 5426#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4510#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4511#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5025#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4754#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4755#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4933#L937-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4560#L942-3 assume !(0 == ~T5_E~0); 4561#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4934#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4935#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5436#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5327#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5328#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5248#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5249#L982-3 assume !(0 == ~E_4~0); 5497#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4884#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4885#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4882#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4883#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 4597#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4598#L443-30 assume 1 == ~m_pc~0; 4631#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4632#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4915#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5463#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5382#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5015#L462-30 assume 1 == ~t1_pc~0; 4860#L463-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4862#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5363#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5364#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5404#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5002#L481-30 assume 1 == ~t2_pc~0; 4721#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4722#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4775#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4688#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4689#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4969#L500-30 assume 1 == ~t3_pc~0; 4726#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4727#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4789#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4790#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4954#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4955#L519-30 assume 1 == ~t4_pc~0; 5289#L520-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5104#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4466#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4467#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5116#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5229#L538-30 assume !(1 == ~t5_pc~0); 4609#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 4608#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4906#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4907#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4684#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4685#L557-30 assume 1 == ~t6_pc~0; 4405#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4406#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5083#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5137#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 4709#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4710#L576-30 assume 1 == ~t7_pc~0; 5222#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4487#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5076#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5443#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4867#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4832#L595-30 assume !(1 == ~t8_pc~0); 4833#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 4764#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4501#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4502#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 5444#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5480#L614-30 assume 1 == ~t9_pc~0; 4769#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4770#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4905#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4599#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 4600#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5208#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4993#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4994#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5178#L1035-3 assume !(1 == ~T3_E~0); 5453#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5493#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5449#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5362#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4499#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4500#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 5384#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5230#L1075-3 assume !(1 == ~E_2~0); 5231#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5454#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5375#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5376#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5395#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5396#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4647#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 4648#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 5408#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 4516#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 4505#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 4506#L1415 assume !(0 == start_simulation_~tmp~3#1); 5108#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 5109#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 4556#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 5118#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 5297#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5498#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5168#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 4729#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 4730#L1396-2 [2022-10-17 10:09:38,814 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:09:38,815 INFO L85 PathProgramCache]: Analyzing trace with hash -208849631, now seen corresponding path program 1 times [2022-10-17 10:09:38,815 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:09:38,815 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1308607275] [2022-10-17 10:09:38,816 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:09:38,816 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:09:38,849 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:09:38,945 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:09:38,945 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:09:38,946 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1308607275] [2022-10-17 10:09:38,946 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1308607275] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:09:38,946 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:09:38,946 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:09:38,947 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1220604829] [2022-10-17 10:09:38,947 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:09:38,947 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:09:38,948 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:09:38,948 INFO L85 PathProgramCache]: Analyzing trace with hash -1113508429, now seen corresponding path program 1 times [2022-10-17 10:09:38,948 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:09:38,948 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1004596582] [2022-10-17 10:09:38,949 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:09:38,949 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:09:38,970 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:09:39,030 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:09:39,031 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:09:39,031 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1004596582] [2022-10-17 10:09:39,031 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1004596582] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:09:39,032 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:09:39,032 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:09:39,032 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1543682083] [2022-10-17 10:09:39,032 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:09:39,033 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:09:39,033 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:09:39,034 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:09:39,034 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:09:39,034 INFO L87 Difference]: Start difference. First operand 1094 states and 1629 transitions. cyclomatic complexity: 536 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:09:39,070 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:09:39,070 INFO L93 Difference]: Finished difference Result 1094 states and 1628 transitions. [2022-10-17 10:09:39,070 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1094 states and 1628 transitions. [2022-10-17 10:09:39,082 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 969 [2022-10-17 10:09:39,093 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1094 states to 1094 states and 1628 transitions. [2022-10-17 10:09:39,093 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1094 [2022-10-17 10:09:39,095 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1094 [2022-10-17 10:09:39,095 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1094 states and 1628 transitions. [2022-10-17 10:09:39,097 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:09:39,097 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1094 states and 1628 transitions. [2022-10-17 10:09:39,100 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1094 states and 1628 transitions. [2022-10-17 10:09:39,117 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1094 to 1094. [2022-10-17 10:09:39,120 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1094 states, 1094 states have (on average 1.4881170018281535) internal successors, (1628), 1093 states have internal predecessors, (1628), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:09:39,126 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1094 states to 1094 states and 1628 transitions. [2022-10-17 10:09:39,127 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1094 states and 1628 transitions. [2022-10-17 10:09:39,127 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:09:39,130 INFO L428 stractBuchiCegarLoop]: Abstraction has 1094 states and 1628 transitions. [2022-10-17 10:09:39,130 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-10-17 10:09:39,130 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1094 states and 1628 transitions. [2022-10-17 10:09:39,139 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 969 [2022-10-17 10:09:39,139 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:09:39,139 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:09:39,141 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:09:39,142 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:09:39,142 INFO L748 eck$LassoCheckResult]: Stem: 7437#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 7438#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 7038#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7039#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7585#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 7586#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7568#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7388#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7389#L656-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 7205#L661-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 7206#L666-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7646#L671-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 7552#L676-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 7260#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 7044#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7045#L922 assume !(0 == ~M_E~0); 7690#L922-2 assume !(0 == ~T1_E~0); 7691#L927-1 assume !(0 == ~T2_E~0); 7445#L932-1 assume !(0 == ~T3_E~0); 7330#L937-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7331#L942-1 assume !(0 == ~T5_E~0); 7387#L947-1 assume !(0 == ~T6_E~0); 7449#L952-1 assume !(0 == ~T7_E~0); 7450#L957-1 assume !(0 == ~T8_E~0); 7512#L962-1 assume !(0 == ~T9_E~0); 7306#L967-1 assume !(0 == ~E_1~0); 7307#L972-1 assume !(0 == ~E_2~0); 7573#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 7574#L982-1 assume !(0 == ~E_4~0); 6814#L987-1 assume !(0 == ~E_5~0); 6815#L992-1 assume !(0 == ~E_6~0); 6823#L997-1 assume !(0 == ~E_7~0); 7239#L1002-1 assume !(0 == ~E_8~0); 7224#L1007-1 assume !(0 == ~E_9~0); 6612#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6613#L443 assume !(1 == ~m_pc~0); 7465#L443-2 is_master_triggered_~__retres1~0#1 := 0; 7456#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7457#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6978#L1140 assume !(0 != activate_threads_~tmp~1#1); 6727#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6728#L462 assume 1 == ~t1_pc~0; 7356#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7324#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6698#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6699#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 7186#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7187#L481 assume !(1 == ~t2_pc~0); 6973#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 6972#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7327#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7066#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 7067#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7161#L500 assume 1 == ~t3_pc~0; 7369#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7370#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7560#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7561#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 6614#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6615#L519 assume 1 == ~t4_pc~0; 6913#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6914#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7158#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7020#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 7021#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6781#L538 assume !(1 == ~t5_pc~0); 6782#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 6688#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6689#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6957#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6958#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7497#L557 assume 1 == ~t6_pc~0; 7294#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6995#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6897#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6898#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 7022#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7673#L576 assume !(1 == ~t7_pc~0); 6982#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 6983#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7227#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7228#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 7544#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7103#L595 assume 1 == ~t8_pc~0; 7104#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 7562#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7563#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7412#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 7413#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 6906#L614 assume !(1 == ~t9_pc~0); 6907#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 6806#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6807#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6986#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 7068#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7069#L1025 assume !(1 == ~M_E~0); 7315#L1025-2 assume !(1 == ~T1_E~0); 7368#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7490#L1035-1 assume !(1 == ~T3_E~0); 7063#L1040-1 assume !(1 == ~T4_E~0); 7064#L1045-1 assume !(1 == ~T5_E~0); 6968#L1050-1 assume !(1 == ~T6_E~0); 6969#L1055-1 assume !(1 == ~T7_E~0); 6790#L1060-1 assume !(1 == ~T8_E~0); 6791#L1065-1 assume !(1 == ~T9_E~0); 6854#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 7451#L1075-1 assume !(1 == ~E_2~0); 7452#L1080-1 assume !(1 == ~E_3~0); 7440#L1085-1 assume !(1 == ~E_4~0); 7441#L1090-1 assume !(1 == ~E_5~0); 7640#L1095-1 assume !(1 == ~E_6~0); 7474#L1100-1 assume !(1 == ~E_7~0); 7475#L1105-1 assume !(1 == ~E_8~0); 6763#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 6764#L1115-1 assume { :end_inline_reset_delta_events } true; 6925#L1396-2 [2022-10-17 10:09:39,143 INFO L750 eck$LassoCheckResult]: Loop: 6925#L1396-2 assume !false; 7008#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7037#L897 assume !false; 7680#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 7587#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 6637#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 6638#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 7635#L766 assume !(0 != eval_~tmp~0#1); 7621#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6705#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6706#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7222#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6949#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6950#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7128#L937-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6755#L942-3 assume !(0 == ~T5_E~0); 6756#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7129#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7130#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 7631#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 7522#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7523#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7443#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7444#L982-3 assume !(0 == ~E_4~0); 7692#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7079#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7080#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 7077#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 7078#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 6792#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6793#L443-30 assume 1 == ~m_pc~0; 6826#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 6827#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7110#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7658#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7577#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7210#L462-30 assume !(1 == ~t1_pc~0); 7056#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 7057#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7558#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7559#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7599#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7197#L481-30 assume 1 == ~t2_pc~0; 6916#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6917#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6970#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6886#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6887#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7164#L500-30 assume 1 == ~t3_pc~0; 6921#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6922#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6984#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6985#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7147#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7148#L519-30 assume !(1 == ~t4_pc~0); 7322#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 7299#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6661#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6662#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7311#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7424#L538-30 assume 1 == ~t5_pc~0; 6802#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6803#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7101#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7102#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6879#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6880#L557-30 assume 1 == ~t6_pc~0; 6600#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6601#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7278#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7332#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 6904#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6905#L576-30 assume 1 == ~t7_pc~0; 7417#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6685#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7271#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7638#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 7062#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7027#L595-30 assume !(1 == ~t8_pc~0); 7028#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 6961#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6696#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6697#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7639#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7675#L614-30 assume 1 == ~t9_pc~0; 6964#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 6965#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7100#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6794#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 6795#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7403#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7188#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7189#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7373#L1035-3 assume !(1 == ~T3_E~0); 7648#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7688#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7644#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7557#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6694#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6695#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7579#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7425#L1075-3 assume !(1 == ~E_2~0); 7426#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7649#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7570#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7571#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 7590#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 7591#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 6842#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 6843#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 7603#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 6711#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 6700#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 6701#L1415 assume !(0 == start_simulation_~tmp~3#1); 7303#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 7304#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 6751#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 7313#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 7492#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7693#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7363#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 6924#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 6925#L1396-2 [2022-10-17 10:09:39,144 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:09:39,144 INFO L85 PathProgramCache]: Analyzing trace with hash 1764315747, now seen corresponding path program 1 times [2022-10-17 10:09:39,145 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:09:39,146 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1070842737] [2022-10-17 10:09:39,146 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:09:39,147 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:09:39,167 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:09:39,228 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:09:39,229 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:09:39,229 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1070842737] [2022-10-17 10:09:39,230 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1070842737] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:09:39,230 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:09:39,231 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:09:39,235 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [693009820] [2022-10-17 10:09:39,235 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:09:39,235 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:09:39,236 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:09:39,236 INFO L85 PathProgramCache]: Analyzing trace with hash -173500974, now seen corresponding path program 1 times [2022-10-17 10:09:39,237 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:09:39,241 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2056567153] [2022-10-17 10:09:39,242 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:09:39,243 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:09:39,271 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:09:39,336 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:09:39,336 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:09:39,336 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2056567153] [2022-10-17 10:09:39,336 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2056567153] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:09:39,337 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:09:39,337 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:09:39,337 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2130571206] [2022-10-17 10:09:39,338 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:09:39,338 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:09:39,338 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:09:39,340 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:09:39,340 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:09:39,340 INFO L87 Difference]: Start difference. First operand 1094 states and 1628 transitions. cyclomatic complexity: 535 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:09:39,368 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:09:39,368 INFO L93 Difference]: Finished difference Result 1094 states and 1627 transitions. [2022-10-17 10:09:39,368 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1094 states and 1627 transitions. [2022-10-17 10:09:39,378 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 969 [2022-10-17 10:09:39,388 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1094 states to 1094 states and 1627 transitions. [2022-10-17 10:09:39,389 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1094 [2022-10-17 10:09:39,390 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1094 [2022-10-17 10:09:39,390 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1094 states and 1627 transitions. [2022-10-17 10:09:39,392 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:09:39,392 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1094 states and 1627 transitions. [2022-10-17 10:09:39,395 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1094 states and 1627 transitions. [2022-10-17 10:09:39,410 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1094 to 1094. [2022-10-17 10:09:39,413 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1094 states, 1094 states have (on average 1.487202925045704) internal successors, (1627), 1093 states have internal predecessors, (1627), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:09:39,419 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1094 states to 1094 states and 1627 transitions. [2022-10-17 10:09:39,419 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1094 states and 1627 transitions. [2022-10-17 10:09:39,419 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:09:39,420 INFO L428 stractBuchiCegarLoop]: Abstraction has 1094 states and 1627 transitions. [2022-10-17 10:09:39,420 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-10-17 10:09:39,421 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1094 states and 1627 transitions. [2022-10-17 10:09:39,428 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 969 [2022-10-17 10:09:39,429 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:09:39,429 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:09:39,431 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:09:39,431 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:09:39,432 INFO L748 eck$LassoCheckResult]: Stem: 9632#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 9633#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 9233#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9234#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9780#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 9781#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9763#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9583#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9584#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9400#L661-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 9401#L666-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 9841#L671-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 9747#L676-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 9455#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 9239#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9240#L922 assume !(0 == ~M_E~0); 9885#L922-2 assume !(0 == ~T1_E~0); 9886#L927-1 assume !(0 == ~T2_E~0); 9640#L932-1 assume !(0 == ~T3_E~0); 9525#L937-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9526#L942-1 assume !(0 == ~T5_E~0); 9582#L947-1 assume !(0 == ~T6_E~0); 9644#L952-1 assume !(0 == ~T7_E~0); 9645#L957-1 assume !(0 == ~T8_E~0); 9707#L962-1 assume !(0 == ~T9_E~0); 9501#L967-1 assume !(0 == ~E_1~0); 9502#L972-1 assume !(0 == ~E_2~0); 9768#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 9769#L982-1 assume !(0 == ~E_4~0); 9009#L987-1 assume !(0 == ~E_5~0); 9010#L992-1 assume !(0 == ~E_6~0); 9018#L997-1 assume !(0 == ~E_7~0); 9434#L1002-1 assume !(0 == ~E_8~0); 9420#L1007-1 assume !(0 == ~E_9~0); 8807#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8808#L443 assume !(1 == ~m_pc~0); 9660#L443-2 is_master_triggered_~__retres1~0#1 := 0; 9651#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9652#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9173#L1140 assume !(0 != activate_threads_~tmp~1#1); 8922#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8923#L462 assume 1 == ~t1_pc~0; 9551#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9519#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8893#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8894#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 9381#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9382#L481 assume !(1 == ~t2_pc~0); 9168#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 9167#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9522#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9261#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 9262#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9356#L500 assume 1 == ~t3_pc~0; 9564#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9565#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9755#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9756#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 8812#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8813#L519 assume 1 == ~t4_pc~0; 9111#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9112#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9353#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9215#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 9216#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8976#L538 assume !(1 == ~t5_pc~0); 8977#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 8883#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8884#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9152#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9153#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9692#L557 assume 1 == ~t6_pc~0; 9489#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 9190#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9092#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9093#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 9217#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9868#L576 assume !(1 == ~t7_pc~0); 9177#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 9178#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9422#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9423#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 9739#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9298#L595 assume 1 == ~t8_pc~0; 9299#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 9757#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9758#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9607#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 9608#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9101#L614 assume !(1 == ~t9_pc~0); 9102#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 9001#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9002#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9181#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 9263#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9264#L1025 assume !(1 == ~M_E~0); 9510#L1025-2 assume !(1 == ~T1_E~0); 9563#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9685#L1035-1 assume !(1 == ~T3_E~0); 9258#L1040-1 assume !(1 == ~T4_E~0); 9259#L1045-1 assume !(1 == ~T5_E~0); 9163#L1050-1 assume !(1 == ~T6_E~0); 9164#L1055-1 assume !(1 == ~T7_E~0); 8985#L1060-1 assume !(1 == ~T8_E~0); 8986#L1065-1 assume !(1 == ~T9_E~0); 9049#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 9646#L1075-1 assume !(1 == ~E_2~0); 9647#L1080-1 assume !(1 == ~E_3~0); 9635#L1085-1 assume !(1 == ~E_4~0); 9636#L1090-1 assume !(1 == ~E_5~0); 9835#L1095-1 assume !(1 == ~E_6~0); 9669#L1100-1 assume !(1 == ~E_7~0); 9670#L1105-1 assume !(1 == ~E_8~0); 8958#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 8959#L1115-1 assume { :end_inline_reset_delta_events } true; 9120#L1396-2 [2022-10-17 10:09:39,432 INFO L750 eck$LassoCheckResult]: Loop: 9120#L1396-2 assume !false; 9206#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9232#L897 assume !false; 9875#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 9782#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 8832#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 8833#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 9830#L766 assume !(0 != eval_~tmp~0#1); 9816#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8900#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8901#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9417#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9144#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9145#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9323#L937-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8950#L942-3 assume !(0 == ~T5_E~0); 8951#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9324#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 9325#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 9826#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 9717#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9718#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9638#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9639#L982-3 assume !(0 == ~E_4~0); 9887#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9274#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9275#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9272#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 9273#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 8987#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8988#L443-30 assume 1 == ~m_pc~0; 9021#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 9022#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9305#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9853#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9773#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9405#L462-30 assume 1 == ~t1_pc~0; 9250#L463-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9252#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9752#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9753#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9794#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9392#L481-30 assume 1 == ~t2_pc~0; 9108#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9109#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9165#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9078#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9079#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9359#L500-30 assume 1 == ~t3_pc~0; 9116#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9117#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9179#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9180#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9342#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9343#L519-30 assume !(1 == ~t4_pc~0); 9517#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 9494#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8856#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8857#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9506#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9619#L538-30 assume 1 == ~t5_pc~0; 8997#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8998#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9296#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9297#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9074#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9075#L557-30 assume 1 == ~t6_pc~0; 8795#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8796#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9473#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9527#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 9099#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9100#L576-30 assume 1 == ~t7_pc~0; 9612#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8880#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9467#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9833#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9257#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9222#L595-30 assume !(1 == ~t8_pc~0); 9223#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 9158#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8891#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8892#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 9834#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9870#L614-30 assume 1 == ~t9_pc~0; 9160#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 9161#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9295#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8989#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 8990#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9598#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9383#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9384#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9568#L1035-3 assume !(1 == ~T3_E~0); 9843#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9883#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9839#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9754#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8889#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8890#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 9774#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9620#L1075-3 assume !(1 == ~E_2~0); 9621#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9844#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9765#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9766#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 9785#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 9786#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 9037#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 9038#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 9798#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 8906#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 8895#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 8896#L1415 assume !(0 == start_simulation_~tmp~3#1); 9499#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 9500#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 8946#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 9508#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 9687#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9888#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9558#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 9119#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 9120#L1396-2 [2022-10-17 10:09:39,435 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:09:39,435 INFO L85 PathProgramCache]: Analyzing trace with hash -388791071, now seen corresponding path program 1 times [2022-10-17 10:09:39,435 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:09:39,435 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [829865491] [2022-10-17 10:09:39,436 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:09:39,436 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:09:39,451 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:09:39,489 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:09:39,489 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:09:39,490 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [829865491] [2022-10-17 10:09:39,490 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [829865491] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:09:39,490 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:09:39,490 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:09:39,490 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [248685432] [2022-10-17 10:09:39,491 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:09:39,491 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:09:39,492 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:09:39,492 INFO L85 PathProgramCache]: Analyzing trace with hash -1095421325, now seen corresponding path program 1 times [2022-10-17 10:09:39,492 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:09:39,493 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [855079692] [2022-10-17 10:09:39,494 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:09:39,494 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:09:39,512 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:09:39,563 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:09:39,563 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:09:39,564 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [855079692] [2022-10-17 10:09:39,564 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [855079692] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:09:39,564 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:09:39,564 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:09:39,564 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1442263637] [2022-10-17 10:09:39,565 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:09:39,565 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:09:39,565 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:09:39,566 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:09:39,566 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:09:39,566 INFO L87 Difference]: Start difference. First operand 1094 states and 1627 transitions. cyclomatic complexity: 534 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:09:39,593 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:09:39,593 INFO L93 Difference]: Finished difference Result 1094 states and 1626 transitions. [2022-10-17 10:09:39,593 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1094 states and 1626 transitions. [2022-10-17 10:09:39,604 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 969 [2022-10-17 10:09:39,614 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1094 states to 1094 states and 1626 transitions. [2022-10-17 10:09:39,615 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1094 [2022-10-17 10:09:39,616 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1094 [2022-10-17 10:09:39,616 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1094 states and 1626 transitions. [2022-10-17 10:09:39,618 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:09:39,618 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1094 states and 1626 transitions. [2022-10-17 10:09:39,621 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1094 states and 1626 transitions. [2022-10-17 10:09:39,636 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1094 to 1094. [2022-10-17 10:09:39,639 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1094 states, 1094 states have (on average 1.4862888482632541) internal successors, (1626), 1093 states have internal predecessors, (1626), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:09:39,644 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1094 states to 1094 states and 1626 transitions. [2022-10-17 10:09:39,645 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1094 states and 1626 transitions. [2022-10-17 10:09:39,645 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:09:39,648 INFO L428 stractBuchiCegarLoop]: Abstraction has 1094 states and 1626 transitions. [2022-10-17 10:09:39,648 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-10-17 10:09:39,648 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1094 states and 1626 transitions. [2022-10-17 10:09:39,656 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 969 [2022-10-17 10:09:39,656 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:09:39,657 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:09:39,659 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:09:39,659 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:09:39,660 INFO L748 eck$LassoCheckResult]: Stem: 11827#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 11828#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 11428#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11429#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11975#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 11976#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11958#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11778#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 11779#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11595#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 11596#L666-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 12036#L671-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 11942#L676-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 11650#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 11434#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11435#L922 assume !(0 == ~M_E~0); 12080#L922-2 assume !(0 == ~T1_E~0); 12081#L927-1 assume !(0 == ~T2_E~0); 11835#L932-1 assume !(0 == ~T3_E~0); 11720#L937-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11721#L942-1 assume !(0 == ~T5_E~0); 11777#L947-1 assume !(0 == ~T6_E~0); 11839#L952-1 assume !(0 == ~T7_E~0); 11840#L957-1 assume !(0 == ~T8_E~0); 11902#L962-1 assume !(0 == ~T9_E~0); 11696#L967-1 assume !(0 == ~E_1~0); 11697#L972-1 assume !(0 == ~E_2~0); 11963#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 11964#L982-1 assume !(0 == ~E_4~0); 11204#L987-1 assume !(0 == ~E_5~0); 11205#L992-1 assume !(0 == ~E_6~0); 11213#L997-1 assume !(0 == ~E_7~0); 11629#L1002-1 assume !(0 == ~E_8~0); 11615#L1007-1 assume !(0 == ~E_9~0); 11002#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11003#L443 assume !(1 == ~m_pc~0); 11855#L443-2 is_master_triggered_~__retres1~0#1 := 0; 11846#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11847#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11368#L1140 assume !(0 != activate_threads_~tmp~1#1); 11117#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11118#L462 assume 1 == ~t1_pc~0; 11746#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11716#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11088#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11089#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 11576#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11577#L481 assume !(1 == ~t2_pc~0); 11363#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 11362#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11717#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11456#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 11457#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11551#L500 assume 1 == ~t3_pc~0; 11759#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11760#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11950#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11951#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 11007#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11008#L519 assume 1 == ~t4_pc~0; 11306#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11307#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11548#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11410#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 11411#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11171#L538 assume !(1 == ~t5_pc~0); 11172#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 11078#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11079#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11347#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11348#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11887#L557 assume 1 == ~t6_pc~0; 11684#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11385#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11287#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11288#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 11412#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12063#L576 assume !(1 == ~t7_pc~0); 11372#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 11373#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11617#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11618#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 11934#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11495#L595 assume 1 == ~t8_pc~0; 11496#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 11952#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11953#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11802#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 11803#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11296#L614 assume !(1 == ~t9_pc~0); 11297#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 11196#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11197#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 11376#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 11458#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11459#L1025 assume !(1 == ~M_E~0); 11705#L1025-2 assume !(1 == ~T1_E~0); 11758#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11881#L1035-1 assume !(1 == ~T3_E~0); 11453#L1040-1 assume !(1 == ~T4_E~0); 11454#L1045-1 assume !(1 == ~T5_E~0); 11358#L1050-1 assume !(1 == ~T6_E~0); 11359#L1055-1 assume !(1 == ~T7_E~0); 11180#L1060-1 assume !(1 == ~T8_E~0); 11181#L1065-1 assume !(1 == ~T9_E~0); 11244#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 11841#L1075-1 assume !(1 == ~E_2~0); 11842#L1080-1 assume !(1 == ~E_3~0); 11830#L1085-1 assume !(1 == ~E_4~0); 11831#L1090-1 assume !(1 == ~E_5~0); 12030#L1095-1 assume !(1 == ~E_6~0); 11864#L1100-1 assume !(1 == ~E_7~0); 11865#L1105-1 assume !(1 == ~E_8~0); 11153#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 11154#L1115-1 assume { :end_inline_reset_delta_events } true; 11315#L1396-2 [2022-10-17 10:09:39,661 INFO L750 eck$LassoCheckResult]: Loop: 11315#L1396-2 assume !false; 11401#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11427#L897 assume !false; 12070#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 11977#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 11027#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 11028#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 12025#L766 assume !(0 != eval_~tmp~0#1); 12011#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11095#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11096#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 11612#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11339#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11340#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11518#L937-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11145#L942-3 assume !(0 == ~T5_E~0); 11146#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11519#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11520#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12021#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 11912#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11913#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11833#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11834#L982-3 assume !(0 == ~E_4~0); 12082#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 11469#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 11470#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 11464#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 11465#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 11182#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11183#L443-30 assume 1 == ~m_pc~0; 11216#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 11217#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11500#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12048#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11967#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11600#L462-30 assume 1 == ~t1_pc~0; 11444#L463-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11446#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11947#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11948#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11989#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11587#L481-30 assume 1 == ~t2_pc~0; 11303#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11304#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11360#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11273#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11274#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11554#L500-30 assume !(1 == ~t3_pc~0); 11313#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 11312#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11374#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11375#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11537#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11538#L519-30 assume 1 == ~t4_pc~0; 11873#L520-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11689#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11051#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11052#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11701#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11814#L538-30 assume 1 == ~t5_pc~0; 11192#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11193#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11491#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11492#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11269#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11270#L557-30 assume !(1 == ~t6_pc~0); 10992#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 10991#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11668#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11722#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 11294#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11295#L576-30 assume !(1 == ~t7_pc~0); 11076#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 11077#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11662#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12028#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11452#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11417#L595-30 assume !(1 == ~t8_pc~0); 11418#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 11353#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11086#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11087#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12029#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12065#L614-30 assume 1 == ~t9_pc~0; 11355#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 11356#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11490#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 11184#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 11185#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11793#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 11578#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11579#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11763#L1035-3 assume !(1 == ~T3_E~0); 12038#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12078#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12034#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 11949#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11084#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 11085#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11969#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11815#L1075-3 assume !(1 == ~E_2~0); 11816#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12039#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 11960#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 11961#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11980#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 11981#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 11232#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 11233#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 11993#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 11101#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 11090#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 11091#L1415 assume !(0 == start_simulation_~tmp~3#1); 11694#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 11695#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 11141#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 11703#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 11882#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12083#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11753#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 11314#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 11315#L1396-2 [2022-10-17 10:09:39,662 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:09:39,662 INFO L85 PathProgramCache]: Analyzing trace with hash 234490531, now seen corresponding path program 1 times [2022-10-17 10:09:39,663 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:09:39,663 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1454855336] [2022-10-17 10:09:39,663 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:09:39,663 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:09:39,680 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:09:39,715 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:09:39,715 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:09:39,716 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1454855336] [2022-10-17 10:09:39,716 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1454855336] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:09:39,716 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:09:39,716 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:09:39,721 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1905567643] [2022-10-17 10:09:39,721 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:09:39,723 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:09:39,725 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:09:39,725 INFO L85 PathProgramCache]: Analyzing trace with hash 1306266033, now seen corresponding path program 1 times [2022-10-17 10:09:39,725 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:09:39,726 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2014058708] [2022-10-17 10:09:39,726 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:09:39,726 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:09:39,776 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:09:39,823 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:09:39,823 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:09:39,824 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2014058708] [2022-10-17 10:09:39,828 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2014058708] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:09:39,828 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:09:39,828 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:09:39,828 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1302801918] [2022-10-17 10:09:39,828 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:09:39,829 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:09:39,829 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:09:39,830 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:09:39,830 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:09:39,831 INFO L87 Difference]: Start difference. First operand 1094 states and 1626 transitions. cyclomatic complexity: 533 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:09:39,864 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:09:39,865 INFO L93 Difference]: Finished difference Result 1094 states and 1625 transitions. [2022-10-17 10:09:39,865 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1094 states and 1625 transitions. [2022-10-17 10:09:39,875 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 969 [2022-10-17 10:09:39,884 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1094 states to 1094 states and 1625 transitions. [2022-10-17 10:09:39,884 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1094 [2022-10-17 10:09:39,885 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1094 [2022-10-17 10:09:39,886 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1094 states and 1625 transitions. [2022-10-17 10:09:39,888 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:09:39,889 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1094 states and 1625 transitions. [2022-10-17 10:09:39,891 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1094 states and 1625 transitions. [2022-10-17 10:09:39,906 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1094 to 1094. [2022-10-17 10:09:39,910 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1094 states, 1094 states have (on average 1.4853747714808043) internal successors, (1625), 1093 states have internal predecessors, (1625), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:09:39,915 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1094 states to 1094 states and 1625 transitions. [2022-10-17 10:09:39,915 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1094 states and 1625 transitions. [2022-10-17 10:09:39,916 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:09:39,917 INFO L428 stractBuchiCegarLoop]: Abstraction has 1094 states and 1625 transitions. [2022-10-17 10:09:39,917 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-10-17 10:09:39,918 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1094 states and 1625 transitions. [2022-10-17 10:09:39,925 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 969 [2022-10-17 10:09:39,925 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:09:39,926 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:09:39,928 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:09:39,928 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:09:39,928 INFO L748 eck$LassoCheckResult]: Stem: 14022#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 14023#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 13623#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13624#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14170#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 14171#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14153#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13973#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 13974#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 13790#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 13791#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 14231#L671-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 14137#L676-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 13845#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 13629#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13630#L922 assume !(0 == ~M_E~0); 14275#L922-2 assume !(0 == ~T1_E~0); 14276#L927-1 assume !(0 == ~T2_E~0); 14030#L932-1 assume !(0 == ~T3_E~0); 13915#L937-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13916#L942-1 assume !(0 == ~T5_E~0); 13972#L947-1 assume !(0 == ~T6_E~0); 14034#L952-1 assume !(0 == ~T7_E~0); 14035#L957-1 assume !(0 == ~T8_E~0); 14098#L962-1 assume !(0 == ~T9_E~0); 13891#L967-1 assume !(0 == ~E_1~0); 13892#L972-1 assume !(0 == ~E_2~0); 14158#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 14159#L982-1 assume !(0 == ~E_4~0); 13401#L987-1 assume !(0 == ~E_5~0); 13402#L992-1 assume !(0 == ~E_6~0); 13408#L997-1 assume !(0 == ~E_7~0); 13824#L1002-1 assume !(0 == ~E_8~0); 13810#L1007-1 assume !(0 == ~E_9~0); 13197#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13198#L443 assume !(1 == ~m_pc~0); 14050#L443-2 is_master_triggered_~__retres1~0#1 := 0; 14041#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14042#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13563#L1140 assume !(0 != activate_threads_~tmp~1#1); 13312#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13313#L462 assume 1 == ~t1_pc~0; 13941#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13911#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13283#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13284#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 13771#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13772#L481 assume !(1 == ~t2_pc~0); 13558#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 13557#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13912#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13651#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 13652#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13746#L500 assume 1 == ~t3_pc~0; 13954#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13955#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14145#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14146#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 13202#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13203#L519 assume 1 == ~t4_pc~0; 13501#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13502#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13743#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13605#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 13606#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13366#L538 assume !(1 == ~t5_pc~0); 13367#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 13273#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13274#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13542#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 13543#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14082#L557 assume 1 == ~t6_pc~0; 13879#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13580#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13484#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13485#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 13607#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14258#L576 assume !(1 == ~t7_pc~0); 13567#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 13568#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13812#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13813#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 14129#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13690#L595 assume 1 == ~t8_pc~0; 13691#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 14147#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14148#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13997#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 13998#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13491#L614 assume !(1 == ~t9_pc~0); 13492#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 13391#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13392#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13571#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 13653#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13654#L1025 assume !(1 == ~M_E~0); 13900#L1025-2 assume !(1 == ~T1_E~0); 13953#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14076#L1035-1 assume !(1 == ~T3_E~0); 13648#L1040-1 assume !(1 == ~T4_E~0); 13649#L1045-1 assume !(1 == ~T5_E~0); 13553#L1050-1 assume !(1 == ~T6_E~0); 13554#L1055-1 assume !(1 == ~T7_E~0); 13375#L1060-1 assume !(1 == ~T8_E~0); 13376#L1065-1 assume !(1 == ~T9_E~0); 13439#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 14036#L1075-1 assume !(1 == ~E_2~0); 14037#L1080-1 assume !(1 == ~E_3~0); 14025#L1085-1 assume !(1 == ~E_4~0); 14026#L1090-1 assume !(1 == ~E_5~0); 14225#L1095-1 assume !(1 == ~E_6~0); 14059#L1100-1 assume !(1 == ~E_7~0); 14060#L1105-1 assume !(1 == ~E_8~0); 13348#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 13349#L1115-1 assume { :end_inline_reset_delta_events } true; 13510#L1396-2 [2022-10-17 10:09:39,929 INFO L750 eck$LassoCheckResult]: Loop: 13510#L1396-2 assume !false; 13596#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13620#L897 assume !false; 14265#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 14172#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 13222#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 13223#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 14220#L766 assume !(0 != eval_~tmp~0#1); 14206#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13290#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13291#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13807#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13534#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13535#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13713#L937-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13340#L942-3 assume !(0 == ~T5_E~0); 13341#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 13714#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 13715#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 14216#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 14107#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14108#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14028#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14029#L982-3 assume !(0 == ~E_4~0); 14277#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13664#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13665#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13659#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 13660#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 13377#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13378#L443-30 assume 1 == ~m_pc~0; 13411#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 13412#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13695#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 14243#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14162#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13795#L462-30 assume 1 == ~t1_pc~0; 13639#L463-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13641#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14142#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14143#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14184#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13782#L481-30 assume 1 == ~t2_pc~0; 13498#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13499#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13555#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13468#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 13469#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13749#L500-30 assume 1 == ~t3_pc~0; 13506#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13507#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13569#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13570#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13732#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13733#L519-30 assume 1 == ~t4_pc~0; 14068#L520-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13884#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13246#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13247#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13896#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14009#L538-30 assume 1 == ~t5_pc~0; 13387#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13388#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13686#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13687#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 13464#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13465#L557-30 assume 1 == ~t6_pc~0; 13185#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13186#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13863#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13920#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 13489#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13490#L576-30 assume 1 == ~t7_pc~0; 14002#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 13272#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13857#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14223#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 13647#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13612#L595-30 assume !(1 == ~t8_pc~0); 13613#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 13548#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13281#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13282#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 14224#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14260#L614-30 assume !(1 == ~t9_pc~0); 13552#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 13551#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13685#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13379#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 13380#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13988#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 13773#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13774#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13958#L1035-3 assume !(1 == ~T3_E~0); 14233#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14273#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14229#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14144#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13279#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 13280#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14164#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 14010#L1075-3 assume !(1 == ~E_2~0); 14011#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14234#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14155#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14156#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14175#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 14176#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 13427#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 13428#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 14189#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 13296#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 13285#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 13286#L1415 assume !(0 == start_simulation_~tmp~3#1); 13889#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 13890#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 13336#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 13898#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 14077#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14278#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13948#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 13509#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 13510#L1396-2 [2022-10-17 10:09:39,930 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:09:39,930 INFO L85 PathProgramCache]: Analyzing trace with hash 116049057, now seen corresponding path program 1 times [2022-10-17 10:09:39,930 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:09:39,930 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1388432526] [2022-10-17 10:09:39,930 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:09:39,931 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:09:39,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:09:39,988 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:09:39,988 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:09:39,988 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1388432526] [2022-10-17 10:09:39,988 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1388432526] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:09:39,989 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:09:39,989 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:09:39,989 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [553347063] [2022-10-17 10:09:39,989 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:09:39,990 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:09:39,990 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:09:39,990 INFO L85 PathProgramCache]: Analyzing trace with hash 1885053619, now seen corresponding path program 1 times [2022-10-17 10:09:39,990 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:09:39,991 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [239332848] [2022-10-17 10:09:39,991 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:09:39,991 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:09:40,007 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:09:40,084 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:09:40,084 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:09:40,084 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [239332848] [2022-10-17 10:09:40,085 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [239332848] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:09:40,085 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:09:40,085 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:09:40,085 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1693502493] [2022-10-17 10:09:40,085 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:09:40,086 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:09:40,086 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:09:40,087 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:09:40,087 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:09:40,087 INFO L87 Difference]: Start difference. First operand 1094 states and 1625 transitions. cyclomatic complexity: 532 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:09:40,114 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:09:40,114 INFO L93 Difference]: Finished difference Result 1094 states and 1624 transitions. [2022-10-17 10:09:40,114 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1094 states and 1624 transitions. [2022-10-17 10:09:40,124 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 969 [2022-10-17 10:09:40,134 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1094 states to 1094 states and 1624 transitions. [2022-10-17 10:09:40,134 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1094 [2022-10-17 10:09:40,136 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1094 [2022-10-17 10:09:40,136 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1094 states and 1624 transitions. [2022-10-17 10:09:40,138 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:09:40,138 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1094 states and 1624 transitions. [2022-10-17 10:09:40,141 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1094 states and 1624 transitions. [2022-10-17 10:09:40,158 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1094 to 1094. [2022-10-17 10:09:40,161 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1094 states, 1094 states have (on average 1.4844606946983547) internal successors, (1624), 1093 states have internal predecessors, (1624), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:09:40,166 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1094 states to 1094 states and 1624 transitions. [2022-10-17 10:09:40,166 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1094 states and 1624 transitions. [2022-10-17 10:09:40,167 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:09:40,169 INFO L428 stractBuchiCegarLoop]: Abstraction has 1094 states and 1624 transitions. [2022-10-17 10:09:40,169 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-10-17 10:09:40,170 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1094 states and 1624 transitions. [2022-10-17 10:09:40,178 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 969 [2022-10-17 10:09:40,178 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:09:40,178 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:09:40,180 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:09:40,180 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:09:40,181 INFO L748 eck$LassoCheckResult]: Stem: 16217#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 16218#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 15818#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15819#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16365#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 16366#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16349#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16168#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16169#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 15985#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 15986#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 16426#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 16332#L676-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 16040#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 15824#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15825#L922 assume !(0 == ~M_E~0); 16470#L922-2 assume !(0 == ~T1_E~0); 16471#L927-1 assume !(0 == ~T2_E~0); 16225#L932-1 assume !(0 == ~T3_E~0); 16110#L937-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 16111#L942-1 assume !(0 == ~T5_E~0); 16167#L947-1 assume !(0 == ~T6_E~0); 16229#L952-1 assume !(0 == ~T7_E~0); 16230#L957-1 assume !(0 == ~T8_E~0); 16293#L962-1 assume !(0 == ~T9_E~0); 16089#L967-1 assume !(0 == ~E_1~0); 16090#L972-1 assume !(0 == ~E_2~0); 16353#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 16354#L982-1 assume !(0 == ~E_4~0); 15596#L987-1 assume !(0 == ~E_5~0); 15597#L992-1 assume !(0 == ~E_6~0); 15603#L997-1 assume !(0 == ~E_7~0); 16019#L1002-1 assume !(0 == ~E_8~0); 16005#L1007-1 assume !(0 == ~E_9~0); 15392#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15393#L443 assume !(1 == ~m_pc~0); 16245#L443-2 is_master_triggered_~__retres1~0#1 := 0; 16236#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16237#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 15758#L1140 assume !(0 != activate_threads_~tmp~1#1); 15507#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15508#L462 assume 1 == ~t1_pc~0; 16136#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16106#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15478#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15479#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 15966#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15967#L481 assume !(1 == ~t2_pc~0); 15753#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 15752#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16107#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15846#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 15847#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15939#L500 assume 1 == ~t3_pc~0; 16149#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16150#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16340#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16341#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 15394#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15395#L519 assume 1 == ~t4_pc~0; 15693#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15694#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15938#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15798#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 15799#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15561#L538 assume !(1 == ~t5_pc~0); 15562#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 15468#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15469#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15737#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15738#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16275#L557 assume 1 == ~t6_pc~0; 16074#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15775#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15672#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15673#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 15800#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16453#L576 assume !(1 == ~t7_pc~0); 15762#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 15763#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16007#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16008#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 16324#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15883#L595 assume 1 == ~t8_pc~0; 15884#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16342#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16343#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16192#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 16193#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 15686#L614 assume !(1 == ~t9_pc~0); 15687#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 15585#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15586#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15766#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 15848#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15849#L1025 assume !(1 == ~M_E~0); 16095#L1025-2 assume !(1 == ~T1_E~0); 16148#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16270#L1035-1 assume !(1 == ~T3_E~0); 15842#L1040-1 assume !(1 == ~T4_E~0); 15843#L1045-1 assume !(1 == ~T5_E~0); 15748#L1050-1 assume !(1 == ~T6_E~0); 15749#L1055-1 assume !(1 == ~T7_E~0); 15570#L1060-1 assume !(1 == ~T8_E~0); 15571#L1065-1 assume !(1 == ~T9_E~0); 15634#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 16231#L1075-1 assume !(1 == ~E_2~0); 16232#L1080-1 assume !(1 == ~E_3~0); 16220#L1085-1 assume !(1 == ~E_4~0); 16221#L1090-1 assume !(1 == ~E_5~0); 16420#L1095-1 assume !(1 == ~E_6~0); 16254#L1100-1 assume !(1 == ~E_7~0); 16255#L1105-1 assume !(1 == ~E_8~0); 15543#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 15544#L1115-1 assume { :end_inline_reset_delta_events } true; 15707#L1396-2 [2022-10-17 10:09:40,181 INFO L750 eck$LassoCheckResult]: Loop: 15707#L1396-2 assume !false; 15788#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 15817#L897 assume !false; 16460#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 16367#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 15415#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 15416#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 16415#L766 assume !(0 != eval_~tmp~0#1); 16401#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15485#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 15486#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 15999#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15729#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15730#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 15908#L937-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15535#L942-3 assume !(0 == ~T5_E~0); 15536#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 15909#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 15910#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16411#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 16302#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16303#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16223#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 16224#L982-3 assume !(0 == ~E_4~0); 16472#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15859#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 15860#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 15854#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 15855#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 15572#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15573#L443-30 assume 1 == ~m_pc~0; 15606#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 15607#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15890#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 16438#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16357#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15990#L462-30 assume 1 == ~t1_pc~0; 15834#L463-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 15836#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16337#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16338#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 16379#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15977#L481-30 assume 1 == ~t2_pc~0; 15696#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 15697#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15750#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15663#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15664#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15944#L500-30 assume 1 == ~t3_pc~0; 15701#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15702#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15764#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15765#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15927#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15928#L519-30 assume 1 == ~t4_pc~0; 16263#L520-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 16079#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15441#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15442#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 16091#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16204#L538-30 assume !(1 == ~t5_pc~0); 15584#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 15583#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15881#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15882#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15659#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15660#L557-30 assume 1 == ~t6_pc~0; 15380#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15381#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16058#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16115#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 15684#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15685#L576-30 assume 1 == ~t7_pc~0; 16197#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 15467#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16052#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16418#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 15844#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15807#L595-30 assume !(1 == ~t8_pc~0); 15808#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 15743#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15476#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15477#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16419#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16455#L614-30 assume 1 == ~t9_pc~0; 15745#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 15746#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15880#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15574#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 15575#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16183#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 15968#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15969#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16153#L1035-3 assume !(1 == ~T3_E~0); 16428#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16468#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16424#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16339#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 15474#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 15475#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 16359#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16205#L1075-3 assume !(1 == ~E_2~0); 16206#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16429#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16350#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16351#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16370#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16371#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 15622#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 15623#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 16384#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 15491#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 15483#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 15484#L1415 assume !(0 == start_simulation_~tmp~3#1); 16084#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 16085#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 15531#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 16093#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 16272#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16473#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16143#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 15706#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 15707#L1396-2 [2022-10-17 10:09:40,182 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:09:40,182 INFO L85 PathProgramCache]: Analyzing trace with hash -1273244957, now seen corresponding path program 1 times [2022-10-17 10:09:40,183 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:09:40,183 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [437685600] [2022-10-17 10:09:40,183 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:09:40,184 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:09:40,198 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:09:40,236 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:09:40,236 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:09:40,236 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [437685600] [2022-10-17 10:09:40,238 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [437685600] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:09:40,239 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:09:40,239 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:09:40,239 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1468859853] [2022-10-17 10:09:40,241 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:09:40,242 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:09:40,242 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:09:40,243 INFO L85 PathProgramCache]: Analyzing trace with hash -1113508429, now seen corresponding path program 2 times [2022-10-17 10:09:40,243 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:09:40,243 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1702132292] [2022-10-17 10:09:40,243 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:09:40,243 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:09:40,259 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:09:40,353 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:09:40,353 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:09:40,354 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1702132292] [2022-10-17 10:09:40,356 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1702132292] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:09:40,356 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:09:40,356 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:09:40,357 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1899374743] [2022-10-17 10:09:40,357 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:09:40,358 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:09:40,358 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:09:40,359 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:09:40,359 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:09:40,359 INFO L87 Difference]: Start difference. First operand 1094 states and 1624 transitions. cyclomatic complexity: 531 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:09:40,389 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:09:40,390 INFO L93 Difference]: Finished difference Result 1094 states and 1623 transitions. [2022-10-17 10:09:40,390 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1094 states and 1623 transitions. [2022-10-17 10:09:40,403 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 969 [2022-10-17 10:09:40,414 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1094 states to 1094 states and 1623 transitions. [2022-10-17 10:09:40,414 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1094 [2022-10-17 10:09:40,415 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1094 [2022-10-17 10:09:40,415 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1094 states and 1623 transitions. [2022-10-17 10:09:40,417 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:09:40,418 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1094 states and 1623 transitions. [2022-10-17 10:09:40,420 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1094 states and 1623 transitions. [2022-10-17 10:09:40,438 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1094 to 1094. [2022-10-17 10:09:40,441 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1094 states, 1094 states have (on average 1.483546617915905) internal successors, (1623), 1093 states have internal predecessors, (1623), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:09:40,447 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1094 states to 1094 states and 1623 transitions. [2022-10-17 10:09:40,447 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1094 states and 1623 transitions. [2022-10-17 10:09:40,448 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:09:40,450 INFO L428 stractBuchiCegarLoop]: Abstraction has 1094 states and 1623 transitions. [2022-10-17 10:09:40,450 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-10-17 10:09:40,450 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1094 states and 1623 transitions. [2022-10-17 10:09:40,457 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 969 [2022-10-17 10:09:40,457 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:09:40,457 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:09:40,459 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:09:40,460 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:09:40,460 INFO L748 eck$LassoCheckResult]: Stem: 18411#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 18412#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 18013#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 18014#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 18560#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 18561#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18543#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18363#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 18364#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 18179#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 18180#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 18620#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 18526#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 18235#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 18019#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18020#L922 assume !(0 == ~M_E~0); 18665#L922-2 assume !(0 == ~T1_E~0); 18666#L927-1 assume !(0 == ~T2_E~0); 18420#L932-1 assume !(0 == ~T3_E~0); 18305#L937-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18306#L942-1 assume !(0 == ~T5_E~0); 18362#L947-1 assume !(0 == ~T6_E~0); 18424#L952-1 assume !(0 == ~T7_E~0); 18425#L957-1 assume !(0 == ~T8_E~0); 18485#L962-1 assume !(0 == ~T9_E~0); 18281#L967-1 assume !(0 == ~E_1~0); 18282#L972-1 assume !(0 == ~E_2~0); 18548#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 18549#L982-1 assume !(0 == ~E_4~0); 17789#L987-1 assume !(0 == ~E_5~0); 17790#L992-1 assume !(0 == ~E_6~0); 17798#L997-1 assume !(0 == ~E_7~0); 18212#L1002-1 assume !(0 == ~E_8~0); 18199#L1007-1 assume !(0 == ~E_9~0); 17587#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17588#L443 assume !(1 == ~m_pc~0); 18440#L443-2 is_master_triggered_~__retres1~0#1 := 0; 18431#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18432#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 17953#L1140 assume !(0 != activate_threads_~tmp~1#1); 17702#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17703#L462 assume 1 == ~t1_pc~0; 18331#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18298#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17673#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 17674#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 18160#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18161#L481 assume !(1 == ~t2_pc~0); 17948#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 17947#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18302#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18041#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 18042#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18134#L500 assume 1 == ~t3_pc~0; 18344#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18345#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18535#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18536#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 17589#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17590#L519 assume 1 == ~t4_pc~0; 17888#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17889#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18133#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17993#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 17994#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17756#L538 assume !(1 == ~t5_pc~0); 17757#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 17663#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17664#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17932#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 17933#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18470#L557 assume 1 == ~t6_pc~0; 18269#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17970#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17867#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17868#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 17995#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18648#L576 assume !(1 == ~t7_pc~0); 17957#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 17958#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 18202#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18203#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 18519#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18078#L595 assume 1 == ~t8_pc~0; 18079#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 18537#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18538#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18387#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 18388#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 17881#L614 assume !(1 == ~t9_pc~0); 17882#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 17780#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17781#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17961#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 18043#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18044#L1025 assume !(1 == ~M_E~0); 18290#L1025-2 assume !(1 == ~T1_E~0); 18343#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18465#L1035-1 assume !(1 == ~T3_E~0); 18037#L1040-1 assume !(1 == ~T4_E~0); 18038#L1045-1 assume !(1 == ~T5_E~0); 17943#L1050-1 assume !(1 == ~T6_E~0); 17944#L1055-1 assume !(1 == ~T7_E~0); 17765#L1060-1 assume !(1 == ~T8_E~0); 17766#L1065-1 assume !(1 == ~T9_E~0); 17829#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 18426#L1075-1 assume !(1 == ~E_2~0); 18427#L1080-1 assume !(1 == ~E_3~0); 18415#L1085-1 assume !(1 == ~E_4~0); 18416#L1090-1 assume !(1 == ~E_5~0); 18615#L1095-1 assume !(1 == ~E_6~0); 18449#L1100-1 assume !(1 == ~E_7~0); 18450#L1105-1 assume !(1 == ~E_8~0); 17738#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 17739#L1115-1 assume { :end_inline_reset_delta_events } true; 17902#L1396-2 [2022-10-17 10:09:40,461 INFO L750 eck$LassoCheckResult]: Loop: 17902#L1396-2 assume !false; 17983#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 18012#L897 assume !false; 18655#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 18562#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 17610#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 17611#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 18610#L766 assume !(0 != eval_~tmp~0#1); 18596#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17680#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17681#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 18194#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17924#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17925#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18103#L937-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17730#L942-3 assume !(0 == ~T5_E~0); 17731#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 18104#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 18105#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 18606#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 18497#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 18498#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 18418#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 18419#L982-3 assume !(0 == ~E_4~0); 18667#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 18054#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 18055#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 18049#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 18050#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 17767#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17768#L443-30 assume 1 == ~m_pc~0; 17801#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 17802#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18085#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 18633#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18552#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18185#L462-30 assume 1 == ~t1_pc~0; 18029#L463-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18031#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18532#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 18533#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 18574#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18172#L481-30 assume 1 == ~t2_pc~0; 17891#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17892#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17945#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 17858#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 17859#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18139#L500-30 assume 1 == ~t3_pc~0; 17896#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17897#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17959#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17960#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 18122#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18123#L519-30 assume 1 == ~t4_pc~0; 18458#L520-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 18274#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17636#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17637#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 18286#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18399#L538-30 assume 1 == ~t5_pc~0; 17777#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17778#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18076#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18077#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 17854#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17855#L557-30 assume 1 == ~t6_pc~0; 17575#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17576#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18253#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18310#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 17879#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17880#L576-30 assume 1 == ~t7_pc~0; 18392#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 17662#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 18247#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18613#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 18039#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18002#L595-30 assume !(1 == ~t8_pc~0); 18003#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 17938#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17671#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17672#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 18614#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 18650#L614-30 assume 1 == ~t9_pc~0; 17940#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 17941#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 18075#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17769#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 17770#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18378#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 18163#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 18164#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18348#L1035-3 assume !(1 == ~T3_E~0); 18623#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18663#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 18619#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 18534#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 17669#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 17670#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 18554#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 18400#L1075-3 assume !(1 == ~E_2~0); 18401#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 18624#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 18545#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 18546#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 18565#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 18566#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 17817#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 17818#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 18579#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 17686#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 17678#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 17679#L1415 assume !(0 == start_simulation_~tmp~3#1); 18279#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 18280#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 17726#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 18288#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 18467#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 18668#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18338#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 17901#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 17902#L1396-2 [2022-10-17 10:09:40,462 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:09:40,462 INFO L85 PathProgramCache]: Analyzing trace with hash 760149089, now seen corresponding path program 1 times [2022-10-17 10:09:40,462 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:09:40,462 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1348155507] [2022-10-17 10:09:40,463 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:09:40,463 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:09:40,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:09:40,577 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:09:40,577 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:09:40,577 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1348155507] [2022-10-17 10:09:40,578 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1348155507] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:09:40,578 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:09:40,578 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:09:40,578 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1501124605] [2022-10-17 10:09:40,578 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:09:40,579 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:09:40,579 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:09:40,579 INFO L85 PathProgramCache]: Analyzing trace with hash 1361732948, now seen corresponding path program 1 times [2022-10-17 10:09:40,580 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:09:40,580 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1552302012] [2022-10-17 10:09:40,580 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:09:40,580 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:09:40,597 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:09:40,644 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:09:40,644 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:09:40,644 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1552302012] [2022-10-17 10:09:40,644 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1552302012] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:09:40,645 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:09:40,645 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:09:40,645 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1495964176] [2022-10-17 10:09:40,645 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:09:40,646 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:09:40,646 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:09:40,646 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-10-17 10:09:40,646 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-10-17 10:09:40,647 INFO L87 Difference]: Start difference. First operand 1094 states and 1623 transitions. cyclomatic complexity: 530 Second operand has 4 states, 4 states have (on average 28.75) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:09:40,858 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:09:40,858 INFO L93 Difference]: Finished difference Result 2080 states and 3079 transitions. [2022-10-17 10:09:40,859 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2080 states and 3079 transitions. [2022-10-17 10:09:40,874 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1938 [2022-10-17 10:09:40,892 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2080 states to 2080 states and 3079 transitions. [2022-10-17 10:09:40,893 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2080 [2022-10-17 10:09:40,895 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2080 [2022-10-17 10:09:40,895 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2080 states and 3079 transitions. [2022-10-17 10:09:40,898 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:09:40,899 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2080 states and 3079 transitions. [2022-10-17 10:09:40,902 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2080 states and 3079 transitions. [2022-10-17 10:09:40,938 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2080 to 2080. [2022-10-17 10:09:40,943 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2080 states, 2080 states have (on average 1.4802884615384615) internal successors, (3079), 2079 states have internal predecessors, (3079), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:09:40,953 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2080 states to 2080 states and 3079 transitions. [2022-10-17 10:09:40,953 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2080 states and 3079 transitions. [2022-10-17 10:09:40,953 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-10-17 10:09:40,954 INFO L428 stractBuchiCegarLoop]: Abstraction has 2080 states and 3079 transitions. [2022-10-17 10:09:40,954 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-10-17 10:09:40,954 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2080 states and 3079 transitions. [2022-10-17 10:09:40,965 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1938 [2022-10-17 10:09:40,965 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:09:40,965 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:09:40,968 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:09:40,968 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:09:40,968 INFO L748 eck$LassoCheckResult]: Stem: 21618#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 21619#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 21198#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21199#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21774#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 21775#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21756#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21562#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21563#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 21369#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 21370#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 21839#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 21738#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 21426#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 21204#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21205#L922 assume !(0 == ~M_E~0); 21908#L922-2 assume !(0 == ~T1_E~0); 21909#L927-1 assume !(0 == ~T2_E~0); 21626#L932-1 assume !(0 == ~T3_E~0); 21498#L937-1 assume !(0 == ~T4_E~0); 21499#L942-1 assume !(0 == ~T5_E~0); 21561#L947-1 assume !(0 == ~T6_E~0); 21630#L952-1 assume !(0 == ~T7_E~0); 21631#L957-1 assume !(0 == ~T8_E~0); 21695#L962-1 assume !(0 == ~T9_E~0); 21473#L967-1 assume !(0 == ~E_1~0); 21474#L972-1 assume !(0 == ~E_2~0); 21761#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 21762#L982-1 assume !(0 == ~E_4~0); 20973#L987-1 assume !(0 == ~E_5~0); 20974#L992-1 assume !(0 == ~E_6~0); 20982#L997-1 assume !(0 == ~E_7~0); 21403#L1002-1 assume !(0 == ~E_8~0); 21390#L1007-1 assume !(0 == ~E_9~0); 20771#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20772#L443 assume !(1 == ~m_pc~0); 21646#L443-2 is_master_triggered_~__retres1~0#1 := 0; 21637#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21638#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 21137#L1140 assume !(0 != activate_threads_~tmp~1#1); 20886#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20887#L462 assume 1 == ~t1_pc~0; 21527#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21491#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20857#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 20858#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 21350#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21351#L481 assume !(1 == ~t2_pc~0); 21132#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 21131#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21495#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 21228#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 21229#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21323#L500 assume 1 == ~t3_pc~0; 21541#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 21542#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21748#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 21749#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 20773#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20774#L519 assume 1 == ~t4_pc~0; 21072#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21073#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21322#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 21178#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 21179#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20940#L538 assume !(1 == ~t5_pc~0); 20941#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 20847#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20848#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 21116#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 21117#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21678#L557 assume 1 == ~t6_pc~0; 21461#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 21154#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21054#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21055#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 21180#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21875#L576 assume !(1 == ~t7_pc~0); 21141#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 21142#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21393#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21394#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 21729#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21266#L595 assume 1 == ~t8_pc~0; 21267#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 21750#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21751#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21590#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 21591#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21065#L614 assume !(1 == ~t9_pc~0); 21066#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 20965#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20966#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21145#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 21230#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21231#L1025 assume !(1 == ~M_E~0); 21482#L1025-2 assume !(1 == ~T1_E~0); 21540#L1030-1 assume !(1 == ~T2_E~0); 21672#L1035-1 assume !(1 == ~T3_E~0); 21223#L1040-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 21224#L1045-1 assume !(1 == ~T5_E~0); 22604#L1050-1 assume !(1 == ~T6_E~0); 22603#L1055-1 assume !(1 == ~T7_E~0); 22602#L1060-1 assume !(1 == ~T8_E~0); 22601#L1065-1 assume !(1 == ~T9_E~0); 22600#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 22599#L1075-1 assume !(1 == ~E_2~0); 22598#L1080-1 assume !(1 == ~E_3~0); 21621#L1085-1 assume !(1 == ~E_4~0); 21622#L1090-1 assume !(1 == ~E_5~0); 21834#L1095-1 assume !(1 == ~E_6~0); 21886#L1100-1 assume !(1 == ~E_7~0); 21662#L1105-1 assume !(1 == ~E_8~0); 20922#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 20923#L1115-1 assume { :end_inline_reset_delta_events } true; 21167#L1396-2 [2022-10-17 10:09:40,969 INFO L750 eck$LassoCheckResult]: Loop: 21167#L1396-2 assume !false; 21168#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21884#L897 assume !false; 21885#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 21911#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 21919#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 21859#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 21860#L766 assume !(0 != eval_~tmp~0#1); 21813#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 20864#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 20865#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 21888#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 21889#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 21917#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22597#L937-3 assume !(0 == ~T4_E~0); 22596#L942-3 assume !(0 == ~T5_E~0); 22595#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 22594#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 22593#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 22592#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 22591#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 22590#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 22589#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 22588#L982-3 assume !(0 == ~E_4~0); 22587#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22586#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 22585#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 22584#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 22583#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 22582#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22581#L443-30 assume 1 == ~m_pc~0; 22579#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 22578#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22577#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 22576#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 22575#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22574#L462-30 assume !(1 == ~t1_pc~0); 22572#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 22571#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22570#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 22569#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22568#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22567#L481-30 assume 1 == ~t2_pc~0; 22565#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22564#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22563#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 22562#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22561#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22560#L500-30 assume !(1 == ~t3_pc~0); 22558#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 22557#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22556#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22555#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 22554#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22553#L519-30 assume 1 == ~t4_pc~0; 22551#L520-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 22550#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22549#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 22548#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 22547#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22546#L538-30 assume !(1 == ~t5_pc~0); 22544#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 22543#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22542#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22541#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 22540#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22539#L557-30 assume 1 == ~t6_pc~0; 22537#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 22536#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22535#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22534#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 22533#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22532#L576-30 assume 1 == ~t7_pc~0; 22530#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 22529#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22528#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22527#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 22526#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22525#L595-30 assume 1 == ~t8_pc~0; 22523#L596-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 22522#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22521#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22520#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 22519#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22518#L614-30 assume 1 == ~t9_pc~0; 22516#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22515#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22514#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 22513#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 22512#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22511#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 22510#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22509#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 21545#L1035-3 assume !(1 == ~T3_E~0); 22508#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 21905#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 22507#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 22506#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 22505#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 22504#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22503#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 22502#L1075-3 assume !(1 == ~E_2~0); 22501#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 22500#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 22499#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 22498#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 22497#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 22496#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 22495#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 22494#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 22113#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 22111#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 22110#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 22109#L1415 assume !(0 == start_simulation_~tmp~3#1); 22107#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 21887#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 20910#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 21480#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 21675#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 21913#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 21914#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 22015#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 21167#L1396-2 [2022-10-17 10:09:40,970 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:09:40,970 INFO L85 PathProgramCache]: Analyzing trace with hash -1269658465, now seen corresponding path program 1 times [2022-10-17 10:09:40,970 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:09:40,970 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [337755919] [2022-10-17 10:09:40,971 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:09:40,971 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:09:40,985 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:09:41,078 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:09:41,079 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:09:41,079 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [337755919] [2022-10-17 10:09:41,079 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [337755919] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:09:41,079 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:09:41,079 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:09:41,080 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1929772480] [2022-10-17 10:09:41,080 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:09:41,080 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:09:41,081 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:09:41,081 INFO L85 PathProgramCache]: Analyzing trace with hash 777468816, now seen corresponding path program 1 times [2022-10-17 10:09:41,081 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:09:41,081 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1666832284] [2022-10-17 10:09:41,081 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:09:41,082 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:09:41,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:09:41,141 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:09:41,141 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:09:41,142 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1666832284] [2022-10-17 10:09:41,142 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1666832284] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:09:41,142 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:09:41,142 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:09:41,142 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1605713102] [2022-10-17 10:09:41,142 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:09:41,143 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:09:41,143 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:09:41,143 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-10-17 10:09:41,144 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-10-17 10:09:41,144 INFO L87 Difference]: Start difference. First operand 2080 states and 3079 transitions. cyclomatic complexity: 1001 Second operand has 4 states, 4 states have (on average 28.75) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:09:41,373 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:09:41,373 INFO L93 Difference]: Finished difference Result 3898 states and 5766 transitions. [2022-10-17 10:09:41,373 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3898 states and 5766 transitions. [2022-10-17 10:09:41,403 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3732 [2022-10-17 10:09:41,437 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3898 states to 3898 states and 5766 transitions. [2022-10-17 10:09:41,437 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3898 [2022-10-17 10:09:41,444 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3898 [2022-10-17 10:09:41,444 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3898 states and 5766 transitions. [2022-10-17 10:09:41,450 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:09:41,450 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3898 states and 5766 transitions. [2022-10-17 10:09:41,455 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3898 states and 5766 transitions. [2022-10-17 10:09:41,529 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3898 to 3896. [2022-10-17 10:09:41,538 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3896 states, 3896 states have (on average 1.4794661190965093) internal successors, (5764), 3895 states have internal predecessors, (5764), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:09:41,556 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3896 states to 3896 states and 5764 transitions. [2022-10-17 10:09:41,556 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3896 states and 5764 transitions. [2022-10-17 10:09:41,557 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-10-17 10:09:41,558 INFO L428 stractBuchiCegarLoop]: Abstraction has 3896 states and 5764 transitions. [2022-10-17 10:09:41,558 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-10-17 10:09:41,558 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3896 states and 5764 transitions. [2022-10-17 10:09:41,575 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3732 [2022-10-17 10:09:41,575 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:09:41,575 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:09:41,577 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:09:41,578 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:09:41,578 INFO L748 eck$LassoCheckResult]: Stem: 27621#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 27622#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 27193#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 27194#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 27793#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 27794#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 27774#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 27564#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 27565#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 27368#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 27369#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 27873#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 27757#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 27430#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 27199#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 27200#L922 assume !(0 == ~M_E~0); 27938#L922-2 assume !(0 == ~T1_E~0); 27939#L927-1 assume !(0 == ~T2_E~0); 27630#L932-1 assume !(0 == ~T3_E~0); 27503#L937-1 assume !(0 == ~T4_E~0); 27504#L942-1 assume !(0 == ~T5_E~0); 27563#L947-1 assume !(0 == ~T6_E~0); 27634#L952-1 assume !(0 == ~T7_E~0); 27635#L957-1 assume !(0 == ~T8_E~0); 27703#L962-1 assume !(0 == ~T9_E~0); 27477#L967-1 assume !(0 == ~E_1~0); 27478#L972-1 assume !(0 == ~E_2~0); 27779#L977-1 assume !(0 == ~E_3~0); 27780#L982-1 assume !(0 == ~E_4~0); 26966#L987-1 assume !(0 == ~E_5~0); 26967#L992-1 assume !(0 == ~E_6~0); 26975#L997-1 assume !(0 == ~E_7~0); 27407#L1002-1 assume !(0 == ~E_8~0); 27393#L1007-1 assume !(0 == ~E_9~0); 26759#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26760#L443 assume !(1 == ~m_pc~0); 27650#L443-2 is_master_triggered_~__retres1~0#1 := 0; 27641#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27642#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 27132#L1140 assume !(0 != activate_threads_~tmp~1#1); 26875#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26876#L462 assume 1 == ~t1_pc~0; 27529#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27497#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26845#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 26846#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 27347#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27348#L481 assume !(1 == ~t2_pc~0); 27127#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 27126#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27500#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 27221#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 27222#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27321#L500 assume 1 == ~t3_pc~0; 27543#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27544#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 27766#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 27767#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 26764#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26765#L519 assume 1 == ~t4_pc~0; 27070#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 27071#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 27318#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 27175#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 27176#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26933#L538 assume !(1 == ~t5_pc~0); 26934#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 26835#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26836#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 27111#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 27112#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 27683#L557 assume 1 == ~t6_pc~0; 27465#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 27150#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27051#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27052#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 27177#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 27907#L576 assume !(1 == ~t7_pc~0); 27136#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 27137#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 27395#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27396#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 27744#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 27258#L595 assume 1 == ~t8_pc~0; 27259#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 27768#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27769#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 27591#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 27592#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 27060#L614 assume !(1 == ~t9_pc~0); 27061#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 26958#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 26959#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 27140#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 27223#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27224#L1025 assume !(1 == ~M_E~0); 27486#L1025-2 assume !(1 == ~T1_E~0); 27542#L1030-1 assume !(1 == ~T2_E~0); 27675#L1035-1 assume !(1 == ~T3_E~0); 27811#L1040-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 28159#L1045-1 assume !(1 == ~T5_E~0); 28115#L1050-1 assume !(1 == ~T6_E~0); 28113#L1055-1 assume !(1 == ~T7_E~0); 28111#L1060-1 assume !(1 == ~T8_E~0); 28110#L1065-1 assume !(1 == ~T9_E~0); 28069#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 28067#L1075-1 assume !(1 == ~E_2~0); 28066#L1080-1 assume 1 == ~E_3~0;~E_3~0 := 2; 28041#L1085-1 assume !(1 == ~E_4~0); 28023#L1090-1 assume !(1 == ~E_5~0); 28021#L1095-1 assume !(1 == ~E_6~0); 28019#L1100-1 assume !(1 == ~E_7~0); 28005#L1105-1 assume !(1 == ~E_8~0); 28003#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 27994#L1115-1 assume { :end_inline_reset_delta_events } true; 27987#L1396-2 [2022-10-17 10:09:41,579 INFO L750 eck$LassoCheckResult]: Loop: 27987#L1396-2 assume !false; 27981#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 27976#L897 assume !false; 27975#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 27974#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 27964#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 27963#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 27961#L766 assume !(0 != eval_~tmp~0#1); 27960#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 27959#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 27958#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 27957#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 27955#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 27956#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 29311#L937-3 assume !(0 == ~T4_E~0); 29298#L942-3 assume !(0 == ~T5_E~0); 27708#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 27285#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 27286#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 29273#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 27715#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 27716#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 29262#L977-3 assume !(0 == ~E_3~0); 29256#L982-3 assume !(0 == ~E_4~0); 29251#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 27234#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 27235#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 27232#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 27233#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 26944#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26945#L443-30 assume 1 == ~m_pc~0; 26978#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 26979#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27265#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 29222#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 29219#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29217#L462-30 assume 1 == ~t1_pc~0; 27210#L463-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27212#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27764#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 27765#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 27809#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27950#L481-30 assume 1 == ~t2_pc~0; 27067#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 27068#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27124#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 27036#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 27037#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27324#L500-30 assume 1 == ~t3_pc~0; 27075#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27076#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 27138#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 27139#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 27304#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 27305#L519-30 assume 1 == ~t4_pc~0; 27721#L520-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 28777#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28775#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 28773#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 28733#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28732#L538-30 assume !(1 == ~t5_pc~0); 28677#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 28644#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28642#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 28606#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 28603#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28572#L557-30 assume 1 == ~t6_pc~0; 28569#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 28567#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28536#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28533#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 28477#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28475#L576-30 assume 1 == ~t7_pc~0; 28471#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 28468#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28466#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 28369#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 28311#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 28309#L595-30 assume 1 == ~t8_pc~0; 28272#L596-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 28270#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 28268#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28266#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 28264#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28262#L614-30 assume 1 == ~t9_pc~0; 28259#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28257#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28256#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28255#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 28254#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28221#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 28219#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 28217#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 27547#L1035-3 assume !(1 == ~T3_E~0); 28214#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 27932#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 28180#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 28147#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 28145#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 28143#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 28141#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28139#L1075-3 assume !(1 == ~E_2~0); 28138#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 28136#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 28135#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 28134#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 28133#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 28132#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 28131#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 28130#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 28096#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 28094#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 28093#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 28092#L1415 assume !(0 == start_simulation_~tmp~3#1); 28090#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 28060#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 28039#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 28022#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 28020#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 28006#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 28004#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 27995#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 27987#L1396-2 [2022-10-17 10:09:41,579 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:09:41,579 INFO L85 PathProgramCache]: Analyzing trace with hash -1455005537, now seen corresponding path program 1 times [2022-10-17 10:09:41,580 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:09:41,580 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [94599425] [2022-10-17 10:09:41,580 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:09:41,580 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:09:41,597 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:09:41,666 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:09:41,667 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:09:41,667 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [94599425] [2022-10-17 10:09:41,667 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [94599425] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:09:41,667 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:09:41,667 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:09:41,668 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1661941072] [2022-10-17 10:09:41,668 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:09:41,668 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:09:41,668 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:09:41,669 INFO L85 PathProgramCache]: Analyzing trace with hash 85925648, now seen corresponding path program 1 times [2022-10-17 10:09:41,669 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:09:41,669 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1725146821] [2022-10-17 10:09:41,669 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:09:41,669 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:09:41,700 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:09:41,772 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:09:41,773 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:09:41,774 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1725146821] [2022-10-17 10:09:41,775 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1725146821] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:09:41,775 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:09:41,775 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:09:41,775 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1807270866] [2022-10-17 10:09:41,775 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:09:41,776 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:09:41,776 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:09:41,777 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-10-17 10:09:41,777 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-10-17 10:09:41,777 INFO L87 Difference]: Start difference. First operand 3896 states and 5764 transitions. cyclomatic complexity: 1872 Second operand has 4 states, 4 states have (on average 28.75) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:09:42,074 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:09:42,074 INFO L93 Difference]: Finished difference Result 10904 states and 15918 transitions. [2022-10-17 10:09:42,074 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10904 states and 15918 transitions. [2022-10-17 10:09:42,146 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10426 [2022-10-17 10:09:42,230 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10904 states to 10904 states and 15918 transitions. [2022-10-17 10:09:42,230 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10904 [2022-10-17 10:09:42,244 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10904 [2022-10-17 10:09:42,244 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10904 states and 15918 transitions. [2022-10-17 10:09:42,259 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:09:42,259 INFO L218 hiAutomatonCegarLoop]: Abstraction has 10904 states and 15918 transitions. [2022-10-17 10:09:42,273 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10904 states and 15918 transitions. [2022-10-17 10:09:42,571 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10904 to 10352. [2022-10-17 10:09:42,616 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10352 states, 10352 states have (on average 1.464258114374034) internal successors, (15158), 10351 states have internal predecessors, (15158), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:09:42,744 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10352 states to 10352 states and 15158 transitions. [2022-10-17 10:09:42,745 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10352 states and 15158 transitions. [2022-10-17 10:09:42,745 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-10-17 10:09:42,746 INFO L428 stractBuchiCegarLoop]: Abstraction has 10352 states and 15158 transitions. [2022-10-17 10:09:42,746 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-10-17 10:09:42,746 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10352 states and 15158 transitions. [2022-10-17 10:09:42,796 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10170 [2022-10-17 10:09:42,796 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:09:42,797 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:09:42,799 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:09:42,799 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:09:42,800 INFO L748 eck$LassoCheckResult]: Stem: 42433#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 42434#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 41999#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 42000#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 42609#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 42610#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 42588#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 42376#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 42377#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 42181#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 42182#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 42686#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 42569#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 42241#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 42005#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 42006#L922 assume !(0 == ~M_E~0); 42753#L922-2 assume !(0 == ~T1_E~0); 42754#L927-1 assume !(0 == ~T2_E~0); 42441#L932-1 assume !(0 == ~T3_E~0); 42314#L937-1 assume !(0 == ~T4_E~0); 42315#L942-1 assume !(0 == ~T5_E~0); 42375#L947-1 assume !(0 == ~T6_E~0); 42445#L952-1 assume !(0 == ~T7_E~0); 42446#L957-1 assume !(0 == ~T8_E~0); 42516#L962-1 assume !(0 == ~T9_E~0); 42291#L967-1 assume !(0 == ~E_1~0); 42292#L972-1 assume !(0 == ~E_2~0); 42593#L977-1 assume !(0 == ~E_3~0); 42594#L982-1 assume !(0 == ~E_4~0); 41773#L987-1 assume !(0 == ~E_5~0); 41774#L992-1 assume !(0 == ~E_6~0); 41780#L997-1 assume !(0 == ~E_7~0); 42219#L1002-1 assume !(0 == ~E_8~0); 42205#L1007-1 assume !(0 == ~E_9~0); 41569#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41570#L443 assume !(1 == ~m_pc~0); 42461#L443-2 is_master_triggered_~__retres1~0#1 := 0; 42451#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 42452#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 41937#L1140 assume !(0 != activate_threads_~tmp~1#1); 41684#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41685#L462 assume !(1 == ~t1_pc~0); 42308#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 42309#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41655#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 41656#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 42159#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42160#L481 assume !(1 == ~t2_pc~0); 41932#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 41931#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 42311#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 42028#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 42029#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 42134#L500 assume 1 == ~t3_pc~0; 42353#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 42354#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42579#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 42580#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 41574#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41575#L519 assume 1 == ~t4_pc~0; 41875#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 41876#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 42131#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 41980#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 41981#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41738#L538 assume !(1 == ~t5_pc~0); 41739#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 41645#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41646#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 41916#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 41917#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42501#L557 assume 1 == ~t6_pc~0; 42276#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 41955#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41858#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41859#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 41982#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 42723#L576 assume !(1 == ~t7_pc~0); 41941#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 41942#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 42207#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 42208#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 42558#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 42069#L595 assume 1 == ~t8_pc~0; 42070#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 42581#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 42582#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 42404#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 42405#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41865#L614 assume !(1 == ~t9_pc~0); 41866#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 41763#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 41764#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 41945#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 42030#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 42031#L1025 assume !(1 == ~M_E~0); 42298#L1025-2 assume !(1 == ~T1_E~0); 42352#L1030-1 assume !(1 == ~T2_E~0); 42492#L1035-1 assume !(1 == ~T3_E~0); 47150#L1040-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 42617#L1045-1 assume !(1 == ~T5_E~0); 42618#L1050-1 assume !(1 == ~T6_E~0); 42121#L1055-1 assume !(1 == ~T7_E~0); 42122#L1060-1 assume !(1 == ~T8_E~0); 50110#L1065-1 assume !(1 == ~T9_E~0); 42730#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 42731#L1075-1 assume !(1 == ~E_2~0); 50072#L1080-1 assume 1 == ~E_3~0;~E_3~0 := 2; 42761#L1085-1 assume !(1 == ~E_4~0); 51520#L1090-1 assume !(1 == ~E_5~0); 51519#L1095-1 assume !(1 == ~E_6~0); 51518#L1100-1 assume !(1 == ~E_7~0); 51517#L1105-1 assume !(1 == ~E_8~0); 51516#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 50320#L1115-1 assume { :end_inline_reset_delta_events } true; 50312#L1396-2 [2022-10-17 10:09:42,800 INFO L750 eck$LassoCheckResult]: Loop: 50312#L1396-2 assume !false; 50301#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 50296#L897 assume !false; 43031#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 43028#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 43019#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 49853#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 49850#L766 assume !(0 != eval_~tmp~0#1); 49851#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 51373#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 51370#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 51368#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 51367#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 51366#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 51365#L937-3 assume !(0 == ~T4_E~0); 51364#L942-3 assume !(0 == ~T5_E~0); 51361#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 50998#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 42666#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 42667#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 42528#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 42529#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 42439#L977-3 assume !(0 == ~E_3~0); 42440#L982-3 assume !(0 == ~E_4~0); 42758#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 42044#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 42045#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 42039#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 42040#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 41749#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41750#L443-30 assume !(1 == ~m_pc~0); 42091#L443-32 is_master_triggered_~__retres1~0#1 := 0; 42074#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 42075#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 42701#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 42599#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 42189#L462-30 assume !(1 == ~t1_pc~0); 42190#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 42592#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42576#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 42577#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 51563#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 51560#L481-30 assume 1 == ~t2_pc~0; 41872#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 41873#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41929#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 41842#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 41843#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 42137#L500-30 assume 1 == ~t3_pc~0; 41880#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 41881#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 41943#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 41944#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 42117#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 42118#L519-30 assume !(1 == ~t4_pc~0); 42307#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 42281#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41618#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 41619#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 42293#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 42419#L538-30 assume !(1 == ~t5_pc~0); 41761#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 41760#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 42065#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 42066#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 41837#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 41838#L557-30 assume 1 == ~t6_pc~0; 41557#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 41558#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 42260#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 42319#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 41863#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 41864#L576-30 assume 1 == ~t7_pc~0; 42409#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 41644#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 42254#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 42677#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 42024#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 41987#L595-30 assume !(1 == ~t8_pc~0); 41988#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 41922#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 41653#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 41654#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 42678#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 42725#L614-30 assume 1 == ~t9_pc~0; 41924#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 41925#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 42064#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 41751#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 41752#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 42393#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 42161#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 42162#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 42358#L1035-3 assume !(1 == ~T3_E~0); 42689#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 42750#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 42684#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 42578#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 41651#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 41652#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 42601#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 42420#L1075-3 assume !(1 == ~E_2~0); 42421#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 42690#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 42589#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 42590#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 42615#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 42616#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 41799#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 41800#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 42634#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 41668#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 41806#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 50501#L1415 assume !(0 == start_simulation_~tmp~3#1); 49867#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 49868#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 50341#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 50339#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 50336#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 50331#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 50326#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 50321#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 50312#L1396-2 [2022-10-17 10:09:42,801 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:09:42,801 INFO L85 PathProgramCache]: Analyzing trace with hash 212114046, now seen corresponding path program 1 times [2022-10-17 10:09:42,802 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:09:42,804 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1091236416] [2022-10-17 10:09:42,804 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:09:42,804 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:09:42,822 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:09:42,903 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:09:42,903 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:09:42,904 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1091236416] [2022-10-17 10:09:42,904 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1091236416] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:09:42,904 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:09:42,904 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:09:42,906 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1510029534] [2022-10-17 10:09:42,906 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:09:42,906 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:09:42,907 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:09:42,907 INFO L85 PathProgramCache]: Analyzing trace with hash -55973428, now seen corresponding path program 1 times [2022-10-17 10:09:42,907 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:09:42,907 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1511419367] [2022-10-17 10:09:42,908 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:09:42,908 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:09:42,925 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:09:42,974 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:09:42,975 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:09:42,975 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1511419367] [2022-10-17 10:09:42,975 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1511419367] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:09:42,975 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:09:42,975 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:09:42,976 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2050787445] [2022-10-17 10:09:42,976 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:09:42,976 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:09:42,977 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:09:42,977 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-10-17 10:09:42,977 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-10-17 10:09:42,978 INFO L87 Difference]: Start difference. First operand 10352 states and 15158 transitions. cyclomatic complexity: 4814 Second operand has 4 states, 4 states have (on average 28.75) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:09:43,475 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:09:43,476 INFO L93 Difference]: Finished difference Result 29295 states and 42485 transitions. [2022-10-17 10:09:43,476 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 29295 states and 42485 transitions. [2022-10-17 10:09:43,646 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 28430 [2022-10-17 10:09:43,759 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 29295 states to 29295 states and 42485 transitions. [2022-10-17 10:09:43,759 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 29295 [2022-10-17 10:09:43,789 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 29295 [2022-10-17 10:09:43,790 INFO L73 IsDeterministic]: Start isDeterministic. Operand 29295 states and 42485 transitions. [2022-10-17 10:09:43,820 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:09:43,821 INFO L218 hiAutomatonCegarLoop]: Abstraction has 29295 states and 42485 transitions. [2022-10-17 10:09:43,859 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29295 states and 42485 transitions. [2022-10-17 10:09:44,437 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29295 to 28051. [2022-10-17 10:09:44,502 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28051 states, 28051 states have (on average 1.4542440554703933) internal successors, (40793), 28050 states have internal predecessors, (40793), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:09:44,611 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28051 states to 28051 states and 40793 transitions. [2022-10-17 10:09:44,612 INFO L240 hiAutomatonCegarLoop]: Abstraction has 28051 states and 40793 transitions. [2022-10-17 10:09:44,612 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-10-17 10:09:44,613 INFO L428 stractBuchiCegarLoop]: Abstraction has 28051 states and 40793 transitions. [2022-10-17 10:09:44,613 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-10-17 10:09:44,613 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28051 states and 40793 transitions. [2022-10-17 10:09:44,848 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 27830 [2022-10-17 10:09:44,848 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:09:44,848 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:09:44,850 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:09:44,851 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:09:44,851 INFO L748 eck$LassoCheckResult]: Stem: 82084#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 82085#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 81657#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 81658#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 82264#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 82265#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 82243#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 82029#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 82030#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 81834#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 81835#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 82350#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 82224#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 81894#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 81663#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 81664#L922 assume !(0 == ~M_E~0); 82428#L922-2 assume !(0 == ~T1_E~0); 82429#L927-1 assume !(0 == ~T2_E~0); 82092#L932-1 assume !(0 == ~T3_E~0); 81970#L937-1 assume !(0 == ~T4_E~0); 81971#L942-1 assume !(0 == ~T5_E~0); 82028#L947-1 assume !(0 == ~T6_E~0); 82096#L952-1 assume !(0 == ~T7_E~0); 82097#L957-1 assume !(0 == ~T8_E~0); 82173#L962-1 assume !(0 == ~T9_E~0); 81947#L967-1 assume !(0 == ~E_1~0); 81948#L972-1 assume !(0 == ~E_2~0); 82248#L977-1 assume !(0 == ~E_3~0); 82249#L982-1 assume !(0 == ~E_4~0); 81430#L987-1 assume !(0 == ~E_5~0); 81431#L992-1 assume !(0 == ~E_6~0); 81437#L997-1 assume !(0 == ~E_7~0); 81869#L1002-1 assume !(0 == ~E_8~0); 81856#L1007-1 assume !(0 == ~E_9~0); 81226#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 81227#L443 assume !(1 == ~m_pc~0); 82117#L443-2 is_master_triggered_~__retres1~0#1 := 0; 82104#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 82105#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 81595#L1140 assume !(0 != activate_threads_~tmp~1#1); 81341#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 81342#L462 assume !(1 == ~t1_pc~0); 81962#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 81963#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 81312#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 81313#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 81814#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 81815#L481 assume !(1 == ~t2_pc~0); 81590#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 81589#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 81967#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 81687#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 81688#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 81788#L500 assume !(1 == ~t3_pc~0); 82313#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 82280#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 82233#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 82234#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 81228#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 81229#L519 assume 1 == ~t4_pc~0; 81532#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 81533#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 81787#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 81638#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 81639#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 81395#L538 assume !(1 == ~t5_pc~0); 81396#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 81302#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 81303#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 81574#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 81575#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 82156#L557 assume 1 == ~t6_pc~0; 81932#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 81612#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 81515#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 81516#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 81640#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 82396#L576 assume !(1 == ~t7_pc~0); 81599#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 81600#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 81859#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 81860#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 82216#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 81728#L595 assume 1 == ~t8_pc~0; 81729#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 82235#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 82236#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 82057#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 82058#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 81522#L614 assume !(1 == ~t9_pc~0); 81523#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 81420#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 81421#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 81603#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 81689#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 81690#L1025 assume !(1 == ~M_E~0); 81954#L1025-2 assume !(1 == ~T1_E~0); 82007#L1030-1 assume !(1 == ~T2_E~0); 82147#L1035-1 assume !(1 == ~T3_E~0); 82284#L1040-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 103621#L1045-1 assume !(1 == ~T5_E~0); 81585#L1050-1 assume !(1 == ~T6_E~0); 81586#L1055-1 assume !(1 == ~T7_E~0); 81404#L1060-1 assume !(1 == ~T8_E~0); 81405#L1065-1 assume !(1 == ~T9_E~0); 82403#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 82404#L1075-1 assume !(1 == ~E_2~0); 82444#L1080-1 assume 1 == ~E_3~0;~E_3~0 := 2; 82445#L1085-1 assume !(1 == ~E_4~0); 104501#L1090-1 assume !(1 == ~E_5~0); 104500#L1095-1 assume !(1 == ~E_6~0); 104499#L1100-1 assume !(1 == ~E_7~0); 104498#L1105-1 assume !(1 == ~E_8~0); 104497#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 104494#L1115-1 assume { :end_inline_reset_delta_events } true; 104495#L1396-2 [2022-10-17 10:09:44,852 INFO L750 eck$LassoCheckResult]: Loop: 104495#L1396-2 assume !false; 104437#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 104433#L897 assume !false; 104423#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 104424#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 105487#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 105486#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 104264#L766 assume !(0 != eval_~tmp~0#1); 104266#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 104888#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 104889#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 104879#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 104880#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 104871#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 104872#L937-3 assume !(0 == ~T4_E~0); 104862#L942-3 assume !(0 == ~T5_E~0); 104863#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 104853#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 104854#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 104845#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 104846#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 104836#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 104837#L977-3 assume !(0 == ~E_3~0); 104827#L982-3 assume !(0 == ~E_4~0); 104828#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 104819#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 104820#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 104810#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 104811#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 104801#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 104802#L443-30 assume !(1 == ~m_pc~0); 104795#L443-32 is_master_triggered_~__retres1~0#1 := 0; 104796#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 104789#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 104790#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 104783#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 104784#L462-30 assume !(1 == ~t1_pc~0); 104779#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 104780#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 104775#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 104776#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 104771#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 104772#L481-30 assume 1 == ~t2_pc~0; 104765#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 104766#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 104761#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 104762#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 104757#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 104758#L500-30 assume !(1 == ~t3_pc~0); 104752#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 104753#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 104746#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 104747#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 104740#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 104741#L519-30 assume 1 == ~t4_pc~0; 104731#L520-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 104732#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 104725#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 104726#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 104719#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 104720#L538-30 assume !(1 == ~t5_pc~0); 104711#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 104712#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 104704#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 104705#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 104698#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 104699#L557-30 assume 1 == ~t6_pc~0; 104690#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 104691#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 104684#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 104685#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 104678#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 104679#L576-30 assume !(1 == ~t7_pc~0); 104672#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 104671#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 104663#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 104664#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 104657#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 104658#L595-30 assume 1 == ~t8_pc~0; 104649#L596-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 104650#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 104642#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 104643#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 104636#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 104637#L614-30 assume 1 == ~t9_pc~0; 104628#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 104629#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 104621#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 104622#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 104615#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 104616#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 104609#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 104610#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 105851#L1035-3 assume !(1 == ~T3_E~0); 105850#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 105846#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 105844#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 105842#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 105840#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 105838#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 105836#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 105834#L1075-3 assume !(1 == ~E_2~0); 105830#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 105829#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 105828#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 105827#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 105826#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 105825#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 105824#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 105823#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 105813#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 105812#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 105811#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 105809#L1415 assume !(0 == start_simulation_~tmp~3#1); 105807#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 104537#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 104528#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 104524#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 104522#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 104509#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 104502#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 104496#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 104495#L1396-2 [2022-10-17 10:09:44,852 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:09:44,853 INFO L85 PathProgramCache]: Analyzing trace with hash 2031839965, now seen corresponding path program 1 times [2022-10-17 10:09:44,853 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:09:44,853 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [916632401] [2022-10-17 10:09:44,853 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:09:44,854 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:09:44,874 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:09:44,944 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:09:44,944 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:09:44,945 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [916632401] [2022-10-17 10:09:44,945 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [916632401] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:09:44,945 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:09:44,945 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-10-17 10:09:44,945 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1105262352] [2022-10-17 10:09:44,946 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:09:44,947 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:09:44,947 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:09:44,947 INFO L85 PathProgramCache]: Analyzing trace with hash -681901236, now seen corresponding path program 1 times [2022-10-17 10:09:44,948 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:09:44,948 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [156728466] [2022-10-17 10:09:44,948 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:09:44,948 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:09:44,965 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:09:45,010 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:09:45,010 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:09:45,011 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [156728466] [2022-10-17 10:09:45,011 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [156728466] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:09:45,011 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:09:45,011 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:09:45,011 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [935264892] [2022-10-17 10:09:45,012 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:09:45,012 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:09:45,012 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:09:45,013 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:09:45,013 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:09:45,013 INFO L87 Difference]: Start difference. First operand 28051 states and 40793 transitions. cyclomatic complexity: 12758 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 2 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:09:45,481 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:09:45,482 INFO L93 Difference]: Finished difference Result 53106 states and 76963 transitions. [2022-10-17 10:09:45,482 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 53106 states and 76963 transitions. [2022-10-17 10:09:45,720 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 52754 [2022-10-17 10:09:46,044 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 53106 states to 53106 states and 76963 transitions. [2022-10-17 10:09:46,045 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 53106 [2022-10-17 10:09:46,095 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 53106 [2022-10-17 10:09:46,095 INFO L73 IsDeterministic]: Start isDeterministic. Operand 53106 states and 76963 transitions. [2022-10-17 10:09:46,145 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:09:46,145 INFO L218 hiAutomatonCegarLoop]: Abstraction has 53106 states and 76963 transitions. [2022-10-17 10:09:46,191 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53106 states and 76963 transitions. [2022-10-17 10:09:46,928 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53106 to 53034. [2022-10-17 10:09:47,033 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 53034 states, 53034 states have (on average 1.4498434966248068) internal successors, (76891), 53033 states have internal predecessors, (76891), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:09:47,386 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53034 states to 53034 states and 76891 transitions. [2022-10-17 10:09:47,386 INFO L240 hiAutomatonCegarLoop]: Abstraction has 53034 states and 76891 transitions. [2022-10-17 10:09:47,387 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:09:47,388 INFO L428 stractBuchiCegarLoop]: Abstraction has 53034 states and 76891 transitions. [2022-10-17 10:09:47,388 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-10-17 10:09:47,388 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 53034 states and 76891 transitions. [2022-10-17 10:09:47,567 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 52682 [2022-10-17 10:09:47,568 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:09:47,568 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:09:47,570 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:09:47,570 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:09:47,571 INFO L748 eck$LassoCheckResult]: Stem: 163256#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 163257#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 162820#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 162821#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 163440#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 163441#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 163422#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 163195#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 163196#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 162995#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 162996#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 163526#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 163402#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 163057#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 162826#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 162827#L922 assume !(0 == ~M_E~0); 163609#L922-2 assume !(0 == ~T1_E~0); 163610#L927-1 assume !(0 == ~T2_E~0); 163264#L932-1 assume !(0 == ~T3_E~0); 163135#L937-1 assume !(0 == ~T4_E~0); 163136#L942-1 assume !(0 == ~T5_E~0); 163194#L947-1 assume !(0 == ~T6_E~0); 163268#L952-1 assume !(0 == ~T7_E~0); 163269#L957-1 assume !(0 == ~T8_E~0); 163350#L962-1 assume !(0 == ~T9_E~0); 163112#L967-1 assume !(0 == ~E_1~0); 163113#L972-1 assume !(0 == ~E_2~0); 163427#L977-1 assume !(0 == ~E_3~0); 163428#L982-1 assume !(0 == ~E_4~0); 162597#L987-1 assume !(0 == ~E_5~0); 162598#L992-1 assume !(0 == ~E_6~0); 162604#L997-1 assume !(0 == ~E_7~0); 163034#L1002-1 assume !(0 == ~E_8~0); 163019#L1007-1 assume !(0 == ~E_9~0); 162390#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 162391#L443 assume !(1 == ~m_pc~0); 163287#L443-2 is_master_triggered_~__retres1~0#1 := 0; 163274#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 163275#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 162759#L1140 assume !(0 != activate_threads_~tmp~1#1); 162505#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 162506#L462 assume !(1 == ~t1_pc~0); 163128#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 163129#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 162476#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 162477#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 162976#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 162977#L481 assume !(1 == ~t2_pc~0); 162754#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 162753#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 163132#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 162850#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 162851#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 162951#L500 assume !(1 == ~t3_pc~0); 163488#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 163455#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 163412#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 163413#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 162395#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 162396#L519 assume !(1 == ~t4_pc~0); 163180#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 162947#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 162948#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 162801#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 162802#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 162562#L538 assume !(1 == ~t5_pc~0); 162563#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 162466#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 162467#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 162738#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 162739#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 163330#L557 assume 1 == ~t6_pc~0; 163097#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 162776#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 162680#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 162681#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 162803#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 163572#L576 assume !(1 == ~t7_pc~0); 162763#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 162764#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 163022#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 163023#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 163392#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 162889#L595 assume 1 == ~t8_pc~0; 162890#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 163414#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 163415#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 163221#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 163222#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 162689#L614 assume !(1 == ~t9_pc~0); 162690#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 162587#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 162588#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 162767#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 162852#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 162853#L1025 assume !(1 == ~M_E~0); 163119#L1025-2 assume !(1 == ~T1_E~0); 163173#L1030-1 assume !(1 == ~T2_E~0); 163319#L1035-1 assume !(1 == ~T3_E~0); 162846#L1040-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 162847#L1045-1 assume !(1 == ~T5_E~0); 162749#L1050-1 assume !(1 == ~T6_E~0); 162750#L1055-1 assume !(1 == ~T7_E~0); 162571#L1060-1 assume !(1 == ~T8_E~0); 162572#L1065-1 assume !(1 == ~T9_E~0); 162636#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 163270#L1075-1 assume !(1 == ~E_2~0); 163271#L1080-1 assume 1 == ~E_3~0;~E_3~0 := 2; 180154#L1085-1 assume !(1 == ~E_4~0); 180152#L1090-1 assume !(1 == ~E_5~0); 180148#L1095-1 assume !(1 == ~E_6~0); 180145#L1100-1 assume !(1 == ~E_7~0); 180141#L1105-1 assume !(1 == ~E_8~0); 179923#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 179907#L1115-1 assume { :end_inline_reset_delta_events } true; 179896#L1396-2 [2022-10-17 10:09:47,571 INFO L750 eck$LassoCheckResult]: Loop: 179896#L1396-2 assume !false; 179885#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 179876#L897 assume !false; 179871#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 179863#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 179847#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 179840#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 179834#L766 assume !(0 != eval_~tmp~0#1); 179835#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 186205#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 186204#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 186202#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 186200#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 186198#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 186196#L937-3 assume !(0 == ~T4_E~0); 186194#L942-3 assume !(0 == ~T5_E~0); 186192#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 186190#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 186188#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 186186#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 186184#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 186182#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 186180#L977-3 assume !(0 == ~E_3~0); 186178#L982-3 assume !(0 == ~E_4~0); 186175#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 186173#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 186171#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 186169#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 186167#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 186165#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 186163#L443-30 assume !(1 == ~m_pc~0); 186161#L443-32 is_master_triggered_~__retres1~0#1 := 0; 186159#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 186157#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 186155#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 186153#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 186151#L462-30 assume !(1 == ~t1_pc~0); 186149#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 186147#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 186145#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 186143#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 186141#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 186138#L481-30 assume 1 == ~t2_pc~0; 186123#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 186121#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 186119#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 186117#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 186114#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 186112#L500-30 assume !(1 == ~t3_pc~0); 186110#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 186108#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 186106#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 186088#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 186077#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 186068#L519-30 assume !(1 == ~t4_pc~0); 186063#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 186058#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 186053#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 186049#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 186044#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 186036#L538-30 assume !(1 == ~t5_pc~0); 186028#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 185585#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 180920#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 180917#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 180915#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 180912#L557-30 assume !(1 == ~t6_pc~0); 180910#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 180906#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 180905#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 180903#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 180901#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 180899#L576-30 assume 1 == ~t7_pc~0; 180896#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 180894#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 180892#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 180891#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 180887#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 180885#L595-30 assume 1 == ~t8_pc~0; 180882#L596-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 180880#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 180878#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 180876#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 180874#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 180871#L614-30 assume 1 == ~t9_pc~0; 180867#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 180865#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 180863#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 180861#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 180859#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 180857#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 180855#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 180853#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 180849#L1035-3 assume !(1 == ~T3_E~0); 180847#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 180843#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 180841#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 180839#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 180837#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 180835#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 180833#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 180830#L1075-3 assume !(1 == ~E_2~0); 180828#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 180824#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 180822#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 180820#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 180818#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 180815#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 180813#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 180811#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 180792#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 180790#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 180788#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 180785#L1415 assume !(0 == start_simulation_~tmp~3#1); 180782#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 179943#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 179933#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 179930#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 179928#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 179926#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 179924#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 179908#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 179896#L1396-2 [2022-10-17 10:09:47,571 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:09:47,571 INFO L85 PathProgramCache]: Analyzing trace with hash 2039590524, now seen corresponding path program 1 times [2022-10-17 10:09:47,572 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:09:47,572 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [540873660] [2022-10-17 10:09:47,572 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:09:47,572 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:09:47,588 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:09:47,654 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:09:47,655 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:09:47,655 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [540873660] [2022-10-17 10:09:47,655 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [540873660] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:09:47,656 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:09:47,656 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-10-17 10:09:47,656 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1734846840] [2022-10-17 10:09:47,656 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:09:47,658 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:09:47,658 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:09:47,659 INFO L85 PathProgramCache]: Analyzing trace with hash -1400967893, now seen corresponding path program 1 times [2022-10-17 10:09:47,659 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:09:47,659 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1075948087] [2022-10-17 10:09:47,659 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:09:47,659 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:09:47,795 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:09:47,844 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:09:47,844 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:09:47,845 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1075948087] [2022-10-17 10:09:47,845 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1075948087] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:09:47,845 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:09:47,845 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:09:47,845 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1815300602] [2022-10-17 10:09:47,845 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:09:47,846 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:09:47,846 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:09:47,847 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-10-17 10:09:47,847 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-10-17 10:09:47,847 INFO L87 Difference]: Start difference. First operand 53034 states and 76891 transitions. cyclomatic complexity: 23889 Second operand has 5 states, 5 states have (on average 23.0) internal successors, (115), 5 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:09:48,684 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:09:48,684 INFO L93 Difference]: Finished difference Result 134547 states and 196410 transitions. [2022-10-17 10:09:48,684 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 134547 states and 196410 transitions. [2022-10-17 10:09:49,497 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 133656 [2022-10-17 10:09:50,250 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 134547 states to 134547 states and 196410 transitions. [2022-10-17 10:09:50,250 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 134547 [2022-10-17 10:09:50,326 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 134547 [2022-10-17 10:09:50,327 INFO L73 IsDeterministic]: Start isDeterministic. Operand 134547 states and 196410 transitions. [2022-10-17 10:09:50,424 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:09:50,424 INFO L218 hiAutomatonCegarLoop]: Abstraction has 134547 states and 196410 transitions. [2022-10-17 10:09:50,523 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 134547 states and 196410 transitions. [2022-10-17 10:09:51,796 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 134547 to 54789. [2022-10-17 10:09:51,899 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 54789 states, 54789 states have (on average 1.4354341199875889) internal successors, (78646), 54788 states have internal predecessors, (78646), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:09:52,083 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54789 states to 54789 states and 78646 transitions. [2022-10-17 10:09:52,083 INFO L240 hiAutomatonCegarLoop]: Abstraction has 54789 states and 78646 transitions. [2022-10-17 10:09:52,085 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-10-17 10:09:52,086 INFO L428 stractBuchiCegarLoop]: Abstraction has 54789 states and 78646 transitions. [2022-10-17 10:09:52,087 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-10-17 10:09:52,087 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 54789 states and 78646 transitions. [2022-10-17 10:09:52,233 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 54434 [2022-10-17 10:09:52,233 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:09:52,233 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:09:52,236 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:09:52,236 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:09:52,237 INFO L748 eck$LassoCheckResult]: Stem: 350876#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 350877#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 350420#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 350421#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 351083#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 351084#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 351061#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 350815#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 350816#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 350601#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 350602#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 351182#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 351038#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 350666#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 350426#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 350427#L922 assume !(0 == ~M_E~0); 351287#L922-2 assume !(0 == ~T1_E~0); 351288#L927-1 assume !(0 == ~T2_E~0); 350886#L932-1 assume !(0 == ~T3_E~0); 350750#L937-1 assume !(0 == ~T4_E~0); 350751#L942-1 assume !(0 == ~T5_E~0); 350814#L947-1 assume !(0 == ~T6_E~0); 350890#L952-1 assume !(0 == ~T7_E~0); 350891#L957-1 assume !(0 == ~T8_E~0); 350981#L962-1 assume !(0 == ~T9_E~0); 350723#L967-1 assume !(0 == ~E_1~0); 350724#L972-1 assume !(0 == ~E_2~0); 351065#L977-1 assume !(0 == ~E_3~0); 351066#L982-1 assume !(0 == ~E_4~0); 350193#L987-1 assume !(0 == ~E_5~0); 350194#L992-1 assume !(0 == ~E_6~0); 350200#L997-1 assume !(0 == ~E_7~0); 350641#L1002-1 assume !(0 == ~E_8~0); 350625#L1007-1 assume !(0 == ~E_9~0); 349984#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 349985#L443 assume !(1 == ~m_pc~0); 350912#L443-2 is_master_triggered_~__retres1~0#1 := 0; 350899#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 350900#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 350357#L1140 assume !(0 != activate_threads_~tmp~1#1); 350101#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 350102#L462 assume !(1 == ~t1_pc~0); 350741#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 350742#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 350070#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 350071#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 350580#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 350581#L481 assume !(1 == ~t2_pc~0); 350352#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 350351#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 350747#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 350450#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 350451#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 350554#L500 assume !(1 == ~t3_pc~0); 351134#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 351099#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 351053#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 351054#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 349989#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 349990#L519 assume !(1 == ~t4_pc~0); 350800#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 350550#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 350551#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 350400#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 350401#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 350158#L538 assume !(1 == ~t5_pc~0); 350159#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 350060#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 350061#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 350335#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 350336#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 350960#L557 assume 1 == ~t6_pc~0; 350707#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 350374#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 350277#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 350278#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 350402#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 351242#L576 assume !(1 == ~t7_pc~0); 350361#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 350362#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 350629#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 350630#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 351022#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 350489#L595 assume 1 == ~t8_pc~0; 350490#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 351055#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 351056#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 350845#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 350846#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 350286#L614 assume !(1 == ~t9_pc~0); 350287#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 350183#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 350184#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 350365#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 350452#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 350453#L1025 assume !(1 == ~M_E~0); 350730#L1025-2 assume !(1 == ~T1_E~0); 350792#L1030-1 assume !(1 == ~T2_E~0); 350949#L1035-1 assume !(1 == ~T3_E~0); 350446#L1040-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 350447#L1045-1 assume !(1 == ~T5_E~0); 350347#L1050-1 assume !(1 == ~T6_E~0); 350348#L1055-1 assume !(1 == ~T7_E~0); 350543#L1060-1 assume !(1 == ~T8_E~0); 368704#L1065-1 assume !(1 == ~T9_E~0); 368701#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 368699#L1075-1 assume !(1 == ~E_2~0); 368691#L1080-1 assume 1 == ~E_3~0;~E_3~0 := 2; 368688#L1085-1 assume !(1 == ~E_4~0); 368686#L1090-1 assume !(1 == ~E_5~0); 368684#L1095-1 assume !(1 == ~E_6~0); 368682#L1100-1 assume !(1 == ~E_7~0); 368680#L1105-1 assume !(1 == ~E_8~0); 368678#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 368555#L1115-1 assume { :end_inline_reset_delta_events } true; 368553#L1396-2 [2022-10-17 10:09:52,237 INFO L750 eck$LassoCheckResult]: Loop: 368553#L1396-2 assume !false; 355190#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 355184#L897 assume !false; 355182#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 355179#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 355170#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 355163#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 355164#L766 assume !(0 != eval_~tmp~0#1); 368304#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 372589#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 372490#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 372488#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 372486#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 372483#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 372481#L937-3 assume !(0 == ~T4_E~0); 372479#L942-3 assume !(0 == ~T5_E~0); 372477#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 372475#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 372473#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 372470#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 372468#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 372466#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 372464#L977-3 assume !(0 == ~E_3~0); 372447#L982-3 assume !(0 == ~E_4~0); 372439#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 372431#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 372379#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 372375#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 372371#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 372366#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 372365#L443-30 assume !(1 == ~m_pc~0); 372364#L443-32 is_master_triggered_~__retres1~0#1 := 0; 372363#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 372362#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 372361#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 372360#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 372359#L462-30 assume !(1 == ~t1_pc~0); 372358#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 372357#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 372356#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 372355#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 372354#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 372353#L481-30 assume !(1 == ~t2_pc~0); 372352#L481-32 is_transmit2_triggered_~__retres1~2#1 := 0; 372350#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 372349#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 372348#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 372347#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 372346#L500-30 assume !(1 == ~t3_pc~0); 372345#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 372344#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 372343#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 372342#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 372341#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 372340#L519-30 assume !(1 == ~t4_pc~0); 372339#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 372338#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 372337#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 372336#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 372335#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 372334#L538-30 assume !(1 == ~t5_pc~0); 372333#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 372331#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 372329#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 372327#L1180-30 assume !(0 != activate_threads_~tmp___4~0#1); 372320#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 372315#L557-30 assume 1 == ~t6_pc~0; 372309#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 372304#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 372298#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 372292#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 372284#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 369711#L576-30 assume !(1 == ~t7_pc~0); 369709#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 369706#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 369703#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 369701#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 369699#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 369697#L595-30 assume !(1 == ~t8_pc~0); 369695#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 369692#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 369689#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 369687#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 369685#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 369684#L614-30 assume !(1 == ~t9_pc~0); 369643#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 369640#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 369637#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 369635#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 369633#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 369631#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 369620#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 369618#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 369614#L1035-3 assume !(1 == ~T3_E~0); 369611#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 369278#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 369276#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 369274#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 369271#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 369269#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 369267#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 369265#L1075-3 assume !(1 == ~E_2~0); 369263#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 369259#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 369256#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 369254#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 369252#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 369250#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 369248#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 369246#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 368596#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 368594#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 368592#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 368588#L1415 assume !(0 == start_simulation_~tmp~3#1); 368585#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 368579#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 368568#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 368566#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 368564#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 368562#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 368560#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 368556#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 368553#L1396-2 [2022-10-17 10:09:52,239 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:09:52,239 INFO L85 PathProgramCache]: Analyzing trace with hash -327104070, now seen corresponding path program 1 times [2022-10-17 10:09:52,239 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:09:52,239 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [926939812] [2022-10-17 10:09:52,240 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:09:52,240 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:09:52,257 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:09:52,324 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:09:52,324 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:09:52,324 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [926939812] [2022-10-17 10:09:52,324 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [926939812] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:09:52,325 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:09:52,325 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:09:52,325 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [689487814] [2022-10-17 10:09:52,325 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:09:52,326 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:09:52,326 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:09:52,326 INFO L85 PathProgramCache]: Analyzing trace with hash 1854786758, now seen corresponding path program 1 times [2022-10-17 10:09:52,326 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:09:52,326 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1294857058] [2022-10-17 10:09:52,327 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:09:52,327 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:09:52,340 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:09:52,376 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:09:52,376 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:09:52,376 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1294857058] [2022-10-17 10:09:52,376 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1294857058] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:09:52,377 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:09:52,377 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:09:52,377 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [6813408] [2022-10-17 10:09:52,377 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:09:52,378 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:09:52,378 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:09:52,378 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-10-17 10:09:52,378 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-10-17 10:09:52,379 INFO L87 Difference]: Start difference. First operand 54789 states and 78646 transitions. cyclomatic complexity: 23889 Second operand has 4 states, 4 states have (on average 28.75) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:09:53,579 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:09:53,580 INFO L93 Difference]: Finished difference Result 154072 states and 219803 transitions. [2022-10-17 10:09:53,581 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 154072 states and 219803 transitions. [2022-10-17 10:09:54,248 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 150598 [2022-10-17 10:09:55,277 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 154072 states to 154072 states and 219803 transitions. [2022-10-17 10:09:55,277 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 154072 [2022-10-17 10:09:55,368 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 154072 [2022-10-17 10:09:55,369 INFO L73 IsDeterministic]: Start isDeterministic. Operand 154072 states and 219803 transitions. [2022-10-17 10:09:55,533 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:09:55,533 INFO L218 hiAutomatonCegarLoop]: Abstraction has 154072 states and 219803 transitions. [2022-10-17 10:09:55,644 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 154072 states and 219803 transitions. [2022-10-17 10:09:57,665 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 154072 to 149168. [2022-10-17 10:09:57,745 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 149168 states, 149168 states have (on average 1.4300855411348279) internal successors, (213323), 149167 states have internal predecessors, (213323), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:09:58,266 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 149168 states to 149168 states and 213323 transitions. [2022-10-17 10:09:58,267 INFO L240 hiAutomatonCegarLoop]: Abstraction has 149168 states and 213323 transitions. [2022-10-17 10:09:58,267 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-10-17 10:09:58,268 INFO L428 stractBuchiCegarLoop]: Abstraction has 149168 states and 213323 transitions. [2022-10-17 10:09:58,268 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-10-17 10:09:58,268 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 149168 states and 213323 transitions. [2022-10-17 10:09:58,625 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 148510 [2022-10-17 10:09:58,625 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:09:58,625 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:09:58,628 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:09:58,629 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:09:58,629 INFO L748 eck$LassoCheckResult]: Stem: 559760#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 559761#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 559292#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 559293#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 559978#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 559979#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 559952#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 559699#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 559700#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 559476#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 559477#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 560080#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 559928#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 559550#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 559298#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 559299#L922 assume !(0 == ~M_E~0); 560190#L922-2 assume !(0 == ~T1_E~0); 560191#L927-1 assume !(0 == ~T2_E~0); 559769#L932-1 assume !(0 == ~T3_E~0); 559629#L937-1 assume !(0 == ~T4_E~0); 559630#L942-1 assume !(0 == ~T5_E~0); 559698#L947-1 assume !(0 == ~T6_E~0); 559773#L952-1 assume !(0 == ~T7_E~0); 559774#L957-1 assume !(0 == ~T8_E~0); 559866#L962-1 assume !(0 == ~T9_E~0); 559600#L967-1 assume !(0 == ~E_1~0); 559601#L972-1 assume !(0 == ~E_2~0); 559958#L977-1 assume !(0 == ~E_3~0); 559959#L982-1 assume !(0 == ~E_4~0); 559060#L987-1 assume !(0 == ~E_5~0); 559061#L992-1 assume !(0 == ~E_6~0); 559069#L997-1 assume !(0 == ~E_7~0); 559519#L1002-1 assume !(0 == ~E_8~0); 559505#L1007-1 assume !(0 == ~E_9~0); 558855#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 558856#L443 assume !(1 == ~m_pc~0); 559794#L443-2 is_master_triggered_~__retres1~0#1 := 0; 559779#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 559780#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 559229#L1140 assume !(0 != activate_threads_~tmp~1#1); 558972#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 558973#L462 assume !(1 == ~t1_pc~0); 559624#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 559625#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 558941#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 558942#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 559456#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 559457#L481 assume !(1 == ~t2_pc~0); 559224#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 559223#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 559626#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 559321#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 559322#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 559427#L500 assume !(1 == ~t3_pc~0); 560038#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 559996#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 559941#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 559942#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 558860#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 558861#L519 assume !(1 == ~t4_pc~0); 559684#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 559425#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 559426#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 559270#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 559271#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 559028#L538 assume !(1 == ~t5_pc~0); 559029#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 558931#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 558932#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 559207#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 559208#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 559840#L557 assume !(1 == ~t6_pc~0); 559245#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 559246#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 559144#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 559145#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 559272#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 560135#L576 assume !(1 == ~t7_pc~0); 559233#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 559234#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 559507#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 559508#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 559914#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 559362#L595 assume 1 == ~t8_pc~0; 559363#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 559943#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 559944#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 559730#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 559731#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 559157#L614 assume !(1 == ~t9_pc~0); 559158#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 559053#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 559054#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 559237#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 559323#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 559324#L1025 assume !(1 == ~M_E~0); 559610#L1025-2 assume !(1 == ~T1_E~0); 559676#L1030-1 assume !(1 == ~T2_E~0); 559830#L1035-1 assume !(1 == ~T3_E~0); 560002#L1040-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 610106#L1045-1 assume !(1 == ~T5_E~0); 559219#L1050-1 assume !(1 == ~T6_E~0); 559220#L1055-1 assume !(1 == ~T7_E~0); 559037#L1060-1 assume !(1 == ~T8_E~0); 559038#L1065-1 assume !(1 == ~T9_E~0); 560146#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 559775#L1075-1 assume !(1 == ~E_2~0); 559776#L1080-1 assume 1 == ~E_3~0;~E_3~0 := 2; 610095#L1085-1 assume !(1 == ~E_4~0); 610094#L1090-1 assume !(1 == ~E_5~0); 610093#L1095-1 assume !(1 == ~E_6~0); 610092#L1100-1 assume !(1 == ~E_7~0); 610091#L1105-1 assume !(1 == ~E_8~0); 610090#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 610087#L1115-1 assume { :end_inline_reset_delta_events } true; 610088#L1396-2 [2022-10-17 10:09:58,630 INFO L750 eck$LassoCheckResult]: Loop: 610088#L1396-2 assume !false; 676160#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 676155#L897 assume !false; 676154#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 676153#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 676143#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 676142#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 676140#L766 assume !(0 != eval_~tmp~0#1); 676141#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 676297#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 676296#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 676295#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 676294#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 676293#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 676292#L937-3 assume !(0 == ~T4_E~0); 676291#L942-3 assume !(0 == ~T5_E~0); 676290#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 676289#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 676288#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 676287#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 676286#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 676285#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 676284#L977-3 assume !(0 == ~E_3~0); 676283#L982-3 assume !(0 == ~E_4~0); 676282#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 676281#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 676280#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 676279#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 676278#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 676277#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 676276#L443-30 assume !(1 == ~m_pc~0); 676275#L443-32 is_master_triggered_~__retres1~0#1 := 0; 676274#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 676273#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 676272#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 676271#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 676270#L462-30 assume !(1 == ~t1_pc~0); 676269#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 676268#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 676267#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 676266#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 676265#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 676264#L481-30 assume 1 == ~t2_pc~0; 676262#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 676261#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 676260#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 676259#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 676258#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 676257#L500-30 assume !(1 == ~t3_pc~0); 676256#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 676255#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 676254#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 676253#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 676252#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 676251#L519-30 assume !(1 == ~t4_pc~0); 676250#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 676249#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 676248#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 676247#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 676246#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 676245#L538-30 assume !(1 == ~t5_pc~0); 676242#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 676241#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 676240#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 676239#L1180-30 assume !(0 != activate_threads_~tmp___4~0#1); 676237#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 676236#L557-30 assume !(1 == ~t6_pc~0); 676235#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 676234#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 676233#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 676232#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 676231#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 676230#L576-30 assume 1 == ~t7_pc~0; 676228#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 676227#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 676226#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 676225#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 676224#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 676223#L595-30 assume !(1 == ~t8_pc~0); 676222#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 676220#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 676219#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 676218#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 676217#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 676216#L614-30 assume 1 == ~t9_pc~0; 676214#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 676213#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 676212#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 676211#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 676210#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 676209#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 676208#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 676207#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 611201#L1035-3 assume !(1 == ~T3_E~0); 676206#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 665207#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 676205#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 676204#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 676203#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 676202#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 676201#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 676200#L1075-3 assume !(1 == ~E_2~0); 676199#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 641877#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 676198#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 676197#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 676196#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 676195#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 676194#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 676193#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 676183#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 676182#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 676181#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 676179#L1415 assume !(0 == start_simulation_~tmp~3#1); 676177#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 676175#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 676166#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 676165#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 676164#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 676163#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 676162#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 676161#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 610088#L1396-2 [2022-10-17 10:09:58,630 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:09:58,631 INFO L85 PathProgramCache]: Analyzing trace with hash -1602206759, now seen corresponding path program 1 times [2022-10-17 10:09:58,631 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:09:58,631 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [180427859] [2022-10-17 10:09:58,631 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:09:58,631 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:09:58,649 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:09:58,693 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:09:58,694 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:09:58,694 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [180427859] [2022-10-17 10:09:58,694 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [180427859] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:09:58,694 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:09:58,694 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-10-17 10:09:58,694 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [89837326] [2022-10-17 10:09:58,695 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:09:58,695 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:09:58,695 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:09:58,695 INFO L85 PathProgramCache]: Analyzing trace with hash 2052625800, now seen corresponding path program 1 times [2022-10-17 10:09:58,696 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:09:58,696 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1332774481] [2022-10-17 10:09:58,696 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:09:58,696 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:09:58,709 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:09:58,743 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:09:58,743 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:09:58,743 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1332774481] [2022-10-17 10:09:58,743 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1332774481] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:09:58,743 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:09:58,744 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:09:58,744 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1772430760] [2022-10-17 10:09:58,744 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:09:58,744 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:09:58,744 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:09:58,744 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:09:58,745 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:09:58,745 INFO L87 Difference]: Start difference. First operand 149168 states and 213323 transitions. cyclomatic complexity: 64219 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 2 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:10:00,374 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:10:00,374 INFO L93 Difference]: Finished difference Result 281089 states and 401272 transitions. [2022-10-17 10:10:00,375 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 281089 states and 401272 transitions. [2022-10-17 10:10:02,215 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 279504