./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/uthash-2.0.2/uthash_FNV_test6-2.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version dbf71c69 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3d3546f3-c140-4a8d-812b-99960e234815/bin/uautomizer-J5u9QxTXDZ/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3d3546f3-c140-4a8d-812b-99960e234815/bin/uautomizer-J5u9QxTXDZ/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3d3546f3-c140-4a8d-812b-99960e234815/bin/uautomizer-J5u9QxTXDZ/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3d3546f3-c140-4a8d-812b-99960e234815/bin/uautomizer-J5u9QxTXDZ/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/uthash-2.0.2/uthash_FNV_test6-2.i -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3d3546f3-c140-4a8d-812b-99960e234815/bin/uautomizer-J5u9QxTXDZ/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3d3546f3-c140-4a8d-812b-99960e234815/bin/uautomizer-J5u9QxTXDZ --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash e4ea247b245ebcaf5e735452e89c4110c7b9dc9b43836e98484a894783fc3462 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-dbf71c6-m [2022-10-17 10:30:29,768 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-10-17 10:30:29,775 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-10-17 10:30:29,839 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-10-17 10:30:29,840 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-10-17 10:30:29,846 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-10-17 10:30:29,850 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-10-17 10:30:29,854 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-10-17 10:30:29,857 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-10-17 10:30:29,865 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-10-17 10:30:29,867 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-10-17 10:30:29,870 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-10-17 10:30:29,870 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-10-17 10:30:29,874 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-10-17 10:30:29,876 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-10-17 10:30:29,878 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-10-17 10:30:29,881 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-10-17 10:30:29,882 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-10-17 10:30:29,884 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-10-17 10:30:29,893 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-10-17 10:30:29,896 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-10-17 10:30:29,898 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-10-17 10:30:29,902 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-10-17 10:30:29,904 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-10-17 10:30:29,916 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-10-17 10:30:29,917 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-10-17 10:30:29,917 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-10-17 10:30:29,920 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-10-17 10:30:29,921 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-10-17 10:30:29,923 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-10-17 10:30:29,925 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-10-17 10:30:29,926 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-10-17 10:30:29,929 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-10-17 10:30:29,931 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-10-17 10:30:29,932 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-10-17 10:30:29,933 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-10-17 10:30:29,934 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-10-17 10:30:29,934 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-10-17 10:30:29,935 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-10-17 10:30:29,936 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-10-17 10:30:29,937 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-10-17 10:30:29,940 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3d3546f3-c140-4a8d-812b-99960e234815/bin/uautomizer-J5u9QxTXDZ/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-10-17 10:30:29,991 INFO L113 SettingsManager]: Loading preferences was successful [2022-10-17 10:30:29,992 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-10-17 10:30:29,992 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-10-17 10:30:29,993 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-10-17 10:30:29,994 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-10-17 10:30:29,995 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-10-17 10:30:29,995 INFO L138 SettingsManager]: * Use SBE=true [2022-10-17 10:30:29,995 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-10-17 10:30:29,996 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-10-17 10:30:29,996 INFO L138 SettingsManager]: * Use old map elimination=false [2022-10-17 10:30:29,997 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-10-17 10:30:29,998 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-10-17 10:30:29,998 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-10-17 10:30:29,998 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-10-17 10:30:29,998 INFO L138 SettingsManager]: * sizeof long=4 [2022-10-17 10:30:29,999 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-10-17 10:30:29,999 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-10-17 10:30:29,999 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-10-17 10:30:30,000 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-10-17 10:30:30,000 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-10-17 10:30:30,000 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-10-17 10:30:30,000 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-10-17 10:30:30,001 INFO L138 SettingsManager]: * sizeof long double=12 [2022-10-17 10:30:30,003 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-10-17 10:30:30,003 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-10-17 10:30:30,003 INFO L138 SettingsManager]: * Use constant arrays=true [2022-10-17 10:30:30,004 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-10-17 10:30:30,004 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-10-17 10:30:30,004 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-10-17 10:30:30,005 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-10-17 10:30:30,005 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-10-17 10:30:30,006 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-10-17 10:30:30,006 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3d3546f3-c140-4a8d-812b-99960e234815/bin/uautomizer-J5u9QxTXDZ/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3d3546f3-c140-4a8d-812b-99960e234815/bin/uautomizer-J5u9QxTXDZ Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> e4ea247b245ebcaf5e735452e89c4110c7b9dc9b43836e98484a894783fc3462 [2022-10-17 10:30:30,367 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-10-17 10:30:30,402 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-10-17 10:30:30,405 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-10-17 10:30:30,407 INFO L271 PluginConnector]: Initializing CDTParser... [2022-10-17 10:30:30,408 INFO L275 PluginConnector]: CDTParser initialized [2022-10-17 10:30:30,409 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3d3546f3-c140-4a8d-812b-99960e234815/bin/uautomizer-J5u9QxTXDZ/../../sv-benchmarks/c/uthash-2.0.2/uthash_FNV_test6-2.i [2022-10-17 10:30:30,500 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3d3546f3-c140-4a8d-812b-99960e234815/bin/uautomizer-J5u9QxTXDZ/data/de0e05579/b6aed2dfe77b4f81b4190e47fb92386d/FLAG43f903dbd [2022-10-17 10:30:31,341 INFO L306 CDTParser]: Found 1 translation units. [2022-10-17 10:30:31,342 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3d3546f3-c140-4a8d-812b-99960e234815/sv-benchmarks/c/uthash-2.0.2/uthash_FNV_test6-2.i [2022-10-17 10:30:31,372 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3d3546f3-c140-4a8d-812b-99960e234815/bin/uautomizer-J5u9QxTXDZ/data/de0e05579/b6aed2dfe77b4f81b4190e47fb92386d/FLAG43f903dbd [2022-10-17 10:30:31,427 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3d3546f3-c140-4a8d-812b-99960e234815/bin/uautomizer-J5u9QxTXDZ/data/de0e05579/b6aed2dfe77b4f81b4190e47fb92386d [2022-10-17 10:30:31,432 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-10-17 10:30:31,434 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-10-17 10:30:31,438 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-10-17 10:30:31,439 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-10-17 10:30:31,444 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-10-17 10:30:31,445 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.10 10:30:31" (1/1) ... [2022-10-17 10:30:31,447 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5dac0659 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:30:31, skipping insertion in model container [2022-10-17 10:30:31,447 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.10 10:30:31" (1/1) ... [2022-10-17 10:30:31,456 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-10-17 10:30:31,586 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-10-17 10:30:32,382 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3d3546f3-c140-4a8d-812b-99960e234815/sv-benchmarks/c/uthash-2.0.2/uthash_FNV_test6-2.i[44118,44131] [2022-10-17 10:30:32,407 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3d3546f3-c140-4a8d-812b-99960e234815/sv-benchmarks/c/uthash-2.0.2/uthash_FNV_test6-2.i[44660,44673] [2022-10-17 10:30:32,567 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3d3546f3-c140-4a8d-812b-99960e234815/sv-benchmarks/c/uthash-2.0.2/uthash_FNV_test6-2.i[56247,56260] [2022-10-17 10:30:32,569 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3d3546f3-c140-4a8d-812b-99960e234815/sv-benchmarks/c/uthash-2.0.2/uthash_FNV_test6-2.i[56368,56381] [2022-10-17 10:30:32,595 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-10-17 10:30:32,614 INFO L203 MainTranslator]: Completed pre-run [2022-10-17 10:30:32,675 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3d3546f3-c140-4a8d-812b-99960e234815/sv-benchmarks/c/uthash-2.0.2/uthash_FNV_test6-2.i[44118,44131] [2022-10-17 10:30:32,678 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3d3546f3-c140-4a8d-812b-99960e234815/sv-benchmarks/c/uthash-2.0.2/uthash_FNV_test6-2.i[44660,44673] [2022-10-17 10:30:32,804 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3d3546f3-c140-4a8d-812b-99960e234815/sv-benchmarks/c/uthash-2.0.2/uthash_FNV_test6-2.i[56247,56260] [2022-10-17 10:30:32,816 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3d3546f3-c140-4a8d-812b-99960e234815/sv-benchmarks/c/uthash-2.0.2/uthash_FNV_test6-2.i[56368,56381] [2022-10-17 10:30:32,836 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-10-17 10:30:33,003 INFO L208 MainTranslator]: Completed translation [2022-10-17 10:30:33,004 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:30:33 WrapperNode [2022-10-17 10:30:33,004 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-10-17 10:30:33,008 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-10-17 10:30:33,008 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-10-17 10:30:33,008 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-10-17 10:30:33,024 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:30:33" (1/1) ... [2022-10-17 10:30:33,077 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:30:33" (1/1) ... [2022-10-17 10:30:33,193 INFO L138 Inliner]: procedures = 282, calls = 347, calls flagged for inlining = 21, calls inlined = 23, statements flattened = 1324 [2022-10-17 10:30:33,193 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-10-17 10:30:33,194 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-10-17 10:30:33,194 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-10-17 10:30:33,195 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-10-17 10:30:33,206 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:30:33" (1/1) ... [2022-10-17 10:30:33,207 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:30:33" (1/1) ... [2022-10-17 10:30:33,226 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:30:33" (1/1) ... [2022-10-17 10:30:33,226 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:30:33" (1/1) ... [2022-10-17 10:30:33,366 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:30:33" (1/1) ... [2022-10-17 10:30:33,401 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:30:33" (1/1) ... [2022-10-17 10:30:33,414 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:30:33" (1/1) ... [2022-10-17 10:30:33,432 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:30:33" (1/1) ... [2022-10-17 10:30:33,460 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-10-17 10:30:33,464 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-10-17 10:30:33,464 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-10-17 10:30:33,464 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-10-17 10:30:33,466 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:30:33" (1/1) ... [2022-10-17 10:30:33,473 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:30:33,489 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3d3546f3-c140-4a8d-812b-99960e234815/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:30:33,508 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3d3546f3-c140-4a8d-812b-99960e234815/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:30:33,523 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3d3546f3-c140-4a8d-812b-99960e234815/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-10-17 10:30:33,566 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset [2022-10-17 10:30:33,567 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset [2022-10-17 10:30:33,567 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2022-10-17 10:30:33,567 INFO L130 BoogieDeclarations]: Found specification of procedure memcmp [2022-10-17 10:30:33,567 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$ [2022-10-17 10:30:33,568 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2022-10-17 10:30:33,568 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2022-10-17 10:30:33,568 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2022-10-17 10:30:33,568 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnHeap [2022-10-17 10:30:33,568 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-10-17 10:30:33,569 INFO L130 BoogieDeclarations]: Found specification of procedure write~$Pointer$ [2022-10-17 10:30:33,569 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-10-17 10:30:33,569 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-10-17 10:30:33,569 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-10-17 10:30:34,015 INFO L235 CfgBuilder]: Building ICFG [2022-10-17 10:30:34,018 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-10-17 10:30:34,023 WARN L816 $ProcedureCfgBuilder]: Label in the middle of a codeblock. [2022-10-17 10:30:36,523 INFO L276 CfgBuilder]: Performing block encoding [2022-10-17 10:30:36,547 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-10-17 10:30:36,548 INFO L300 CfgBuilder]: Removed 72 assume(true) statements. [2022-10-17 10:30:36,552 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 17.10 10:30:36 BoogieIcfgContainer [2022-10-17 10:30:36,552 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-10-17 10:30:36,555 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-10-17 10:30:36,555 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-10-17 10:30:36,560 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-10-17 10:30:36,560 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-10-17 10:30:36,561 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 17.10 10:30:31" (1/3) ... [2022-10-17 10:30:36,563 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@56fd7829 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.10 10:30:36, skipping insertion in model container [2022-10-17 10:30:36,563 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-10-17 10:30:36,563 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:30:33" (2/3) ... [2022-10-17 10:30:36,565 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@56fd7829 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.10 10:30:36, skipping insertion in model container [2022-10-17 10:30:36,565 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-10-17 10:30:36,566 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 17.10 10:30:36" (3/3) ... [2022-10-17 10:30:36,567 INFO L332 chiAutomizerObserver]: Analyzing ICFG uthash_FNV_test6-2.i [2022-10-17 10:30:36,666 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-10-17 10:30:36,667 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-10-17 10:30:36,667 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-10-17 10:30:36,668 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-10-17 10:30:36,668 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-10-17 10:30:36,668 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-10-17 10:30:36,668 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-10-17 10:30:36,669 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-10-17 10:30:36,678 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 257 states, 252 states have (on average 1.626984126984127) internal successors, (410), 252 states have internal predecessors, (410), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-10-17 10:30:36,758 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 236 [2022-10-17 10:30:36,758 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:30:36,759 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:30:36,767 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-10-17 10:30:36,768 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:30:36,768 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-10-17 10:30:36,770 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 257 states, 252 states have (on average 1.626984126984127) internal successors, (410), 252 states have internal predecessors, (410), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-10-17 10:30:36,782 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 236 [2022-10-17 10:30:36,782 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:30:36,783 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:30:36,783 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-10-17 10:30:36,784 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:30:36,793 INFO L748 eck$LassoCheckResult]: Stem: 250#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call #Ultimate.allocInit(40, 3);#memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, ~#alt_malloc_sizes~0.base);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0; 160#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret43#1.base, main_#t~ret43#1.offset, main_#t~mem44#1, main_#t~mem45#1, main_#t~mem46#1, main_#t~mem48#1, main_#t~mem47#1, main_#t~mem49#1, main_#t~mem50#1, main_#t~mem52#1, main_#t~mem51#1, main_#t~mem53#1, main_#t~mem54#1, main_#t~mem56#1, main_#t~mem55#1, main_#t~mem57#1, main_#t~mem58#1, main_#t~switch59#1, main_#t~mem60#1, main_#t~mem61#1, main_#t~mem62#1, main_#t~mem63#1, main_#t~mem64#1, main_#t~mem65#1, main_#t~mem66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret71#1.base, main_#t~ret71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1.base, main_#t~mem78#1.offset, main_#t~ret79#1.base, main_#t~ret79#1.offset, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1.base, main_#t~mem82#1.offset, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~mem95#1, main_#t~post96#1, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1, main_#t~post102#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem107#1, main_#t~mem106#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~short110#1, main_#t~mem111#1.base, main_#t~mem111#1.offset, main_#t~mem112#1, main_#t~ret113#1.base, main_#t~ret113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem122#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem126#1, main_#t~mem124#1.base, main_#t~mem124#1.offset, main_#t~mem125#1, main_#t~ite127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem138#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem140#1, main_#t~pre141#1, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1, main_#t~post146#1, main_#t~mem150#1, main_#t~mem148#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem149#1, main_#t~mem151#1, main_#t~post152#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_#t~mem155#1.base, main_#t~mem155#1.offset, main_#t~post129#1, main_#t~mem130#1.base, main_#t~mem130#1.offset, main_#t~mem131#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_#t~mem159#1, main_#t~mem160#1.base, main_#t~mem160#1.offset, main_#t~mem161#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem163#1, main_#t~post164#1, main_#t~mem165#1.base, main_#t~mem165#1.offset, main_#t~mem166#1.base, main_#t~mem166#1.offset, main_#t~mem167#1.base, main_#t~mem167#1.offset, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem171#1, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1, main_#t~ite174#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1, main_#t~mem175#1.base, main_#t~mem175#1.offset, main_#t~mem176#1, main_#t~mem177#1.base, main_#t~mem177#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~#_he_new_buckets~0#1.base, main_~#_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem40#1, main_#t~post41#1, main_#t~mem42#1, main_#t~mem182#1, main_#t~mem181#1, main_#t~mem183#1, main_#t~mem184#1, main_#t~mem186#1, main_#t~mem185#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem190#1, main_#t~mem189#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~switch193#1, main_#t~mem194#1, main_#t~mem195#1, main_#t~mem196#1, main_#t~mem197#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem200#1, main_#t~mem201#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem204#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem205#1.base, main_#t~mem205#1.offset, main_#t~mem206#1, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1.base, main_#t~mem212#1.offset, main_#t~mem213#1.base, main_#t~mem213#1.offset, main_#t~mem214#1, main_#t~mem215#1, main_#t~mem216#1, main_#t~short217#1, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~ret219#1, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1.base, main_#t~mem221#1.offset, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~mem225#1.base, main_#t~mem225#1.offset, main_#t~short226#1, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~mem228#1.base, main_#t~mem228#1.offset, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1.base, main_#t~mem233#1.offset, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1.base, main_#t~mem239#1.offset, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1, main_#t~mem248#1.base, main_#t~mem248#1.offset, main_#t~mem251#1, main_#t~mem249#1.base, main_#t~mem249#1.offset, main_#t~mem250#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~mem253#1.base, main_#t~mem253#1.offset, main_#t~mem254#1, main_#t~post255#1, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem264#1.base, main_#t~mem264#1.offset, main_#t~mem265#1, main_#t~post266#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem178#1, main_#t~post179#1, main_#t~mem180#1, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~ite269#1.base, main_#t~ite269#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~short274#1, main_#t~mem275#1.base, main_#t~mem275#1.offset, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1.base, main_#t~mem281#1.offset, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1.base, main_#t~mem284#1.offset, main_#t~mem285#1, main_#t~mem286#1.base, main_#t~mem286#1.offset, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~mem290#1.base, main_#t~mem290#1.offset, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem299#1, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1, main_#t~mem300#1.base, main_#t~mem300#1.offset, main_#t~mem301#1.base, main_#t~mem301#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem306#1.base, main_#t~mem306#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~mem309#1.base, main_#t~mem309#1.offset, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~post314#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite271#1.base, main_#t~ite271#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4); 10#L989-4true [2022-10-17 10:30:36,794 INFO L750 eck$LassoCheckResult]: Loop: 10#L989-4true call main_#t~mem42#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4); 4#L989-1true assume !!(main_#t~mem42#1 < 10);havoc main_#t~mem42#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset; 97#L979true main_#t~ret43#1.base, main_#t~ret43#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret43#1.base, main_#t~ret43#1.offset;havoc main_#t~ret43#1.base, main_#t~ret43#1.offset; 11#L991true assume main_~user~0#1.base == 0 && main_~user~0#1.offset == 0;assume false; 90#L991-2true call main_#t~mem44#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int(main_#t~mem44#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem44#1;call main_#t~mem45#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem46#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int(main_#t~mem45#1 * main_#t~mem46#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem45#1;havoc main_#t~mem46#1; 238#L996-118true assume !true; 235#L989-3true call main_#t~mem40#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post41#1 := main_#t~mem40#1;call write~int(1 + main_#t~post41#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem40#1;havoc main_#t~post41#1; 10#L989-4true [2022-10-17 10:30:36,801 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:30:36,801 INFO L85 PathProgramCache]: Analyzing trace with hash 1251, now seen corresponding path program 1 times [2022-10-17 10:30:36,813 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:30:36,814 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1994795268] [2022-10-17 10:30:36,814 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:30:36,815 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:30:36,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:30:36,960 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:30:36,991 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:30:37,035 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:30:37,038 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:30:37,038 INFO L85 PathProgramCache]: Analyzing trace with hash -1530816074, now seen corresponding path program 1 times [2022-10-17 10:30:37,039 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:30:37,039 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [625266798] [2022-10-17 10:30:37,040 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:30:37,040 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:30:37,067 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:30:37,098 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:30:37,099 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [625266798] [2022-10-17 10:30:37,099 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: Unsupported non-linear arithmetic [2022-10-17 10:30:37,100 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1264630981] [2022-10-17 10:30:37,100 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:30:37,100 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 10:30:37,101 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3d3546f3-c140-4a8d-812b-99960e234815/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:30:37,103 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3d3546f3-c140-4a8d-812b-99960e234815/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 10:30:37,151 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3d3546f3-c140-4a8d-812b-99960e234815/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2022-10-17 10:30:37,326 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:30:37,328 INFO L263 TraceCheckSpWp]: Trace formula consists of 82 conjuncts, 1 conjunts are in the unsatisfiable core [2022-10-17 10:30:37,331 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:30:37,355 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:30:37,356 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-10-17 10:30:37,357 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1264630981] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:30:37,358 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:30:37,358 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-10-17 10:30:37,359 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1449872599] [2022-10-17 10:30:37,360 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:30:37,364 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:30:37,367 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:30:37,416 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2022-10-17 10:30:37,418 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2022-10-17 10:30:37,422 INFO L87 Difference]: Start difference. First operand has 257 states, 252 states have (on average 1.626984126984127) internal successors, (410), 252 states have internal predecessors, (410), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Second operand has 2 states, 2 states have (on average 3.5) internal successors, (7), 2 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:30:37,473 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:30:37,474 INFO L93 Difference]: Finished difference Result 253 states and 322 transitions. [2022-10-17 10:30:37,476 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 253 states and 322 transitions. [2022-10-17 10:30:37,489 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 231 [2022-10-17 10:30:37,504 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 253 states to 249 states and 318 transitions. [2022-10-17 10:30:37,507 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 249 [2022-10-17 10:30:37,509 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 249 [2022-10-17 10:30:37,510 INFO L73 IsDeterministic]: Start isDeterministic. Operand 249 states and 318 transitions. [2022-10-17 10:30:37,520 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:30:37,520 INFO L218 hiAutomatonCegarLoop]: Abstraction has 249 states and 318 transitions. [2022-10-17 10:30:37,545 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 249 states and 318 transitions. [2022-10-17 10:30:37,588 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 249 to 249. [2022-10-17 10:30:37,592 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 249 states, 245 states have (on average 1.273469387755102) internal successors, (312), 244 states have internal predecessors, (312), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-10-17 10:30:37,598 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 249 states to 249 states and 318 transitions. [2022-10-17 10:30:37,600 INFO L240 hiAutomatonCegarLoop]: Abstraction has 249 states and 318 transitions. [2022-10-17 10:30:37,601 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-10-17 10:30:37,606 INFO L428 stractBuchiCegarLoop]: Abstraction has 249 states and 318 transitions. [2022-10-17 10:30:37,607 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-10-17 10:30:37,608 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 249 states and 318 transitions. [2022-10-17 10:30:37,610 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 231 [2022-10-17 10:30:37,611 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:30:37,612 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:30:37,623 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-10-17 10:30:37,623 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:30:37,624 INFO L748 eck$LassoCheckResult]: Stem: 784#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call #Ultimate.allocInit(40, 3);#memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, ~#alt_malloc_sizes~0.base);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0; 754#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret43#1.base, main_#t~ret43#1.offset, main_#t~mem44#1, main_#t~mem45#1, main_#t~mem46#1, main_#t~mem48#1, main_#t~mem47#1, main_#t~mem49#1, main_#t~mem50#1, main_#t~mem52#1, main_#t~mem51#1, main_#t~mem53#1, main_#t~mem54#1, main_#t~mem56#1, main_#t~mem55#1, main_#t~mem57#1, main_#t~mem58#1, main_#t~switch59#1, main_#t~mem60#1, main_#t~mem61#1, main_#t~mem62#1, main_#t~mem63#1, main_#t~mem64#1, main_#t~mem65#1, main_#t~mem66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret71#1.base, main_#t~ret71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1.base, main_#t~mem78#1.offset, main_#t~ret79#1.base, main_#t~ret79#1.offset, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1.base, main_#t~mem82#1.offset, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~mem95#1, main_#t~post96#1, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1, main_#t~post102#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem107#1, main_#t~mem106#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~short110#1, main_#t~mem111#1.base, main_#t~mem111#1.offset, main_#t~mem112#1, main_#t~ret113#1.base, main_#t~ret113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem122#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem126#1, main_#t~mem124#1.base, main_#t~mem124#1.offset, main_#t~mem125#1, main_#t~ite127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem138#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem140#1, main_#t~pre141#1, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1, main_#t~post146#1, main_#t~mem150#1, main_#t~mem148#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem149#1, main_#t~mem151#1, main_#t~post152#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_#t~mem155#1.base, main_#t~mem155#1.offset, main_#t~post129#1, main_#t~mem130#1.base, main_#t~mem130#1.offset, main_#t~mem131#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_#t~mem159#1, main_#t~mem160#1.base, main_#t~mem160#1.offset, main_#t~mem161#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem163#1, main_#t~post164#1, main_#t~mem165#1.base, main_#t~mem165#1.offset, main_#t~mem166#1.base, main_#t~mem166#1.offset, main_#t~mem167#1.base, main_#t~mem167#1.offset, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem171#1, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1, main_#t~ite174#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1, main_#t~mem175#1.base, main_#t~mem175#1.offset, main_#t~mem176#1, main_#t~mem177#1.base, main_#t~mem177#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~#_he_new_buckets~0#1.base, main_~#_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem40#1, main_#t~post41#1, main_#t~mem42#1, main_#t~mem182#1, main_#t~mem181#1, main_#t~mem183#1, main_#t~mem184#1, main_#t~mem186#1, main_#t~mem185#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem190#1, main_#t~mem189#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~switch193#1, main_#t~mem194#1, main_#t~mem195#1, main_#t~mem196#1, main_#t~mem197#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem200#1, main_#t~mem201#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem204#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem205#1.base, main_#t~mem205#1.offset, main_#t~mem206#1, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1.base, main_#t~mem212#1.offset, main_#t~mem213#1.base, main_#t~mem213#1.offset, main_#t~mem214#1, main_#t~mem215#1, main_#t~mem216#1, main_#t~short217#1, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~ret219#1, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1.base, main_#t~mem221#1.offset, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~mem225#1.base, main_#t~mem225#1.offset, main_#t~short226#1, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~mem228#1.base, main_#t~mem228#1.offset, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1.base, main_#t~mem233#1.offset, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1.base, main_#t~mem239#1.offset, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1, main_#t~mem248#1.base, main_#t~mem248#1.offset, main_#t~mem251#1, main_#t~mem249#1.base, main_#t~mem249#1.offset, main_#t~mem250#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~mem253#1.base, main_#t~mem253#1.offset, main_#t~mem254#1, main_#t~post255#1, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem264#1.base, main_#t~mem264#1.offset, main_#t~mem265#1, main_#t~post266#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem178#1, main_#t~post179#1, main_#t~mem180#1, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~ite269#1.base, main_#t~ite269#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~short274#1, main_#t~mem275#1.base, main_#t~mem275#1.offset, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1.base, main_#t~mem281#1.offset, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1.base, main_#t~mem284#1.offset, main_#t~mem285#1, main_#t~mem286#1.base, main_#t~mem286#1.offset, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~mem290#1.base, main_#t~mem290#1.offset, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem299#1, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1, main_#t~mem300#1.base, main_#t~mem300#1.offset, main_#t~mem301#1.base, main_#t~mem301#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem306#1.base, main_#t~mem306#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~mem309#1.base, main_#t~mem309#1.offset, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~post314#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite271#1.base, main_#t~ite271#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4); 551#L989-4 [2022-10-17 10:30:37,634 INFO L750 eck$LassoCheckResult]: Loop: 551#L989-4 call main_#t~mem42#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4); 540#L989-1 assume !!(main_#t~mem42#1 < 10);havoc main_#t~mem42#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset; 542#L979 main_#t~ret43#1.base, main_#t~ret43#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret43#1.base, main_#t~ret43#1.offset;havoc main_#t~ret43#1.base, main_#t~ret43#1.offset; 552#L991 assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0); 553#L991-2 call main_#t~mem44#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int(main_#t~mem44#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem44#1;call main_#t~mem45#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem46#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int(main_#t~mem45#1 * main_#t~mem46#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem45#1;havoc main_#t~mem46#1; 683#L996-118 havoc main_~_ha_hashv~0#1; 739#L996-49 goto; 740#L996-47 havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4; 544#L996-8 assume !(main_~_hj_k~0#1 % 4294967296 >= 12); 576#L996-9 main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch59#1 := 11 == main_~_hj_k~0#1; 775#L996-10 assume main_#t~switch59#1;call main_#t~mem60#1 := read~int(main_~_hj_key~0#1.base, 10 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 16777216 * (main_#t~mem60#1 % 256);havoc main_#t~mem60#1; 783#L996-12 main_#t~switch59#1 := main_#t~switch59#1 || 10 == main_~_hj_k~0#1; 653#L996-13 assume main_#t~switch59#1;call main_#t~mem61#1 := read~int(main_~_hj_key~0#1.base, 9 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 65536 * (main_#t~mem61#1 % 256);havoc main_#t~mem61#1; 654#L996-15 main_#t~switch59#1 := main_#t~switch59#1 || 9 == main_~_hj_k~0#1; 778#L996-16 assume main_#t~switch59#1;call main_#t~mem62#1 := read~int(main_~_hj_key~0#1.base, 8 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 256 * (main_#t~mem62#1 % 256);havoc main_#t~mem62#1; 779#L996-18 main_#t~switch59#1 := main_#t~switch59#1 || 8 == main_~_hj_k~0#1; 766#L996-19 assume main_#t~switch59#1;call main_#t~mem63#1 := read~int(main_~_hj_key~0#1.base, 7 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 16777216 * (main_#t~mem63#1 % 256);havoc main_#t~mem63#1; 761#L996-21 main_#t~switch59#1 := main_#t~switch59#1 || 7 == main_~_hj_k~0#1; 736#L996-22 assume main_#t~switch59#1;call main_#t~mem64#1 := read~int(main_~_hj_key~0#1.base, 6 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 65536 * (main_#t~mem64#1 % 256);havoc main_#t~mem64#1; 737#L996-24 main_#t~switch59#1 := main_#t~switch59#1 || 6 == main_~_hj_k~0#1; 757#L996-25 assume main_#t~switch59#1;call main_#t~mem65#1 := read~int(main_~_hj_key~0#1.base, 5 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 256 * (main_#t~mem65#1 % 256);havoc main_#t~mem65#1; 724#L996-27 main_#t~switch59#1 := main_#t~switch59#1 || 5 == main_~_hj_k~0#1; 545#L996-28 assume !main_#t~switch59#1; 546#L996-30 main_#t~switch59#1 := main_#t~switch59#1 || 4 == main_~_hj_k~0#1; 693#L996-31 assume main_#t~switch59#1;call main_#t~mem67#1 := read~int(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem67#1 % 256);havoc main_#t~mem67#1; 714#L996-33 main_#t~switch59#1 := main_#t~switch59#1 || 3 == main_~_hj_k~0#1; 674#L996-34 assume main_#t~switch59#1;call main_#t~mem68#1 := read~int(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem68#1 % 256);havoc main_#t~mem68#1; 675#L996-36 main_#t~switch59#1 := main_#t~switch59#1 || 2 == main_~_hj_k~0#1; 635#L996-37 assume main_#t~switch59#1;call main_#t~mem69#1 := read~int(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem69#1 % 256);havoc main_#t~mem69#1; 636#L996-39 main_#t~switch59#1 := main_#t~switch59#1 || 1 == main_~_hj_k~0#1; 657#L996-40 assume main_#t~switch59#1;call main_#t~mem70#1 := read~int(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + main_#t~mem70#1 % 256;havoc main_#t~mem70#1; 694#L996-42 havoc main_#t~switch59#1; 604#L996-45 main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if (1 == main_~_hj_i~0#1 || 0 == main_~_hj_i~0#1) && (1 == main_~_ha_hashv~0#1 / 8192 || 0 == main_~_ha_hashv~0#1 / 8192) then (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 8192 then 0 else 1) else (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 8192 else (if 0 == main_~_ha_hashv~0#1 / 8192 then main_~_hj_i~0#1 else ~bitwiseXOr(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8192))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if (1 == main_~_hj_j~0#1 || 0 == main_~_hj_j~0#1) && (1 == 256 * main_~_hj_i~0#1 || 0 == 256 * main_~_hj_i~0#1) then (if main_~_hj_j~0#1 == 256 * main_~_hj_i~0#1 then 0 else 1) else (if 0 == main_~_hj_j~0#1 then 256 * main_~_hj_i~0#1 else (if 0 == 256 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else ~bitwiseXOr(main_~_hj_j~0#1, 256 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if (1 == main_~_ha_hashv~0#1 || 0 == main_~_ha_hashv~0#1) && (1 == main_~_hj_j~0#1 / 8192 || 0 == main_~_hj_j~0#1 / 8192) then (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 8192 then 0 else 1) else (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 8192 else (if 0 == main_~_hj_j~0#1 / 8192 then main_~_ha_hashv~0#1 else ~bitwiseXOr(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 8192))));main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if (1 == main_~_hj_i~0#1 || 0 == main_~_hj_i~0#1) && (1 == main_~_ha_hashv~0#1 / 4096 || 0 == main_~_ha_hashv~0#1 / 4096) then (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 4096 then 0 else 1) else (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 4096 else (if 0 == main_~_ha_hashv~0#1 / 4096 then main_~_hj_i~0#1 else ~bitwiseXOr(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 4096))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if (1 == main_~_hj_j~0#1 || 0 == main_~_hj_j~0#1) && (1 == 65536 * main_~_hj_i~0#1 || 0 == 65536 * main_~_hj_i~0#1) then (if main_~_hj_j~0#1 == 65536 * main_~_hj_i~0#1 then 0 else 1) else (if 0 == main_~_hj_j~0#1 then 65536 * main_~_hj_i~0#1 else (if 0 == 65536 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else ~bitwiseXOr(main_~_hj_j~0#1, 65536 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if (1 == main_~_ha_hashv~0#1 || 0 == main_~_ha_hashv~0#1) && (1 == main_~_hj_j~0#1 / 32 || 0 == main_~_hj_j~0#1 / 32) then (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 32 then 0 else 1) else (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 32 else (if 0 == main_~_hj_j~0#1 / 32 then main_~_ha_hashv~0#1 else ~bitwiseXOr(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32))));main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if (1 == main_~_hj_i~0#1 || 0 == main_~_hj_i~0#1) && (1 == main_~_ha_hashv~0#1 / 8 || 0 == main_~_ha_hashv~0#1 / 8) then (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 8 then 0 else 1) else (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 8 else (if 0 == main_~_ha_hashv~0#1 / 8 then main_~_hj_i~0#1 else ~bitwiseXOr(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if (1 == main_~_hj_j~0#1 || 0 == main_~_hj_j~0#1) && (1 == 1024 * main_~_hj_i~0#1 || 0 == 1024 * main_~_hj_i~0#1) then (if main_~_hj_j~0#1 == 1024 * main_~_hj_i~0#1 then 0 else 1) else (if 0 == main_~_hj_j~0#1 then 1024 * main_~_hj_i~0#1 else (if 0 == 1024 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else ~bitwiseXOr(main_~_hj_j~0#1, 1024 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if (1 == main_~_ha_hashv~0#1 || 0 == main_~_ha_hashv~0#1) && (1 == main_~_hj_j~0#1 / 32768 || 0 == main_~_hj_j~0#1 / 32768) then (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 32768 then 0 else 1) else (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 32768 else (if 0 == main_~_hj_j~0#1 / 32768 then main_~_ha_hashv~0#1 else ~bitwiseXOr(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32768)))); 605#L996-44 goto; 709#L996-46 goto; 726#L996-48 goto; 764#L996-116 call write~int(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4); 765#L996-51 assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem86#1.base, main_#t~mem86#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_#t~mem86#1.base, main_#t~mem86#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem86#1.base, main_#t~mem86#1.offset; 664#L996-63 call write~$Pointer$(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$(main_#t~mem87#1.base, 16 + main_#t~mem87#1.offset, 4);call main_#t~mem89#1.base, main_#t~mem89#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem90#1 := read~int(main_#t~mem89#1.base, 20 + main_#t~mem89#1.offset, 4);call write~$Pointer$(main_#t~mem88#1.base, main_#t~mem88#1.offset - main_#t~mem90#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;havoc main_#t~mem89#1.base, main_#t~mem89#1.offset;havoc main_#t~mem90#1;call main_#t~mem91#1.base, main_#t~mem91#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem92#1.base, main_#t~mem92#1.offset := read~$Pointer$(main_#t~mem91#1.base, 16 + main_#t~mem91#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem92#1.base, 8 + main_#t~mem92#1.offset, 4);havoc main_#t~mem91#1.base, main_#t~mem91#1.offset;havoc main_#t~mem92#1.base, main_#t~mem92#1.offset;call main_#t~mem93#1.base, main_#t~mem93#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem93#1.base, 16 + main_#t~mem93#1.offset, 4);havoc main_#t~mem93#1.base, main_#t~mem93#1.offset; 665#L996-62 goto; 609#L996-114 havoc main_~_ha_bkt~0#1;call main_#t~mem94#1.base, main_#t~mem94#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem95#1 := read~int(main_#t~mem94#1.base, 12 + main_#t~mem94#1.offset, 4);main_#t~post96#1 := main_#t~mem95#1;call write~int(1 + main_#t~post96#1, main_#t~mem94#1.base, 12 + main_#t~mem94#1.offset, 4);havoc main_#t~mem94#1.base, main_#t~mem94#1.offset;havoc main_#t~mem95#1;havoc main_#t~post96#1; 652#L996-67 call main_#t~mem97#1.base, main_#t~mem97#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem98#1 := read~int(main_#t~mem97#1.base, 4 + main_#t~mem97#1.offset, 4);main_~_ha_bkt~0#1 := (if 0 == main_~_ha_hashv~0#1 || 0 == main_#t~mem98#1 - 1 then 0 else (if 1 == main_#t~mem98#1 - 1 then (if 1 == main_~_ha_hashv~0#1 || 0 == main_~_ha_hashv~0#1 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 >= 0 then main_~_ha_hashv~0#1 % 2 else ~bitwiseAnd(main_~_ha_hashv~0#1, main_#t~mem98#1 - 1))) else (if 1 == main_~_ha_hashv~0#1 then (if 1 == main_#t~mem98#1 - 1 || 0 == main_#t~mem98#1 - 1 then main_#t~mem98#1 - 1 else (if main_#t~mem98#1 - 1 >= 0 then (main_#t~mem98#1 - 1) % 2 else ~bitwiseAnd(main_~_ha_hashv~0#1, main_#t~mem98#1 - 1))) else ~bitwiseAnd(main_~_ha_hashv~0#1, main_#t~mem98#1 - 1))));havoc main_#t~mem97#1.base, main_#t~mem97#1.offset;havoc main_#t~mem98#1; 721#L996-66 goto; 771#L996-112 call main_#t~mem99#1.base, main_#t~mem99#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem100#1.base, main_#t~mem100#1.offset := read~$Pointer$(main_#t~mem99#1.base, main_#t~mem99#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem100#1.base, main_#t~mem100#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem99#1.base, main_#t~mem99#1.offset;havoc main_#t~mem100#1.base, main_#t~mem100#1.offset;call main_#t~mem101#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post102#1 := main_#t~mem101#1;call write~int(1 + main_#t~post102#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem101#1;havoc main_#t~post102#1;call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_#t~mem103#1.base, main_#t~mem103#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;call write~$Pointer$(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4); 758#L996-69 assume main_#t~mem104#1.base != 0 || main_#t~mem104#1.offset != 0;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem105#1.base, 12 + main_#t~mem105#1.offset, 4);havoc main_#t~mem105#1.base, main_#t~mem105#1.offset; 577#L996-71 call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem107#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem106#1 := read~int(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short110#1 := main_#t~mem107#1 % 4294967296 >= 10 * (1 + main_#t~mem106#1) % 4294967296; 578#L996-72 assume main_#t~short110#1;call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem109#1 := read~int(main_#t~mem108#1.base, 36 + main_#t~mem108#1.offset, 4);main_#t~short110#1 := 0 == main_#t~mem109#1 % 4294967296; 640#L996-74 assume !main_#t~short110#1;havoc main_#t~mem107#1;havoc main_#t~mem106#1;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;havoc main_#t~mem109#1;havoc main_#t~short110#1; 595#L996-111 goto; 592#L996-113 goto; 593#L996-115 goto; 717#L996-117 goto; 718#L989-3 call main_#t~mem40#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post41#1 := main_#t~mem40#1;call write~int(1 + main_#t~post41#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem40#1;havoc main_#t~post41#1; 551#L989-4 [2022-10-17 10:30:37,637 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:30:37,643 INFO L85 PathProgramCache]: Analyzing trace with hash 1251, now seen corresponding path program 2 times [2022-10-17 10:30:37,644 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:30:37,644 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1629678157] [2022-10-17 10:30:37,645 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:30:37,645 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:30:37,699 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:30:37,703 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:30:37,737 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:30:37,769 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:30:37,780 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:30:37,780 INFO L85 PathProgramCache]: Analyzing trace with hash 1942584983, now seen corresponding path program 1 times [2022-10-17 10:30:37,780 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:30:37,782 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [433686577] [2022-10-17 10:30:37,782 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:30:37,783 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:30:38,068 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-10-17 10:30:38,069 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [233063040] [2022-10-17 10:30:38,069 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:30:38,070 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 10:30:38,070 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3d3546f3-c140-4a8d-812b-99960e234815/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:30:38,072 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3d3546f3-c140-4a8d-812b-99960e234815/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 10:30:38,095 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3d3546f3-c140-4a8d-812b-99960e234815/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2022-10-17 10:30:39,023 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:30:39,037 INFO L263 TraceCheckSpWp]: Trace formula consists of 1858 conjuncts, 3 conjunts are in the unsatisfiable core [2022-10-17 10:30:39,043 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:30:39,109 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:30:39,112 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-10-17 10:30:39,113 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:30:39,113 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [433686577] [2022-10-17 10:30:39,114 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-10-17 10:30:39,114 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [233063040] [2022-10-17 10:30:39,114 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [233063040] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:30:39,114 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:30:39,115 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:30:39,115 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [363042764] [2022-10-17 10:30:39,115 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:30:39,116 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:30:39,116 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:30:39,117 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:30:39,117 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:30:39,118 INFO L87 Difference]: Start difference. First operand 249 states and 318 transitions. cyclomatic complexity: 73 Second operand has 3 states, 3 states have (on average 17.666666666666668) internal successors, (53), 3 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:30:39,257 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:30:39,258 INFO L93 Difference]: Finished difference Result 270 states and 339 transitions. [2022-10-17 10:30:39,258 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 270 states and 339 transitions. [2022-10-17 10:30:39,264 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 252 [2022-10-17 10:30:39,270 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 270 states to 270 states and 339 transitions. [2022-10-17 10:30:39,271 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 270 [2022-10-17 10:30:39,272 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 270 [2022-10-17 10:30:39,273 INFO L73 IsDeterministic]: Start isDeterministic. Operand 270 states and 339 transitions. [2022-10-17 10:30:39,276 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:30:39,276 INFO L218 hiAutomatonCegarLoop]: Abstraction has 270 states and 339 transitions. [2022-10-17 10:30:39,279 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 270 states and 339 transitions. [2022-10-17 10:30:39,295 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 270 to 269. [2022-10-17 10:30:39,304 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 269 states, 265 states have (on average 1.2528301886792452) internal successors, (332), 264 states have internal predecessors, (332), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-10-17 10:30:39,306 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 269 states to 269 states and 338 transitions. [2022-10-17 10:30:39,306 INFO L240 hiAutomatonCegarLoop]: Abstraction has 269 states and 338 transitions. [2022-10-17 10:30:39,307 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:30:39,308 INFO L428 stractBuchiCegarLoop]: Abstraction has 269 states and 338 transitions. [2022-10-17 10:30:39,308 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-10-17 10:30:39,308 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 269 states and 338 transitions. [2022-10-17 10:30:39,310 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 251 [2022-10-17 10:30:39,311 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:30:39,311 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:30:39,314 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-10-17 10:30:39,315 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:30:39,315 INFO L748 eck$LassoCheckResult]: Stem: 1470#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call #Ultimate.allocInit(40, 3);#memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, ~#alt_malloc_sizes~0.base);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0; 1435#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret43#1.base, main_#t~ret43#1.offset, main_#t~mem44#1, main_#t~mem45#1, main_#t~mem46#1, main_#t~mem48#1, main_#t~mem47#1, main_#t~mem49#1, main_#t~mem50#1, main_#t~mem52#1, main_#t~mem51#1, main_#t~mem53#1, main_#t~mem54#1, main_#t~mem56#1, main_#t~mem55#1, main_#t~mem57#1, main_#t~mem58#1, main_#t~switch59#1, main_#t~mem60#1, main_#t~mem61#1, main_#t~mem62#1, main_#t~mem63#1, main_#t~mem64#1, main_#t~mem65#1, main_#t~mem66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret71#1.base, main_#t~ret71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1.base, main_#t~mem78#1.offset, main_#t~ret79#1.base, main_#t~ret79#1.offset, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1.base, main_#t~mem82#1.offset, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~mem95#1, main_#t~post96#1, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1, main_#t~post102#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem107#1, main_#t~mem106#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~short110#1, main_#t~mem111#1.base, main_#t~mem111#1.offset, main_#t~mem112#1, main_#t~ret113#1.base, main_#t~ret113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem122#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem126#1, main_#t~mem124#1.base, main_#t~mem124#1.offset, main_#t~mem125#1, main_#t~ite127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem138#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem140#1, main_#t~pre141#1, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1, main_#t~post146#1, main_#t~mem150#1, main_#t~mem148#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem149#1, main_#t~mem151#1, main_#t~post152#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_#t~mem155#1.base, main_#t~mem155#1.offset, main_#t~post129#1, main_#t~mem130#1.base, main_#t~mem130#1.offset, main_#t~mem131#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_#t~mem159#1, main_#t~mem160#1.base, main_#t~mem160#1.offset, main_#t~mem161#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem163#1, main_#t~post164#1, main_#t~mem165#1.base, main_#t~mem165#1.offset, main_#t~mem166#1.base, main_#t~mem166#1.offset, main_#t~mem167#1.base, main_#t~mem167#1.offset, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem171#1, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1, main_#t~ite174#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1, main_#t~mem175#1.base, main_#t~mem175#1.offset, main_#t~mem176#1, main_#t~mem177#1.base, main_#t~mem177#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~#_he_new_buckets~0#1.base, main_~#_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem40#1, main_#t~post41#1, main_#t~mem42#1, main_#t~mem182#1, main_#t~mem181#1, main_#t~mem183#1, main_#t~mem184#1, main_#t~mem186#1, main_#t~mem185#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem190#1, main_#t~mem189#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~switch193#1, main_#t~mem194#1, main_#t~mem195#1, main_#t~mem196#1, main_#t~mem197#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem200#1, main_#t~mem201#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem204#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem205#1.base, main_#t~mem205#1.offset, main_#t~mem206#1, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1.base, main_#t~mem212#1.offset, main_#t~mem213#1.base, main_#t~mem213#1.offset, main_#t~mem214#1, main_#t~mem215#1, main_#t~mem216#1, main_#t~short217#1, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~ret219#1, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1.base, main_#t~mem221#1.offset, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~mem225#1.base, main_#t~mem225#1.offset, main_#t~short226#1, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~mem228#1.base, main_#t~mem228#1.offset, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1.base, main_#t~mem233#1.offset, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1.base, main_#t~mem239#1.offset, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1, main_#t~mem248#1.base, main_#t~mem248#1.offset, main_#t~mem251#1, main_#t~mem249#1.base, main_#t~mem249#1.offset, main_#t~mem250#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~mem253#1.base, main_#t~mem253#1.offset, main_#t~mem254#1, main_#t~post255#1, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem264#1.base, main_#t~mem264#1.offset, main_#t~mem265#1, main_#t~post266#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem178#1, main_#t~post179#1, main_#t~mem180#1, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~ite269#1.base, main_#t~ite269#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~short274#1, main_#t~mem275#1.base, main_#t~mem275#1.offset, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1.base, main_#t~mem281#1.offset, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1.base, main_#t~mem284#1.offset, main_#t~mem285#1, main_#t~mem286#1.base, main_#t~mem286#1.offset, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~mem290#1.base, main_#t~mem290#1.offset, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem299#1, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1, main_#t~mem300#1.base, main_#t~mem300#1.offset, main_#t~mem301#1.base, main_#t~mem301#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem306#1.base, main_#t~mem306#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~mem309#1.base, main_#t~mem309#1.offset, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~post314#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite271#1.base, main_#t~ite271#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4); 1232#L989-4 [2022-10-17 10:30:39,316 INFO L750 eck$LassoCheckResult]: Loop: 1232#L989-4 call main_#t~mem42#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4); 1221#L989-1 assume !!(main_#t~mem42#1 < 10);havoc main_#t~mem42#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset; 1223#L979 main_#t~ret43#1.base, main_#t~ret43#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret43#1.base, main_#t~ret43#1.offset;havoc main_#t~ret43#1.base, main_#t~ret43#1.offset; 1233#L991 assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0); 1234#L991-2 call main_#t~mem44#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int(main_#t~mem44#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem44#1;call main_#t~mem45#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem46#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int(main_#t~mem45#1 * main_#t~mem46#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem45#1;havoc main_#t~mem46#1; 1364#L996-118 havoc main_~_ha_hashv~0#1; 1420#L996-49 goto; 1421#L996-47 havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4; 1225#L996-8 assume !(main_~_hj_k~0#1 % 4294967296 >= 12); 1259#L996-9 main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch59#1 := 11 == main_~_hj_k~0#1; 1458#L996-10 assume main_#t~switch59#1;call main_#t~mem60#1 := read~int(main_~_hj_key~0#1.base, 10 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 16777216 * (main_#t~mem60#1 % 256);havoc main_#t~mem60#1; 1466#L996-12 main_#t~switch59#1 := main_#t~switch59#1 || 10 == main_~_hj_k~0#1; 1334#L996-13 assume main_#t~switch59#1;call main_#t~mem61#1 := read~int(main_~_hj_key~0#1.base, 9 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 65536 * (main_#t~mem61#1 % 256);havoc main_#t~mem61#1; 1335#L996-15 main_#t~switch59#1 := main_#t~switch59#1 || 9 == main_~_hj_k~0#1; 1461#L996-16 assume main_#t~switch59#1;call main_#t~mem62#1 := read~int(main_~_hj_key~0#1.base, 8 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 256 * (main_#t~mem62#1 % 256);havoc main_#t~mem62#1; 1462#L996-18 main_#t~switch59#1 := main_#t~switch59#1 || 8 == main_~_hj_k~0#1; 1449#L996-19 assume main_#t~switch59#1;call main_#t~mem63#1 := read~int(main_~_hj_key~0#1.base, 7 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 16777216 * (main_#t~mem63#1 % 256);havoc main_#t~mem63#1; 1444#L996-21 main_#t~switch59#1 := main_#t~switch59#1 || 7 == main_~_hj_k~0#1; 1417#L996-22 assume main_#t~switch59#1;call main_#t~mem64#1 := read~int(main_~_hj_key~0#1.base, 6 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 65536 * (main_#t~mem64#1 % 256);havoc main_#t~mem64#1; 1418#L996-24 main_#t~switch59#1 := main_#t~switch59#1 || 6 == main_~_hj_k~0#1; 1442#L996-25 assume main_#t~switch59#1;call main_#t~mem65#1 := read~int(main_~_hj_key~0#1.base, 5 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 256 * (main_#t~mem65#1 % 256);havoc main_#t~mem65#1; 1405#L996-27 main_#t~switch59#1 := main_#t~switch59#1 || 5 == main_~_hj_k~0#1; 1226#L996-28 assume main_#t~switch59#1;call main_#t~mem66#1 := read~int(main_~_hj_key~0#1.base, 4 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + main_#t~mem66#1 % 256;havoc main_#t~mem66#1; 1227#L996-30 main_#t~switch59#1 := main_#t~switch59#1 || 4 == main_~_hj_k~0#1; 1374#L996-31 assume main_#t~switch59#1;call main_#t~mem67#1 := read~int(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem67#1 % 256);havoc main_#t~mem67#1; 1394#L996-33 main_#t~switch59#1 := main_#t~switch59#1 || 3 == main_~_hj_k~0#1; 1355#L996-34 assume main_#t~switch59#1;call main_#t~mem68#1 := read~int(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem68#1 % 256);havoc main_#t~mem68#1; 1356#L996-36 main_#t~switch59#1 := main_#t~switch59#1 || 2 == main_~_hj_k~0#1; 1316#L996-37 assume main_#t~switch59#1;call main_#t~mem69#1 := read~int(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem69#1 % 256);havoc main_#t~mem69#1; 1317#L996-39 main_#t~switch59#1 := main_#t~switch59#1 || 1 == main_~_hj_k~0#1; 1338#L996-40 assume main_#t~switch59#1;call main_#t~mem70#1 := read~int(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + main_#t~mem70#1 % 256;havoc main_#t~mem70#1; 1375#L996-42 havoc main_#t~switch59#1; 1285#L996-45 main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if (1 == main_~_hj_i~0#1 || 0 == main_~_hj_i~0#1) && (1 == main_~_ha_hashv~0#1 / 8192 || 0 == main_~_ha_hashv~0#1 / 8192) then (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 8192 then 0 else 1) else (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 8192 else (if 0 == main_~_ha_hashv~0#1 / 8192 then main_~_hj_i~0#1 else ~bitwiseXOr(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8192))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if (1 == main_~_hj_j~0#1 || 0 == main_~_hj_j~0#1) && (1 == 256 * main_~_hj_i~0#1 || 0 == 256 * main_~_hj_i~0#1) then (if main_~_hj_j~0#1 == 256 * main_~_hj_i~0#1 then 0 else 1) else (if 0 == main_~_hj_j~0#1 then 256 * main_~_hj_i~0#1 else (if 0 == 256 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else ~bitwiseXOr(main_~_hj_j~0#1, 256 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if (1 == main_~_ha_hashv~0#1 || 0 == main_~_ha_hashv~0#1) && (1 == main_~_hj_j~0#1 / 8192 || 0 == main_~_hj_j~0#1 / 8192) then (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 8192 then 0 else 1) else (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 8192 else (if 0 == main_~_hj_j~0#1 / 8192 then main_~_ha_hashv~0#1 else ~bitwiseXOr(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 8192))));main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if (1 == main_~_hj_i~0#1 || 0 == main_~_hj_i~0#1) && (1 == main_~_ha_hashv~0#1 / 4096 || 0 == main_~_ha_hashv~0#1 / 4096) then (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 4096 then 0 else 1) else (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 4096 else (if 0 == main_~_ha_hashv~0#1 / 4096 then main_~_hj_i~0#1 else ~bitwiseXOr(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 4096))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if (1 == main_~_hj_j~0#1 || 0 == main_~_hj_j~0#1) && (1 == 65536 * main_~_hj_i~0#1 || 0 == 65536 * main_~_hj_i~0#1) then (if main_~_hj_j~0#1 == 65536 * main_~_hj_i~0#1 then 0 else 1) else (if 0 == main_~_hj_j~0#1 then 65536 * main_~_hj_i~0#1 else (if 0 == 65536 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else ~bitwiseXOr(main_~_hj_j~0#1, 65536 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if (1 == main_~_ha_hashv~0#1 || 0 == main_~_ha_hashv~0#1) && (1 == main_~_hj_j~0#1 / 32 || 0 == main_~_hj_j~0#1 / 32) then (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 32 then 0 else 1) else (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 32 else (if 0 == main_~_hj_j~0#1 / 32 then main_~_ha_hashv~0#1 else ~bitwiseXOr(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32))));main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if (1 == main_~_hj_i~0#1 || 0 == main_~_hj_i~0#1) && (1 == main_~_ha_hashv~0#1 / 8 || 0 == main_~_ha_hashv~0#1 / 8) then (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 8 then 0 else 1) else (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 8 else (if 0 == main_~_ha_hashv~0#1 / 8 then main_~_hj_i~0#1 else ~bitwiseXOr(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if (1 == main_~_hj_j~0#1 || 0 == main_~_hj_j~0#1) && (1 == 1024 * main_~_hj_i~0#1 || 0 == 1024 * main_~_hj_i~0#1) then (if main_~_hj_j~0#1 == 1024 * main_~_hj_i~0#1 then 0 else 1) else (if 0 == main_~_hj_j~0#1 then 1024 * main_~_hj_i~0#1 else (if 0 == 1024 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else ~bitwiseXOr(main_~_hj_j~0#1, 1024 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if (1 == main_~_ha_hashv~0#1 || 0 == main_~_ha_hashv~0#1) && (1 == main_~_hj_j~0#1 / 32768 || 0 == main_~_hj_j~0#1 / 32768) then (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 32768 then 0 else 1) else (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 32768 else (if 0 == main_~_hj_j~0#1 / 32768 then main_~_ha_hashv~0#1 else ~bitwiseXOr(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32768)))); 1286#L996-44 goto; 1390#L996-46 goto; 1407#L996-48 goto; 1447#L996-116 call write~int(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4); 1448#L996-51 assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem86#1.base, main_#t~mem86#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_#t~mem86#1.base, main_#t~mem86#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem86#1.base, main_#t~mem86#1.offset; 1342#L996-63 call write~$Pointer$(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$(main_#t~mem87#1.base, 16 + main_#t~mem87#1.offset, 4);call main_#t~mem89#1.base, main_#t~mem89#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem90#1 := read~int(main_#t~mem89#1.base, 20 + main_#t~mem89#1.offset, 4);call write~$Pointer$(main_#t~mem88#1.base, main_#t~mem88#1.offset - main_#t~mem90#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;havoc main_#t~mem89#1.base, main_#t~mem89#1.offset;havoc main_#t~mem90#1;call main_#t~mem91#1.base, main_#t~mem91#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem92#1.base, main_#t~mem92#1.offset := read~$Pointer$(main_#t~mem91#1.base, 16 + main_#t~mem91#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem92#1.base, 8 + main_#t~mem92#1.offset, 4);havoc main_#t~mem91#1.base, main_#t~mem91#1.offset;havoc main_#t~mem92#1.base, main_#t~mem92#1.offset;call main_#t~mem93#1.base, main_#t~mem93#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem93#1.base, 16 + main_#t~mem93#1.offset, 4);havoc main_#t~mem93#1.base, main_#t~mem93#1.offset; 1343#L996-62 goto; 1290#L996-114 havoc main_~_ha_bkt~0#1;call main_#t~mem94#1.base, main_#t~mem94#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem95#1 := read~int(main_#t~mem94#1.base, 12 + main_#t~mem94#1.offset, 4);main_#t~post96#1 := main_#t~mem95#1;call write~int(1 + main_#t~post96#1, main_#t~mem94#1.base, 12 + main_#t~mem94#1.offset, 4);havoc main_#t~mem94#1.base, main_#t~mem94#1.offset;havoc main_#t~mem95#1;havoc main_#t~post96#1; 1331#L996-67 call main_#t~mem97#1.base, main_#t~mem97#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem98#1 := read~int(main_#t~mem97#1.base, 4 + main_#t~mem97#1.offset, 4);main_~_ha_bkt~0#1 := (if 0 == main_~_ha_hashv~0#1 || 0 == main_#t~mem98#1 - 1 then 0 else (if 1 == main_#t~mem98#1 - 1 then (if 1 == main_~_ha_hashv~0#1 || 0 == main_~_ha_hashv~0#1 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 >= 0 then main_~_ha_hashv~0#1 % 2 else ~bitwiseAnd(main_~_ha_hashv~0#1, main_#t~mem98#1 - 1))) else (if 1 == main_~_ha_hashv~0#1 then (if 1 == main_#t~mem98#1 - 1 || 0 == main_#t~mem98#1 - 1 then main_#t~mem98#1 - 1 else (if main_#t~mem98#1 - 1 >= 0 then (main_#t~mem98#1 - 1) % 2 else ~bitwiseAnd(main_~_ha_hashv~0#1, main_#t~mem98#1 - 1))) else ~bitwiseAnd(main_~_ha_hashv~0#1, main_#t~mem98#1 - 1))));havoc main_#t~mem97#1.base, main_#t~mem97#1.offset;havoc main_#t~mem98#1; 1401#L996-66 goto; 1452#L996-112 call main_#t~mem99#1.base, main_#t~mem99#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem100#1.base, main_#t~mem100#1.offset := read~$Pointer$(main_#t~mem99#1.base, main_#t~mem99#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem100#1.base, main_#t~mem100#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem99#1.base, main_#t~mem99#1.offset;havoc main_#t~mem100#1.base, main_#t~mem100#1.offset;call main_#t~mem101#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post102#1 := main_#t~mem101#1;call write~int(1 + main_#t~post102#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem101#1;havoc main_#t~post102#1;call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_#t~mem103#1.base, main_#t~mem103#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;call write~$Pointer$(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4); 1440#L996-69 assume main_#t~mem104#1.base != 0 || main_#t~mem104#1.offset != 0;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem105#1.base, 12 + main_#t~mem105#1.offset, 4);havoc main_#t~mem105#1.base, main_#t~mem105#1.offset; 1256#L996-71 call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem107#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem106#1 := read~int(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short110#1 := main_#t~mem107#1 % 4294967296 >= 10 * (1 + main_#t~mem106#1) % 4294967296; 1257#L996-72 assume main_#t~short110#1;call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem109#1 := read~int(main_#t~mem108#1.base, 36 + main_#t~mem108#1.offset, 4);main_#t~short110#1 := 0 == main_#t~mem109#1 % 4294967296; 1321#L996-74 assume !main_#t~short110#1;havoc main_#t~mem107#1;havoc main_#t~mem106#1;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;havoc main_#t~mem109#1;havoc main_#t~short110#1; 1276#L996-111 goto; 1273#L996-113 goto; 1274#L996-115 goto; 1396#L996-117 goto; 1397#L989-3 call main_#t~mem40#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post41#1 := main_#t~mem40#1;call write~int(1 + main_#t~post41#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem40#1;havoc main_#t~post41#1; 1232#L989-4 [2022-10-17 10:30:39,317 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:30:39,318 INFO L85 PathProgramCache]: Analyzing trace with hash 1251, now seen corresponding path program 3 times [2022-10-17 10:30:39,318 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:30:39,318 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [70777936] [2022-10-17 10:30:39,318 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:30:39,319 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:30:39,372 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:30:39,372 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:30:39,386 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:30:39,411 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:30:39,411 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:30:39,412 INFO L85 PathProgramCache]: Analyzing trace with hash 1240985109, now seen corresponding path program 1 times [2022-10-17 10:30:39,412 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:30:39,412 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [965493948] [2022-10-17 10:30:39,412 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:30:39,413 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:30:39,649 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-10-17 10:30:39,649 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [81615982] [2022-10-17 10:30:39,649 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:30:39,650 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 10:30:39,650 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3d3546f3-c140-4a8d-812b-99960e234815/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:30:39,668 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3d3546f3-c140-4a8d-812b-99960e234815/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 10:30:39,686 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3d3546f3-c140-4a8d-812b-99960e234815/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2022-10-17 10:30:40,656 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:30:40,669 INFO L263 TraceCheckSpWp]: Trace formula consists of 1864 conjuncts, 3 conjunts are in the unsatisfiable core [2022-10-17 10:30:40,674 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:30:40,724 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:30:40,725 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-10-17 10:30:40,725 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:30:40,725 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [965493948] [2022-10-17 10:30:40,725 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-10-17 10:30:40,725 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [81615982] [2022-10-17 10:30:40,726 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [81615982] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:30:40,726 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:30:40,726 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-10-17 10:30:40,726 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [983593053] [2022-10-17 10:30:40,727 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:30:40,727 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:30:40,727 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:30:40,728 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-10-17 10:30:40,728 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-10-17 10:30:40,728 INFO L87 Difference]: Start difference. First operand 269 states and 338 transitions. cyclomatic complexity: 73 Second operand has 4 states, 4 states have (on average 13.25) internal successors, (53), 4 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:30:40,867 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:30:40,867 INFO L93 Difference]: Finished difference Result 396 states and 497 transitions. [2022-10-17 10:30:40,867 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 396 states and 497 transitions. [2022-10-17 10:30:40,874 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 358 [2022-10-17 10:30:40,884 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 396 states to 396 states and 497 transitions. [2022-10-17 10:30:40,884 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 396 [2022-10-17 10:30:40,885 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 396 [2022-10-17 10:30:40,885 INFO L73 IsDeterministic]: Start isDeterministic. Operand 396 states and 497 transitions. [2022-10-17 10:30:40,886 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:30:40,886 INFO L218 hiAutomatonCegarLoop]: Abstraction has 396 states and 497 transitions. [2022-10-17 10:30:40,888 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 396 states and 497 transitions. [2022-10-17 10:30:40,906 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 396 to 255. [2022-10-17 10:30:40,907 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 255 states, 251 states have (on average 1.2390438247011952) internal successors, (311), 250 states have internal predecessors, (311), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-10-17 10:30:40,911 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 255 states to 255 states and 317 transitions. [2022-10-17 10:30:40,911 INFO L240 hiAutomatonCegarLoop]: Abstraction has 255 states and 317 transitions. [2022-10-17 10:30:40,912 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-10-17 10:30:40,913 INFO L428 stractBuchiCegarLoop]: Abstraction has 255 states and 317 transitions. [2022-10-17 10:30:40,914 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-10-17 10:30:40,914 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 255 states and 317 transitions. [2022-10-17 10:30:40,916 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 237 [2022-10-17 10:30:40,916 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:30:40,916 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:30:40,917 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-10-17 10:30:40,917 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:30:40,917 INFO L748 eck$LassoCheckResult]: Stem: 2298#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call #Ultimate.allocInit(40, 3);#memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, ~#alt_malloc_sizes~0.base);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0; 2266#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret43#1.base, main_#t~ret43#1.offset, main_#t~mem44#1, main_#t~mem45#1, main_#t~mem46#1, main_#t~mem48#1, main_#t~mem47#1, main_#t~mem49#1, main_#t~mem50#1, main_#t~mem52#1, main_#t~mem51#1, main_#t~mem53#1, main_#t~mem54#1, main_#t~mem56#1, main_#t~mem55#1, main_#t~mem57#1, main_#t~mem58#1, main_#t~switch59#1, main_#t~mem60#1, main_#t~mem61#1, main_#t~mem62#1, main_#t~mem63#1, main_#t~mem64#1, main_#t~mem65#1, main_#t~mem66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret71#1.base, main_#t~ret71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1.base, main_#t~mem78#1.offset, main_#t~ret79#1.base, main_#t~ret79#1.offset, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1.base, main_#t~mem82#1.offset, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~mem95#1, main_#t~post96#1, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1, main_#t~post102#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem107#1, main_#t~mem106#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~short110#1, main_#t~mem111#1.base, main_#t~mem111#1.offset, main_#t~mem112#1, main_#t~ret113#1.base, main_#t~ret113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem122#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem126#1, main_#t~mem124#1.base, main_#t~mem124#1.offset, main_#t~mem125#1, main_#t~ite127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem138#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem140#1, main_#t~pre141#1, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1, main_#t~post146#1, main_#t~mem150#1, main_#t~mem148#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem149#1, main_#t~mem151#1, main_#t~post152#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_#t~mem155#1.base, main_#t~mem155#1.offset, main_#t~post129#1, main_#t~mem130#1.base, main_#t~mem130#1.offset, main_#t~mem131#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_#t~mem159#1, main_#t~mem160#1.base, main_#t~mem160#1.offset, main_#t~mem161#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem163#1, main_#t~post164#1, main_#t~mem165#1.base, main_#t~mem165#1.offset, main_#t~mem166#1.base, main_#t~mem166#1.offset, main_#t~mem167#1.base, main_#t~mem167#1.offset, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem171#1, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1, main_#t~ite174#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1, main_#t~mem175#1.base, main_#t~mem175#1.offset, main_#t~mem176#1, main_#t~mem177#1.base, main_#t~mem177#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~#_he_new_buckets~0#1.base, main_~#_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem40#1, main_#t~post41#1, main_#t~mem42#1, main_#t~mem182#1, main_#t~mem181#1, main_#t~mem183#1, main_#t~mem184#1, main_#t~mem186#1, main_#t~mem185#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem190#1, main_#t~mem189#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~switch193#1, main_#t~mem194#1, main_#t~mem195#1, main_#t~mem196#1, main_#t~mem197#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem200#1, main_#t~mem201#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem204#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem205#1.base, main_#t~mem205#1.offset, main_#t~mem206#1, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1.base, main_#t~mem212#1.offset, main_#t~mem213#1.base, main_#t~mem213#1.offset, main_#t~mem214#1, main_#t~mem215#1, main_#t~mem216#1, main_#t~short217#1, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~ret219#1, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1.base, main_#t~mem221#1.offset, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~mem225#1.base, main_#t~mem225#1.offset, main_#t~short226#1, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~mem228#1.base, main_#t~mem228#1.offset, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1.base, main_#t~mem233#1.offset, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1.base, main_#t~mem239#1.offset, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1, main_#t~mem248#1.base, main_#t~mem248#1.offset, main_#t~mem251#1, main_#t~mem249#1.base, main_#t~mem249#1.offset, main_#t~mem250#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~mem253#1.base, main_#t~mem253#1.offset, main_#t~mem254#1, main_#t~post255#1, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem264#1.base, main_#t~mem264#1.offset, main_#t~mem265#1, main_#t~post266#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem178#1, main_#t~post179#1, main_#t~mem180#1, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~ite269#1.base, main_#t~ite269#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~short274#1, main_#t~mem275#1.base, main_#t~mem275#1.offset, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1.base, main_#t~mem281#1.offset, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1.base, main_#t~mem284#1.offset, main_#t~mem285#1, main_#t~mem286#1.base, main_#t~mem286#1.offset, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~mem290#1.base, main_#t~mem290#1.offset, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem299#1, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1, main_#t~mem300#1.base, main_#t~mem300#1.offset, main_#t~mem301#1.base, main_#t~mem301#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem306#1.base, main_#t~mem306#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~mem309#1.base, main_#t~mem309#1.offset, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~post314#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite271#1.base, main_#t~ite271#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4); 2062#L989-4 [2022-10-17 10:30:40,918 INFO L750 eck$LassoCheckResult]: Loop: 2062#L989-4 call main_#t~mem42#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4); 2051#L989-1 assume !!(main_#t~mem42#1 < 10);havoc main_#t~mem42#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset; 2053#L979 main_#t~ret43#1.base, main_#t~ret43#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret43#1.base, main_#t~ret43#1.offset;havoc main_#t~ret43#1.base, main_#t~ret43#1.offset; 2063#L991 assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0); 2064#L991-2 call main_#t~mem44#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int(main_#t~mem44#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem44#1;call main_#t~mem45#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem46#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int(main_#t~mem45#1 * main_#t~mem46#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem45#1;havoc main_#t~mem46#1; 2195#L996-118 havoc main_~_ha_hashv~0#1; 2251#L996-49 goto; 2252#L996-47 havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4; 2055#L996-8 assume !(main_~_hj_k~0#1 % 4294967296 >= 12); 2087#L996-9 main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch59#1 := 11 == main_~_hj_k~0#1; 2288#L996-10 assume !main_#t~switch59#1; 2297#L996-12 main_#t~switch59#1 := main_#t~switch59#1 || 10 == main_~_hj_k~0#1; 2164#L996-13 assume !main_#t~switch59#1; 2165#L996-15 main_#t~switch59#1 := main_#t~switch59#1 || 9 == main_~_hj_k~0#1; 2292#L996-16 assume !main_#t~switch59#1; 2293#L996-18 main_#t~switch59#1 := main_#t~switch59#1 || 8 == main_~_hj_k~0#1; 2278#L996-19 assume !main_#t~switch59#1; 2273#L996-21 main_#t~switch59#1 := main_#t~switch59#1 || 7 == main_~_hj_k~0#1; 2248#L996-22 assume !main_#t~switch59#1; 2249#L996-24 main_#t~switch59#1 := main_#t~switch59#1 || 6 == main_~_hj_k~0#1; 2269#L996-25 assume !main_#t~switch59#1; 2236#L996-27 main_#t~switch59#1 := main_#t~switch59#1 || 5 == main_~_hj_k~0#1; 2056#L996-28 assume !main_#t~switch59#1; 2057#L996-30 main_#t~switch59#1 := main_#t~switch59#1 || 4 == main_~_hj_k~0#1; 2205#L996-31 assume main_#t~switch59#1;call main_#t~mem67#1 := read~int(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem67#1 % 256);havoc main_#t~mem67#1; 2226#L996-33 main_#t~switch59#1 := main_#t~switch59#1 || 3 == main_~_hj_k~0#1; 2186#L996-34 assume main_#t~switch59#1;call main_#t~mem68#1 := read~int(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem68#1 % 256);havoc main_#t~mem68#1; 2187#L996-36 main_#t~switch59#1 := main_#t~switch59#1 || 2 == main_~_hj_k~0#1; 2146#L996-37 assume main_#t~switch59#1;call main_#t~mem69#1 := read~int(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem69#1 % 256);havoc main_#t~mem69#1; 2147#L996-39 main_#t~switch59#1 := main_#t~switch59#1 || 1 == main_~_hj_k~0#1; 2279#L996-40 assume main_#t~switch59#1;call main_#t~mem70#1 := read~int(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + main_#t~mem70#1 % 256;havoc main_#t~mem70#1; 2206#L996-42 havoc main_#t~switch59#1; 2115#L996-45 main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if (1 == main_~_hj_i~0#1 || 0 == main_~_hj_i~0#1) && (1 == main_~_ha_hashv~0#1 / 8192 || 0 == main_~_ha_hashv~0#1 / 8192) then (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 8192 then 0 else 1) else (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 8192 else (if 0 == main_~_ha_hashv~0#1 / 8192 then main_~_hj_i~0#1 else ~bitwiseXOr(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8192))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if (1 == main_~_hj_j~0#1 || 0 == main_~_hj_j~0#1) && (1 == 256 * main_~_hj_i~0#1 || 0 == 256 * main_~_hj_i~0#1) then (if main_~_hj_j~0#1 == 256 * main_~_hj_i~0#1 then 0 else 1) else (if 0 == main_~_hj_j~0#1 then 256 * main_~_hj_i~0#1 else (if 0 == 256 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else ~bitwiseXOr(main_~_hj_j~0#1, 256 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if (1 == main_~_ha_hashv~0#1 || 0 == main_~_ha_hashv~0#1) && (1 == main_~_hj_j~0#1 / 8192 || 0 == main_~_hj_j~0#1 / 8192) then (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 8192 then 0 else 1) else (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 8192 else (if 0 == main_~_hj_j~0#1 / 8192 then main_~_ha_hashv~0#1 else ~bitwiseXOr(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 8192))));main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if (1 == main_~_hj_i~0#1 || 0 == main_~_hj_i~0#1) && (1 == main_~_ha_hashv~0#1 / 4096 || 0 == main_~_ha_hashv~0#1 / 4096) then (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 4096 then 0 else 1) else (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 4096 else (if 0 == main_~_ha_hashv~0#1 / 4096 then main_~_hj_i~0#1 else ~bitwiseXOr(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 4096))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if (1 == main_~_hj_j~0#1 || 0 == main_~_hj_j~0#1) && (1 == 65536 * main_~_hj_i~0#1 || 0 == 65536 * main_~_hj_i~0#1) then (if main_~_hj_j~0#1 == 65536 * main_~_hj_i~0#1 then 0 else 1) else (if 0 == main_~_hj_j~0#1 then 65536 * main_~_hj_i~0#1 else (if 0 == 65536 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else ~bitwiseXOr(main_~_hj_j~0#1, 65536 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if (1 == main_~_ha_hashv~0#1 || 0 == main_~_ha_hashv~0#1) && (1 == main_~_hj_j~0#1 / 32 || 0 == main_~_hj_j~0#1 / 32) then (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 32 then 0 else 1) else (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 32 else (if 0 == main_~_hj_j~0#1 / 32 then main_~_ha_hashv~0#1 else ~bitwiseXOr(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32))));main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if (1 == main_~_hj_i~0#1 || 0 == main_~_hj_i~0#1) && (1 == main_~_ha_hashv~0#1 / 8 || 0 == main_~_ha_hashv~0#1 / 8) then (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 8 then 0 else 1) else (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 8 else (if 0 == main_~_ha_hashv~0#1 / 8 then main_~_hj_i~0#1 else ~bitwiseXOr(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if (1 == main_~_hj_j~0#1 || 0 == main_~_hj_j~0#1) && (1 == 1024 * main_~_hj_i~0#1 || 0 == 1024 * main_~_hj_i~0#1) then (if main_~_hj_j~0#1 == 1024 * main_~_hj_i~0#1 then 0 else 1) else (if 0 == main_~_hj_j~0#1 then 1024 * main_~_hj_i~0#1 else (if 0 == 1024 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else ~bitwiseXOr(main_~_hj_j~0#1, 1024 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if (1 == main_~_ha_hashv~0#1 || 0 == main_~_ha_hashv~0#1) && (1 == main_~_hj_j~0#1 / 32768 || 0 == main_~_hj_j~0#1 / 32768) then (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 32768 then 0 else 1) else (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 32768 else (if 0 == main_~_hj_j~0#1 / 32768 then main_~_ha_hashv~0#1 else ~bitwiseXOr(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32768)))); 2116#L996-44 goto; 2221#L996-46 goto; 2238#L996-48 goto; 2276#L996-116 call write~int(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4); 2277#L996-51 assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem86#1.base, main_#t~mem86#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_#t~mem86#1.base, main_#t~mem86#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem86#1.base, main_#t~mem86#1.offset; 2176#L996-63 call write~$Pointer$(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$(main_#t~mem87#1.base, 16 + main_#t~mem87#1.offset, 4);call main_#t~mem89#1.base, main_#t~mem89#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem90#1 := read~int(main_#t~mem89#1.base, 20 + main_#t~mem89#1.offset, 4);call write~$Pointer$(main_#t~mem88#1.base, main_#t~mem88#1.offset - main_#t~mem90#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;havoc main_#t~mem89#1.base, main_#t~mem89#1.offset;havoc main_#t~mem90#1;call main_#t~mem91#1.base, main_#t~mem91#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem92#1.base, main_#t~mem92#1.offset := read~$Pointer$(main_#t~mem91#1.base, 16 + main_#t~mem91#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem92#1.base, 8 + main_#t~mem92#1.offset, 4);havoc main_#t~mem91#1.base, main_#t~mem91#1.offset;havoc main_#t~mem92#1.base, main_#t~mem92#1.offset;call main_#t~mem93#1.base, main_#t~mem93#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem93#1.base, 16 + main_#t~mem93#1.offset, 4);havoc main_#t~mem93#1.base, main_#t~mem93#1.offset; 2177#L996-62 goto; 2120#L996-114 havoc main_~_ha_bkt~0#1;call main_#t~mem94#1.base, main_#t~mem94#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem95#1 := read~int(main_#t~mem94#1.base, 12 + main_#t~mem94#1.offset, 4);main_#t~post96#1 := main_#t~mem95#1;call write~int(1 + main_#t~post96#1, main_#t~mem94#1.base, 12 + main_#t~mem94#1.offset, 4);havoc main_#t~mem94#1.base, main_#t~mem94#1.offset;havoc main_#t~mem95#1;havoc main_#t~post96#1; 2163#L996-67 call main_#t~mem97#1.base, main_#t~mem97#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem98#1 := read~int(main_#t~mem97#1.base, 4 + main_#t~mem97#1.offset, 4);main_~_ha_bkt~0#1 := (if 0 == main_~_ha_hashv~0#1 || 0 == main_#t~mem98#1 - 1 then 0 else (if 1 == main_#t~mem98#1 - 1 then (if 1 == main_~_ha_hashv~0#1 || 0 == main_~_ha_hashv~0#1 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 >= 0 then main_~_ha_hashv~0#1 % 2 else ~bitwiseAnd(main_~_ha_hashv~0#1, main_#t~mem98#1 - 1))) else (if 1 == main_~_ha_hashv~0#1 then (if 1 == main_#t~mem98#1 - 1 || 0 == main_#t~mem98#1 - 1 then main_#t~mem98#1 - 1 else (if main_#t~mem98#1 - 1 >= 0 then (main_#t~mem98#1 - 1) % 2 else ~bitwiseAnd(main_~_ha_hashv~0#1, main_#t~mem98#1 - 1))) else ~bitwiseAnd(main_~_ha_hashv~0#1, main_#t~mem98#1 - 1))));havoc main_#t~mem97#1.base, main_#t~mem97#1.offset;havoc main_#t~mem98#1; 2233#L996-66 goto; 2284#L996-112 call main_#t~mem99#1.base, main_#t~mem99#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem100#1.base, main_#t~mem100#1.offset := read~$Pointer$(main_#t~mem99#1.base, main_#t~mem99#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem100#1.base, main_#t~mem100#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem99#1.base, main_#t~mem99#1.offset;havoc main_#t~mem100#1.base, main_#t~mem100#1.offset;call main_#t~mem101#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post102#1 := main_#t~mem101#1;call write~int(1 + main_#t~post102#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem101#1;havoc main_#t~post102#1;call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_#t~mem103#1.base, main_#t~mem103#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;call write~$Pointer$(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4); 2270#L996-69 assume main_#t~mem104#1.base != 0 || main_#t~mem104#1.offset != 0;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem105#1.base, 12 + main_#t~mem105#1.offset, 4);havoc main_#t~mem105#1.base, main_#t~mem105#1.offset; 2088#L996-71 call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem107#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem106#1 := read~int(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short110#1 := main_#t~mem107#1 % 4294967296 >= 10 * (1 + main_#t~mem106#1) % 4294967296; 2089#L996-72 assume main_#t~short110#1;call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem109#1 := read~int(main_#t~mem108#1.base, 36 + main_#t~mem108#1.offset, 4);main_#t~short110#1 := 0 == main_#t~mem109#1 % 4294967296; 2151#L996-74 assume !main_#t~short110#1;havoc main_#t~mem107#1;havoc main_#t~mem106#1;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;havoc main_#t~mem109#1;havoc main_#t~short110#1; 2108#L996-111 goto; 2103#L996-113 goto; 2104#L996-115 goto; 2229#L996-117 goto; 2230#L989-3 call main_#t~mem40#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post41#1 := main_#t~mem40#1;call write~int(1 + main_#t~post41#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem40#1;havoc main_#t~post41#1; 2062#L989-4 [2022-10-17 10:30:40,918 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:30:40,918 INFO L85 PathProgramCache]: Analyzing trace with hash 1251, now seen corresponding path program 4 times [2022-10-17 10:30:40,919 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:30:40,924 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1290237178] [2022-10-17 10:30:40,924 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:30:40,925 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:30:40,994 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:30:40,994 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:30:41,006 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:30:41,024 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:30:41,025 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:30:41,025 INFO L85 PathProgramCache]: Analyzing trace with hash -633389277, now seen corresponding path program 1 times [2022-10-17 10:30:41,025 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:30:41,026 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1777052184] [2022-10-17 10:30:41,026 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:30:41,026 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:30:41,193 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-10-17 10:30:41,193 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [382569330] [2022-10-17 10:30:41,194 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:30:41,194 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 10:30:41,194 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3d3546f3-c140-4a8d-812b-99960e234815/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:30:41,199 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3d3546f3-c140-4a8d-812b-99960e234815/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 10:30:41,225 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3d3546f3-c140-4a8d-812b-99960e234815/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process