./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/uthash-2.0.2/uthash_OAT_test7-1.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version dbf71c69 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cf4cc610-6584-43c2-a4b2-fc8d2c4ba5ac/bin/uautomizer-J5u9QxTXDZ/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cf4cc610-6584-43c2-a4b2-fc8d2c4ba5ac/bin/uautomizer-J5u9QxTXDZ/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cf4cc610-6584-43c2-a4b2-fc8d2c4ba5ac/bin/uautomizer-J5u9QxTXDZ/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cf4cc610-6584-43c2-a4b2-fc8d2c4ba5ac/bin/uautomizer-J5u9QxTXDZ/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/uthash-2.0.2/uthash_OAT_test7-1.i -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cf4cc610-6584-43c2-a4b2-fc8d2c4ba5ac/bin/uautomizer-J5u9QxTXDZ/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cf4cc610-6584-43c2-a4b2-fc8d2c4ba5ac/bin/uautomizer-J5u9QxTXDZ --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 23c0dee81707c82be8d9645ea65556f17c2a25b7864c310b805b07f657c0bc23 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-dbf71c6-m [2022-10-17 11:09:15,936 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-10-17 11:09:15,939 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-10-17 11:09:16,013 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-10-17 11:09:16,014 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-10-17 11:09:16,021 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-10-17 11:09:16,024 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-10-17 11:09:16,031 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-10-17 11:09:16,034 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-10-17 11:09:16,035 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-10-17 11:09:16,037 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-10-17 11:09:16,038 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-10-17 11:09:16,039 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-10-17 11:09:16,041 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-10-17 11:09:16,045 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-10-17 11:09:16,048 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-10-17 11:09:16,050 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-10-17 11:09:16,060 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-10-17 11:09:16,063 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-10-17 11:09:16,072 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-10-17 11:09:16,075 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-10-17 11:09:16,079 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-10-17 11:09:16,084 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-10-17 11:09:16,086 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-10-17 11:09:16,096 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-10-17 11:09:16,096 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-10-17 11:09:16,096 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-10-17 11:09:16,099 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-10-17 11:09:16,100 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-10-17 11:09:16,101 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-10-17 11:09:16,102 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-10-17 11:09:16,104 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-10-17 11:09:16,106 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-10-17 11:09:16,108 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-10-17 11:09:16,109 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-10-17 11:09:16,109 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-10-17 11:09:16,110 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-10-17 11:09:16,110 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-10-17 11:09:16,110 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-10-17 11:09:16,112 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-10-17 11:09:16,121 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-10-17 11:09:16,122 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cf4cc610-6584-43c2-a4b2-fc8d2c4ba5ac/bin/uautomizer-J5u9QxTXDZ/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-10-17 11:09:16,182 INFO L113 SettingsManager]: Loading preferences was successful [2022-10-17 11:09:16,184 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-10-17 11:09:16,184 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-10-17 11:09:16,185 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-10-17 11:09:16,186 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-10-17 11:09:16,187 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-10-17 11:09:16,187 INFO L138 SettingsManager]: * Use SBE=true [2022-10-17 11:09:16,187 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-10-17 11:09:16,187 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-10-17 11:09:16,188 INFO L138 SettingsManager]: * Use old map elimination=false [2022-10-17 11:09:16,189 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-10-17 11:09:16,190 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-10-17 11:09:16,190 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-10-17 11:09:16,190 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-10-17 11:09:16,190 INFO L138 SettingsManager]: * sizeof long=4 [2022-10-17 11:09:16,191 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-10-17 11:09:16,191 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-10-17 11:09:16,191 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-10-17 11:09:16,191 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-10-17 11:09:16,192 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-10-17 11:09:16,192 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-10-17 11:09:16,192 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-10-17 11:09:16,193 INFO L138 SettingsManager]: * sizeof long double=12 [2022-10-17 11:09:16,195 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-10-17 11:09:16,195 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-10-17 11:09:16,195 INFO L138 SettingsManager]: * Use constant arrays=true [2022-10-17 11:09:16,196 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-10-17 11:09:16,196 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-10-17 11:09:16,196 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-10-17 11:09:16,197 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-10-17 11:09:16,197 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-10-17 11:09:16,198 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-10-17 11:09:16,199 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cf4cc610-6584-43c2-a4b2-fc8d2c4ba5ac/bin/uautomizer-J5u9QxTXDZ/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cf4cc610-6584-43c2-a4b2-fc8d2c4ba5ac/bin/uautomizer-J5u9QxTXDZ Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 23c0dee81707c82be8d9645ea65556f17c2a25b7864c310b805b07f657c0bc23 [2022-10-17 11:09:16,555 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-10-17 11:09:16,587 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-10-17 11:09:16,590 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-10-17 11:09:16,592 INFO L271 PluginConnector]: Initializing CDTParser... [2022-10-17 11:09:16,593 INFO L275 PluginConnector]: CDTParser initialized [2022-10-17 11:09:16,594 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cf4cc610-6584-43c2-a4b2-fc8d2c4ba5ac/bin/uautomizer-J5u9QxTXDZ/../../sv-benchmarks/c/uthash-2.0.2/uthash_OAT_test7-1.i [2022-10-17 11:09:16,669 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cf4cc610-6584-43c2-a4b2-fc8d2c4ba5ac/bin/uautomizer-J5u9QxTXDZ/data/0b0538713/337a5092191149788990eb721c30bffe/FLAG73094b526 [2022-10-17 11:09:17,410 INFO L306 CDTParser]: Found 1 translation units. [2022-10-17 11:09:17,411 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cf4cc610-6584-43c2-a4b2-fc8d2c4ba5ac/sv-benchmarks/c/uthash-2.0.2/uthash_OAT_test7-1.i [2022-10-17 11:09:17,453 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cf4cc610-6584-43c2-a4b2-fc8d2c4ba5ac/bin/uautomizer-J5u9QxTXDZ/data/0b0538713/337a5092191149788990eb721c30bffe/FLAG73094b526 [2022-10-17 11:09:17,580 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cf4cc610-6584-43c2-a4b2-fc8d2c4ba5ac/bin/uautomizer-J5u9QxTXDZ/data/0b0538713/337a5092191149788990eb721c30bffe [2022-10-17 11:09:17,583 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-10-17 11:09:17,585 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-10-17 11:09:17,586 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-10-17 11:09:17,587 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-10-17 11:09:17,604 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-10-17 11:09:17,605 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.10 11:09:17" (1/1) ... [2022-10-17 11:09:17,607 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@218b0098 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 11:09:17, skipping insertion in model container [2022-10-17 11:09:17,607 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.10 11:09:17" (1/1) ... [2022-10-17 11:09:17,618 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-10-17 11:09:17,701 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-10-17 11:09:18,317 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cf4cc610-6584-43c2-a4b2-fc8d2c4ba5ac/sv-benchmarks/c/uthash-2.0.2/uthash_OAT_test7-1.i[33021,33034] [2022-10-17 11:09:18,485 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cf4cc610-6584-43c2-a4b2-fc8d2c4ba5ac/sv-benchmarks/c/uthash-2.0.2/uthash_OAT_test7-1.i[44124,44137] [2022-10-17 11:09:18,487 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cf4cc610-6584-43c2-a4b2-fc8d2c4ba5ac/sv-benchmarks/c/uthash-2.0.2/uthash_OAT_test7-1.i[44245,44258] [2022-10-17 11:09:18,497 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-10-17 11:09:18,509 INFO L203 MainTranslator]: Completed pre-run [2022-10-17 11:09:18,558 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cf4cc610-6584-43c2-a4b2-fc8d2c4ba5ac/sv-benchmarks/c/uthash-2.0.2/uthash_OAT_test7-1.i[33021,33034] [2022-10-17 11:09:18,679 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cf4cc610-6584-43c2-a4b2-fc8d2c4ba5ac/sv-benchmarks/c/uthash-2.0.2/uthash_OAT_test7-1.i[44124,44137] [2022-10-17 11:09:18,680 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cf4cc610-6584-43c2-a4b2-fc8d2c4ba5ac/sv-benchmarks/c/uthash-2.0.2/uthash_OAT_test7-1.i[44245,44258] [2022-10-17 11:09:18,686 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-10-17 11:09:18,770 INFO L208 MainTranslator]: Completed translation [2022-10-17 11:09:18,785 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 11:09:18 WrapperNode [2022-10-17 11:09:18,792 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-10-17 11:09:18,793 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-10-17 11:09:18,793 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-10-17 11:09:18,793 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-10-17 11:09:18,802 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 11:09:18" (1/1) ... [2022-10-17 11:09:18,841 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 11:09:18" (1/1) ... [2022-10-17 11:09:18,901 INFO L138 Inliner]: procedures = 176, calls = 277, calls flagged for inlining = 2, calls inlined = 2, statements flattened = 996 [2022-10-17 11:09:18,902 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-10-17 11:09:18,903 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-10-17 11:09:18,903 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-10-17 11:09:18,903 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-10-17 11:09:18,912 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 11:09:18" (1/1) ... [2022-10-17 11:09:18,913 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 11:09:18" (1/1) ... [2022-10-17 11:09:18,925 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 11:09:18" (1/1) ... [2022-10-17 11:09:18,925 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 11:09:18" (1/1) ... [2022-10-17 11:09:18,979 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 11:09:18" (1/1) ... [2022-10-17 11:09:18,992 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 11:09:18" (1/1) ... [2022-10-17 11:09:18,997 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 11:09:18" (1/1) ... [2022-10-17 11:09:19,004 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 11:09:18" (1/1) ... [2022-10-17 11:09:19,014 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-10-17 11:09:19,015 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-10-17 11:09:19,015 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-10-17 11:09:19,015 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-10-17 11:09:19,020 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 11:09:18" (1/1) ... [2022-10-17 11:09:19,027 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 11:09:19,038 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cf4cc610-6584-43c2-a4b2-fc8d2c4ba5ac/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 11:09:19,076 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cf4cc610-6584-43c2-a4b2-fc8d2c4ba5ac/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 11:09:19,100 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cf4cc610-6584-43c2-a4b2-fc8d2c4ba5ac/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-10-17 11:09:19,134 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2022-10-17 11:09:19,135 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2022-10-17 11:09:19,136 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset [2022-10-17 11:09:19,137 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset [2022-10-17 11:09:19,137 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnHeap [2022-10-17 11:09:19,138 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-10-17 11:09:19,138 INFO L130 BoogieDeclarations]: Found specification of procedure write~$Pointer$ [2022-10-17 11:09:19,138 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2022-10-17 11:09:19,138 INFO L130 BoogieDeclarations]: Found specification of procedure memcmp [2022-10-17 11:09:19,139 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$ [2022-10-17 11:09:19,139 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2022-10-17 11:09:19,139 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-10-17 11:09:19,139 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-10-17 11:09:19,139 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-10-17 11:09:19,418 INFO L235 CfgBuilder]: Building ICFG [2022-10-17 11:09:19,420 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-10-17 11:09:19,424 WARN L816 $ProcedureCfgBuilder]: Label in the middle of a codeblock. [2022-10-17 11:09:21,664 INFO L276 CfgBuilder]: Performing block encoding [2022-10-17 11:09:21,680 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-10-17 11:09:21,681 INFO L300 CfgBuilder]: Removed 63 assume(true) statements. [2022-10-17 11:09:21,684 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 17.10 11:09:21 BoogieIcfgContainer [2022-10-17 11:09:21,684 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-10-17 11:09:21,686 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-10-17 11:09:21,686 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-10-17 11:09:21,691 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-10-17 11:09:21,692 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-10-17 11:09:21,692 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 17.10 11:09:17" (1/3) ... [2022-10-17 11:09:21,693 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7277d74d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.10 11:09:21, skipping insertion in model container [2022-10-17 11:09:21,694 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-10-17 11:09:21,695 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 11:09:18" (2/3) ... [2022-10-17 11:09:21,696 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7277d74d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.10 11:09:21, skipping insertion in model container [2022-10-17 11:09:21,696 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-10-17 11:09:21,696 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 17.10 11:09:21" (3/3) ... [2022-10-17 11:09:21,698 INFO L332 chiAutomizerObserver]: Analyzing ICFG uthash_OAT_test7-1.i [2022-10-17 11:09:21,799 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-10-17 11:09:21,799 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-10-17 11:09:21,800 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-10-17 11:09:21,800 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-10-17 11:09:21,800 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-10-17 11:09:21,800 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-10-17 11:09:21,800 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-10-17 11:09:21,800 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-10-17 11:09:21,807 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 183 states, 178 states have (on average 1.6910112359550562) internal successors, (301), 178 states have internal predecessors, (301), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-10-17 11:09:21,854 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 171 [2022-10-17 11:09:21,855 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 11:09:21,855 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 11:09:21,863 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-10-17 11:09:21,863 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1] [2022-10-17 11:09:21,863 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-10-17 11:09:21,865 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 183 states, 178 states have (on average 1.6910112359550562) internal successors, (301), 178 states have internal predecessors, (301), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-10-17 11:09:21,876 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 171 [2022-10-17 11:09:21,877 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 11:09:21,877 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 11:09:21,881 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-10-17 11:09:21,882 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1] [2022-10-17 11:09:21,892 INFO L748 eck$LassoCheckResult]: Stem: 166#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2); 64#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem7#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~mem19#1, main_#t~mem18#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~switch22#1, main_#t~mem23#1, main_#t~mem24#1, main_#t~mem25#1, main_#t~mem26#1, main_#t~mem27#1, main_#t~mem28#1, main_#t~mem29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc34#1.base, main_#t~malloc34#1.offset, main_#t~mem35#1.base, main_#t~mem35#1.offset, main_#t~mem36#1.base, main_#t~mem36#1.offset, main_#t~memset~res37#1.base, main_#t~memset~res37#1.offset, main_#t~mem38#1.base, main_#t~mem38#1.offset, main_#t~mem39#1.base, main_#t~mem39#1.offset, main_#t~mem40#1.base, main_#t~mem40#1.offset, main_#t~mem41#1.base, main_#t~mem41#1.offset, main_#t~mem42#1.base, main_#t~mem42#1.offset, main_#t~malloc43#1.base, main_#t~malloc43#1.offset, main_#t~mem44#1.base, main_#t~mem44#1.offset, main_#t~mem45#1.base, main_#t~mem45#1.offset, main_#t~mem46#1.base, main_#t~mem46#1.offset, main_#t~mem47#1.base, main_#t~mem47#1.offset, main_#t~mem48#1.base, main_#t~mem48#1.offset, main_#t~mem49#1.base, main_#t~mem49#1.offset, main_#t~memset~res50#1.base, main_#t~memset~res50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~mem52#1.base, main_#t~mem52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1, main_#t~post61#1, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1, main_#t~post67#1, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem72#1, main_#t~mem71#1, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1, main_#t~short75#1, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1, main_#t~malloc78#1.base, main_#t~malloc78#1.offset, main_#t~mem79#1.base, main_#t~mem79#1.offset, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1, main_#t~memset~res83#1.base, main_#t~memset~res83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem88#1, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem87#1, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem92#1, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1, main_#t~ite93#1, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem104#1, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~pre107#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem116#1, main_#t~mem114#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem115#1, main_#t~mem117#1, main_#t~post118#1, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~post95#1, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem124#1.base, main_#t~mem124#1.offset, main_#t~mem125#1, main_#t~mem126#1.base, main_#t~mem126#1.offset, main_#t~mem127#1, main_#t~post128#1, main_#t~mem129#1.base, main_#t~mem129#1.offset, main_#t~mem130#1.base, main_#t~mem130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem135#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1, main_#t~ite138#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem140#1, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~#_he_new_buckets~0#1.base, main_~#_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem3#1, main_#t~post4#1, main_#t~mem5#1, main_#t~mem146#1, main_#t~mem145#1, main_#t~mem147#1, main_#t~mem148#1, main_#t~mem150#1, main_#t~mem149#1, main_#t~mem151#1, main_#t~mem152#1, main_#t~mem154#1, main_#t~mem153#1, main_#t~mem155#1, main_#t~mem156#1, main_#t~switch157#1, main_#t~mem158#1, main_#t~mem159#1, main_#t~mem160#1, main_#t~mem161#1, main_#t~mem162#1, main_#t~mem163#1, main_#t~mem164#1, main_#t~mem165#1, main_#t~mem166#1, main_#t~mem167#1, main_#t~mem168#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1, main_#t~mem171#1.base, main_#t~mem171#1.offset, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1.base, main_#t~mem175#1.offset, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1.base, main_#t~mem177#1.offset, main_#t~mem178#1, main_#t~mem179#1, main_#t~mem180#1, main_#t~short181#1, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~ret183#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1.base, main_#t~mem185#1.offset, main_#t~mem186#1.base, main_#t~mem186#1.offset, main_#t~mem187#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem188#1.base, main_#t~mem188#1.offset, main_#t~mem189#1.base, main_#t~mem189#1.offset, main_#t~short190#1, main_#t~mem191#1.base, main_#t~mem191#1.offset, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_#t~mem193#1.base, main_#t~mem193#1.offset, main_#t~mem194#1.base, main_#t~mem194#1.offset, main_#t~mem195#1.base, main_#t~mem195#1.offset, main_#t~mem196#1.base, main_#t~mem196#1.offset, main_#t~mem197#1.base, main_#t~mem197#1.offset, main_#t~mem198#1.base, main_#t~mem198#1.offset, main_#t~mem199#1, main_#t~mem200#1.base, main_#t~mem200#1.offset, main_#t~mem201#1.base, main_#t~mem201#1.offset, main_#t~mem202#1.base, main_#t~mem202#1.offset, main_#t~mem203#1, main_#t~mem204#1.base, main_#t~mem204#1.offset, main_#t~mem205#1.base, main_#t~mem205#1.offset, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem213#1, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1, main_#t~mem214#1.base, main_#t~mem214#1.offset, main_#t~mem215#1.base, main_#t~mem215#1.offset, main_#t~mem216#1, main_#t~post217#1, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~mem219#1.base, main_#t~mem219#1.offset, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1.base, main_#t~mem221#1.offset, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~mem225#1.base, main_#t~mem225#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem226#1.base, main_#t~mem226#1.offset, main_#t~mem227#1, main_#t~post228#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem142#1, main_#t~post143#1, main_#t~mem144#1, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4); 139#L715-4true [2022-10-17 11:09:21,893 INFO L750 eck$LassoCheckResult]: Loop: 139#L715-4true call main_#t~mem5#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4); 116#L715-1true assume !!(main_#t~mem5#1 < 1000);havoc main_#t~mem5#1;call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset; 37#L717true assume main_~user~0#1.base == 0 && main_~user~0#1.offset == 0;assume false; 142#L717-2true call main_#t~mem7#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int(main_#t~mem7#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem7#1;call main_#t~mem8#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem9#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int(main_#t~mem8#1 * main_#t~mem9#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem8#1;havoc main_#t~mem9#1; 127#L722-124true assume !true; 79#L715-3true call main_#t~mem3#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post4#1 := main_#t~mem3#1;call write~int(1 + main_#t~post4#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem3#1;havoc main_#t~post4#1; 139#L715-4true [2022-10-17 11:09:21,900 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:09:21,901 INFO L85 PathProgramCache]: Analyzing trace with hash 1251, now seen corresponding path program 1 times [2022-10-17 11:09:21,912 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:09:21,913 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [624651156] [2022-10-17 11:09:21,914 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:09:21,914 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:09:22,089 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 11:09:22,090 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 11:09:22,142 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 11:09:22,201 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 11:09:22,207 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:09:22,207 INFO L85 PathProgramCache]: Analyzing trace with hash 1336134572, now seen corresponding path program 1 times [2022-10-17 11:09:22,208 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:09:22,208 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [961615673] [2022-10-17 11:09:22,208 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:09:22,209 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:09:22,246 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:09:22,295 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:09:22,297 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [961615673] [2022-10-17 11:09:22,298 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: Unsupported non-linear arithmetic [2022-10-17 11:09:22,299 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [890457173] [2022-10-17 11:09:22,300 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:09:22,300 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 11:09:22,300 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cf4cc610-6584-43c2-a4b2-fc8d2c4ba5ac/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 11:09:22,302 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cf4cc610-6584-43c2-a4b2-fc8d2c4ba5ac/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 11:09:22,321 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cf4cc610-6584-43c2-a4b2-fc8d2c4ba5ac/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2022-10-17 11:09:22,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:09:22,459 INFO L263 TraceCheckSpWp]: Trace formula consists of 74 conjuncts, 1 conjunts are in the unsatisfiable core [2022-10-17 11:09:22,461 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 11:09:22,484 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:09:22,484 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-10-17 11:09:22,487 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [890457173] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:09:22,487 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:09:22,487 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-10-17 11:09:22,488 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1795986484] [2022-10-17 11:09:22,489 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:09:22,494 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 11:09:22,495 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 11:09:22,544 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2022-10-17 11:09:22,545 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2022-10-17 11:09:22,551 INFO L87 Difference]: Start difference. First operand has 183 states, 178 states have (on average 1.6910112359550562) internal successors, (301), 178 states have internal predecessors, (301), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Second operand has 2 states, 2 states have (on average 3.0) internal successors, (6), 2 states have internal predecessors, (6), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:09:22,608 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 11:09:22,610 INFO L93 Difference]: Finished difference Result 182 states and 237 transitions. [2022-10-17 11:09:22,611 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 182 states and 237 transitions. [2022-10-17 11:09:22,625 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 169 [2022-10-17 11:09:22,636 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 182 states to 176 states and 231 transitions. [2022-10-17 11:09:22,638 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 176 [2022-10-17 11:09:22,639 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 176 [2022-10-17 11:09:22,640 INFO L73 IsDeterministic]: Start isDeterministic. Operand 176 states and 231 transitions. [2022-10-17 11:09:22,643 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 11:09:22,644 INFO L218 hiAutomatonCegarLoop]: Abstraction has 176 states and 231 transitions. [2022-10-17 11:09:22,666 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 176 states and 231 transitions. [2022-10-17 11:09:22,694 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 176 to 176. [2022-10-17 11:09:22,697 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 176 states, 172 states have (on average 1.308139534883721) internal successors, (225), 171 states have internal predecessors, (225), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-10-17 11:09:22,698 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 176 states to 176 states and 231 transitions. [2022-10-17 11:09:22,700 INFO L240 hiAutomatonCegarLoop]: Abstraction has 176 states and 231 transitions. [2022-10-17 11:09:22,706 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-10-17 11:09:22,714 INFO L428 stractBuchiCegarLoop]: Abstraction has 176 states and 231 transitions. [2022-10-17 11:09:22,714 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-10-17 11:09:22,714 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 176 states and 231 transitions. [2022-10-17 11:09:22,717 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 169 [2022-10-17 11:09:22,718 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 11:09:22,718 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 11:09:22,721 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-10-17 11:09:22,721 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:09:22,729 INFO L748 eck$LassoCheckResult]: Stem: 563#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2); 495#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem7#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~mem19#1, main_#t~mem18#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~switch22#1, main_#t~mem23#1, main_#t~mem24#1, main_#t~mem25#1, main_#t~mem26#1, main_#t~mem27#1, main_#t~mem28#1, main_#t~mem29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc34#1.base, main_#t~malloc34#1.offset, main_#t~mem35#1.base, main_#t~mem35#1.offset, main_#t~mem36#1.base, main_#t~mem36#1.offset, main_#t~memset~res37#1.base, main_#t~memset~res37#1.offset, main_#t~mem38#1.base, main_#t~mem38#1.offset, main_#t~mem39#1.base, main_#t~mem39#1.offset, main_#t~mem40#1.base, main_#t~mem40#1.offset, main_#t~mem41#1.base, main_#t~mem41#1.offset, main_#t~mem42#1.base, main_#t~mem42#1.offset, main_#t~malloc43#1.base, main_#t~malloc43#1.offset, main_#t~mem44#1.base, main_#t~mem44#1.offset, main_#t~mem45#1.base, main_#t~mem45#1.offset, main_#t~mem46#1.base, main_#t~mem46#1.offset, main_#t~mem47#1.base, main_#t~mem47#1.offset, main_#t~mem48#1.base, main_#t~mem48#1.offset, main_#t~mem49#1.base, main_#t~mem49#1.offset, main_#t~memset~res50#1.base, main_#t~memset~res50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~mem52#1.base, main_#t~mem52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1, main_#t~post61#1, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1, main_#t~post67#1, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem72#1, main_#t~mem71#1, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1, main_#t~short75#1, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1, main_#t~malloc78#1.base, main_#t~malloc78#1.offset, main_#t~mem79#1.base, main_#t~mem79#1.offset, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1, main_#t~memset~res83#1.base, main_#t~memset~res83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem88#1, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem87#1, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem92#1, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1, main_#t~ite93#1, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem104#1, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~pre107#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem116#1, main_#t~mem114#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem115#1, main_#t~mem117#1, main_#t~post118#1, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~post95#1, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem124#1.base, main_#t~mem124#1.offset, main_#t~mem125#1, main_#t~mem126#1.base, main_#t~mem126#1.offset, main_#t~mem127#1, main_#t~post128#1, main_#t~mem129#1.base, main_#t~mem129#1.offset, main_#t~mem130#1.base, main_#t~mem130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem135#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1, main_#t~ite138#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem140#1, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~#_he_new_buckets~0#1.base, main_~#_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem3#1, main_#t~post4#1, main_#t~mem5#1, main_#t~mem146#1, main_#t~mem145#1, main_#t~mem147#1, main_#t~mem148#1, main_#t~mem150#1, main_#t~mem149#1, main_#t~mem151#1, main_#t~mem152#1, main_#t~mem154#1, main_#t~mem153#1, main_#t~mem155#1, main_#t~mem156#1, main_#t~switch157#1, main_#t~mem158#1, main_#t~mem159#1, main_#t~mem160#1, main_#t~mem161#1, main_#t~mem162#1, main_#t~mem163#1, main_#t~mem164#1, main_#t~mem165#1, main_#t~mem166#1, main_#t~mem167#1, main_#t~mem168#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1, main_#t~mem171#1.base, main_#t~mem171#1.offset, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1.base, main_#t~mem175#1.offset, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1.base, main_#t~mem177#1.offset, main_#t~mem178#1, main_#t~mem179#1, main_#t~mem180#1, main_#t~short181#1, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~ret183#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1.base, main_#t~mem185#1.offset, main_#t~mem186#1.base, main_#t~mem186#1.offset, main_#t~mem187#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem188#1.base, main_#t~mem188#1.offset, main_#t~mem189#1.base, main_#t~mem189#1.offset, main_#t~short190#1, main_#t~mem191#1.base, main_#t~mem191#1.offset, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_#t~mem193#1.base, main_#t~mem193#1.offset, main_#t~mem194#1.base, main_#t~mem194#1.offset, main_#t~mem195#1.base, main_#t~mem195#1.offset, main_#t~mem196#1.base, main_#t~mem196#1.offset, main_#t~mem197#1.base, main_#t~mem197#1.offset, main_#t~mem198#1.base, main_#t~mem198#1.offset, main_#t~mem199#1, main_#t~mem200#1.base, main_#t~mem200#1.offset, main_#t~mem201#1.base, main_#t~mem201#1.offset, main_#t~mem202#1.base, main_#t~mem202#1.offset, main_#t~mem203#1, main_#t~mem204#1.base, main_#t~mem204#1.offset, main_#t~mem205#1.base, main_#t~mem205#1.offset, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem213#1, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1, main_#t~mem214#1.base, main_#t~mem214#1.offset, main_#t~mem215#1.base, main_#t~mem215#1.offset, main_#t~mem216#1, main_#t~post217#1, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~mem219#1.base, main_#t~mem219#1.offset, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1.base, main_#t~mem221#1.offset, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~mem225#1.base, main_#t~mem225#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem226#1.base, main_#t~mem226#1.offset, main_#t~mem227#1, main_#t~post228#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem142#1, main_#t~post143#1, main_#t~mem144#1, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4); 496#L715-4 [2022-10-17 11:09:22,738 INFO L750 eck$LassoCheckResult]: Loop: 496#L715-4 call main_#t~mem5#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4); 543#L715-1 assume !!(main_#t~mem5#1 < 1000);havoc main_#t~mem5#1;call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset; 458#L717 assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0); 459#L717-2 call main_#t~mem7#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int(main_#t~mem7#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem7#1;call main_#t~mem8#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem9#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int(main_#t~mem8#1 * main_#t~mem9#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem8#1;havoc main_#t~mem9#1; 551#L722-124 havoc main_~_ha_hashv~0#1; 552#L722-49 goto; 491#L722-47 havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4; 441#L722-8 assume !(main_~_hj_k~0#1 % 4294967296 >= 12); 442#L722-9 main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch22#1 := 11 == main_~_hj_k~0#1; 501#L722-10 assume main_#t~switch22#1;call main_#t~mem23#1 := read~int(main_~_hj_key~0#1.base, 10 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 16777216 * (main_#t~mem23#1 % 256);havoc main_#t~mem23#1; 516#L722-12 main_#t~switch22#1 := main_#t~switch22#1 || 10 == main_~_hj_k~0#1; 475#L722-13 assume main_#t~switch22#1;call main_#t~mem24#1 := read~int(main_~_hj_key~0#1.base, 9 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 65536 * (main_#t~mem24#1 % 256);havoc main_#t~mem24#1; 476#L722-15 main_#t~switch22#1 := main_#t~switch22#1 || 9 == main_~_hj_k~0#1; 509#L722-16 assume main_#t~switch22#1;call main_#t~mem25#1 := read~int(main_~_hj_key~0#1.base, 8 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 256 * (main_#t~mem25#1 % 256);havoc main_#t~mem25#1; 536#L722-18 main_#t~switch22#1 := main_#t~switch22#1 || 8 == main_~_hj_k~0#1; 435#L722-19 assume main_#t~switch22#1;call main_#t~mem26#1 := read~int(main_~_hj_key~0#1.base, 7 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 16777216 * (main_#t~mem26#1 % 256);havoc main_#t~mem26#1; 436#L722-21 main_#t~switch22#1 := main_#t~switch22#1 || 7 == main_~_hj_k~0#1; 542#L722-22 assume !main_#t~switch22#1; 537#L722-24 main_#t~switch22#1 := main_#t~switch22#1 || 6 == main_~_hj_k~0#1; 538#L722-25 assume main_#t~switch22#1;call main_#t~mem28#1 := read~int(main_~_hj_key~0#1.base, 5 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 256 * (main_#t~mem28#1 % 256);havoc main_#t~mem28#1; 467#L722-27 main_#t~switch22#1 := main_#t~switch22#1 || 5 == main_~_hj_k~0#1; 468#L722-28 assume main_#t~switch22#1;call main_#t~mem29#1 := read~int(main_~_hj_key~0#1.base, 4 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + main_#t~mem29#1 % 256;havoc main_#t~mem29#1; 548#L722-30 main_#t~switch22#1 := main_#t~switch22#1 || 4 == main_~_hj_k~0#1; 549#L722-31 assume main_#t~switch22#1;call main_#t~mem30#1 := read~int(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem30#1 % 256);havoc main_#t~mem30#1; 499#L722-33 main_#t~switch22#1 := main_#t~switch22#1 || 3 == main_~_hj_k~0#1; 437#L722-34 assume main_#t~switch22#1;call main_#t~mem31#1 := read~int(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem31#1 % 256);havoc main_#t~mem31#1; 438#L722-36 main_#t~switch22#1 := main_#t~switch22#1 || 2 == main_~_hj_k~0#1; 530#L722-37 assume main_#t~switch22#1;call main_#t~mem32#1 := read~int(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem32#1 % 256);havoc main_#t~mem32#1; 391#L722-39 main_#t~switch22#1 := main_#t~switch22#1 || 1 == main_~_hj_k~0#1; 392#L722-40 assume main_#t~switch22#1;call main_#t~mem33#1 := read~int(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + main_#t~mem33#1 % 256;havoc main_#t~mem33#1; 520#L722-42 havoc main_#t~switch22#1; 521#L722-45 main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if (1 == main_~_hj_i~0#1 || 0 == main_~_hj_i~0#1) && (1 == main_~_ha_hashv~0#1 / 8192 || 0 == main_~_ha_hashv~0#1 / 8192) then (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 8192 then 0 else 1) else (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 8192 else (if 0 == main_~_ha_hashv~0#1 / 8192 then main_~_hj_i~0#1 else ~bitwiseXOr(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8192))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if (1 == main_~_hj_j~0#1 || 0 == main_~_hj_j~0#1) && (1 == 256 * main_~_hj_i~0#1 || 0 == 256 * main_~_hj_i~0#1) then (if main_~_hj_j~0#1 == 256 * main_~_hj_i~0#1 then 0 else 1) else (if 0 == main_~_hj_j~0#1 then 256 * main_~_hj_i~0#1 else (if 0 == 256 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else ~bitwiseXOr(main_~_hj_j~0#1, 256 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if (1 == main_~_ha_hashv~0#1 || 0 == main_~_ha_hashv~0#1) && (1 == main_~_hj_j~0#1 / 8192 || 0 == main_~_hj_j~0#1 / 8192) then (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 8192 then 0 else 1) else (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 8192 else (if 0 == main_~_hj_j~0#1 / 8192 then main_~_ha_hashv~0#1 else ~bitwiseXOr(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 8192))));main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if (1 == main_~_hj_i~0#1 || 0 == main_~_hj_i~0#1) && (1 == main_~_ha_hashv~0#1 / 4096 || 0 == main_~_ha_hashv~0#1 / 4096) then (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 4096 then 0 else 1) else (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 4096 else (if 0 == main_~_ha_hashv~0#1 / 4096 then main_~_hj_i~0#1 else ~bitwiseXOr(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 4096))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if (1 == main_~_hj_j~0#1 || 0 == main_~_hj_j~0#1) && (1 == 65536 * main_~_hj_i~0#1 || 0 == 65536 * main_~_hj_i~0#1) then (if main_~_hj_j~0#1 == 65536 * main_~_hj_i~0#1 then 0 else 1) else (if 0 == main_~_hj_j~0#1 then 65536 * main_~_hj_i~0#1 else (if 0 == 65536 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else ~bitwiseXOr(main_~_hj_j~0#1, 65536 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if (1 == main_~_ha_hashv~0#1 || 0 == main_~_ha_hashv~0#1) && (1 == main_~_hj_j~0#1 / 32 || 0 == main_~_hj_j~0#1 / 32) then (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 32 then 0 else 1) else (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 32 else (if 0 == main_~_hj_j~0#1 / 32 then main_~_ha_hashv~0#1 else ~bitwiseXOr(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32))));main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if (1 == main_~_hj_i~0#1 || 0 == main_~_hj_i~0#1) && (1 == main_~_ha_hashv~0#1 / 8 || 0 == main_~_ha_hashv~0#1 / 8) then (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 8 then 0 else 1) else (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 8 else (if 0 == main_~_ha_hashv~0#1 / 8 then main_~_hj_i~0#1 else ~bitwiseXOr(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if (1 == main_~_hj_j~0#1 || 0 == main_~_hj_j~0#1) && (1 == 1024 * main_~_hj_i~0#1 || 0 == 1024 * main_~_hj_i~0#1) then (if main_~_hj_j~0#1 == 1024 * main_~_hj_i~0#1 then 0 else 1) else (if 0 == main_~_hj_j~0#1 then 1024 * main_~_hj_i~0#1 else (if 0 == 1024 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else ~bitwiseXOr(main_~_hj_j~0#1, 1024 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if (1 == main_~_ha_hashv~0#1 || 0 == main_~_ha_hashv~0#1) && (1 == main_~_hj_j~0#1 / 32768 || 0 == main_~_hj_j~0#1 / 32768) then (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 32768 then 0 else 1) else (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 32768 else (if 0 == main_~_hj_j~0#1 / 32768 then main_~_ha_hashv~0#1 else ~bitwiseXOr(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32768)))); 547#L722-44 goto; 418#L722-46 goto; 419#L722-48 goto; 561#L722-122 call write~int(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4); 560#L722-51 assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem51#1.base, main_#t~mem51#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_#t~mem51#1.base, main_#t~mem51#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem51#1.base, main_#t~mem51#1.offset; 534#L722-67 call write~$Pointer$(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem52#1.base, main_#t~mem52#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem53#1.base, main_#t~mem53#1.offset := read~$Pointer$(main_#t~mem52#1.base, 16 + main_#t~mem52#1.offset, 4);call main_#t~mem54#1.base, main_#t~mem54#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem55#1 := read~int(main_#t~mem54#1.base, 20 + main_#t~mem54#1.offset, 4);call write~$Pointer$(main_#t~mem53#1.base, main_#t~mem53#1.offset - main_#t~mem55#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem52#1.base, main_#t~mem52#1.offset;havoc main_#t~mem53#1.base, main_#t~mem53#1.offset;havoc main_#t~mem54#1.base, main_#t~mem54#1.offset;havoc main_#t~mem55#1;call main_#t~mem56#1.base, main_#t~mem56#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem57#1.base, main_#t~mem57#1.offset := read~$Pointer$(main_#t~mem56#1.base, 16 + main_#t~mem56#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem57#1.base, 8 + main_#t~mem57#1.offset, 4);havoc main_#t~mem56#1.base, main_#t~mem56#1.offset;havoc main_#t~mem57#1.base, main_#t~mem57#1.offset;call main_#t~mem58#1.base, main_#t~mem58#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem58#1.base, 16 + main_#t~mem58#1.offset, 4);havoc main_#t~mem58#1.base, main_#t~mem58#1.offset; 535#L722-66 goto; 503#L722-120 havoc main_~_ha_bkt~0#1;call main_#t~mem59#1.base, main_#t~mem59#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem60#1 := read~int(main_#t~mem59#1.base, 12 + main_#t~mem59#1.offset, 4);main_#t~post61#1 := main_#t~mem60#1;call write~int(1 + main_#t~post61#1, main_#t~mem59#1.base, 12 + main_#t~mem59#1.offset, 4);havoc main_#t~mem59#1.base, main_#t~mem59#1.offset;havoc main_#t~mem60#1;havoc main_#t~post61#1; 492#L722-71 call main_#t~mem62#1.base, main_#t~mem62#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem63#1 := read~int(main_#t~mem62#1.base, 4 + main_#t~mem62#1.offset, 4);main_~_ha_bkt~0#1 := (if 0 == main_~_ha_hashv~0#1 || 0 == main_#t~mem63#1 - 1 then 0 else (if 1 == main_#t~mem63#1 - 1 then (if 1 == main_~_ha_hashv~0#1 || 0 == main_~_ha_hashv~0#1 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 >= 0 then main_~_ha_hashv~0#1 % 2 else ~bitwiseAnd(main_~_ha_hashv~0#1, main_#t~mem63#1 - 1))) else (if 1 == main_~_ha_hashv~0#1 then (if 1 == main_#t~mem63#1 - 1 || 0 == main_#t~mem63#1 - 1 then main_#t~mem63#1 - 1 else (if main_#t~mem63#1 - 1 >= 0 then (main_#t~mem63#1 - 1) % 2 else ~bitwiseAnd(main_~_ha_hashv~0#1, main_#t~mem63#1 - 1))) else ~bitwiseAnd(main_~_ha_hashv~0#1, main_#t~mem63#1 - 1))));havoc main_#t~mem62#1.base, main_#t~mem62#1.offset;havoc main_#t~mem63#1; 493#L722-70 goto; 556#L722-118 call main_#t~mem64#1.base, main_#t~mem64#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem65#1.base, main_#t~mem65#1.offset := read~$Pointer$(main_#t~mem64#1.base, main_#t~mem64#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem65#1.base, main_#t~mem65#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem64#1.base, main_#t~mem64#1.offset;havoc main_#t~mem65#1.base, main_#t~mem65#1.offset;call main_#t~mem66#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post67#1 := main_#t~mem66#1;call write~int(1 + main_#t~post67#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem66#1;havoc main_#t~post67#1;call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_#t~mem68#1.base, main_#t~mem68#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;call write~$Pointer$(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4); 422#L722-73 assume main_#t~mem69#1.base != 0 || main_#t~mem69#1.offset != 0;havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem70#1.base, 12 + main_#t~mem70#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset; 423#L722-75 call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem72#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem71#1 := read~int(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short75#1 := main_#t~mem72#1 % 4294967296 >= 10 * (1 + main_#t~mem71#1) % 4294967296; 512#L722-76 assume main_#t~short75#1;call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem74#1 := read~int(main_#t~mem73#1.base, 36 + main_#t~mem73#1.offset, 4);main_#t~short75#1 := 0 == main_#t~mem74#1 % 4294967296; 388#L722-78 assume !main_#t~short75#1;havoc main_#t~mem72#1;havoc main_#t~mem71#1;havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;havoc main_#t~mem74#1;havoc main_#t~short75#1; 390#L722-117 goto; 486#L722-119 goto; 506#L722-121 goto; 405#L722-123 goto; 406#L715-3 call main_#t~mem3#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post4#1 := main_#t~mem3#1;call write~int(1 + main_#t~post4#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem3#1;havoc main_#t~post4#1; 496#L715-4 [2022-10-17 11:09:22,739 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:09:22,739 INFO L85 PathProgramCache]: Analyzing trace with hash 1251, now seen corresponding path program 2 times [2022-10-17 11:09:22,740 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:09:22,740 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [432015709] [2022-10-17 11:09:22,747 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:09:22,747 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:09:22,785 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 11:09:22,786 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 11:09:22,819 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 11:09:22,831 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 11:09:22,831 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:09:22,832 INFO L85 PathProgramCache]: Analyzing trace with hash -1570577107, now seen corresponding path program 1 times [2022-10-17 11:09:22,833 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:09:22,833 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [890286201] [2022-10-17 11:09:22,834 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:09:22,834 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:09:23,053 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-10-17 11:09:23,054 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [318410055] [2022-10-17 11:09:23,055 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:09:23,055 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 11:09:23,055 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cf4cc610-6584-43c2-a4b2-fc8d2c4ba5ac/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 11:09:23,057 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cf4cc610-6584-43c2-a4b2-fc8d2c4ba5ac/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 11:09:23,081 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cf4cc610-6584-43c2-a4b2-fc8d2c4ba5ac/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2022-10-17 11:09:23,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:09:23,941 INFO L263 TraceCheckSpWp]: Trace formula consists of 1850 conjuncts, 3 conjunts are in the unsatisfiable core [2022-10-17 11:09:23,980 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 11:09:24,049 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:09:24,050 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-10-17 11:09:24,051 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:09:24,051 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [890286201] [2022-10-17 11:09:24,051 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-10-17 11:09:24,052 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [318410055] [2022-10-17 11:09:24,052 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [318410055] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:09:24,052 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:09:24,053 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:09:24,053 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [998850203] [2022-10-17 11:09:24,053 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:09:24,055 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 11:09:24,055 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 11:09:24,057 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 11:09:24,057 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 11:09:24,057 INFO L87 Difference]: Start difference. First operand 176 states and 231 transitions. cyclomatic complexity: 58 Second operand has 3 states, 3 states have (on average 17.333333333333332) internal successors, (52), 3 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:09:24,220 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 11:09:24,220 INFO L93 Difference]: Finished difference Result 197 states and 252 transitions. [2022-10-17 11:09:24,220 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 197 states and 252 transitions. [2022-10-17 11:09:24,223 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 190 [2022-10-17 11:09:24,231 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 197 states to 197 states and 252 transitions. [2022-10-17 11:09:24,232 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 197 [2022-10-17 11:09:24,233 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 197 [2022-10-17 11:09:24,234 INFO L73 IsDeterministic]: Start isDeterministic. Operand 197 states and 252 transitions. [2022-10-17 11:09:24,243 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 11:09:24,243 INFO L218 hiAutomatonCegarLoop]: Abstraction has 197 states and 252 transitions. [2022-10-17 11:09:24,246 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 197 states and 252 transitions. [2022-10-17 11:09:24,259 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 197 to 196. [2022-10-17 11:09:24,264 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 196 states, 192 states have (on average 1.2760416666666667) internal successors, (245), 191 states have internal predecessors, (245), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-10-17 11:09:24,266 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 196 states to 196 states and 251 transitions. [2022-10-17 11:09:24,266 INFO L240 hiAutomatonCegarLoop]: Abstraction has 196 states and 251 transitions. [2022-10-17 11:09:24,267 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 11:09:24,268 INFO L428 stractBuchiCegarLoop]: Abstraction has 196 states and 251 transitions. [2022-10-17 11:09:24,268 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-10-17 11:09:24,269 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 196 states and 251 transitions. [2022-10-17 11:09:24,270 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 189 [2022-10-17 11:09:24,272 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 11:09:24,272 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 11:09:24,278 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-10-17 11:09:24,278 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:09:24,279 INFO L748 eck$LassoCheckResult]: Stem: 1099#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2); 1027#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem7#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~mem19#1, main_#t~mem18#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~switch22#1, main_#t~mem23#1, main_#t~mem24#1, main_#t~mem25#1, main_#t~mem26#1, main_#t~mem27#1, main_#t~mem28#1, main_#t~mem29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc34#1.base, main_#t~malloc34#1.offset, main_#t~mem35#1.base, main_#t~mem35#1.offset, main_#t~mem36#1.base, main_#t~mem36#1.offset, main_#t~memset~res37#1.base, main_#t~memset~res37#1.offset, main_#t~mem38#1.base, main_#t~mem38#1.offset, main_#t~mem39#1.base, main_#t~mem39#1.offset, main_#t~mem40#1.base, main_#t~mem40#1.offset, main_#t~mem41#1.base, main_#t~mem41#1.offset, main_#t~mem42#1.base, main_#t~mem42#1.offset, main_#t~malloc43#1.base, main_#t~malloc43#1.offset, main_#t~mem44#1.base, main_#t~mem44#1.offset, main_#t~mem45#1.base, main_#t~mem45#1.offset, main_#t~mem46#1.base, main_#t~mem46#1.offset, main_#t~mem47#1.base, main_#t~mem47#1.offset, main_#t~mem48#1.base, main_#t~mem48#1.offset, main_#t~mem49#1.base, main_#t~mem49#1.offset, main_#t~memset~res50#1.base, main_#t~memset~res50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~mem52#1.base, main_#t~mem52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1, main_#t~post61#1, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1, main_#t~post67#1, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem72#1, main_#t~mem71#1, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1, main_#t~short75#1, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1, main_#t~malloc78#1.base, main_#t~malloc78#1.offset, main_#t~mem79#1.base, main_#t~mem79#1.offset, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1, main_#t~memset~res83#1.base, main_#t~memset~res83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem88#1, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem87#1, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem92#1, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1, main_#t~ite93#1, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem104#1, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~pre107#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem116#1, main_#t~mem114#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem115#1, main_#t~mem117#1, main_#t~post118#1, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~post95#1, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem124#1.base, main_#t~mem124#1.offset, main_#t~mem125#1, main_#t~mem126#1.base, main_#t~mem126#1.offset, main_#t~mem127#1, main_#t~post128#1, main_#t~mem129#1.base, main_#t~mem129#1.offset, main_#t~mem130#1.base, main_#t~mem130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem135#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1, main_#t~ite138#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem140#1, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~#_he_new_buckets~0#1.base, main_~#_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem3#1, main_#t~post4#1, main_#t~mem5#1, main_#t~mem146#1, main_#t~mem145#1, main_#t~mem147#1, main_#t~mem148#1, main_#t~mem150#1, main_#t~mem149#1, main_#t~mem151#1, main_#t~mem152#1, main_#t~mem154#1, main_#t~mem153#1, main_#t~mem155#1, main_#t~mem156#1, main_#t~switch157#1, main_#t~mem158#1, main_#t~mem159#1, main_#t~mem160#1, main_#t~mem161#1, main_#t~mem162#1, main_#t~mem163#1, main_#t~mem164#1, main_#t~mem165#1, main_#t~mem166#1, main_#t~mem167#1, main_#t~mem168#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1, main_#t~mem171#1.base, main_#t~mem171#1.offset, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1.base, main_#t~mem175#1.offset, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1.base, main_#t~mem177#1.offset, main_#t~mem178#1, main_#t~mem179#1, main_#t~mem180#1, main_#t~short181#1, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~ret183#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1.base, main_#t~mem185#1.offset, main_#t~mem186#1.base, main_#t~mem186#1.offset, main_#t~mem187#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem188#1.base, main_#t~mem188#1.offset, main_#t~mem189#1.base, main_#t~mem189#1.offset, main_#t~short190#1, main_#t~mem191#1.base, main_#t~mem191#1.offset, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_#t~mem193#1.base, main_#t~mem193#1.offset, main_#t~mem194#1.base, main_#t~mem194#1.offset, main_#t~mem195#1.base, main_#t~mem195#1.offset, main_#t~mem196#1.base, main_#t~mem196#1.offset, main_#t~mem197#1.base, main_#t~mem197#1.offset, main_#t~mem198#1.base, main_#t~mem198#1.offset, main_#t~mem199#1, main_#t~mem200#1.base, main_#t~mem200#1.offset, main_#t~mem201#1.base, main_#t~mem201#1.offset, main_#t~mem202#1.base, main_#t~mem202#1.offset, main_#t~mem203#1, main_#t~mem204#1.base, main_#t~mem204#1.offset, main_#t~mem205#1.base, main_#t~mem205#1.offset, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem213#1, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1, main_#t~mem214#1.base, main_#t~mem214#1.offset, main_#t~mem215#1.base, main_#t~mem215#1.offset, main_#t~mem216#1, main_#t~post217#1, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~mem219#1.base, main_#t~mem219#1.offset, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1.base, main_#t~mem221#1.offset, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~mem225#1.base, main_#t~mem225#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem226#1.base, main_#t~mem226#1.offset, main_#t~mem227#1, main_#t~post228#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem142#1, main_#t~post143#1, main_#t~mem144#1, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4); 1028#L715-4 [2022-10-17 11:09:24,279 INFO L750 eck$LassoCheckResult]: Loop: 1028#L715-4 call main_#t~mem5#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4); 1079#L715-1 assume !!(main_#t~mem5#1 < 1000);havoc main_#t~mem5#1;call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset; 990#L717 assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0); 991#L717-2 call main_#t~mem7#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int(main_#t~mem7#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem7#1;call main_#t~mem8#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem9#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int(main_#t~mem8#1 * main_#t~mem9#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem8#1;havoc main_#t~mem9#1; 1087#L722-124 havoc main_~_ha_hashv~0#1; 1088#L722-49 goto; 1021#L722-47 havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4; 969#L722-8 assume !(main_~_hj_k~0#1 % 4294967296 >= 12); 970#L722-9 main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch22#1 := 11 == main_~_hj_k~0#1; 1034#L722-10 assume !main_#t~switch22#1; 1078#L722-12 main_#t~switch22#1 := main_#t~switch22#1 || 10 == main_~_hj_k~0#1; 1101#L722-13 assume main_#t~switch22#1;call main_#t~mem24#1 := read~int(main_~_hj_key~0#1.base, 9 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 65536 * (main_#t~mem24#1 % 256);havoc main_#t~mem24#1; 1000#L722-15 main_#t~switch22#1 := main_#t~switch22#1 || 9 == main_~_hj_k~0#1; 1042#L722-16 assume main_#t~switch22#1;call main_#t~mem25#1 := read~int(main_~_hj_key~0#1.base, 8 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 256 * (main_#t~mem25#1 % 256);havoc main_#t~mem25#1; 1071#L722-18 main_#t~switch22#1 := main_#t~switch22#1 || 8 == main_~_hj_k~0#1; 960#L722-19 assume main_#t~switch22#1;call main_#t~mem26#1 := read~int(main_~_hj_key~0#1.base, 7 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 16777216 * (main_#t~mem26#1 % 256);havoc main_#t~mem26#1; 961#L722-21 main_#t~switch22#1 := main_#t~switch22#1 || 7 == main_~_hj_k~0#1; 1076#L722-22 assume main_#t~switch22#1;call main_#t~mem27#1 := read~int(main_~_hj_key~0#1.base, 6 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 65536 * (main_#t~mem27#1 % 256);havoc main_#t~mem27#1; 1072#L722-24 main_#t~switch22#1 := main_#t~switch22#1 || 6 == main_~_hj_k~0#1; 1073#L722-25 assume main_#t~switch22#1;call main_#t~mem28#1 := read~int(main_~_hj_key~0#1.base, 5 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 256 * (main_#t~mem28#1 % 256);havoc main_#t~mem28#1; 1001#L722-27 main_#t~switch22#1 := main_#t~switch22#1 || 5 == main_~_hj_k~0#1; 1002#L722-28 assume main_#t~switch22#1;call main_#t~mem29#1 := read~int(main_~_hj_key~0#1.base, 4 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + main_#t~mem29#1 % 256;havoc main_#t~mem29#1; 1084#L722-30 main_#t~switch22#1 := main_#t~switch22#1 || 4 == main_~_hj_k~0#1; 1085#L722-31 assume main_#t~switch22#1;call main_#t~mem30#1 := read~int(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem30#1 % 256);havoc main_#t~mem30#1; 1100#L722-33 main_#t~switch22#1 := main_#t~switch22#1 || 3 == main_~_hj_k~0#1; 972#L722-34 assume main_#t~switch22#1;call main_#t~mem31#1 := read~int(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem31#1 % 256);havoc main_#t~mem31#1; 973#L722-36 main_#t~switch22#1 := main_#t~switch22#1 || 2 == main_~_hj_k~0#1; 1064#L722-37 assume main_#t~switch22#1;call main_#t~mem32#1 := read~int(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem32#1 % 256);havoc main_#t~mem32#1; 1065#L722-39 main_#t~switch22#1 := main_#t~switch22#1 || 1 == main_~_hj_k~0#1; 1070#L722-40 assume main_#t~switch22#1;call main_#t~mem33#1 := read~int(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + main_#t~mem33#1 % 256;havoc main_#t~mem33#1; 1055#L722-42 havoc main_#t~switch22#1; 1056#L722-45 main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if (1 == main_~_hj_i~0#1 || 0 == main_~_hj_i~0#1) && (1 == main_~_ha_hashv~0#1 / 8192 || 0 == main_~_ha_hashv~0#1 / 8192) then (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 8192 then 0 else 1) else (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 8192 else (if 0 == main_~_ha_hashv~0#1 / 8192 then main_~_hj_i~0#1 else ~bitwiseXOr(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8192))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if (1 == main_~_hj_j~0#1 || 0 == main_~_hj_j~0#1) && (1 == 256 * main_~_hj_i~0#1 || 0 == 256 * main_~_hj_i~0#1) then (if main_~_hj_j~0#1 == 256 * main_~_hj_i~0#1 then 0 else 1) else (if 0 == main_~_hj_j~0#1 then 256 * main_~_hj_i~0#1 else (if 0 == 256 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else ~bitwiseXOr(main_~_hj_j~0#1, 256 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if (1 == main_~_ha_hashv~0#1 || 0 == main_~_ha_hashv~0#1) && (1 == main_~_hj_j~0#1 / 8192 || 0 == main_~_hj_j~0#1 / 8192) then (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 8192 then 0 else 1) else (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 8192 else (if 0 == main_~_hj_j~0#1 / 8192 then main_~_ha_hashv~0#1 else ~bitwiseXOr(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 8192))));main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if (1 == main_~_hj_i~0#1 || 0 == main_~_hj_i~0#1) && (1 == main_~_ha_hashv~0#1 / 4096 || 0 == main_~_ha_hashv~0#1 / 4096) then (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 4096 then 0 else 1) else (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 4096 else (if 0 == main_~_ha_hashv~0#1 / 4096 then main_~_hj_i~0#1 else ~bitwiseXOr(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 4096))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if (1 == main_~_hj_j~0#1 || 0 == main_~_hj_j~0#1) && (1 == 65536 * main_~_hj_i~0#1 || 0 == 65536 * main_~_hj_i~0#1) then (if main_~_hj_j~0#1 == 65536 * main_~_hj_i~0#1 then 0 else 1) else (if 0 == main_~_hj_j~0#1 then 65536 * main_~_hj_i~0#1 else (if 0 == 65536 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else ~bitwiseXOr(main_~_hj_j~0#1, 65536 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if (1 == main_~_ha_hashv~0#1 || 0 == main_~_ha_hashv~0#1) && (1 == main_~_hj_j~0#1 / 32 || 0 == main_~_hj_j~0#1 / 32) then (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 32 then 0 else 1) else (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 32 else (if 0 == main_~_hj_j~0#1 / 32 then main_~_ha_hashv~0#1 else ~bitwiseXOr(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32))));main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if (1 == main_~_hj_i~0#1 || 0 == main_~_hj_i~0#1) && (1 == main_~_ha_hashv~0#1 / 8 || 0 == main_~_ha_hashv~0#1 / 8) then (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 8 then 0 else 1) else (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 8 else (if 0 == main_~_ha_hashv~0#1 / 8 then main_~_hj_i~0#1 else ~bitwiseXOr(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if (1 == main_~_hj_j~0#1 || 0 == main_~_hj_j~0#1) && (1 == 1024 * main_~_hj_i~0#1 || 0 == 1024 * main_~_hj_i~0#1) then (if main_~_hj_j~0#1 == 1024 * main_~_hj_i~0#1 then 0 else 1) else (if 0 == main_~_hj_j~0#1 then 1024 * main_~_hj_i~0#1 else (if 0 == 1024 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else ~bitwiseXOr(main_~_hj_j~0#1, 1024 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if (1 == main_~_ha_hashv~0#1 || 0 == main_~_ha_hashv~0#1) && (1 == main_~_hj_j~0#1 / 32768 || 0 == main_~_hj_j~0#1 / 32768) then (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 32768 then 0 else 1) else (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 32768 else (if 0 == main_~_hj_j~0#1 / 32768 then main_~_ha_hashv~0#1 else ~bitwiseXOr(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32768)))); 1083#L722-44 goto; 950#L722-46 goto; 951#L722-48 goto; 1097#L722-122 call write~int(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4); 1096#L722-51 assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem51#1.base, main_#t~mem51#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_#t~mem51#1.base, main_#t~mem51#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem51#1.base, main_#t~mem51#1.offset; 1068#L722-67 call write~$Pointer$(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem52#1.base, main_#t~mem52#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem53#1.base, main_#t~mem53#1.offset := read~$Pointer$(main_#t~mem52#1.base, 16 + main_#t~mem52#1.offset, 4);call main_#t~mem54#1.base, main_#t~mem54#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem55#1 := read~int(main_#t~mem54#1.base, 20 + main_#t~mem54#1.offset, 4);call write~$Pointer$(main_#t~mem53#1.base, main_#t~mem53#1.offset - main_#t~mem55#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem52#1.base, main_#t~mem52#1.offset;havoc main_#t~mem53#1.base, main_#t~mem53#1.offset;havoc main_#t~mem54#1.base, main_#t~mem54#1.offset;havoc main_#t~mem55#1;call main_#t~mem56#1.base, main_#t~mem56#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem57#1.base, main_#t~mem57#1.offset := read~$Pointer$(main_#t~mem56#1.base, 16 + main_#t~mem56#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem57#1.base, 8 + main_#t~mem57#1.offset, 4);havoc main_#t~mem56#1.base, main_#t~mem56#1.offset;havoc main_#t~mem57#1.base, main_#t~mem57#1.offset;call main_#t~mem58#1.base, main_#t~mem58#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem58#1.base, 16 + main_#t~mem58#1.offset, 4);havoc main_#t~mem58#1.base, main_#t~mem58#1.offset; 1069#L722-66 goto; 1038#L722-120 havoc main_~_ha_bkt~0#1;call main_#t~mem59#1.base, main_#t~mem59#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem60#1 := read~int(main_#t~mem59#1.base, 12 + main_#t~mem59#1.offset, 4);main_#t~post61#1 := main_#t~mem60#1;call write~int(1 + main_#t~post61#1, main_#t~mem59#1.base, 12 + main_#t~mem59#1.offset, 4);havoc main_#t~mem59#1.base, main_#t~mem59#1.offset;havoc main_#t~mem60#1;havoc main_#t~post61#1; 1024#L722-71 call main_#t~mem62#1.base, main_#t~mem62#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem63#1 := read~int(main_#t~mem62#1.base, 4 + main_#t~mem62#1.offset, 4);main_~_ha_bkt~0#1 := (if 0 == main_~_ha_hashv~0#1 || 0 == main_#t~mem63#1 - 1 then 0 else (if 1 == main_#t~mem63#1 - 1 then (if 1 == main_~_ha_hashv~0#1 || 0 == main_~_ha_hashv~0#1 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 >= 0 then main_~_ha_hashv~0#1 % 2 else ~bitwiseAnd(main_~_ha_hashv~0#1, main_#t~mem63#1 - 1))) else (if 1 == main_~_ha_hashv~0#1 then (if 1 == main_#t~mem63#1 - 1 || 0 == main_#t~mem63#1 - 1 then main_#t~mem63#1 - 1 else (if main_#t~mem63#1 - 1 >= 0 then (main_#t~mem63#1 - 1) % 2 else ~bitwiseAnd(main_~_ha_hashv~0#1, main_#t~mem63#1 - 1))) else ~bitwiseAnd(main_~_ha_hashv~0#1, main_#t~mem63#1 - 1))));havoc main_#t~mem62#1.base, main_#t~mem62#1.offset;havoc main_#t~mem63#1; 1025#L722-70 goto; 1092#L722-118 call main_#t~mem64#1.base, main_#t~mem64#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem65#1.base, main_#t~mem65#1.offset := read~$Pointer$(main_#t~mem64#1.base, main_#t~mem64#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem65#1.base, main_#t~mem65#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem64#1.base, main_#t~mem64#1.offset;havoc main_#t~mem65#1.base, main_#t~mem65#1.offset;call main_#t~mem66#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post67#1 := main_#t~mem66#1;call write~int(1 + main_#t~post67#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem66#1;havoc main_#t~post67#1;call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_#t~mem68#1.base, main_#t~mem68#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;call write~$Pointer$(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4); 954#L722-73 assume main_#t~mem69#1.base != 0 || main_#t~mem69#1.offset != 0;havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem70#1.base, 12 + main_#t~mem70#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset; 955#L722-75 call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem72#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem71#1 := read~int(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short75#1 := main_#t~mem72#1 % 4294967296 >= 10 * (1 + main_#t~mem71#1) % 4294967296; 1045#L722-76 assume main_#t~short75#1;call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem74#1 := read~int(main_#t~mem73#1.base, 36 + main_#t~mem73#1.offset, 4);main_#t~short75#1 := 0 == main_#t~mem74#1 % 4294967296; 920#L722-78 assume !main_#t~short75#1;havoc main_#t~mem72#1;havoc main_#t~mem71#1;havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;havoc main_#t~mem74#1;havoc main_#t~short75#1; 922#L722-117 goto; 1018#L722-119 goto; 1039#L722-121 goto; 939#L722-123 goto; 940#L715-3 call main_#t~mem3#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post4#1 := main_#t~mem3#1;call write~int(1 + main_#t~post4#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem3#1;havoc main_#t~post4#1; 1028#L715-4 [2022-10-17 11:09:24,280 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:09:24,280 INFO L85 PathProgramCache]: Analyzing trace with hash 1251, now seen corresponding path program 3 times [2022-10-17 11:09:24,280 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:09:24,280 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1388098943] [2022-10-17 11:09:24,281 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:09:24,281 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:09:24,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 11:09:24,303 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 11:09:24,314 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 11:09:24,330 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 11:09:24,330 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:09:24,330 INFO L85 PathProgramCache]: Analyzing trace with hash -1623964883, now seen corresponding path program 1 times [2022-10-17 11:09:24,331 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:09:24,331 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1381768120] [2022-10-17 11:09:24,331 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:09:24,331 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:09:24,489 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-10-17 11:09:24,490 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [2076939394] [2022-10-17 11:09:24,490 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:09:24,490 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 11:09:24,491 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cf4cc610-6584-43c2-a4b2-fc8d2c4ba5ac/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 11:09:24,535 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cf4cc610-6584-43c2-a4b2-fc8d2c4ba5ac/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 11:09:24,558 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cf4cc610-6584-43c2-a4b2-fc8d2c4ba5ac/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2022-10-17 11:09:25,522 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:09:25,534 INFO L263 TraceCheckSpWp]: Trace formula consists of 1850 conjuncts, 4 conjunts are in the unsatisfiable core [2022-10-17 11:09:25,539 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 11:09:25,582 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:09:25,582 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-10-17 11:09:25,582 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:09:25,582 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1381768120] [2022-10-17 11:09:25,583 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-10-17 11:09:25,583 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2076939394] [2022-10-17 11:09:25,583 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2076939394] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:09:25,583 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:09:25,583 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-10-17 11:09:25,584 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1083753879] [2022-10-17 11:09:25,584 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:09:25,584 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 11:09:25,585 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 11:09:25,585 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-10-17 11:09:25,585 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-10-17 11:09:25,586 INFO L87 Difference]: Start difference. First operand 196 states and 251 transitions. cyclomatic complexity: 58 Second operand has 5 states, 5 states have (on average 10.4) internal successors, (52), 5 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:09:25,714 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 11:09:25,714 INFO L93 Difference]: Finished difference Result 271 states and 347 transitions. [2022-10-17 11:09:25,714 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 271 states and 347 transitions. [2022-10-17 11:09:25,717 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 256 [2022-10-17 11:09:25,720 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 271 states to 271 states and 347 transitions. [2022-10-17 11:09:25,721 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 271 [2022-10-17 11:09:25,721 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 271 [2022-10-17 11:09:25,721 INFO L73 IsDeterministic]: Start isDeterministic. Operand 271 states and 347 transitions. [2022-10-17 11:09:25,722 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 11:09:25,722 INFO L218 hiAutomatonCegarLoop]: Abstraction has 271 states and 347 transitions. [2022-10-17 11:09:25,723 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 271 states and 347 transitions. [2022-10-17 11:09:25,731 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 271 to 182. [2022-10-17 11:09:25,732 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 182 states, 178 states have (on average 1.2584269662921348) internal successors, (224), 177 states have internal predecessors, (224), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-10-17 11:09:25,733 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 182 states to 182 states and 230 transitions. [2022-10-17 11:09:25,733 INFO L240 hiAutomatonCegarLoop]: Abstraction has 182 states and 230 transitions. [2022-10-17 11:09:25,734 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-10-17 11:09:25,735 INFO L428 stractBuchiCegarLoop]: Abstraction has 182 states and 230 transitions. [2022-10-17 11:09:25,735 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-10-17 11:09:25,735 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 182 states and 230 transitions. [2022-10-17 11:09:25,736 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 175 [2022-10-17 11:09:25,736 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 11:09:25,737 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 11:09:25,737 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-10-17 11:09:25,738 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:09:25,738 INFO L748 eck$LassoCheckResult]: Stem: 1726#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2); 1655#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem7#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~mem19#1, main_#t~mem18#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~switch22#1, main_#t~mem23#1, main_#t~mem24#1, main_#t~mem25#1, main_#t~mem26#1, main_#t~mem27#1, main_#t~mem28#1, main_#t~mem29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc34#1.base, main_#t~malloc34#1.offset, main_#t~mem35#1.base, main_#t~mem35#1.offset, main_#t~mem36#1.base, main_#t~mem36#1.offset, main_#t~memset~res37#1.base, main_#t~memset~res37#1.offset, main_#t~mem38#1.base, main_#t~mem38#1.offset, main_#t~mem39#1.base, main_#t~mem39#1.offset, main_#t~mem40#1.base, main_#t~mem40#1.offset, main_#t~mem41#1.base, main_#t~mem41#1.offset, main_#t~mem42#1.base, main_#t~mem42#1.offset, main_#t~malloc43#1.base, main_#t~malloc43#1.offset, main_#t~mem44#1.base, main_#t~mem44#1.offset, main_#t~mem45#1.base, main_#t~mem45#1.offset, main_#t~mem46#1.base, main_#t~mem46#1.offset, main_#t~mem47#1.base, main_#t~mem47#1.offset, main_#t~mem48#1.base, main_#t~mem48#1.offset, main_#t~mem49#1.base, main_#t~mem49#1.offset, main_#t~memset~res50#1.base, main_#t~memset~res50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~mem52#1.base, main_#t~mem52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1, main_#t~post61#1, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1, main_#t~post67#1, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem72#1, main_#t~mem71#1, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1, main_#t~short75#1, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1, main_#t~malloc78#1.base, main_#t~malloc78#1.offset, main_#t~mem79#1.base, main_#t~mem79#1.offset, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1, main_#t~memset~res83#1.base, main_#t~memset~res83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem88#1, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem87#1, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem92#1, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1, main_#t~ite93#1, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem104#1, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~pre107#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem116#1, main_#t~mem114#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem115#1, main_#t~mem117#1, main_#t~post118#1, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~post95#1, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem124#1.base, main_#t~mem124#1.offset, main_#t~mem125#1, main_#t~mem126#1.base, main_#t~mem126#1.offset, main_#t~mem127#1, main_#t~post128#1, main_#t~mem129#1.base, main_#t~mem129#1.offset, main_#t~mem130#1.base, main_#t~mem130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem135#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1, main_#t~ite138#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem140#1, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~#_he_new_buckets~0#1.base, main_~#_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem3#1, main_#t~post4#1, main_#t~mem5#1, main_#t~mem146#1, main_#t~mem145#1, main_#t~mem147#1, main_#t~mem148#1, main_#t~mem150#1, main_#t~mem149#1, main_#t~mem151#1, main_#t~mem152#1, main_#t~mem154#1, main_#t~mem153#1, main_#t~mem155#1, main_#t~mem156#1, main_#t~switch157#1, main_#t~mem158#1, main_#t~mem159#1, main_#t~mem160#1, main_#t~mem161#1, main_#t~mem162#1, main_#t~mem163#1, main_#t~mem164#1, main_#t~mem165#1, main_#t~mem166#1, main_#t~mem167#1, main_#t~mem168#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1, main_#t~mem171#1.base, main_#t~mem171#1.offset, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1.base, main_#t~mem175#1.offset, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1.base, main_#t~mem177#1.offset, main_#t~mem178#1, main_#t~mem179#1, main_#t~mem180#1, main_#t~short181#1, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~ret183#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1.base, main_#t~mem185#1.offset, main_#t~mem186#1.base, main_#t~mem186#1.offset, main_#t~mem187#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem188#1.base, main_#t~mem188#1.offset, main_#t~mem189#1.base, main_#t~mem189#1.offset, main_#t~short190#1, main_#t~mem191#1.base, main_#t~mem191#1.offset, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_#t~mem193#1.base, main_#t~mem193#1.offset, main_#t~mem194#1.base, main_#t~mem194#1.offset, main_#t~mem195#1.base, main_#t~mem195#1.offset, main_#t~mem196#1.base, main_#t~mem196#1.offset, main_#t~mem197#1.base, main_#t~mem197#1.offset, main_#t~mem198#1.base, main_#t~mem198#1.offset, main_#t~mem199#1, main_#t~mem200#1.base, main_#t~mem200#1.offset, main_#t~mem201#1.base, main_#t~mem201#1.offset, main_#t~mem202#1.base, main_#t~mem202#1.offset, main_#t~mem203#1, main_#t~mem204#1.base, main_#t~mem204#1.offset, main_#t~mem205#1.base, main_#t~mem205#1.offset, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem213#1, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1, main_#t~mem214#1.base, main_#t~mem214#1.offset, main_#t~mem215#1.base, main_#t~mem215#1.offset, main_#t~mem216#1, main_#t~post217#1, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~mem219#1.base, main_#t~mem219#1.offset, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1.base, main_#t~mem221#1.offset, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~mem225#1.base, main_#t~mem225#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem226#1.base, main_#t~mem226#1.offset, main_#t~mem227#1, main_#t~post228#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem142#1, main_#t~post143#1, main_#t~mem144#1, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4); 1656#L715-4 [2022-10-17 11:09:25,738 INFO L750 eck$LassoCheckResult]: Loop: 1656#L715-4 call main_#t~mem5#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4); 1704#L715-1 assume !!(main_#t~mem5#1 < 1000);havoc main_#t~mem5#1;call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset; 1618#L717 assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0); 1619#L717-2 call main_#t~mem7#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int(main_#t~mem7#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem7#1;call main_#t~mem8#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem9#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int(main_#t~mem8#1 * main_#t~mem9#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem8#1;havoc main_#t~mem9#1; 1712#L722-124 havoc main_~_ha_hashv~0#1; 1713#L722-49 goto; 1649#L722-47 havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4; 1597#L722-8 assume !(main_~_hj_k~0#1 % 4294967296 >= 12); 1598#L722-9 main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch22#1 := 11 == main_~_hj_k~0#1; 1662#L722-10 assume !main_#t~switch22#1; 1677#L722-12 main_#t~switch22#1 := main_#t~switch22#1 || 10 == main_~_hj_k~0#1; 1627#L722-13 assume !main_#t~switch22#1; 1628#L722-15 main_#t~switch22#1 := main_#t~switch22#1 || 9 == main_~_hj_k~0#1; 1670#L722-16 assume !main_#t~switch22#1; 1697#L722-18 main_#t~switch22#1 := main_#t~switch22#1 || 8 == main_~_hj_k~0#1; 1588#L722-19 assume !main_#t~switch22#1; 1589#L722-21 main_#t~switch22#1 := main_#t~switch22#1 || 7 == main_~_hj_k~0#1; 1702#L722-22 assume !main_#t~switch22#1; 1698#L722-24 main_#t~switch22#1 := main_#t~switch22#1 || 6 == main_~_hj_k~0#1; 1699#L722-25 assume !main_#t~switch22#1; 1629#L722-27 main_#t~switch22#1 := main_#t~switch22#1 || 5 == main_~_hj_k~0#1; 1630#L722-28 assume !main_#t~switch22#1; 1709#L722-30 main_#t~switch22#1 := main_#t~switch22#1 || 4 == main_~_hj_k~0#1; 1710#L722-31 assume !main_#t~switch22#1; 1659#L722-33 main_#t~switch22#1 := main_#t~switch22#1 || 3 == main_~_hj_k~0#1; 1660#L722-34 assume main_#t~switch22#1;call main_#t~mem31#1 := read~int(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem31#1 % 256);havoc main_#t~mem31#1; 1601#L722-36 main_#t~switch22#1 := main_#t~switch22#1 || 2 == main_~_hj_k~0#1; 1692#L722-37 assume main_#t~switch22#1;call main_#t~mem32#1 := read~int(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem32#1 % 256);havoc main_#t~mem32#1; 1551#L722-39 main_#t~switch22#1 := main_#t~switch22#1 || 1 == main_~_hj_k~0#1; 1552#L722-40 assume main_#t~switch22#1;call main_#t~mem33#1 := read~int(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + main_#t~mem33#1 % 256;havoc main_#t~mem33#1; 1683#L722-42 havoc main_#t~switch22#1; 1684#L722-45 main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if (1 == main_~_hj_i~0#1 || 0 == main_~_hj_i~0#1) && (1 == main_~_ha_hashv~0#1 / 8192 || 0 == main_~_ha_hashv~0#1 / 8192) then (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 8192 then 0 else 1) else (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 8192 else (if 0 == main_~_ha_hashv~0#1 / 8192 then main_~_hj_i~0#1 else ~bitwiseXOr(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8192))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if (1 == main_~_hj_j~0#1 || 0 == main_~_hj_j~0#1) && (1 == 256 * main_~_hj_i~0#1 || 0 == 256 * main_~_hj_i~0#1) then (if main_~_hj_j~0#1 == 256 * main_~_hj_i~0#1 then 0 else 1) else (if 0 == main_~_hj_j~0#1 then 256 * main_~_hj_i~0#1 else (if 0 == 256 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else ~bitwiseXOr(main_~_hj_j~0#1, 256 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if (1 == main_~_ha_hashv~0#1 || 0 == main_~_ha_hashv~0#1) && (1 == main_~_hj_j~0#1 / 8192 || 0 == main_~_hj_j~0#1 / 8192) then (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 8192 then 0 else 1) else (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 8192 else (if 0 == main_~_hj_j~0#1 / 8192 then main_~_ha_hashv~0#1 else ~bitwiseXOr(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 8192))));main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if (1 == main_~_hj_i~0#1 || 0 == main_~_hj_i~0#1) && (1 == main_~_ha_hashv~0#1 / 4096 || 0 == main_~_ha_hashv~0#1 / 4096) then (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 4096 then 0 else 1) else (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 4096 else (if 0 == main_~_ha_hashv~0#1 / 4096 then main_~_hj_i~0#1 else ~bitwiseXOr(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 4096))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if (1 == main_~_hj_j~0#1 || 0 == main_~_hj_j~0#1) && (1 == 65536 * main_~_hj_i~0#1 || 0 == 65536 * main_~_hj_i~0#1) then (if main_~_hj_j~0#1 == 65536 * main_~_hj_i~0#1 then 0 else 1) else (if 0 == main_~_hj_j~0#1 then 65536 * main_~_hj_i~0#1 else (if 0 == 65536 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else ~bitwiseXOr(main_~_hj_j~0#1, 65536 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if (1 == main_~_ha_hashv~0#1 || 0 == main_~_ha_hashv~0#1) && (1 == main_~_hj_j~0#1 / 32 || 0 == main_~_hj_j~0#1 / 32) then (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 32 then 0 else 1) else (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 32 else (if 0 == main_~_hj_j~0#1 / 32 then main_~_ha_hashv~0#1 else ~bitwiseXOr(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32))));main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if (1 == main_~_hj_i~0#1 || 0 == main_~_hj_i~0#1) && (1 == main_~_ha_hashv~0#1 / 8 || 0 == main_~_ha_hashv~0#1 / 8) then (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 8 then 0 else 1) else (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 8 else (if 0 == main_~_ha_hashv~0#1 / 8 then main_~_hj_i~0#1 else ~bitwiseXOr(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if (1 == main_~_hj_j~0#1 || 0 == main_~_hj_j~0#1) && (1 == 1024 * main_~_hj_i~0#1 || 0 == 1024 * main_~_hj_i~0#1) then (if main_~_hj_j~0#1 == 1024 * main_~_hj_i~0#1 then 0 else 1) else (if 0 == main_~_hj_j~0#1 then 1024 * main_~_hj_i~0#1 else (if 0 == 1024 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else ~bitwiseXOr(main_~_hj_j~0#1, 1024 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if (1 == main_~_ha_hashv~0#1 || 0 == main_~_ha_hashv~0#1) && (1 == main_~_hj_j~0#1 / 32768 || 0 == main_~_hj_j~0#1 / 32768) then (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 32768 then 0 else 1) else (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 32768 else (if 0 == main_~_hj_j~0#1 / 32768 then main_~_ha_hashv~0#1 else ~bitwiseXOr(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32768)))); 1708#L722-44 goto; 1578#L722-46 goto; 1579#L722-48 goto; 1724#L722-122 call write~int(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4); 1723#L722-51 assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem51#1.base, main_#t~mem51#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_#t~mem51#1.base, main_#t~mem51#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem51#1.base, main_#t~mem51#1.offset; 1695#L722-67 call write~$Pointer$(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem52#1.base, main_#t~mem52#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem53#1.base, main_#t~mem53#1.offset := read~$Pointer$(main_#t~mem52#1.base, 16 + main_#t~mem52#1.offset, 4);call main_#t~mem54#1.base, main_#t~mem54#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem55#1 := read~int(main_#t~mem54#1.base, 20 + main_#t~mem54#1.offset, 4);call write~$Pointer$(main_#t~mem53#1.base, main_#t~mem53#1.offset - main_#t~mem55#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem52#1.base, main_#t~mem52#1.offset;havoc main_#t~mem53#1.base, main_#t~mem53#1.offset;havoc main_#t~mem54#1.base, main_#t~mem54#1.offset;havoc main_#t~mem55#1;call main_#t~mem56#1.base, main_#t~mem56#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem57#1.base, main_#t~mem57#1.offset := read~$Pointer$(main_#t~mem56#1.base, 16 + main_#t~mem56#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem57#1.base, 8 + main_#t~mem57#1.offset, 4);havoc main_#t~mem56#1.base, main_#t~mem56#1.offset;havoc main_#t~mem57#1.base, main_#t~mem57#1.offset;call main_#t~mem58#1.base, main_#t~mem58#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem58#1.base, 16 + main_#t~mem58#1.offset, 4);havoc main_#t~mem58#1.base, main_#t~mem58#1.offset; 1696#L722-66 goto; 1666#L722-120 havoc main_~_ha_bkt~0#1;call main_#t~mem59#1.base, main_#t~mem59#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem60#1 := read~int(main_#t~mem59#1.base, 12 + main_#t~mem59#1.offset, 4);main_#t~post61#1 := main_#t~mem60#1;call write~int(1 + main_#t~post61#1, main_#t~mem59#1.base, 12 + main_#t~mem59#1.offset, 4);havoc main_#t~mem59#1.base, main_#t~mem59#1.offset;havoc main_#t~mem60#1;havoc main_#t~post61#1; 1652#L722-71 call main_#t~mem62#1.base, main_#t~mem62#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem63#1 := read~int(main_#t~mem62#1.base, 4 + main_#t~mem62#1.offset, 4);main_~_ha_bkt~0#1 := (if 0 == main_~_ha_hashv~0#1 || 0 == main_#t~mem63#1 - 1 then 0 else (if 1 == main_#t~mem63#1 - 1 then (if 1 == main_~_ha_hashv~0#1 || 0 == main_~_ha_hashv~0#1 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 >= 0 then main_~_ha_hashv~0#1 % 2 else ~bitwiseAnd(main_~_ha_hashv~0#1, main_#t~mem63#1 - 1))) else (if 1 == main_~_ha_hashv~0#1 then (if 1 == main_#t~mem63#1 - 1 || 0 == main_#t~mem63#1 - 1 then main_#t~mem63#1 - 1 else (if main_#t~mem63#1 - 1 >= 0 then (main_#t~mem63#1 - 1) % 2 else ~bitwiseAnd(main_~_ha_hashv~0#1, main_#t~mem63#1 - 1))) else ~bitwiseAnd(main_~_ha_hashv~0#1, main_#t~mem63#1 - 1))));havoc main_#t~mem62#1.base, main_#t~mem62#1.offset;havoc main_#t~mem63#1; 1653#L722-70 goto; 1719#L722-118 call main_#t~mem64#1.base, main_#t~mem64#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem65#1.base, main_#t~mem65#1.offset := read~$Pointer$(main_#t~mem64#1.base, main_#t~mem64#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem65#1.base, main_#t~mem65#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem64#1.base, main_#t~mem64#1.offset;havoc main_#t~mem65#1.base, main_#t~mem65#1.offset;call main_#t~mem66#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post67#1 := main_#t~mem66#1;call write~int(1 + main_#t~post67#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem66#1;havoc main_#t~post67#1;call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_#t~mem68#1.base, main_#t~mem68#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;call write~$Pointer$(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4); 1582#L722-73 assume main_#t~mem69#1.base != 0 || main_#t~mem69#1.offset != 0;havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem70#1.base, 12 + main_#t~mem70#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset; 1583#L722-75 call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem72#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem71#1 := read~int(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short75#1 := main_#t~mem72#1 % 4294967296 >= 10 * (1 + main_#t~mem71#1) % 4294967296; 1673#L722-76 assume main_#t~short75#1;call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem74#1 := read~int(main_#t~mem73#1.base, 36 + main_#t~mem73#1.offset, 4);main_#t~short75#1 := 0 == main_#t~mem74#1 % 4294967296; 1548#L722-78 assume !main_#t~short75#1;havoc main_#t~mem72#1;havoc main_#t~mem71#1;havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;havoc main_#t~mem74#1;havoc main_#t~short75#1; 1550#L722-117 goto; 1646#L722-119 goto; 1667#L722-121 goto; 1567#L722-123 goto; 1568#L715-3 call main_#t~mem3#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post4#1 := main_#t~mem3#1;call write~int(1 + main_#t~post4#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem3#1;havoc main_#t~post4#1; 1656#L715-4 [2022-10-17 11:09:25,739 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:09:25,739 INFO L85 PathProgramCache]: Analyzing trace with hash 1251, now seen corresponding path program 4 times [2022-10-17 11:09:25,739 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:09:25,740 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [815438482] [2022-10-17 11:09:25,740 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:09:25,740 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:09:25,760 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 11:09:25,761 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 11:09:25,770 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 11:09:25,783 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 11:09:25,783 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:09:25,784 INFO L85 PathProgramCache]: Analyzing trace with hash -1214742597, now seen corresponding path program 1 times [2022-10-17 11:09:25,784 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:09:25,784 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [577660337] [2022-10-17 11:09:25,784 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:09:25,785 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:09:25,962 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-10-17 11:09:25,962 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [2114295920] [2022-10-17 11:09:25,962 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:09:25,963 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 11:09:25,963 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cf4cc610-6584-43c2-a4b2-fc8d2c4ba5ac/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 11:09:25,965 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cf4cc610-6584-43c2-a4b2-fc8d2c4ba5ac/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 11:09:25,989 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cf4cc610-6584-43c2-a4b2-fc8d2c4ba5ac/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2022-10-17 11:09:26,941 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:09:26,952 INFO L263 TraceCheckSpWp]: Trace formula consists of 1808 conjuncts, 4 conjunts are in the unsatisfiable core [2022-10-17 11:09:26,956 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 11:09:27,017 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:09:27,017 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-10-17 11:09:27,018 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:09:27,018 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [577660337] [2022-10-17 11:09:27,018 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-10-17 11:09:27,018 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2114295920] [2022-10-17 11:09:27,019 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2114295920] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:09:27,019 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:09:27,019 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-10-17 11:09:27,019 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [178405072] [2022-10-17 11:09:27,019 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:09:27,020 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 11:09:27,020 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 11:09:27,021 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-10-17 11:09:27,021 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-10-17 11:09:27,021 INFO L87 Difference]: Start difference. First operand 182 states and 230 transitions. cyclomatic complexity: 51 Second operand has 5 states, 5 states have (on average 10.4) internal successors, (52), 5 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:09:27,210 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 11:09:27,211 INFO L93 Difference]: Finished difference Result 359 states and 452 transitions. [2022-10-17 11:09:27,211 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 359 states and 452 transitions. [2022-10-17 11:09:27,215 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 351 [2022-10-17 11:09:27,219 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 359 states to 359 states and 452 transitions. [2022-10-17 11:09:27,224 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 359 [2022-10-17 11:09:27,225 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 359 [2022-10-17 11:09:27,225 INFO L73 IsDeterministic]: Start isDeterministic. Operand 359 states and 452 transitions. [2022-10-17 11:09:27,226 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 11:09:27,226 INFO L218 hiAutomatonCegarLoop]: Abstraction has 359 states and 452 transitions. [2022-10-17 11:09:27,227 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 359 states and 452 transitions. [2022-10-17 11:09:27,235 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 359 to 205. [2022-10-17 11:09:27,246 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 205 states, 201 states have (on average 1.2388059701492538) internal successors, (249), 200 states have internal predecessors, (249), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-10-17 11:09:27,248 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 205 states to 205 states and 255 transitions. [2022-10-17 11:09:27,248 INFO L240 hiAutomatonCegarLoop]: Abstraction has 205 states and 255 transitions. [2022-10-17 11:09:27,262 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-10-17 11:09:27,262 INFO L428 stractBuchiCegarLoop]: Abstraction has 205 states and 255 transitions. [2022-10-17 11:09:27,263 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-10-17 11:09:27,263 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 205 states and 255 transitions. [2022-10-17 11:09:27,264 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 198 [2022-10-17 11:09:27,264 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 11:09:27,265 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 11:09:27,265 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-10-17 11:09:27,266 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:09:27,266 INFO L748 eck$LassoCheckResult]: Stem: 2440#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2); 2357#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem7#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~mem19#1, main_#t~mem18#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~switch22#1, main_#t~mem23#1, main_#t~mem24#1, main_#t~mem25#1, main_#t~mem26#1, main_#t~mem27#1, main_#t~mem28#1, main_#t~mem29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc34#1.base, main_#t~malloc34#1.offset, main_#t~mem35#1.base, main_#t~mem35#1.offset, main_#t~mem36#1.base, main_#t~mem36#1.offset, main_#t~memset~res37#1.base, main_#t~memset~res37#1.offset, main_#t~mem38#1.base, main_#t~mem38#1.offset, main_#t~mem39#1.base, main_#t~mem39#1.offset, main_#t~mem40#1.base, main_#t~mem40#1.offset, main_#t~mem41#1.base, main_#t~mem41#1.offset, main_#t~mem42#1.base, main_#t~mem42#1.offset, main_#t~malloc43#1.base, main_#t~malloc43#1.offset, main_#t~mem44#1.base, main_#t~mem44#1.offset, main_#t~mem45#1.base, main_#t~mem45#1.offset, main_#t~mem46#1.base, main_#t~mem46#1.offset, main_#t~mem47#1.base, main_#t~mem47#1.offset, main_#t~mem48#1.base, main_#t~mem48#1.offset, main_#t~mem49#1.base, main_#t~mem49#1.offset, main_#t~memset~res50#1.base, main_#t~memset~res50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~mem52#1.base, main_#t~mem52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1, main_#t~post61#1, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1, main_#t~post67#1, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem72#1, main_#t~mem71#1, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1, main_#t~short75#1, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1, main_#t~malloc78#1.base, main_#t~malloc78#1.offset, main_#t~mem79#1.base, main_#t~mem79#1.offset, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1, main_#t~memset~res83#1.base, main_#t~memset~res83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem88#1, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem87#1, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem92#1, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1, main_#t~ite93#1, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem104#1, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~pre107#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem116#1, main_#t~mem114#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem115#1, main_#t~mem117#1, main_#t~post118#1, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~post95#1, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem124#1.base, main_#t~mem124#1.offset, main_#t~mem125#1, main_#t~mem126#1.base, main_#t~mem126#1.offset, main_#t~mem127#1, main_#t~post128#1, main_#t~mem129#1.base, main_#t~mem129#1.offset, main_#t~mem130#1.base, main_#t~mem130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem135#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1, main_#t~ite138#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem140#1, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~#_he_new_buckets~0#1.base, main_~#_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem3#1, main_#t~post4#1, main_#t~mem5#1, main_#t~mem146#1, main_#t~mem145#1, main_#t~mem147#1, main_#t~mem148#1, main_#t~mem150#1, main_#t~mem149#1, main_#t~mem151#1, main_#t~mem152#1, main_#t~mem154#1, main_#t~mem153#1, main_#t~mem155#1, main_#t~mem156#1, main_#t~switch157#1, main_#t~mem158#1, main_#t~mem159#1, main_#t~mem160#1, main_#t~mem161#1, main_#t~mem162#1, main_#t~mem163#1, main_#t~mem164#1, main_#t~mem165#1, main_#t~mem166#1, main_#t~mem167#1, main_#t~mem168#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1, main_#t~mem171#1.base, main_#t~mem171#1.offset, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1.base, main_#t~mem175#1.offset, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1.base, main_#t~mem177#1.offset, main_#t~mem178#1, main_#t~mem179#1, main_#t~mem180#1, main_#t~short181#1, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~ret183#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1.base, main_#t~mem185#1.offset, main_#t~mem186#1.base, main_#t~mem186#1.offset, main_#t~mem187#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem188#1.base, main_#t~mem188#1.offset, main_#t~mem189#1.base, main_#t~mem189#1.offset, main_#t~short190#1, main_#t~mem191#1.base, main_#t~mem191#1.offset, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_#t~mem193#1.base, main_#t~mem193#1.offset, main_#t~mem194#1.base, main_#t~mem194#1.offset, main_#t~mem195#1.base, main_#t~mem195#1.offset, main_#t~mem196#1.base, main_#t~mem196#1.offset, main_#t~mem197#1.base, main_#t~mem197#1.offset, main_#t~mem198#1.base, main_#t~mem198#1.offset, main_#t~mem199#1, main_#t~mem200#1.base, main_#t~mem200#1.offset, main_#t~mem201#1.base, main_#t~mem201#1.offset, main_#t~mem202#1.base, main_#t~mem202#1.offset, main_#t~mem203#1, main_#t~mem204#1.base, main_#t~mem204#1.offset, main_#t~mem205#1.base, main_#t~mem205#1.offset, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem213#1, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1, main_#t~mem214#1.base, main_#t~mem214#1.offset, main_#t~mem215#1.base, main_#t~mem215#1.offset, main_#t~mem216#1, main_#t~post217#1, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~mem219#1.base, main_#t~mem219#1.offset, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1.base, main_#t~mem221#1.offset, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~mem225#1.base, main_#t~mem225#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem226#1.base, main_#t~mem226#1.offset, main_#t~mem227#1, main_#t~post228#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem142#1, main_#t~post143#1, main_#t~mem144#1, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4); 2358#L715-4 [2022-10-17 11:09:27,266 INFO L750 eck$LassoCheckResult]: Loop: 2358#L715-4 call main_#t~mem5#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4); 2415#L715-1 assume !!(main_#t~mem5#1 < 1000);havoc main_#t~mem5#1;call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset; 2320#L717 assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0); 2321#L717-2 call main_#t~mem7#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int(main_#t~mem7#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem7#1;call main_#t~mem8#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem9#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int(main_#t~mem8#1 * main_#t~mem9#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem8#1;havoc main_#t~mem9#1; 2423#L722-124 havoc main_~_ha_hashv~0#1; 2424#L722-49 goto; 2352#L722-47 havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4; 2301#L722-8 assume !(main_~_hj_k~0#1 % 4294967296 >= 12); 2302#L722-9 main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch22#1 := 11 == main_~_hj_k~0#1; 2413#L722-10 assume !main_#t~switch22#1; 2414#L722-12 main_#t~switch22#1 := main_#t~switch22#1 || 10 == main_~_hj_k~0#1; 2333#L722-13 assume !main_#t~switch22#1; 2334#L722-15 main_#t~switch22#1 := main_#t~switch22#1 || 9 == main_~_hj_k~0#1; 2402#L722-16 assume !main_#t~switch22#1; 2403#L722-18 main_#t~switch22#1 := main_#t~switch22#1 || 8 == main_~_hj_k~0#1; 2297#L722-19 assume !main_#t~switch22#1; 2298#L722-21 main_#t~switch22#1 := main_#t~switch22#1 || 7 == main_~_hj_k~0#1; 2411#L722-22 assume !main_#t~switch22#1; 2412#L722-24 main_#t~switch22#1 := main_#t~switch22#1 || 6 == main_~_hj_k~0#1; 2406#L722-25 assume !main_#t~switch22#1; 2407#L722-27 main_#t~switch22#1 := main_#t~switch22#1 || 5 == main_~_hj_k~0#1; 2443#L722-28 assume !main_#t~switch22#1; 2444#L722-30 main_#t~switch22#1 := main_#t~switch22#1 || 4 == main_~_hj_k~0#1; 2441#L722-31 assume main_#t~switch22#1;call main_#t~mem30#1 := read~int(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem30#1 % 256);havoc main_#t~mem30#1; 2361#L722-33 main_#t~switch22#1 := main_#t~switch22#1 || 3 == main_~_hj_k~0#1; 2304#L722-34 assume main_#t~switch22#1;call main_#t~mem31#1 := read~int(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem31#1 % 256);havoc main_#t~mem31#1; 2305#L722-36 main_#t~switch22#1 := main_#t~switch22#1 || 2 == main_~_hj_k~0#1; 2396#L722-37 assume main_#t~switch22#1;call main_#t~mem32#1 := read~int(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem32#1 % 256);havoc main_#t~mem32#1; 2253#L722-39 main_#t~switch22#1 := main_#t~switch22#1 || 1 == main_~_hj_k~0#1; 2254#L722-40 assume main_#t~switch22#1;call main_#t~mem33#1 := read~int(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + main_#t~mem33#1 % 256;havoc main_#t~mem33#1; 2387#L722-42 havoc main_#t~switch22#1; 2388#L722-45 main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if (1 == main_~_hj_i~0#1 || 0 == main_~_hj_i~0#1) && (1 == main_~_ha_hashv~0#1 / 8192 || 0 == main_~_ha_hashv~0#1 / 8192) then (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 8192 then 0 else 1) else (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 8192 else (if 0 == main_~_ha_hashv~0#1 / 8192 then main_~_hj_i~0#1 else ~bitwiseXOr(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8192))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if (1 == main_~_hj_j~0#1 || 0 == main_~_hj_j~0#1) && (1 == 256 * main_~_hj_i~0#1 || 0 == 256 * main_~_hj_i~0#1) then (if main_~_hj_j~0#1 == 256 * main_~_hj_i~0#1 then 0 else 1) else (if 0 == main_~_hj_j~0#1 then 256 * main_~_hj_i~0#1 else (if 0 == 256 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else ~bitwiseXOr(main_~_hj_j~0#1, 256 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if (1 == main_~_ha_hashv~0#1 || 0 == main_~_ha_hashv~0#1) && (1 == main_~_hj_j~0#1 / 8192 || 0 == main_~_hj_j~0#1 / 8192) then (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 8192 then 0 else 1) else (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 8192 else (if 0 == main_~_hj_j~0#1 / 8192 then main_~_ha_hashv~0#1 else ~bitwiseXOr(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 8192))));main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if (1 == main_~_hj_i~0#1 || 0 == main_~_hj_i~0#1) && (1 == main_~_ha_hashv~0#1 / 4096 || 0 == main_~_ha_hashv~0#1 / 4096) then (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 4096 then 0 else 1) else (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 4096 else (if 0 == main_~_ha_hashv~0#1 / 4096 then main_~_hj_i~0#1 else ~bitwiseXOr(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 4096))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if (1 == main_~_hj_j~0#1 || 0 == main_~_hj_j~0#1) && (1 == 65536 * main_~_hj_i~0#1 || 0 == 65536 * main_~_hj_i~0#1) then (if main_~_hj_j~0#1 == 65536 * main_~_hj_i~0#1 then 0 else 1) else (if 0 == main_~_hj_j~0#1 then 65536 * main_~_hj_i~0#1 else (if 0 == 65536 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else ~bitwiseXOr(main_~_hj_j~0#1, 65536 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if (1 == main_~_ha_hashv~0#1 || 0 == main_~_ha_hashv~0#1) && (1 == main_~_hj_j~0#1 / 32 || 0 == main_~_hj_j~0#1 / 32) then (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 32 then 0 else 1) else (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 32 else (if 0 == main_~_hj_j~0#1 / 32 then main_~_ha_hashv~0#1 else ~bitwiseXOr(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32))));main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if (1 == main_~_hj_i~0#1 || 0 == main_~_hj_i~0#1) && (1 == main_~_ha_hashv~0#1 / 8 || 0 == main_~_ha_hashv~0#1 / 8) then (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 8 then 0 else 1) else (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 8 else (if 0 == main_~_ha_hashv~0#1 / 8 then main_~_hj_i~0#1 else ~bitwiseXOr(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if (1 == main_~_hj_j~0#1 || 0 == main_~_hj_j~0#1) && (1 == 1024 * main_~_hj_i~0#1 || 0 == 1024 * main_~_hj_i~0#1) then (if main_~_hj_j~0#1 == 1024 * main_~_hj_i~0#1 then 0 else 1) else (if 0 == main_~_hj_j~0#1 then 1024 * main_~_hj_i~0#1 else (if 0 == 1024 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else ~bitwiseXOr(main_~_hj_j~0#1, 1024 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if (1 == main_~_ha_hashv~0#1 || 0 == main_~_ha_hashv~0#1) && (1 == main_~_hj_j~0#1 / 32768 || 0 == main_~_hj_j~0#1 / 32768) then (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 32768 then 0 else 1) else (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 32768 else (if 0 == main_~_hj_j~0#1 / 32768 then main_~_ha_hashv~0#1 else ~bitwiseXOr(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32768)))); 2419#L722-44 goto; 2280#L722-46 goto; 2281#L722-48 goto; 2436#L722-122 call write~int(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4); 2435#L722-51 assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem51#1.base, main_#t~mem51#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_#t~mem51#1.base, main_#t~mem51#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem51#1.base, main_#t~mem51#1.offset; 2399#L722-67 call write~$Pointer$(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem52#1.base, main_#t~mem52#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem53#1.base, main_#t~mem53#1.offset := read~$Pointer$(main_#t~mem52#1.base, 16 + main_#t~mem52#1.offset, 4);call main_#t~mem54#1.base, main_#t~mem54#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem55#1 := read~int(main_#t~mem54#1.base, 20 + main_#t~mem54#1.offset, 4);call write~$Pointer$(main_#t~mem53#1.base, main_#t~mem53#1.offset - main_#t~mem55#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem52#1.base, main_#t~mem52#1.offset;havoc main_#t~mem53#1.base, main_#t~mem53#1.offset;havoc main_#t~mem54#1.base, main_#t~mem54#1.offset;havoc main_#t~mem55#1;call main_#t~mem56#1.base, main_#t~mem56#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem57#1.base, main_#t~mem57#1.offset := read~$Pointer$(main_#t~mem56#1.base, 16 + main_#t~mem56#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem57#1.base, 8 + main_#t~mem57#1.offset, 4);havoc main_#t~mem56#1.base, main_#t~mem56#1.offset;havoc main_#t~mem57#1.base, main_#t~mem57#1.offset;call main_#t~mem58#1.base, main_#t~mem58#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem58#1.base, 16 + main_#t~mem58#1.offset, 4);havoc main_#t~mem58#1.base, main_#t~mem58#1.offset; 2400#L722-66 goto; 2368#L722-120 havoc main_~_ha_bkt~0#1;call main_#t~mem59#1.base, main_#t~mem59#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem60#1 := read~int(main_#t~mem59#1.base, 12 + main_#t~mem59#1.offset, 4);main_#t~post61#1 := main_#t~mem60#1;call write~int(1 + main_#t~post61#1, main_#t~mem59#1.base, 12 + main_#t~mem59#1.offset, 4);havoc main_#t~mem59#1.base, main_#t~mem59#1.offset;havoc main_#t~mem60#1;havoc main_#t~post61#1; 2354#L722-71 call main_#t~mem62#1.base, main_#t~mem62#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem63#1 := read~int(main_#t~mem62#1.base, 4 + main_#t~mem62#1.offset, 4);main_~_ha_bkt~0#1 := (if 0 == main_~_ha_hashv~0#1 || 0 == main_#t~mem63#1 - 1 then 0 else (if 1 == main_#t~mem63#1 - 1 then (if 1 == main_~_ha_hashv~0#1 || 0 == main_~_ha_hashv~0#1 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 >= 0 then main_~_ha_hashv~0#1 % 2 else ~bitwiseAnd(main_~_ha_hashv~0#1, main_#t~mem63#1 - 1))) else (if 1 == main_~_ha_hashv~0#1 then (if 1 == main_#t~mem63#1 - 1 || 0 == main_#t~mem63#1 - 1 then main_#t~mem63#1 - 1 else (if main_#t~mem63#1 - 1 >= 0 then (main_#t~mem63#1 - 1) % 2 else ~bitwiseAnd(main_~_ha_hashv~0#1, main_#t~mem63#1 - 1))) else ~bitwiseAnd(main_~_ha_hashv~0#1, main_#t~mem63#1 - 1))));havoc main_#t~mem62#1.base, main_#t~mem62#1.offset;havoc main_#t~mem63#1; 2355#L722-70 goto; 2431#L722-118 call main_#t~mem64#1.base, main_#t~mem64#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem65#1.base, main_#t~mem65#1.offset := read~$Pointer$(main_#t~mem64#1.base, main_#t~mem64#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem65#1.base, main_#t~mem65#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem64#1.base, main_#t~mem64#1.offset;havoc main_#t~mem65#1.base, main_#t~mem65#1.offset;call main_#t~mem66#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post67#1 := main_#t~mem66#1;call write~int(1 + main_#t~post67#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem66#1;havoc main_#t~post67#1;call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_#t~mem68#1.base, main_#t~mem68#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;call write~$Pointer$(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4); 2282#L722-73 assume main_#t~mem69#1.base != 0 || main_#t~mem69#1.offset != 0;havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem70#1.base, 12 + main_#t~mem70#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset; 2283#L722-75 call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem72#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem71#1 := read~int(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short75#1 := main_#t~mem72#1 % 4294967296 >= 10 * (1 + main_#t~mem71#1) % 4294967296; 2376#L722-76 assume main_#t~short75#1;call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem74#1 := read~int(main_#t~mem73#1.base, 36 + main_#t~mem73#1.offset, 4);main_#t~short75#1 := 0 == main_#t~mem74#1 % 4294967296; 2250#L722-78 assume !main_#t~short75#1;havoc main_#t~mem72#1;havoc main_#t~mem71#1;havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;havoc main_#t~mem74#1;havoc main_#t~short75#1; 2252#L722-117 goto; 2346#L722-119 goto; 2369#L722-121 goto; 2265#L722-123 goto; 2266#L715-3 call main_#t~mem3#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post4#1 := main_#t~mem3#1;call write~int(1 + main_#t~post4#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem3#1;havoc main_#t~post4#1; 2358#L715-4 [2022-10-17 11:09:27,266 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:09:27,267 INFO L85 PathProgramCache]: Analyzing trace with hash 1251, now seen corresponding path program 5 times [2022-10-17 11:09:27,267 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:09:27,267 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [533747269] [2022-10-17 11:09:27,267 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:09:27,267 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:09:27,305 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 11:09:27,305 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 11:09:27,331 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 11:09:27,365 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 11:09:27,366 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:09:27,366 INFO L85 PathProgramCache]: Analyzing trace with hash 1694021305, now seen corresponding path program 1 times [2022-10-17 11:09:27,366 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:09:27,366 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [868451111] [2022-10-17 11:09:27,367 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:09:27,367 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:09:27,550 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-10-17 11:09:27,550 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [712969440] [2022-10-17 11:09:27,551 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:09:27,551 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 11:09:27,551 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cf4cc610-6584-43c2-a4b2-fc8d2c4ba5ac/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 11:09:27,558 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cf4cc610-6584-43c2-a4b2-fc8d2c4ba5ac/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 11:09:27,581 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cf4cc610-6584-43c2-a4b2-fc8d2c4ba5ac/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process