./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/uthash-2.0.2/uthash_SAX_test6-1.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version dbf71c69 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_42b4b8d7-ef45-46b3-ab68-f03ee3b0d7ca/bin/uautomizer-J5u9QxTXDZ/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_42b4b8d7-ef45-46b3-ab68-f03ee3b0d7ca/bin/uautomizer-J5u9QxTXDZ/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_42b4b8d7-ef45-46b3-ab68-f03ee3b0d7ca/bin/uautomizer-J5u9QxTXDZ/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_42b4b8d7-ef45-46b3-ab68-f03ee3b0d7ca/bin/uautomizer-J5u9QxTXDZ/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/uthash-2.0.2/uthash_SAX_test6-1.i -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_42b4b8d7-ef45-46b3-ab68-f03ee3b0d7ca/bin/uautomizer-J5u9QxTXDZ/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_42b4b8d7-ef45-46b3-ab68-f03ee3b0d7ca/bin/uautomizer-J5u9QxTXDZ --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash ff5be3465740cb655882704e7eef418c95d0bbd56a2060e741c7d3e996e58af7 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-dbf71c6-m [2022-10-17 10:37:15,082 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-10-17 10:37:15,084 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-10-17 10:37:15,127 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-10-17 10:37:15,128 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-10-17 10:37:15,132 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-10-17 10:37:15,134 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-10-17 10:37:15,140 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-10-17 10:37:15,143 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-10-17 10:37:15,149 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-10-17 10:37:15,150 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-10-17 10:37:15,153 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-10-17 10:37:15,154 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-10-17 10:37:15,157 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-10-17 10:37:15,160 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-10-17 10:37:15,162 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-10-17 10:37:15,164 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-10-17 10:37:15,165 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-10-17 10:37:15,168 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-10-17 10:37:15,177 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-10-17 10:37:15,179 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-10-17 10:37:15,180 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-10-17 10:37:15,184 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-10-17 10:37:15,186 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-10-17 10:37:15,197 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-10-17 10:37:15,198 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-10-17 10:37:15,198 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-10-17 10:37:15,201 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-10-17 10:37:15,201 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-10-17 10:37:15,203 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-10-17 10:37:15,203 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-10-17 10:37:15,206 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-10-17 10:37:15,209 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-10-17 10:37:15,211 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-10-17 10:37:15,212 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-10-17 10:37:15,213 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-10-17 10:37:15,213 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-10-17 10:37:15,214 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-10-17 10:37:15,214 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-10-17 10:37:15,215 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-10-17 10:37:15,217 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-10-17 10:37:15,218 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_42b4b8d7-ef45-46b3-ab68-f03ee3b0d7ca/bin/uautomizer-J5u9QxTXDZ/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-10-17 10:37:15,277 INFO L113 SettingsManager]: Loading preferences was successful [2022-10-17 10:37:15,277 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-10-17 10:37:15,278 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-10-17 10:37:15,279 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-10-17 10:37:15,280 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-10-17 10:37:15,285 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-10-17 10:37:15,285 INFO L138 SettingsManager]: * Use SBE=true [2022-10-17 10:37:15,286 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-10-17 10:37:15,286 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-10-17 10:37:15,286 INFO L138 SettingsManager]: * Use old map elimination=false [2022-10-17 10:37:15,287 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-10-17 10:37:15,288 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-10-17 10:37:15,288 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-10-17 10:37:15,289 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-10-17 10:37:15,289 INFO L138 SettingsManager]: * sizeof long=4 [2022-10-17 10:37:15,289 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-10-17 10:37:15,290 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-10-17 10:37:15,290 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-10-17 10:37:15,290 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-10-17 10:37:15,290 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-10-17 10:37:15,291 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-10-17 10:37:15,291 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-10-17 10:37:15,291 INFO L138 SettingsManager]: * sizeof long double=12 [2022-10-17 10:37:15,313 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-10-17 10:37:15,313 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-10-17 10:37:15,314 INFO L138 SettingsManager]: * Use constant arrays=true [2022-10-17 10:37:15,314 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-10-17 10:37:15,314 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-10-17 10:37:15,314 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-10-17 10:37:15,315 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-10-17 10:37:15,315 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-10-17 10:37:15,316 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-10-17 10:37:15,316 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_42b4b8d7-ef45-46b3-ab68-f03ee3b0d7ca/bin/uautomizer-J5u9QxTXDZ/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_42b4b8d7-ef45-46b3-ab68-f03ee3b0d7ca/bin/uautomizer-J5u9QxTXDZ Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> ff5be3465740cb655882704e7eef418c95d0bbd56a2060e741c7d3e996e58af7 [2022-10-17 10:37:15,647 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-10-17 10:37:15,678 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-10-17 10:37:15,681 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-10-17 10:37:15,682 INFO L271 PluginConnector]: Initializing CDTParser... [2022-10-17 10:37:15,684 INFO L275 PluginConnector]: CDTParser initialized [2022-10-17 10:37:15,686 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_42b4b8d7-ef45-46b3-ab68-f03ee3b0d7ca/bin/uautomizer-J5u9QxTXDZ/../../sv-benchmarks/c/uthash-2.0.2/uthash_SAX_test6-1.i [2022-10-17 10:37:15,777 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_42b4b8d7-ef45-46b3-ab68-f03ee3b0d7ca/bin/uautomizer-J5u9QxTXDZ/data/9bb0ccaef/a2bed5a09d944c428da9ac6cbafa0874/FLAGa5e1248b4 [2022-10-17 10:37:16,448 INFO L306 CDTParser]: Found 1 translation units. [2022-10-17 10:37:16,448 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_42b4b8d7-ef45-46b3-ab68-f03ee3b0d7ca/sv-benchmarks/c/uthash-2.0.2/uthash_SAX_test6-1.i [2022-10-17 10:37:16,473 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_42b4b8d7-ef45-46b3-ab68-f03ee3b0d7ca/bin/uautomizer-J5u9QxTXDZ/data/9bb0ccaef/a2bed5a09d944c428da9ac6cbafa0874/FLAGa5e1248b4 [2022-10-17 10:37:16,624 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_42b4b8d7-ef45-46b3-ab68-f03ee3b0d7ca/bin/uautomizer-J5u9QxTXDZ/data/9bb0ccaef/a2bed5a09d944c428da9ac6cbafa0874 [2022-10-17 10:37:16,627 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-10-17 10:37:16,629 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-10-17 10:37:16,630 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-10-17 10:37:16,631 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-10-17 10:37:16,635 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-10-17 10:37:16,636 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.10 10:37:16" (1/1) ... [2022-10-17 10:37:16,637 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6cc8643d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:37:16, skipping insertion in model container [2022-10-17 10:37:16,637 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.10 10:37:16" (1/1) ... [2022-10-17 10:37:16,646 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-10-17 10:37:16,713 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-10-17 10:37:17,466 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_42b4b8d7-ef45-46b3-ab68-f03ee3b0d7ca/sv-benchmarks/c/uthash-2.0.2/uthash_SAX_test6-1.i[44118,44131] [2022-10-17 10:37:17,494 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_42b4b8d7-ef45-46b3-ab68-f03ee3b0d7ca/sv-benchmarks/c/uthash-2.0.2/uthash_SAX_test6-1.i[44660,44673] [2022-10-17 10:37:17,653 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_42b4b8d7-ef45-46b3-ab68-f03ee3b0d7ca/sv-benchmarks/c/uthash-2.0.2/uthash_SAX_test6-1.i[56247,56260] [2022-10-17 10:37:17,654 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_42b4b8d7-ef45-46b3-ab68-f03ee3b0d7ca/sv-benchmarks/c/uthash-2.0.2/uthash_SAX_test6-1.i[56368,56381] [2022-10-17 10:37:17,663 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-10-17 10:37:17,673 INFO L203 MainTranslator]: Completed pre-run [2022-10-17 10:37:17,703 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_42b4b8d7-ef45-46b3-ab68-f03ee3b0d7ca/sv-benchmarks/c/uthash-2.0.2/uthash_SAX_test6-1.i[44118,44131] [2022-10-17 10:37:17,707 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_42b4b8d7-ef45-46b3-ab68-f03ee3b0d7ca/sv-benchmarks/c/uthash-2.0.2/uthash_SAX_test6-1.i[44660,44673] [2022-10-17 10:37:17,827 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_42b4b8d7-ef45-46b3-ab68-f03ee3b0d7ca/sv-benchmarks/c/uthash-2.0.2/uthash_SAX_test6-1.i[56247,56260] [2022-10-17 10:37:17,831 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_42b4b8d7-ef45-46b3-ab68-f03ee3b0d7ca/sv-benchmarks/c/uthash-2.0.2/uthash_SAX_test6-1.i[56368,56381] [2022-10-17 10:37:17,847 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-10-17 10:37:17,936 INFO L208 MainTranslator]: Completed translation [2022-10-17 10:37:17,937 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:37:17 WrapperNode [2022-10-17 10:37:17,937 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-10-17 10:37:17,939 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-10-17 10:37:17,939 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-10-17 10:37:17,939 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-10-17 10:37:17,948 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:37:17" (1/1) ... [2022-10-17 10:37:17,995 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:37:17" (1/1) ... [2022-10-17 10:37:18,080 INFO L138 Inliner]: procedures = 282, calls = 294, calls flagged for inlining = 19, calls inlined = 21, statements flattened = 1143 [2022-10-17 10:37:18,081 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-10-17 10:37:18,082 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-10-17 10:37:18,082 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-10-17 10:37:18,083 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-10-17 10:37:18,093 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:37:17" (1/1) ... [2022-10-17 10:37:18,094 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:37:17" (1/1) ... [2022-10-17 10:37:18,110 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:37:17" (1/1) ... [2022-10-17 10:37:18,111 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:37:17" (1/1) ... [2022-10-17 10:37:18,180 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:37:17" (1/1) ... [2022-10-17 10:37:18,209 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:37:17" (1/1) ... [2022-10-17 10:37:18,215 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:37:17" (1/1) ... [2022-10-17 10:37:18,239 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:37:17" (1/1) ... [2022-10-17 10:37:18,252 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-10-17 10:37:18,254 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-10-17 10:37:18,255 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-10-17 10:37:18,255 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-10-17 10:37:18,256 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:37:17" (1/1) ... [2022-10-17 10:37:18,262 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:37:18,274 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_42b4b8d7-ef45-46b3-ab68-f03ee3b0d7ca/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:37:18,295 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_42b4b8d7-ef45-46b3-ab68-f03ee3b0d7ca/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:37:18,325 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_42b4b8d7-ef45-46b3-ab68-f03ee3b0d7ca/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-10-17 10:37:18,358 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset [2022-10-17 10:37:18,358 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset [2022-10-17 10:37:18,359 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2022-10-17 10:37:18,359 INFO L130 BoogieDeclarations]: Found specification of procedure memcmp [2022-10-17 10:37:18,359 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$ [2022-10-17 10:37:18,359 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2022-10-17 10:37:18,360 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2022-10-17 10:37:18,360 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2022-10-17 10:37:18,360 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnHeap [2022-10-17 10:37:18,360 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-10-17 10:37:18,360 INFO L130 BoogieDeclarations]: Found specification of procedure write~$Pointer$ [2022-10-17 10:37:18,361 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-10-17 10:37:18,361 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-10-17 10:37:18,361 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-10-17 10:37:18,627 INFO L235 CfgBuilder]: Building ICFG [2022-10-17 10:37:18,629 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-10-17 10:37:18,634 WARN L816 $ProcedureCfgBuilder]: Label in the middle of a codeblock. [2022-10-17 10:37:20,740 INFO L276 CfgBuilder]: Performing block encoding [2022-10-17 10:37:20,757 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-10-17 10:37:20,757 INFO L300 CfgBuilder]: Removed 63 assume(true) statements. [2022-10-17 10:37:20,760 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 17.10 10:37:20 BoogieIcfgContainer [2022-10-17 10:37:20,760 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-10-17 10:37:20,762 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-10-17 10:37:20,762 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-10-17 10:37:20,767 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-10-17 10:37:20,768 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-10-17 10:37:20,768 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 17.10 10:37:16" (1/3) ... [2022-10-17 10:37:20,770 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2f77ea76 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.10 10:37:20, skipping insertion in model container [2022-10-17 10:37:20,770 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-10-17 10:37:20,771 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:37:17" (2/3) ... [2022-10-17 10:37:20,772 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2f77ea76 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.10 10:37:20, skipping insertion in model container [2022-10-17 10:37:20,772 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-10-17 10:37:20,772 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 17.10 10:37:20" (3/3) ... [2022-10-17 10:37:20,774 INFO L332 chiAutomizerObserver]: Analyzing ICFG uthash_SAX_test6-1.i [2022-10-17 10:37:20,850 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-10-17 10:37:20,851 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-10-17 10:37:20,851 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-10-17 10:37:20,851 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-10-17 10:37:20,851 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-10-17 10:37:20,851 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-10-17 10:37:20,851 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-10-17 10:37:20,852 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-10-17 10:37:20,857 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 222 states, 217 states have (on average 1.6267281105990783) internal successors, (353), 217 states have internal predecessors, (353), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-10-17 10:37:20,900 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 204 [2022-10-17 10:37:20,900 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:37:20,900 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:37:20,912 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-10-17 10:37:20,912 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:37:20,912 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-10-17 10:37:20,917 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 222 states, 217 states have (on average 1.6267281105990783) internal successors, (353), 217 states have internal predecessors, (353), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-10-17 10:37:20,935 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 204 [2022-10-17 10:37:20,935 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:37:20,935 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:37:20,936 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-10-17 10:37:20,936 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:37:20,945 INFO L748 eck$LassoCheckResult]: Stem: 215#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call #Ultimate.allocInit(40, 3);#memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, ~#alt_malloc_sizes~0.base);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0; 139#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret43#1.base, main_#t~ret43#1.offset, main_#t~mem44#1, main_#t~mem45#1, main_#t~mem46#1, main_#t~mem48#1, main_#t~mem47#1, main_#t~mem49#1, main_#t~mem50#1, main_#t~mem52#1, main_#t~mem51#1, main_#t~mem53#1, main_#t~mem54#1, main_#t~mem56#1, main_#t~mem55#1, main_#t~mem57#1, main_#t~mem58#1, main_#t~switch59#1, main_#t~mem60#1, main_#t~mem61#1, main_#t~mem62#1, main_#t~mem63#1, main_#t~mem64#1, main_#t~mem65#1, main_#t~mem66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret71#1.base, main_#t~ret71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1.base, main_#t~mem78#1.offset, main_#t~ret79#1.base, main_#t~ret79#1.offset, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1.base, main_#t~mem82#1.offset, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~mem95#1, main_#t~post96#1, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1, main_#t~post102#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem107#1, main_#t~mem106#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~short110#1, main_#t~mem111#1.base, main_#t~mem111#1.offset, main_#t~mem112#1, main_#t~ret113#1.base, main_#t~ret113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem122#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem126#1, main_#t~mem124#1.base, main_#t~mem124#1.offset, main_#t~mem125#1, main_#t~ite127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem138#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem140#1, main_#t~pre141#1, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1, main_#t~post146#1, main_#t~mem150#1, main_#t~mem148#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem149#1, main_#t~mem151#1, main_#t~post152#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_#t~mem155#1.base, main_#t~mem155#1.offset, main_#t~post129#1, main_#t~mem130#1.base, main_#t~mem130#1.offset, main_#t~mem131#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_#t~mem159#1, main_#t~mem160#1.base, main_#t~mem160#1.offset, main_#t~mem161#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem163#1, main_#t~post164#1, main_#t~mem165#1.base, main_#t~mem165#1.offset, main_#t~mem166#1.base, main_#t~mem166#1.offset, main_#t~mem167#1.base, main_#t~mem167#1.offset, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem171#1, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1, main_#t~ite174#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1, main_#t~mem175#1.base, main_#t~mem175#1.offset, main_#t~mem176#1, main_#t~mem177#1.base, main_#t~mem177#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~#_he_new_buckets~0#1.base, main_~#_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem40#1, main_#t~post41#1, main_#t~mem42#1, main_#t~mem182#1, main_#t~mem181#1, main_#t~mem183#1, main_#t~mem184#1, main_#t~mem186#1, main_#t~mem185#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem190#1, main_#t~mem189#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~switch193#1, main_#t~mem194#1, main_#t~mem195#1, main_#t~mem196#1, main_#t~mem197#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem200#1, main_#t~mem201#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem204#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem205#1.base, main_#t~mem205#1.offset, main_#t~mem206#1, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1.base, main_#t~mem212#1.offset, main_#t~mem213#1.base, main_#t~mem213#1.offset, main_#t~mem214#1, main_#t~mem215#1, main_#t~mem216#1, main_#t~short217#1, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~ret219#1, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1.base, main_#t~mem221#1.offset, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~mem225#1.base, main_#t~mem225#1.offset, main_#t~short226#1, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~mem228#1.base, main_#t~mem228#1.offset, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1.base, main_#t~mem233#1.offset, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1.base, main_#t~mem239#1.offset, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1, main_#t~mem248#1.base, main_#t~mem248#1.offset, main_#t~mem251#1, main_#t~mem249#1.base, main_#t~mem249#1.offset, main_#t~mem250#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~mem253#1.base, main_#t~mem253#1.offset, main_#t~mem254#1, main_#t~post255#1, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem264#1.base, main_#t~mem264#1.offset, main_#t~mem265#1, main_#t~post266#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem178#1, main_#t~post179#1, main_#t~mem180#1, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4); 9#L989-4true [2022-10-17 10:37:20,949 INFO L750 eck$LassoCheckResult]: Loop: 9#L989-4true call main_#t~mem42#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4); 4#L989-1true assume !!(main_#t~mem42#1 < 10);havoc main_#t~mem42#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset; 87#L979true main_#t~ret43#1.base, main_#t~ret43#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret43#1.base, main_#t~ret43#1.offset;havoc main_#t~ret43#1.base, main_#t~ret43#1.offset; 10#L991true assume main_~user~0#1.base == 0 && main_~user~0#1.offset == 0;assume false; 81#L991-2true call main_#t~mem44#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int(main_#t~mem44#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem44#1;call main_#t~mem45#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem46#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int(main_#t~mem45#1 * main_#t~mem46#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem45#1;havoc main_#t~mem46#1; 204#L996-118true assume !true; 201#L989-3true call main_#t~mem40#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post41#1 := main_#t~mem40#1;call write~int(1 + main_#t~post41#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem40#1;havoc main_#t~post41#1; 9#L989-4true [2022-10-17 10:37:20,955 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:37:20,955 INFO L85 PathProgramCache]: Analyzing trace with hash 1251, now seen corresponding path program 1 times [2022-10-17 10:37:20,965 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:37:20,965 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [786686973] [2022-10-17 10:37:20,966 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:37:20,966 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:37:21,091 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:37:21,091 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:37:21,116 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:37:21,152 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:37:21,156 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:37:21,156 INFO L85 PathProgramCache]: Analyzing trace with hash -1530816074, now seen corresponding path program 1 times [2022-10-17 10:37:21,156 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:37:21,156 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2116242570] [2022-10-17 10:37:21,157 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:37:21,157 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:37:21,182 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:37:21,213 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:37:21,214 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2116242570] [2022-10-17 10:37:21,217 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: Unsupported non-linear arithmetic [2022-10-17 10:37:21,217 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1697644090] [2022-10-17 10:37:21,218 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:37:21,218 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 10:37:21,218 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_42b4b8d7-ef45-46b3-ab68-f03ee3b0d7ca/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:37:21,233 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_42b4b8d7-ef45-46b3-ab68-f03ee3b0d7ca/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 10:37:21,257 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_42b4b8d7-ef45-46b3-ab68-f03ee3b0d7ca/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2022-10-17 10:37:21,390 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:37:21,393 INFO L263 TraceCheckSpWp]: Trace formula consists of 82 conjuncts, 1 conjunts are in the unsatisfiable core [2022-10-17 10:37:21,401 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:37:21,424 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:37:21,425 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-10-17 10:37:21,426 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1697644090] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:37:21,426 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:37:21,426 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-10-17 10:37:21,427 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1517006349] [2022-10-17 10:37:21,428 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:37:21,432 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:37:21,433 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:37:21,489 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2022-10-17 10:37:21,491 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2022-10-17 10:37:21,494 INFO L87 Difference]: Start difference. First operand has 222 states, 217 states have (on average 1.6267281105990783) internal successors, (353), 217 states have internal predecessors, (353), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Second operand has 2 states, 2 states have (on average 3.5) internal successors, (7), 2 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:37:21,540 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:37:21,541 INFO L93 Difference]: Finished difference Result 218 states and 276 transitions. [2022-10-17 10:37:21,542 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 218 states and 276 transitions. [2022-10-17 10:37:21,563 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 199 [2022-10-17 10:37:21,578 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 218 states to 206 states and 264 transitions. [2022-10-17 10:37:21,579 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 206 [2022-10-17 10:37:21,582 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 206 [2022-10-17 10:37:21,582 INFO L73 IsDeterministic]: Start isDeterministic. Operand 206 states and 264 transitions. [2022-10-17 10:37:21,587 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:37:21,587 INFO L218 hiAutomatonCegarLoop]: Abstraction has 206 states and 264 transitions. [2022-10-17 10:37:21,609 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 206 states and 264 transitions. [2022-10-17 10:37:21,645 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 206 to 206. [2022-10-17 10:37:21,649 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 206 states, 202 states have (on average 1.2772277227722773) internal successors, (258), 201 states have internal predecessors, (258), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-10-17 10:37:21,654 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 206 states to 206 states and 264 transitions. [2022-10-17 10:37:21,655 INFO L240 hiAutomatonCegarLoop]: Abstraction has 206 states and 264 transitions. [2022-10-17 10:37:21,656 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-10-17 10:37:21,665 INFO L428 stractBuchiCegarLoop]: Abstraction has 206 states and 264 transitions. [2022-10-17 10:37:21,665 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-10-17 10:37:21,667 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 206 states and 264 transitions. [2022-10-17 10:37:21,671 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 199 [2022-10-17 10:37:21,671 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:37:21,671 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:37:21,678 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-10-17 10:37:21,679 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:37:21,679 INFO L748 eck$LassoCheckResult]: Stem: 671#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call #Ultimate.allocInit(40, 3);#memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, ~#alt_malloc_sizes~0.base);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0; 649#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret43#1.base, main_#t~ret43#1.offset, main_#t~mem44#1, main_#t~mem45#1, main_#t~mem46#1, main_#t~mem48#1, main_#t~mem47#1, main_#t~mem49#1, main_#t~mem50#1, main_#t~mem52#1, main_#t~mem51#1, main_#t~mem53#1, main_#t~mem54#1, main_#t~mem56#1, main_#t~mem55#1, main_#t~mem57#1, main_#t~mem58#1, main_#t~switch59#1, main_#t~mem60#1, main_#t~mem61#1, main_#t~mem62#1, main_#t~mem63#1, main_#t~mem64#1, main_#t~mem65#1, main_#t~mem66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret71#1.base, main_#t~ret71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1.base, main_#t~mem78#1.offset, main_#t~ret79#1.base, main_#t~ret79#1.offset, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1.base, main_#t~mem82#1.offset, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~mem95#1, main_#t~post96#1, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1, main_#t~post102#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem107#1, main_#t~mem106#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~short110#1, main_#t~mem111#1.base, main_#t~mem111#1.offset, main_#t~mem112#1, main_#t~ret113#1.base, main_#t~ret113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem122#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem126#1, main_#t~mem124#1.base, main_#t~mem124#1.offset, main_#t~mem125#1, main_#t~ite127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem138#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem140#1, main_#t~pre141#1, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1, main_#t~post146#1, main_#t~mem150#1, main_#t~mem148#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem149#1, main_#t~mem151#1, main_#t~post152#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_#t~mem155#1.base, main_#t~mem155#1.offset, main_#t~post129#1, main_#t~mem130#1.base, main_#t~mem130#1.offset, main_#t~mem131#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_#t~mem159#1, main_#t~mem160#1.base, main_#t~mem160#1.offset, main_#t~mem161#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem163#1, main_#t~post164#1, main_#t~mem165#1.base, main_#t~mem165#1.offset, main_#t~mem166#1.base, main_#t~mem166#1.offset, main_#t~mem167#1.base, main_#t~mem167#1.offset, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem171#1, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1, main_#t~ite174#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1, main_#t~mem175#1.base, main_#t~mem175#1.offset, main_#t~mem176#1, main_#t~mem177#1.base, main_#t~mem177#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~#_he_new_buckets~0#1.base, main_~#_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem40#1, main_#t~post41#1, main_#t~mem42#1, main_#t~mem182#1, main_#t~mem181#1, main_#t~mem183#1, main_#t~mem184#1, main_#t~mem186#1, main_#t~mem185#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem190#1, main_#t~mem189#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~switch193#1, main_#t~mem194#1, main_#t~mem195#1, main_#t~mem196#1, main_#t~mem197#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem200#1, main_#t~mem201#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem204#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem205#1.base, main_#t~mem205#1.offset, main_#t~mem206#1, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1.base, main_#t~mem212#1.offset, main_#t~mem213#1.base, main_#t~mem213#1.offset, main_#t~mem214#1, main_#t~mem215#1, main_#t~mem216#1, main_#t~short217#1, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~ret219#1, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1.base, main_#t~mem221#1.offset, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~mem225#1.base, main_#t~mem225#1.offset, main_#t~short226#1, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~mem228#1.base, main_#t~mem228#1.offset, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1.base, main_#t~mem233#1.offset, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1.base, main_#t~mem239#1.offset, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1, main_#t~mem248#1.base, main_#t~mem248#1.offset, main_#t~mem251#1, main_#t~mem249#1.base, main_#t~mem249#1.offset, main_#t~mem250#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~mem253#1.base, main_#t~mem253#1.offset, main_#t~mem254#1, main_#t~post255#1, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem264#1.base, main_#t~mem264#1.offset, main_#t~mem265#1, main_#t~post266#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem178#1, main_#t~post179#1, main_#t~mem180#1, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4); 479#L989-4 [2022-10-17 10:37:21,681 INFO L750 eck$LassoCheckResult]: Loop: 479#L989-4 call main_#t~mem42#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4); 470#L989-1 assume !!(main_#t~mem42#1 < 10);havoc main_#t~mem42#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset; 472#L979 main_#t~ret43#1.base, main_#t~ret43#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret43#1.base, main_#t~ret43#1.offset;havoc main_#t~ret43#1.base, main_#t~ret43#1.offset; 480#L991 assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0); 481#L991-2 call main_#t~mem44#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int(main_#t~mem44#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem44#1;call main_#t~mem45#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem46#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int(main_#t~mem45#1 * main_#t~mem46#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem45#1;havoc main_#t~mem46#1; 595#L996-118 havoc main_~_ha_hashv~0#1; 639#L996-49 goto; 640#L996-47 havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4; 474#L996-8 assume !(main_~_hj_k~0#1 % 4294967296 >= 12); 498#L996-9 main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch59#1 := 11 == main_~_hj_k~0#1; 666#L996-10 assume main_#t~switch59#1;call main_#t~mem60#1 := read~int(main_~_hj_key~0#1.base, 10 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 16777216 * (main_#t~mem60#1 % 256);havoc main_#t~mem60#1; 670#L996-12 main_#t~switch59#1 := main_#t~switch59#1 || 10 == main_~_hj_k~0#1; 570#L996-13 assume main_#t~switch59#1;call main_#t~mem61#1 := read~int(main_~_hj_key~0#1.base, 9 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 65536 * (main_#t~mem61#1 % 256);havoc main_#t~mem61#1; 571#L996-15 main_#t~switch59#1 := main_#t~switch59#1 || 9 == main_~_hj_k~0#1; 667#L996-16 assume main_#t~switch59#1;call main_#t~mem62#1 := read~int(main_~_hj_key~0#1.base, 8 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 256 * (main_#t~mem62#1 % 256);havoc main_#t~mem62#1; 668#L996-18 main_#t~switch59#1 := main_#t~switch59#1 || 8 == main_~_hj_k~0#1; 659#L996-19 assume main_#t~switch59#1;call main_#t~mem63#1 := read~int(main_~_hj_key~0#1.base, 7 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 16777216 * (main_#t~mem63#1 % 256);havoc main_#t~mem63#1; 655#L996-21 main_#t~switch59#1 := main_#t~switch59#1 || 7 == main_~_hj_k~0#1; 636#L996-22 assume main_#t~switch59#1;call main_#t~mem64#1 := read~int(main_~_hj_key~0#1.base, 6 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 65536 * (main_#t~mem64#1 % 256);havoc main_#t~mem64#1; 637#L996-24 main_#t~switch59#1 := main_#t~switch59#1 || 6 == main_~_hj_k~0#1; 652#L996-25 assume main_#t~switch59#1;call main_#t~mem65#1 := read~int(main_~_hj_key~0#1.base, 5 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 256 * (main_#t~mem65#1 % 256);havoc main_#t~mem65#1; 630#L996-27 main_#t~switch59#1 := main_#t~switch59#1 || 5 == main_~_hj_k~0#1; 475#L996-28 assume !main_#t~switch59#1; 476#L996-30 main_#t~switch59#1 := main_#t~switch59#1 || 4 == main_~_hj_k~0#1; 603#L996-31 assume main_#t~switch59#1;call main_#t~mem67#1 := read~int(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem67#1 % 256);havoc main_#t~mem67#1; 621#L996-33 main_#t~switch59#1 := main_#t~switch59#1 || 3 == main_~_hj_k~0#1; 590#L996-34 assume main_#t~switch59#1;call main_#t~mem68#1 := read~int(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem68#1 % 256);havoc main_#t~mem68#1; 591#L996-36 main_#t~switch59#1 := main_#t~switch59#1 || 2 == main_~_hj_k~0#1; 553#L996-37 assume main_#t~switch59#1;call main_#t~mem69#1 := read~int(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem69#1 % 256);havoc main_#t~mem69#1; 554#L996-39 main_#t~switch59#1 := main_#t~switch59#1 || 1 == main_~_hj_k~0#1; 574#L996-40 assume main_#t~switch59#1;call main_#t~mem70#1 := read~int(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + main_#t~mem70#1 % 256;havoc main_#t~mem70#1; 604#L996-42 havoc main_#t~switch59#1; 525#L996-45 main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if (1 == main_~_hj_i~0#1 || 0 == main_~_hj_i~0#1) && (1 == main_~_ha_hashv~0#1 / 8192 || 0 == main_~_ha_hashv~0#1 / 8192) then (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 8192 then 0 else 1) else (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 8192 else (if 0 == main_~_ha_hashv~0#1 / 8192 then main_~_hj_i~0#1 else ~bitwiseXOr(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8192))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if (1 == main_~_hj_j~0#1 || 0 == main_~_hj_j~0#1) && (1 == 256 * main_~_hj_i~0#1 || 0 == 256 * main_~_hj_i~0#1) then (if main_~_hj_j~0#1 == 256 * main_~_hj_i~0#1 then 0 else 1) else (if 0 == main_~_hj_j~0#1 then 256 * main_~_hj_i~0#1 else (if 0 == 256 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else ~bitwiseXOr(main_~_hj_j~0#1, 256 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if (1 == main_~_ha_hashv~0#1 || 0 == main_~_ha_hashv~0#1) && (1 == main_~_hj_j~0#1 / 8192 || 0 == main_~_hj_j~0#1 / 8192) then (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 8192 then 0 else 1) else (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 8192 else (if 0 == main_~_hj_j~0#1 / 8192 then main_~_ha_hashv~0#1 else ~bitwiseXOr(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 8192))));main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if (1 == main_~_hj_i~0#1 || 0 == main_~_hj_i~0#1) && (1 == main_~_ha_hashv~0#1 / 4096 || 0 == main_~_ha_hashv~0#1 / 4096) then (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 4096 then 0 else 1) else (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 4096 else (if 0 == main_~_ha_hashv~0#1 / 4096 then main_~_hj_i~0#1 else ~bitwiseXOr(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 4096))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if (1 == main_~_hj_j~0#1 || 0 == main_~_hj_j~0#1) && (1 == 65536 * main_~_hj_i~0#1 || 0 == 65536 * main_~_hj_i~0#1) then (if main_~_hj_j~0#1 == 65536 * main_~_hj_i~0#1 then 0 else 1) else (if 0 == main_~_hj_j~0#1 then 65536 * main_~_hj_i~0#1 else (if 0 == 65536 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else ~bitwiseXOr(main_~_hj_j~0#1, 65536 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if (1 == main_~_ha_hashv~0#1 || 0 == main_~_ha_hashv~0#1) && (1 == main_~_hj_j~0#1 / 32 || 0 == main_~_hj_j~0#1 / 32) then (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 32 then 0 else 1) else (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 32 else (if 0 == main_~_hj_j~0#1 / 32 then main_~_ha_hashv~0#1 else ~bitwiseXOr(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32))));main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if (1 == main_~_hj_i~0#1 || 0 == main_~_hj_i~0#1) && (1 == main_~_ha_hashv~0#1 / 8 || 0 == main_~_ha_hashv~0#1 / 8) then (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 8 then 0 else 1) else (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 8 else (if 0 == main_~_ha_hashv~0#1 / 8 then main_~_hj_i~0#1 else ~bitwiseXOr(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if (1 == main_~_hj_j~0#1 || 0 == main_~_hj_j~0#1) && (1 == 1024 * main_~_hj_i~0#1 || 0 == 1024 * main_~_hj_i~0#1) then (if main_~_hj_j~0#1 == 1024 * main_~_hj_i~0#1 then 0 else 1) else (if 0 == main_~_hj_j~0#1 then 1024 * main_~_hj_i~0#1 else (if 0 == 1024 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else ~bitwiseXOr(main_~_hj_j~0#1, 1024 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if (1 == main_~_ha_hashv~0#1 || 0 == main_~_ha_hashv~0#1) && (1 == main_~_hj_j~0#1 / 32768 || 0 == main_~_hj_j~0#1 / 32768) then (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 32768 then 0 else 1) else (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 32768 else (if 0 == main_~_hj_j~0#1 / 32768 then main_~_ha_hashv~0#1 else ~bitwiseXOr(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32768)))); 526#L996-44 goto; 616#L996-46 goto; 631#L996-48 goto; 657#L996-116 call write~int(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4); 658#L996-51 assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem86#1.base, main_#t~mem86#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_#t~mem86#1.base, main_#t~mem86#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem86#1.base, main_#t~mem86#1.offset; 580#L996-63 call write~$Pointer$(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$(main_#t~mem87#1.base, 16 + main_#t~mem87#1.offset, 4);call main_#t~mem89#1.base, main_#t~mem89#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem90#1 := read~int(main_#t~mem89#1.base, 20 + main_#t~mem89#1.offset, 4);call write~$Pointer$(main_#t~mem88#1.base, main_#t~mem88#1.offset - main_#t~mem90#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;havoc main_#t~mem89#1.base, main_#t~mem89#1.offset;havoc main_#t~mem90#1;call main_#t~mem91#1.base, main_#t~mem91#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem92#1.base, main_#t~mem92#1.offset := read~$Pointer$(main_#t~mem91#1.base, 16 + main_#t~mem91#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem92#1.base, 8 + main_#t~mem92#1.offset, 4);havoc main_#t~mem91#1.base, main_#t~mem91#1.offset;havoc main_#t~mem92#1.base, main_#t~mem92#1.offset;call main_#t~mem93#1.base, main_#t~mem93#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem93#1.base, 16 + main_#t~mem93#1.offset, 4);havoc main_#t~mem93#1.base, main_#t~mem93#1.offset; 581#L996-62 goto; 528#L996-114 havoc main_~_ha_bkt~0#1;call main_#t~mem94#1.base, main_#t~mem94#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem95#1 := read~int(main_#t~mem94#1.base, 12 + main_#t~mem94#1.offset, 4);main_#t~post96#1 := main_#t~mem95#1;call write~int(1 + main_#t~post96#1, main_#t~mem94#1.base, 12 + main_#t~mem94#1.offset, 4);havoc main_#t~mem94#1.base, main_#t~mem94#1.offset;havoc main_#t~mem95#1;havoc main_#t~post96#1; 569#L996-67 call main_#t~mem97#1.base, main_#t~mem97#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem98#1 := read~int(main_#t~mem97#1.base, 4 + main_#t~mem97#1.offset, 4);main_~_ha_bkt~0#1 := (if 0 == main_~_ha_hashv~0#1 || 0 == main_#t~mem98#1 - 1 then 0 else (if 1 == main_#t~mem98#1 - 1 then (if 1 == main_~_ha_hashv~0#1 || 0 == main_~_ha_hashv~0#1 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 >= 0 then main_~_ha_hashv~0#1 % 2 else ~bitwiseAnd(main_~_ha_hashv~0#1, main_#t~mem98#1 - 1))) else (if 1 == main_~_ha_hashv~0#1 then (if 1 == main_#t~mem98#1 - 1 || 0 == main_#t~mem98#1 - 1 then main_#t~mem98#1 - 1 else (if main_#t~mem98#1 - 1 >= 0 then (main_#t~mem98#1 - 1) % 2 else ~bitwiseAnd(main_~_ha_hashv~0#1, main_#t~mem98#1 - 1))) else ~bitwiseAnd(main_~_ha_hashv~0#1, main_#t~mem98#1 - 1))));havoc main_#t~mem97#1.base, main_#t~mem97#1.offset;havoc main_#t~mem98#1; 627#L996-66 goto; 663#L996-112 call main_#t~mem99#1.base, main_#t~mem99#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem100#1.base, main_#t~mem100#1.offset := read~$Pointer$(main_#t~mem99#1.base, main_#t~mem99#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem100#1.base, main_#t~mem100#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem99#1.base, main_#t~mem99#1.offset;havoc main_#t~mem100#1.base, main_#t~mem100#1.offset;call main_#t~mem101#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post102#1 := main_#t~mem101#1;call write~int(1 + main_#t~post102#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem101#1;havoc main_#t~post102#1;call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_#t~mem103#1.base, main_#t~mem103#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;call write~$Pointer$(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4); 653#L996-69 assume main_#t~mem104#1.base != 0 || main_#t~mem104#1.offset != 0;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem105#1.base, 12 + main_#t~mem105#1.offset, 4);havoc main_#t~mem105#1.base, main_#t~mem105#1.offset; 499#L996-71 call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem107#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem106#1 := read~int(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short110#1 := main_#t~mem107#1 % 4294967296 >= 10 * (1 + main_#t~mem106#1) % 4294967296; 500#L996-72 assume main_#t~short110#1;call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem109#1 := read~int(main_#t~mem108#1.base, 36 + main_#t~mem108#1.offset, 4);main_#t~short110#1 := 0 == main_#t~mem109#1 % 4294967296; 558#L996-74 assume !main_#t~short110#1;havoc main_#t~mem107#1;havoc main_#t~mem106#1;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;havoc main_#t~mem109#1;havoc main_#t~short110#1; 518#L996-111 goto; 513#L996-113 goto; 514#L996-115 goto; 624#L996-117 goto; 625#L989-3 call main_#t~mem40#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post41#1 := main_#t~mem40#1;call write~int(1 + main_#t~post41#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem40#1;havoc main_#t~post41#1; 479#L989-4 [2022-10-17 10:37:21,682 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:37:21,682 INFO L85 PathProgramCache]: Analyzing trace with hash 1251, now seen corresponding path program 2 times [2022-10-17 10:37:21,683 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:37:21,683 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1029806152] [2022-10-17 10:37:21,683 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:37:21,683 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:37:21,726 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:37:21,727 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:37:21,743 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:37:21,757 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:37:21,758 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:37:21,758 INFO L85 PathProgramCache]: Analyzing trace with hash 1942584983, now seen corresponding path program 1 times [2022-10-17 10:37:21,758 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:37:21,759 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1229137210] [2022-10-17 10:37:21,759 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:37:21,759 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:37:22,002 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-10-17 10:37:22,003 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1431993333] [2022-10-17 10:37:22,003 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:37:22,003 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 10:37:22,003 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_42b4b8d7-ef45-46b3-ab68-f03ee3b0d7ca/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:37:22,006 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_42b4b8d7-ef45-46b3-ab68-f03ee3b0d7ca/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 10:37:22,048 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_42b4b8d7-ef45-46b3-ab68-f03ee3b0d7ca/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2022-10-17 10:37:22,875 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:37:22,887 INFO L263 TraceCheckSpWp]: Trace formula consists of 1858 conjuncts, 3 conjunts are in the unsatisfiable core [2022-10-17 10:37:22,892 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:37:22,939 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:37:22,939 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-10-17 10:37:22,940 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:37:22,940 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1229137210] [2022-10-17 10:37:22,940 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-10-17 10:37:22,940 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1431993333] [2022-10-17 10:37:22,941 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1431993333] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:37:22,941 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:37:22,945 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:37:22,945 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [882511989] [2022-10-17 10:37:22,946 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:37:22,947 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:37:22,947 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:37:22,948 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:37:22,949 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:37:22,950 INFO L87 Difference]: Start difference. First operand 206 states and 264 transitions. cyclomatic complexity: 61 Second operand has 3 states, 3 states have (on average 17.666666666666668) internal successors, (53), 3 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:37:23,089 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:37:23,090 INFO L93 Difference]: Finished difference Result 227 states and 285 transitions. [2022-10-17 10:37:23,090 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 227 states and 285 transitions. [2022-10-17 10:37:23,092 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 220 [2022-10-17 10:37:23,096 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 227 states to 227 states and 285 transitions. [2022-10-17 10:37:23,096 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 227 [2022-10-17 10:37:23,096 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 227 [2022-10-17 10:37:23,097 INFO L73 IsDeterministic]: Start isDeterministic. Operand 227 states and 285 transitions. [2022-10-17 10:37:23,108 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:37:23,108 INFO L218 hiAutomatonCegarLoop]: Abstraction has 227 states and 285 transitions. [2022-10-17 10:37:23,111 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 227 states and 285 transitions. [2022-10-17 10:37:23,128 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 227 to 226. [2022-10-17 10:37:23,128 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 226 states, 222 states have (on average 1.2522522522522523) internal successors, (278), 221 states have internal predecessors, (278), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-10-17 10:37:23,130 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 226 states to 226 states and 284 transitions. [2022-10-17 10:37:23,130 INFO L240 hiAutomatonCegarLoop]: Abstraction has 226 states and 284 transitions. [2022-10-17 10:37:23,132 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:37:23,133 INFO L428 stractBuchiCegarLoop]: Abstraction has 226 states and 284 transitions. [2022-10-17 10:37:23,133 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-10-17 10:37:23,135 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 226 states and 284 transitions. [2022-10-17 10:37:23,137 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 219 [2022-10-17 10:37:23,137 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:37:23,137 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:37:23,141 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-10-17 10:37:23,141 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:37:23,141 INFO L748 eck$LassoCheckResult]: Stem: 1269#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call #Ultimate.allocInit(40, 3);#memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, ~#alt_malloc_sizes~0.base);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0; 1245#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret43#1.base, main_#t~ret43#1.offset, main_#t~mem44#1, main_#t~mem45#1, main_#t~mem46#1, main_#t~mem48#1, main_#t~mem47#1, main_#t~mem49#1, main_#t~mem50#1, main_#t~mem52#1, main_#t~mem51#1, main_#t~mem53#1, main_#t~mem54#1, main_#t~mem56#1, main_#t~mem55#1, main_#t~mem57#1, main_#t~mem58#1, main_#t~switch59#1, main_#t~mem60#1, main_#t~mem61#1, main_#t~mem62#1, main_#t~mem63#1, main_#t~mem64#1, main_#t~mem65#1, main_#t~mem66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret71#1.base, main_#t~ret71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1.base, main_#t~mem78#1.offset, main_#t~ret79#1.base, main_#t~ret79#1.offset, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1.base, main_#t~mem82#1.offset, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~mem95#1, main_#t~post96#1, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1, main_#t~post102#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem107#1, main_#t~mem106#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~short110#1, main_#t~mem111#1.base, main_#t~mem111#1.offset, main_#t~mem112#1, main_#t~ret113#1.base, main_#t~ret113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem122#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem126#1, main_#t~mem124#1.base, main_#t~mem124#1.offset, main_#t~mem125#1, main_#t~ite127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem138#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem140#1, main_#t~pre141#1, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1, main_#t~post146#1, main_#t~mem150#1, main_#t~mem148#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem149#1, main_#t~mem151#1, main_#t~post152#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_#t~mem155#1.base, main_#t~mem155#1.offset, main_#t~post129#1, main_#t~mem130#1.base, main_#t~mem130#1.offset, main_#t~mem131#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_#t~mem159#1, main_#t~mem160#1.base, main_#t~mem160#1.offset, main_#t~mem161#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem163#1, main_#t~post164#1, main_#t~mem165#1.base, main_#t~mem165#1.offset, main_#t~mem166#1.base, main_#t~mem166#1.offset, main_#t~mem167#1.base, main_#t~mem167#1.offset, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem171#1, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1, main_#t~ite174#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1, main_#t~mem175#1.base, main_#t~mem175#1.offset, main_#t~mem176#1, main_#t~mem177#1.base, main_#t~mem177#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~#_he_new_buckets~0#1.base, main_~#_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem40#1, main_#t~post41#1, main_#t~mem42#1, main_#t~mem182#1, main_#t~mem181#1, main_#t~mem183#1, main_#t~mem184#1, main_#t~mem186#1, main_#t~mem185#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem190#1, main_#t~mem189#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~switch193#1, main_#t~mem194#1, main_#t~mem195#1, main_#t~mem196#1, main_#t~mem197#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem200#1, main_#t~mem201#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem204#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem205#1.base, main_#t~mem205#1.offset, main_#t~mem206#1, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1.base, main_#t~mem212#1.offset, main_#t~mem213#1.base, main_#t~mem213#1.offset, main_#t~mem214#1, main_#t~mem215#1, main_#t~mem216#1, main_#t~short217#1, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~ret219#1, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1.base, main_#t~mem221#1.offset, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~mem225#1.base, main_#t~mem225#1.offset, main_#t~short226#1, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~mem228#1.base, main_#t~mem228#1.offset, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1.base, main_#t~mem233#1.offset, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1.base, main_#t~mem239#1.offset, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1, main_#t~mem248#1.base, main_#t~mem248#1.offset, main_#t~mem251#1, main_#t~mem249#1.base, main_#t~mem249#1.offset, main_#t~mem250#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~mem253#1.base, main_#t~mem253#1.offset, main_#t~mem254#1, main_#t~post255#1, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem264#1.base, main_#t~mem264#1.offset, main_#t~mem265#1, main_#t~post266#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem178#1, main_#t~post179#1, main_#t~mem180#1, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4); 1074#L989-4 [2022-10-17 10:37:23,143 INFO L750 eck$LassoCheckResult]: Loop: 1074#L989-4 call main_#t~mem42#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4); 1065#L989-1 assume !!(main_#t~mem42#1 < 10);havoc main_#t~mem42#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset; 1067#L979 main_#t~ret43#1.base, main_#t~ret43#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret43#1.base, main_#t~ret43#1.offset;havoc main_#t~ret43#1.base, main_#t~ret43#1.offset; 1075#L991 assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0); 1076#L991-2 call main_#t~mem44#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int(main_#t~mem44#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem44#1;call main_#t~mem45#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem46#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int(main_#t~mem45#1 * main_#t~mem46#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem45#1;havoc main_#t~mem46#1; 1191#L996-118 havoc main_~_ha_hashv~0#1; 1235#L996-49 goto; 1236#L996-47 havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4; 1069#L996-8 assume !(main_~_hj_k~0#1 % 4294967296 >= 12); 1093#L996-9 main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch59#1 := 11 == main_~_hj_k~0#1; 1263#L996-10 assume main_#t~switch59#1;call main_#t~mem60#1 := read~int(main_~_hj_key~0#1.base, 10 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 16777216 * (main_#t~mem60#1 % 256);havoc main_#t~mem60#1; 1267#L996-12 main_#t~switch59#1 := main_#t~switch59#1 || 10 == main_~_hj_k~0#1; 1165#L996-13 assume main_#t~switch59#1;call main_#t~mem61#1 := read~int(main_~_hj_key~0#1.base, 9 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 65536 * (main_#t~mem61#1 % 256);havoc main_#t~mem61#1; 1166#L996-15 main_#t~switch59#1 := main_#t~switch59#1 || 9 == main_~_hj_k~0#1; 1264#L996-16 assume main_#t~switch59#1;call main_#t~mem62#1 := read~int(main_~_hj_key~0#1.base, 8 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 256 * (main_#t~mem62#1 % 256);havoc main_#t~mem62#1; 1265#L996-18 main_#t~switch59#1 := main_#t~switch59#1 || 8 == main_~_hj_k~0#1; 1255#L996-19 assume main_#t~switch59#1;call main_#t~mem63#1 := read~int(main_~_hj_key~0#1.base, 7 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 16777216 * (main_#t~mem63#1 % 256);havoc main_#t~mem63#1; 1251#L996-21 main_#t~switch59#1 := main_#t~switch59#1 || 7 == main_~_hj_k~0#1; 1232#L996-22 assume main_#t~switch59#1;call main_#t~mem64#1 := read~int(main_~_hj_key~0#1.base, 6 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 65536 * (main_#t~mem64#1 % 256);havoc main_#t~mem64#1; 1233#L996-24 main_#t~switch59#1 := main_#t~switch59#1 || 6 == main_~_hj_k~0#1; 1248#L996-25 assume main_#t~switch59#1;call main_#t~mem65#1 := read~int(main_~_hj_key~0#1.base, 5 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 256 * (main_#t~mem65#1 % 256);havoc main_#t~mem65#1; 1226#L996-27 main_#t~switch59#1 := main_#t~switch59#1 || 5 == main_~_hj_k~0#1; 1070#L996-28 assume main_#t~switch59#1;call main_#t~mem66#1 := read~int(main_~_hj_key~0#1.base, 4 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + main_#t~mem66#1 % 256;havoc main_#t~mem66#1; 1071#L996-30 main_#t~switch59#1 := main_#t~switch59#1 || 4 == main_~_hj_k~0#1; 1199#L996-31 assume main_#t~switch59#1;call main_#t~mem67#1 := read~int(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem67#1 % 256);havoc main_#t~mem67#1; 1217#L996-33 main_#t~switch59#1 := main_#t~switch59#1 || 3 == main_~_hj_k~0#1; 1186#L996-34 assume main_#t~switch59#1;call main_#t~mem68#1 := read~int(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem68#1 % 256);havoc main_#t~mem68#1; 1187#L996-36 main_#t~switch59#1 := main_#t~switch59#1 || 2 == main_~_hj_k~0#1; 1148#L996-37 assume main_#t~switch59#1;call main_#t~mem69#1 := read~int(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem69#1 % 256);havoc main_#t~mem69#1; 1149#L996-39 main_#t~switch59#1 := main_#t~switch59#1 || 1 == main_~_hj_k~0#1; 1256#L996-40 assume main_#t~switch59#1;call main_#t~mem70#1 := read~int(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + main_#t~mem70#1 % 256;havoc main_#t~mem70#1; 1200#L996-42 havoc main_#t~switch59#1; 1120#L996-45 main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if (1 == main_~_hj_i~0#1 || 0 == main_~_hj_i~0#1) && (1 == main_~_ha_hashv~0#1 / 8192 || 0 == main_~_ha_hashv~0#1 / 8192) then (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 8192 then 0 else 1) else (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 8192 else (if 0 == main_~_ha_hashv~0#1 / 8192 then main_~_hj_i~0#1 else ~bitwiseXOr(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8192))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if (1 == main_~_hj_j~0#1 || 0 == main_~_hj_j~0#1) && (1 == 256 * main_~_hj_i~0#1 || 0 == 256 * main_~_hj_i~0#1) then (if main_~_hj_j~0#1 == 256 * main_~_hj_i~0#1 then 0 else 1) else (if 0 == main_~_hj_j~0#1 then 256 * main_~_hj_i~0#1 else (if 0 == 256 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else ~bitwiseXOr(main_~_hj_j~0#1, 256 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if (1 == main_~_ha_hashv~0#1 || 0 == main_~_ha_hashv~0#1) && (1 == main_~_hj_j~0#1 / 8192 || 0 == main_~_hj_j~0#1 / 8192) then (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 8192 then 0 else 1) else (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 8192 else (if 0 == main_~_hj_j~0#1 / 8192 then main_~_ha_hashv~0#1 else ~bitwiseXOr(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 8192))));main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if (1 == main_~_hj_i~0#1 || 0 == main_~_hj_i~0#1) && (1 == main_~_ha_hashv~0#1 / 4096 || 0 == main_~_ha_hashv~0#1 / 4096) then (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 4096 then 0 else 1) else (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 4096 else (if 0 == main_~_ha_hashv~0#1 / 4096 then main_~_hj_i~0#1 else ~bitwiseXOr(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 4096))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if (1 == main_~_hj_j~0#1 || 0 == main_~_hj_j~0#1) && (1 == 65536 * main_~_hj_i~0#1 || 0 == 65536 * main_~_hj_i~0#1) then (if main_~_hj_j~0#1 == 65536 * main_~_hj_i~0#1 then 0 else 1) else (if 0 == main_~_hj_j~0#1 then 65536 * main_~_hj_i~0#1 else (if 0 == 65536 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else ~bitwiseXOr(main_~_hj_j~0#1, 65536 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if (1 == main_~_ha_hashv~0#1 || 0 == main_~_ha_hashv~0#1) && (1 == main_~_hj_j~0#1 / 32 || 0 == main_~_hj_j~0#1 / 32) then (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 32 then 0 else 1) else (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 32 else (if 0 == main_~_hj_j~0#1 / 32 then main_~_ha_hashv~0#1 else ~bitwiseXOr(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32))));main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if (1 == main_~_hj_i~0#1 || 0 == main_~_hj_i~0#1) && (1 == main_~_ha_hashv~0#1 / 8 || 0 == main_~_ha_hashv~0#1 / 8) then (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 8 then 0 else 1) else (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 8 else (if 0 == main_~_ha_hashv~0#1 / 8 then main_~_hj_i~0#1 else ~bitwiseXOr(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if (1 == main_~_hj_j~0#1 || 0 == main_~_hj_j~0#1) && (1 == 1024 * main_~_hj_i~0#1 || 0 == 1024 * main_~_hj_i~0#1) then (if main_~_hj_j~0#1 == 1024 * main_~_hj_i~0#1 then 0 else 1) else (if 0 == main_~_hj_j~0#1 then 1024 * main_~_hj_i~0#1 else (if 0 == 1024 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else ~bitwiseXOr(main_~_hj_j~0#1, 1024 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if (1 == main_~_ha_hashv~0#1 || 0 == main_~_ha_hashv~0#1) && (1 == main_~_hj_j~0#1 / 32768 || 0 == main_~_hj_j~0#1 / 32768) then (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 32768 then 0 else 1) else (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 32768 else (if 0 == main_~_hj_j~0#1 / 32768 then main_~_ha_hashv~0#1 else ~bitwiseXOr(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32768)))); 1121#L996-44 goto; 1212#L996-46 goto; 1227#L996-48 goto; 1253#L996-116 call write~int(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4); 1254#L996-51 assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem86#1.base, main_#t~mem86#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_#t~mem86#1.base, main_#t~mem86#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem86#1.base, main_#t~mem86#1.offset; 1177#L996-63 call write~$Pointer$(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$(main_#t~mem87#1.base, 16 + main_#t~mem87#1.offset, 4);call main_#t~mem89#1.base, main_#t~mem89#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem90#1 := read~int(main_#t~mem89#1.base, 20 + main_#t~mem89#1.offset, 4);call write~$Pointer$(main_#t~mem88#1.base, main_#t~mem88#1.offset - main_#t~mem90#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;havoc main_#t~mem89#1.base, main_#t~mem89#1.offset;havoc main_#t~mem90#1;call main_#t~mem91#1.base, main_#t~mem91#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem92#1.base, main_#t~mem92#1.offset := read~$Pointer$(main_#t~mem91#1.base, 16 + main_#t~mem91#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem92#1.base, 8 + main_#t~mem92#1.offset, 4);havoc main_#t~mem91#1.base, main_#t~mem91#1.offset;havoc main_#t~mem92#1.base, main_#t~mem92#1.offset;call main_#t~mem93#1.base, main_#t~mem93#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem93#1.base, 16 + main_#t~mem93#1.offset, 4);havoc main_#t~mem93#1.base, main_#t~mem93#1.offset; 1178#L996-62 goto; 1123#L996-114 havoc main_~_ha_bkt~0#1;call main_#t~mem94#1.base, main_#t~mem94#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem95#1 := read~int(main_#t~mem94#1.base, 12 + main_#t~mem94#1.offset, 4);main_#t~post96#1 := main_#t~mem95#1;call write~int(1 + main_#t~post96#1, main_#t~mem94#1.base, 12 + main_#t~mem94#1.offset, 4);havoc main_#t~mem94#1.base, main_#t~mem94#1.offset;havoc main_#t~mem95#1;havoc main_#t~post96#1; 1164#L996-67 call main_#t~mem97#1.base, main_#t~mem97#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem98#1 := read~int(main_#t~mem97#1.base, 4 + main_#t~mem97#1.offset, 4);main_~_ha_bkt~0#1 := (if 0 == main_~_ha_hashv~0#1 || 0 == main_#t~mem98#1 - 1 then 0 else (if 1 == main_#t~mem98#1 - 1 then (if 1 == main_~_ha_hashv~0#1 || 0 == main_~_ha_hashv~0#1 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 >= 0 then main_~_ha_hashv~0#1 % 2 else ~bitwiseAnd(main_~_ha_hashv~0#1, main_#t~mem98#1 - 1))) else (if 1 == main_~_ha_hashv~0#1 then (if 1 == main_#t~mem98#1 - 1 || 0 == main_#t~mem98#1 - 1 then main_#t~mem98#1 - 1 else (if main_#t~mem98#1 - 1 >= 0 then (main_#t~mem98#1 - 1) % 2 else ~bitwiseAnd(main_~_ha_hashv~0#1, main_#t~mem98#1 - 1))) else ~bitwiseAnd(main_~_ha_hashv~0#1, main_#t~mem98#1 - 1))));havoc main_#t~mem97#1.base, main_#t~mem97#1.offset;havoc main_#t~mem98#1; 1223#L996-66 goto; 1260#L996-112 call main_#t~mem99#1.base, main_#t~mem99#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem100#1.base, main_#t~mem100#1.offset := read~$Pointer$(main_#t~mem99#1.base, main_#t~mem99#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem100#1.base, main_#t~mem100#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem99#1.base, main_#t~mem99#1.offset;havoc main_#t~mem100#1.base, main_#t~mem100#1.offset;call main_#t~mem101#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post102#1 := main_#t~mem101#1;call write~int(1 + main_#t~post102#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem101#1;havoc main_#t~post102#1;call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_#t~mem103#1.base, main_#t~mem103#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;call write~$Pointer$(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4); 1249#L996-69 assume main_#t~mem104#1.base != 0 || main_#t~mem104#1.offset != 0;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem105#1.base, 12 + main_#t~mem105#1.offset, 4);havoc main_#t~mem105#1.base, main_#t~mem105#1.offset; 1094#L996-71 call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem107#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem106#1 := read~int(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short110#1 := main_#t~mem107#1 % 4294967296 >= 10 * (1 + main_#t~mem106#1) % 4294967296; 1095#L996-72 assume main_#t~short110#1;call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem109#1 := read~int(main_#t~mem108#1.base, 36 + main_#t~mem108#1.offset, 4);main_#t~short110#1 := 0 == main_#t~mem109#1 % 4294967296; 1153#L996-74 assume !main_#t~short110#1;havoc main_#t~mem107#1;havoc main_#t~mem106#1;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;havoc main_#t~mem109#1;havoc main_#t~short110#1; 1111#L996-111 goto; 1108#L996-113 goto; 1109#L996-115 goto; 1220#L996-117 goto; 1221#L989-3 call main_#t~mem40#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post41#1 := main_#t~mem40#1;call write~int(1 + main_#t~post41#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem40#1;havoc main_#t~post41#1; 1074#L989-4 [2022-10-17 10:37:23,149 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:37:23,149 INFO L85 PathProgramCache]: Analyzing trace with hash 1251, now seen corresponding path program 3 times [2022-10-17 10:37:23,149 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:37:23,149 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [74121504] [2022-10-17 10:37:23,149 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:37:23,150 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:37:23,200 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:37:23,200 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:37:23,212 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:37:23,237 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:37:23,237 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:37:23,237 INFO L85 PathProgramCache]: Analyzing trace with hash 1240985109, now seen corresponding path program 1 times [2022-10-17 10:37:23,238 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:37:23,238 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2129437093] [2022-10-17 10:37:23,238 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:37:23,239 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:37:23,412 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-10-17 10:37:23,412 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1450973296] [2022-10-17 10:37:23,412 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:37:23,413 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 10:37:23,413 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_42b4b8d7-ef45-46b3-ab68-f03ee3b0d7ca/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:37:23,417 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_42b4b8d7-ef45-46b3-ab68-f03ee3b0d7ca/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 10:37:23,437 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_42b4b8d7-ef45-46b3-ab68-f03ee3b0d7ca/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2022-10-17 10:37:24,274 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:37:24,288 INFO L263 TraceCheckSpWp]: Trace formula consists of 1864 conjuncts, 3 conjunts are in the unsatisfiable core [2022-10-17 10:37:24,301 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:37:24,347 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:37:24,347 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-10-17 10:37:24,347 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:37:24,348 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2129437093] [2022-10-17 10:37:24,348 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-10-17 10:37:24,348 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1450973296] [2022-10-17 10:37:24,348 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1450973296] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:37:24,348 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:37:24,349 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-10-17 10:37:24,349 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [178526987] [2022-10-17 10:37:24,349 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:37:24,360 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:37:24,360 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:37:24,361 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-10-17 10:37:24,361 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-10-17 10:37:24,361 INFO L87 Difference]: Start difference. First operand 226 states and 284 transitions. cyclomatic complexity: 61 Second operand has 4 states, 4 states have (on average 13.25) internal successors, (53), 4 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:37:24,485 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:37:24,485 INFO L93 Difference]: Finished difference Result 310 states and 389 transitions. [2022-10-17 10:37:24,485 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 310 states and 389 transitions. [2022-10-17 10:37:24,489 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 294 [2022-10-17 10:37:24,493 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 310 states to 310 states and 389 transitions. [2022-10-17 10:37:24,493 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 310 [2022-10-17 10:37:24,494 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 310 [2022-10-17 10:37:24,494 INFO L73 IsDeterministic]: Start isDeterministic. Operand 310 states and 389 transitions. [2022-10-17 10:37:24,495 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:37:24,495 INFO L218 hiAutomatonCegarLoop]: Abstraction has 310 states and 389 transitions. [2022-10-17 10:37:24,496 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 310 states and 389 transitions. [2022-10-17 10:37:24,502 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 310 to 212. [2022-10-17 10:37:24,503 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 212 states, 208 states have (on average 1.2355769230769231) internal successors, (257), 207 states have internal predecessors, (257), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-10-17 10:37:24,505 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 212 states to 212 states and 263 transitions. [2022-10-17 10:37:24,505 INFO L240 hiAutomatonCegarLoop]: Abstraction has 212 states and 263 transitions. [2022-10-17 10:37:24,505 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-10-17 10:37:24,506 INFO L428 stractBuchiCegarLoop]: Abstraction has 212 states and 263 transitions. [2022-10-17 10:37:24,506 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-10-17 10:37:24,506 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 212 states and 263 transitions. [2022-10-17 10:37:24,508 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 205 [2022-10-17 10:37:24,508 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:37:24,508 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:37:24,509 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-10-17 10:37:24,509 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:37:24,510 INFO L748 eck$LassoCheckResult]: Stem: 1971#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call #Ultimate.allocInit(40, 3);#memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, ~#alt_malloc_sizes~0.base);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0; 1947#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret43#1.base, main_#t~ret43#1.offset, main_#t~mem44#1, main_#t~mem45#1, main_#t~mem46#1, main_#t~mem48#1, main_#t~mem47#1, main_#t~mem49#1, main_#t~mem50#1, main_#t~mem52#1, main_#t~mem51#1, main_#t~mem53#1, main_#t~mem54#1, main_#t~mem56#1, main_#t~mem55#1, main_#t~mem57#1, main_#t~mem58#1, main_#t~switch59#1, main_#t~mem60#1, main_#t~mem61#1, main_#t~mem62#1, main_#t~mem63#1, main_#t~mem64#1, main_#t~mem65#1, main_#t~mem66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret71#1.base, main_#t~ret71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1.base, main_#t~mem78#1.offset, main_#t~ret79#1.base, main_#t~ret79#1.offset, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1.base, main_#t~mem82#1.offset, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~mem95#1, main_#t~post96#1, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1, main_#t~post102#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem107#1, main_#t~mem106#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~short110#1, main_#t~mem111#1.base, main_#t~mem111#1.offset, main_#t~mem112#1, main_#t~ret113#1.base, main_#t~ret113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem122#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem126#1, main_#t~mem124#1.base, main_#t~mem124#1.offset, main_#t~mem125#1, main_#t~ite127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem138#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem140#1, main_#t~pre141#1, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1, main_#t~post146#1, main_#t~mem150#1, main_#t~mem148#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem149#1, main_#t~mem151#1, main_#t~post152#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_#t~mem155#1.base, main_#t~mem155#1.offset, main_#t~post129#1, main_#t~mem130#1.base, main_#t~mem130#1.offset, main_#t~mem131#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_#t~mem159#1, main_#t~mem160#1.base, main_#t~mem160#1.offset, main_#t~mem161#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem163#1, main_#t~post164#1, main_#t~mem165#1.base, main_#t~mem165#1.offset, main_#t~mem166#1.base, main_#t~mem166#1.offset, main_#t~mem167#1.base, main_#t~mem167#1.offset, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem171#1, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1, main_#t~ite174#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1, main_#t~mem175#1.base, main_#t~mem175#1.offset, main_#t~mem176#1, main_#t~mem177#1.base, main_#t~mem177#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~#_he_new_buckets~0#1.base, main_~#_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem40#1, main_#t~post41#1, main_#t~mem42#1, main_#t~mem182#1, main_#t~mem181#1, main_#t~mem183#1, main_#t~mem184#1, main_#t~mem186#1, main_#t~mem185#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem190#1, main_#t~mem189#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~switch193#1, main_#t~mem194#1, main_#t~mem195#1, main_#t~mem196#1, main_#t~mem197#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem200#1, main_#t~mem201#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem204#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem205#1.base, main_#t~mem205#1.offset, main_#t~mem206#1, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1.base, main_#t~mem212#1.offset, main_#t~mem213#1.base, main_#t~mem213#1.offset, main_#t~mem214#1, main_#t~mem215#1, main_#t~mem216#1, main_#t~short217#1, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~ret219#1, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1.base, main_#t~mem221#1.offset, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~mem225#1.base, main_#t~mem225#1.offset, main_#t~short226#1, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~mem228#1.base, main_#t~mem228#1.offset, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1.base, main_#t~mem233#1.offset, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1.base, main_#t~mem239#1.offset, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1, main_#t~mem248#1.base, main_#t~mem248#1.offset, main_#t~mem251#1, main_#t~mem249#1.base, main_#t~mem249#1.offset, main_#t~mem250#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~mem253#1.base, main_#t~mem253#1.offset, main_#t~mem254#1, main_#t~post255#1, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem264#1.base, main_#t~mem264#1.offset, main_#t~mem265#1, main_#t~post266#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem178#1, main_#t~post179#1, main_#t~mem180#1, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4); 1775#L989-4 [2022-10-17 10:37:24,510 INFO L750 eck$LassoCheckResult]: Loop: 1775#L989-4 call main_#t~mem42#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4); 1766#L989-1 assume !!(main_#t~mem42#1 < 10);havoc main_#t~mem42#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset; 1768#L979 main_#t~ret43#1.base, main_#t~ret43#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret43#1.base, main_#t~ret43#1.offset;havoc main_#t~ret43#1.base, main_#t~ret43#1.offset; 1776#L991 assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0); 1777#L991-2 call main_#t~mem44#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int(main_#t~mem44#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem44#1;call main_#t~mem45#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem46#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int(main_#t~mem45#1 * main_#t~mem46#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem45#1;havoc main_#t~mem46#1; 1892#L996-118 havoc main_~_ha_hashv~0#1; 1937#L996-49 goto; 1938#L996-47 havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4; 1770#L996-8 assume !(main_~_hj_k~0#1 % 4294967296 >= 12); 1796#L996-9 main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch59#1 := 11 == main_~_hj_k~0#1; 1965#L996-10 assume !main_#t~switch59#1; 1970#L996-12 main_#t~switch59#1 := main_#t~switch59#1 || 10 == main_~_hj_k~0#1; 1866#L996-13 assume !main_#t~switch59#1; 1867#L996-15 main_#t~switch59#1 := main_#t~switch59#1 || 9 == main_~_hj_k~0#1; 1967#L996-16 assume !main_#t~switch59#1; 1968#L996-18 main_#t~switch59#1 := main_#t~switch59#1 || 8 == main_~_hj_k~0#1; 1957#L996-19 assume !main_#t~switch59#1; 1953#L996-21 main_#t~switch59#1 := main_#t~switch59#1 || 7 == main_~_hj_k~0#1; 1934#L996-22 assume !main_#t~switch59#1; 1935#L996-24 main_#t~switch59#1 := main_#t~switch59#1 || 6 == main_~_hj_k~0#1; 1950#L996-25 assume !main_#t~switch59#1; 1928#L996-27 main_#t~switch59#1 := main_#t~switch59#1 || 5 == main_~_hj_k~0#1; 1771#L996-28 assume !main_#t~switch59#1; 1772#L996-30 main_#t~switch59#1 := main_#t~switch59#1 || 4 == main_~_hj_k~0#1; 1900#L996-31 assume main_#t~switch59#1;call main_#t~mem67#1 := read~int(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem67#1 % 256);havoc main_#t~mem67#1; 1966#L996-33 main_#t~switch59#1 := main_#t~switch59#1 || 3 == main_~_hj_k~0#1; 1887#L996-34 assume main_#t~switch59#1;call main_#t~mem68#1 := read~int(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem68#1 % 256);havoc main_#t~mem68#1; 1888#L996-36 main_#t~switch59#1 := main_#t~switch59#1 || 2 == main_~_hj_k~0#1; 1849#L996-37 assume main_#t~switch59#1;call main_#t~mem69#1 := read~int(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem69#1 % 256);havoc main_#t~mem69#1; 1850#L996-39 main_#t~switch59#1 := main_#t~switch59#1 || 1 == main_~_hj_k~0#1; 1958#L996-40 assume main_#t~switch59#1;call main_#t~mem70#1 := read~int(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + main_#t~mem70#1 % 256;havoc main_#t~mem70#1; 1901#L996-42 havoc main_#t~switch59#1; 1821#L996-45 main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if (1 == main_~_hj_i~0#1 || 0 == main_~_hj_i~0#1) && (1 == main_~_ha_hashv~0#1 / 8192 || 0 == main_~_ha_hashv~0#1 / 8192) then (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 8192 then 0 else 1) else (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 8192 else (if 0 == main_~_ha_hashv~0#1 / 8192 then main_~_hj_i~0#1 else ~bitwiseXOr(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8192))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if (1 == main_~_hj_j~0#1 || 0 == main_~_hj_j~0#1) && (1 == 256 * main_~_hj_i~0#1 || 0 == 256 * main_~_hj_i~0#1) then (if main_~_hj_j~0#1 == 256 * main_~_hj_i~0#1 then 0 else 1) else (if 0 == main_~_hj_j~0#1 then 256 * main_~_hj_i~0#1 else (if 0 == 256 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else ~bitwiseXOr(main_~_hj_j~0#1, 256 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if (1 == main_~_ha_hashv~0#1 || 0 == main_~_ha_hashv~0#1) && (1 == main_~_hj_j~0#1 / 8192 || 0 == main_~_hj_j~0#1 / 8192) then (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 8192 then 0 else 1) else (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 8192 else (if 0 == main_~_hj_j~0#1 / 8192 then main_~_ha_hashv~0#1 else ~bitwiseXOr(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 8192))));main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if (1 == main_~_hj_i~0#1 || 0 == main_~_hj_i~0#1) && (1 == main_~_ha_hashv~0#1 / 4096 || 0 == main_~_ha_hashv~0#1 / 4096) then (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 4096 then 0 else 1) else (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 4096 else (if 0 == main_~_ha_hashv~0#1 / 4096 then main_~_hj_i~0#1 else ~bitwiseXOr(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 4096))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if (1 == main_~_hj_j~0#1 || 0 == main_~_hj_j~0#1) && (1 == 65536 * main_~_hj_i~0#1 || 0 == 65536 * main_~_hj_i~0#1) then (if main_~_hj_j~0#1 == 65536 * main_~_hj_i~0#1 then 0 else 1) else (if 0 == main_~_hj_j~0#1 then 65536 * main_~_hj_i~0#1 else (if 0 == 65536 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else ~bitwiseXOr(main_~_hj_j~0#1, 65536 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if (1 == main_~_ha_hashv~0#1 || 0 == main_~_ha_hashv~0#1) && (1 == main_~_hj_j~0#1 / 32 || 0 == main_~_hj_j~0#1 / 32) then (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 32 then 0 else 1) else (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 32 else (if 0 == main_~_hj_j~0#1 / 32 then main_~_ha_hashv~0#1 else ~bitwiseXOr(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32))));main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if (1 == main_~_hj_i~0#1 || 0 == main_~_hj_i~0#1) && (1 == main_~_ha_hashv~0#1 / 8 || 0 == main_~_ha_hashv~0#1 / 8) then (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 8 then 0 else 1) else (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 8 else (if 0 == main_~_ha_hashv~0#1 / 8 then main_~_hj_i~0#1 else ~bitwiseXOr(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if (1 == main_~_hj_j~0#1 || 0 == main_~_hj_j~0#1) && (1 == 1024 * main_~_hj_i~0#1 || 0 == 1024 * main_~_hj_i~0#1) then (if main_~_hj_j~0#1 == 1024 * main_~_hj_i~0#1 then 0 else 1) else (if 0 == main_~_hj_j~0#1 then 1024 * main_~_hj_i~0#1 else (if 0 == 1024 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else ~bitwiseXOr(main_~_hj_j~0#1, 1024 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if (1 == main_~_ha_hashv~0#1 || 0 == main_~_ha_hashv~0#1) && (1 == main_~_hj_j~0#1 / 32768 || 0 == main_~_hj_j~0#1 / 32768) then (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 32768 then 0 else 1) else (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 32768 else (if 0 == main_~_hj_j~0#1 / 32768 then main_~_ha_hashv~0#1 else ~bitwiseXOr(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32768)))); 1822#L996-44 goto; 1915#L996-46 goto; 1929#L996-48 goto; 1955#L996-116 call write~int(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4); 1956#L996-51 assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem86#1.base, main_#t~mem86#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_#t~mem86#1.base, main_#t~mem86#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem86#1.base, main_#t~mem86#1.offset; 1875#L996-63 call write~$Pointer$(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$(main_#t~mem87#1.base, 16 + main_#t~mem87#1.offset, 4);call main_#t~mem89#1.base, main_#t~mem89#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem90#1 := read~int(main_#t~mem89#1.base, 20 + main_#t~mem89#1.offset, 4);call write~$Pointer$(main_#t~mem88#1.base, main_#t~mem88#1.offset - main_#t~mem90#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;havoc main_#t~mem89#1.base, main_#t~mem89#1.offset;havoc main_#t~mem90#1;call main_#t~mem91#1.base, main_#t~mem91#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem92#1.base, main_#t~mem92#1.offset := read~$Pointer$(main_#t~mem91#1.base, 16 + main_#t~mem91#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem92#1.base, 8 + main_#t~mem92#1.offset, 4);havoc main_#t~mem91#1.base, main_#t~mem91#1.offset;havoc main_#t~mem92#1.base, main_#t~mem92#1.offset;call main_#t~mem93#1.base, main_#t~mem93#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem93#1.base, 16 + main_#t~mem93#1.offset, 4);havoc main_#t~mem93#1.base, main_#t~mem93#1.offset; 1876#L996-62 goto; 1824#L996-114 havoc main_~_ha_bkt~0#1;call main_#t~mem94#1.base, main_#t~mem94#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem95#1 := read~int(main_#t~mem94#1.base, 12 + main_#t~mem94#1.offset, 4);main_#t~post96#1 := main_#t~mem95#1;call write~int(1 + main_#t~post96#1, main_#t~mem94#1.base, 12 + main_#t~mem94#1.offset, 4);havoc main_#t~mem94#1.base, main_#t~mem94#1.offset;havoc main_#t~mem95#1;havoc main_#t~post96#1; 1863#L996-67 call main_#t~mem97#1.base, main_#t~mem97#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem98#1 := read~int(main_#t~mem97#1.base, 4 + main_#t~mem97#1.offset, 4);main_~_ha_bkt~0#1 := (if 0 == main_~_ha_hashv~0#1 || 0 == main_#t~mem98#1 - 1 then 0 else (if 1 == main_#t~mem98#1 - 1 then (if 1 == main_~_ha_hashv~0#1 || 0 == main_~_ha_hashv~0#1 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 >= 0 then main_~_ha_hashv~0#1 % 2 else ~bitwiseAnd(main_~_ha_hashv~0#1, main_#t~mem98#1 - 1))) else (if 1 == main_~_ha_hashv~0#1 then (if 1 == main_#t~mem98#1 - 1 || 0 == main_#t~mem98#1 - 1 then main_#t~mem98#1 - 1 else (if main_#t~mem98#1 - 1 >= 0 then (main_#t~mem98#1 - 1) % 2 else ~bitwiseAnd(main_~_ha_hashv~0#1, main_#t~mem98#1 - 1))) else ~bitwiseAnd(main_~_ha_hashv~0#1, main_#t~mem98#1 - 1))));havoc main_#t~mem97#1.base, main_#t~mem97#1.offset;havoc main_#t~mem98#1; 1925#L996-66 goto; 1961#L996-112 call main_#t~mem99#1.base, main_#t~mem99#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem100#1.base, main_#t~mem100#1.offset := read~$Pointer$(main_#t~mem99#1.base, main_#t~mem99#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem100#1.base, main_#t~mem100#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem99#1.base, main_#t~mem99#1.offset;havoc main_#t~mem100#1.base, main_#t~mem100#1.offset;call main_#t~mem101#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post102#1 := main_#t~mem101#1;call write~int(1 + main_#t~post102#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem101#1;havoc main_#t~post102#1;call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_#t~mem103#1.base, main_#t~mem103#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;call write~$Pointer$(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4); 1951#L996-69 assume main_#t~mem104#1.base != 0 || main_#t~mem104#1.offset != 0;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem105#1.base, 12 + main_#t~mem105#1.offset, 4);havoc main_#t~mem105#1.base, main_#t~mem105#1.offset; 1793#L996-71 call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem107#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem106#1 := read~int(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short110#1 := main_#t~mem107#1 % 4294967296 >= 10 * (1 + main_#t~mem106#1) % 4294967296; 1794#L996-72 assume main_#t~short110#1;call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem109#1 := read~int(main_#t~mem108#1.base, 36 + main_#t~mem108#1.offset, 4);main_#t~short110#1 := 0 == main_#t~mem109#1 % 4294967296; 1854#L996-74 assume !main_#t~short110#1;havoc main_#t~mem107#1;havoc main_#t~mem106#1;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;havoc main_#t~mem109#1;havoc main_#t~short110#1; 1814#L996-111 goto; 1809#L996-113 goto; 1810#L996-115 goto; 1920#L996-117 goto; 1921#L989-3 call main_#t~mem40#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post41#1 := main_#t~mem40#1;call write~int(1 + main_#t~post41#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem40#1;havoc main_#t~post41#1; 1775#L989-4 [2022-10-17 10:37:24,510 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:37:24,511 INFO L85 PathProgramCache]: Analyzing trace with hash 1251, now seen corresponding path program 4 times [2022-10-17 10:37:24,511 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:37:24,511 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1968581200] [2022-10-17 10:37:24,511 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:37:24,511 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:37:24,532 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:37:24,532 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:37:24,543 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:37:24,556 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:37:24,556 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:37:24,557 INFO L85 PathProgramCache]: Analyzing trace with hash -633389277, now seen corresponding path program 1 times [2022-10-17 10:37:24,557 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:37:24,557 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1073442207] [2022-10-17 10:37:24,557 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:37:24,558 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:37:24,748 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-10-17 10:37:24,749 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [970398059] [2022-10-17 10:37:24,749 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:37:24,749 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 10:37:24,749 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_42b4b8d7-ef45-46b3-ab68-f03ee3b0d7ca/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:37:24,751 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_42b4b8d7-ef45-46b3-ab68-f03ee3b0d7ca/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 10:37:24,769 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_42b4b8d7-ef45-46b3-ab68-f03ee3b0d7ca/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process