./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/termination-memory-alloca/Urban-2013WST-Fig2-modified1000-alloca.i --full-output --architecture 64bit
--------------------------------------------------------------------------------
Checking for termination
Using default analysis
Version 5e519f3a
Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96df67be-2121-48b2-a4fd-9c987158c42d/bin/uautomizer-Dbtcem3rbc/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96df67be-2121-48b2-a4fd-9c987158c42d/bin/uautomizer-Dbtcem3rbc/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96df67be-2121-48b2-a4fd-9c987158c42d/bin/uautomizer-Dbtcem3rbc/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96df67be-2121-48b2-a4fd-9c987158c42d/bin/uautomizer-Dbtcem3rbc/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/termination-memory-alloca/Urban-2013WST-Fig2-modified1000-alloca.i -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96df67be-2121-48b2-a4fd-9c987158c42d/bin/uautomizer-Dbtcem3rbc/config/svcomp-Termination-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96df67be-2121-48b2-a4fd-9c987158c42d/bin/uautomizer-Dbtcem3rbc --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) )
--witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 68763c9a2179c48c1fc2989bd19031bbd8829c13b9c8eeaf244defd8aef53cfe
--- Real Ultimate output ---
[0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset.
This is Ultimate 0.2.2-dev-5e519f3
[2022-11-02 20:21:06,207 INFO L177 SettingsManager]: Resetting all preferences to default values...
[2022-11-02 20:21:06,211 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values
[2022-11-02 20:21:06,276 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring...
[2022-11-02 20:21:06,277 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values
[2022-11-02 20:21:06,281 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values
[2022-11-02 20:21:06,284 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values
[2022-11-02 20:21:06,288 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values
[2022-11-02 20:21:06,291 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values
[2022-11-02 20:21:06,297 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values
[2022-11-02 20:21:06,303 INFO L181 SettingsManager]: Resetting Sifa preferences to default values
[2022-11-02 20:21:06,304 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring...
[2022-11-02 20:21:06,304 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values
[2022-11-02 20:21:06,305 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values
[2022-11-02 20:21:06,308 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values
[2022-11-02 20:21:06,310 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values
[2022-11-02 20:21:06,312 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values
[2022-11-02 20:21:06,313 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values
[2022-11-02 20:21:06,315 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values
[2022-11-02 20:21:06,324 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values
[2022-11-02 20:21:06,326 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values
[2022-11-02 20:21:06,327 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values
[2022-11-02 20:21:06,331 INFO L181 SettingsManager]: Resetting Referee preferences to default values
[2022-11-02 20:21:06,333 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values
[2022-11-02 20:21:06,343 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring...
[2022-11-02 20:21:06,344 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring...
[2022-11-02 20:21:06,345 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values
[2022-11-02 20:21:06,348 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values
[2022-11-02 20:21:06,348 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values
[2022-11-02 20:21:06,349 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring...
[2022-11-02 20:21:06,350 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values
[2022-11-02 20:21:06,351 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values
[2022-11-02 20:21:06,353 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values
[2022-11-02 20:21:06,355 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values
[2022-11-02 20:21:06,356 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring...
[2022-11-02 20:21:06,357 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values
[2022-11-02 20:21:06,358 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring...
[2022-11-02 20:21:06,358 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring...
[2022-11-02 20:21:06,358 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values
[2022-11-02 20:21:06,359 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values
[2022-11-02 20:21:06,361 INFO L188 SettingsManager]: Finished resetting all preferences to default values...
[2022-11-02 20:21:06,362 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96df67be-2121-48b2-a4fd-9c987158c42d/bin/uautomizer-Dbtcem3rbc/config/svcomp-Termination-64bit-Automizer_Default.epf
[2022-11-02 20:21:06,411 INFO L113 SettingsManager]: Loading preferences was successful
[2022-11-02 20:21:06,411 INFO L115 SettingsManager]: Preferences different from defaults after loading the file:
[2022-11-02 20:21:06,412 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults:
[2022-11-02 20:21:06,412 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR;
[2022-11-02 20:21:06,413 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults:
[2022-11-02 20:21:06,414 INFO L138 SettingsManager]: * Create parallel compositions if possible=false
[2022-11-02 20:21:06,414 INFO L138 SettingsManager]: * Use SBE=true
[2022-11-02 20:21:06,414 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults:
[2022-11-02 20:21:06,415 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3
[2022-11-02 20:21:06,415 INFO L138 SettingsManager]: * Use old map elimination=false
[2022-11-02 20:21:06,416 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false
[2022-11-02 20:21:06,416 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true
[2022-11-02 20:21:06,417 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES
[2022-11-02 20:21:06,417 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults:
[2022-11-02 20:21:06,417 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false
[2022-11-02 20:21:06,417 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true
[2022-11-02 20:21:06,418 INFO L138 SettingsManager]: * Check division by zero=IGNORE
[2022-11-02 20:21:06,418 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME
[2022-11-02 20:21:06,418 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME
[2022-11-02 20:21:06,418 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME
[2022-11-02 20:21:06,418 INFO L138 SettingsManager]: * Check if freed pointer was valid=false
[2022-11-02 20:21:06,419 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false
[2022-11-02 20:21:06,419 INFO L138 SettingsManager]: * Use constant arrays=true
[2022-11-02 20:21:06,419 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME
[2022-11-02 20:21:06,419 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults:
[2022-11-02 20:21:06,420 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements
[2022-11-02 20:21:06,420 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults:
[2022-11-02 20:21:06,420 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL
[2022-11-02 20:21:06,421 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults:
[2022-11-02 20:21:06,422 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR
WARNING: An illegal reflective access operation has occurred
WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96df67be-2121-48b2-a4fd-9c987158c42d/bin/uautomizer-Dbtcem3rbc/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int)
WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1
WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations
WARNING: All illegal access operations will be denied in a future release
Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96df67be-2121-48b2-a4fd-9c987158c42d/bin/uautomizer-Dbtcem3rbc
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) )
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 68763c9a2179c48c1fc2989bd19031bbd8829c13b9c8eeaf244defd8aef53cfe
[2022-11-02 20:21:06,840 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp
[2022-11-02 20:21:06,886 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized
[2022-11-02 20:21:06,890 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected.
[2022-11-02 20:21:06,892 INFO L271 PluginConnector]: Initializing CDTParser...
[2022-11-02 20:21:06,893 INFO L275 PluginConnector]: CDTParser initialized
[2022-11-02 20:21:06,895 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96df67be-2121-48b2-a4fd-9c987158c42d/bin/uautomizer-Dbtcem3rbc/../../sv-benchmarks/c/termination-memory-alloca/Urban-2013WST-Fig2-modified1000-alloca.i
[2022-11-02 20:21:06,983 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96df67be-2121-48b2-a4fd-9c987158c42d/bin/uautomizer-Dbtcem3rbc/data/e761f6ef5/4a154ca5fa6c4dd692db0d08b7042210/FLAGdfd940be0
[2022-11-02 20:21:07,652 INFO L306 CDTParser]: Found 1 translation units.
[2022-11-02 20:21:07,653 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96df67be-2121-48b2-a4fd-9c987158c42d/sv-benchmarks/c/termination-memory-alloca/Urban-2013WST-Fig2-modified1000-alloca.i
[2022-11-02 20:21:07,675 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96df67be-2121-48b2-a4fd-9c987158c42d/bin/uautomizer-Dbtcem3rbc/data/e761f6ef5/4a154ca5fa6c4dd692db0d08b7042210/FLAGdfd940be0
[2022-11-02 20:21:07,930 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96df67be-2121-48b2-a4fd-9c987158c42d/bin/uautomizer-Dbtcem3rbc/data/e761f6ef5/4a154ca5fa6c4dd692db0d08b7042210
[2022-11-02 20:21:07,934 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] #######################
[2022-11-02 20:21:07,935 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements.
[2022-11-02 20:21:07,937 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator----------------------------
[2022-11-02 20:21:07,938 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator...
[2022-11-02 20:21:07,949 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized
[2022-11-02 20:21:07,950 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.11 08:21:07" (1/1) ...
[2022-11-02 20:21:07,952 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@1d802199 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 08:21:07, skipping insertion in model container
[2022-11-02 20:21:07,952 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.11 08:21:07" (1/1) ...
[2022-11-02 20:21:07,963 INFO L145 MainTranslator]: Starting translation in SV-COMP mode
[2022-11-02 20:21:08,026 INFO L178 MainTranslator]: Built tables and reachable declarations
[2022-11-02 20:21:08,368 INFO L210 PostProcessor]: Analyzing one entry point: main
[2022-11-02 20:21:08,379 INFO L203 MainTranslator]: Completed pre-run
[2022-11-02 20:21:08,457 INFO L210 PostProcessor]: Analyzing one entry point: main
[2022-11-02 20:21:08,491 INFO L208 MainTranslator]: Completed translation
[2022-11-02 20:21:08,492 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 08:21:08 WrapperNode
[2022-11-02 20:21:08,493 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator----------------------------
[2022-11-02 20:21:08,494 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner----------------------------
[2022-11-02 20:21:08,494 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner...
[2022-11-02 20:21:08,495 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized
[2022-11-02 20:21:08,504 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 08:21:08" (1/1) ...
[2022-11-02 20:21:08,531 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 08:21:08" (1/1) ...
[2022-11-02 20:21:08,559 INFO L138 Inliner]: procedures = 109, calls = 13, calls flagged for inlining = 2, calls inlined = 2, statements flattened = 34
[2022-11-02 20:21:08,561 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner----------------------------
[2022-11-02 20:21:08,562 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor----------------------------
[2022-11-02 20:21:08,562 INFO L271 PluginConnector]: Initializing Boogie Preprocessor...
[2022-11-02 20:21:08,562 INFO L275 PluginConnector]: Boogie Preprocessor initialized
[2022-11-02 20:21:08,572 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 08:21:08" (1/1) ...
[2022-11-02 20:21:08,572 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 08:21:08" (1/1) ...
[2022-11-02 20:21:08,592 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 08:21:08" (1/1) ...
[2022-11-02 20:21:08,593 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 08:21:08" (1/1) ...
[2022-11-02 20:21:08,596 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 08:21:08" (1/1) ...
[2022-11-02 20:21:08,603 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 08:21:08" (1/1) ...
[2022-11-02 20:21:08,605 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 08:21:08" (1/1) ...
[2022-11-02 20:21:08,612 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 08:21:08" (1/1) ...
[2022-11-02 20:21:08,614 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor----------------------------
[2022-11-02 20:21:08,617 INFO L113 PluginConnector]: ------------------------RCFGBuilder----------------------------
[2022-11-02 20:21:08,618 INFO L271 PluginConnector]: Initializing RCFGBuilder...
[2022-11-02 20:21:08,618 INFO L275 PluginConnector]: RCFGBuilder initialized
[2022-11-02 20:21:08,620 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 08:21:08" (1/1) ...
[2022-11-02 20:21:08,629 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000
[2022-11-02 20:21:08,641 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96df67be-2121-48b2-a4fd-9c987158c42d/bin/uautomizer-Dbtcem3rbc/z3
[2022-11-02 20:21:08,656 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96df67be-2121-48b2-a4fd-9c987158c42d/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null)
[2022-11-02 20:21:08,694 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96df67be-2121-48b2-a4fd-9c987158c42d/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process
[2022-11-02 20:21:08,710 INFO L130 BoogieDeclarations]: Found specification of procedure read~int
[2022-11-02 20:21:08,710 INFO L130 BoogieDeclarations]: Found specification of procedure write~int
[2022-11-02 20:21:08,710 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack
[2022-11-02 20:21:08,712 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc
[2022-11-02 20:21:08,712 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start
[2022-11-02 20:21:08,712 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start
[2022-11-02 20:21:08,869 INFO L235 CfgBuilder]: Building ICFG
[2022-11-02 20:21:08,872 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation
[2022-11-02 20:21:09,076 INFO L276 CfgBuilder]: Performing block encoding
[2022-11-02 20:21:09,083 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start)
[2022-11-02 20:21:09,083 INFO L300 CfgBuilder]: Removed 2 assume(true) statements.
[2022-11-02 20:21:09,085 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.11 08:21:09 BoogieIcfgContainer
[2022-11-02 20:21:09,086 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder----------------------------
[2022-11-02 20:21:09,087 INFO L113 PluginConnector]: ------------------------BuchiAutomizer----------------------------
[2022-11-02 20:21:09,087 INFO L271 PluginConnector]: Initializing BuchiAutomizer...
[2022-11-02 20:21:09,101 INFO L275 PluginConnector]: BuchiAutomizer initialized
[2022-11-02 20:21:09,102 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis
[2022-11-02 20:21:09,103 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 02.11 08:21:07" (1/3) ...
[2022-11-02 20:21:09,104 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7c588b1d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 02.11 08:21:09, skipping insertion in model container
[2022-11-02 20:21:09,118 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis
[2022-11-02 20:21:09,118 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 08:21:08" (2/3) ...
[2022-11-02 20:21:09,119 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7c588b1d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 02.11 08:21:09, skipping insertion in model container
[2022-11-02 20:21:09,119 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis
[2022-11-02 20:21:09,119 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.11 08:21:09" (3/3) ...
[2022-11-02 20:21:09,121 INFO L332 chiAutomizerObserver]: Analyzing ICFG Urban-2013WST-Fig2-modified1000-alloca.i
[2022-11-02 20:21:09,237 INFO L303 stractBuchiCegarLoop]: Interprodecural is true
[2022-11-02 20:21:09,247 INFO L304 stractBuchiCegarLoop]: Hoare is false
[2022-11-02 20:21:09,248 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates
[2022-11-02 20:21:09,248 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE
[2022-11-02 20:21:09,248 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION
[2022-11-02 20:21:09,248 INFO L308 stractBuchiCegarLoop]: Difference is false
[2022-11-02 20:21:09,249 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA
[2022-11-02 20:21:09,249 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ========
[2022-11-02 20:21:09,254 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 11 states, 10 states have (on average 1.4) internal successors, (14), 10 states have internal predecessors, (14), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2022-11-02 20:21:09,294 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5
[2022-11-02 20:21:09,306 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2022-11-02 20:21:09,306 INFO L119 BuchiIsEmpty]: Starting construction of run
[2022-11-02 20:21:09,326 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1]
[2022-11-02 20:21:09,327 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1]
[2022-11-02 20:21:09,327 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============
[2022-11-02 20:21:09,327 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 11 states, 10 states have (on average 1.4) internal successors, (14), 10 states have internal predecessors, (14), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2022-11-02 20:21:09,329 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5
[2022-11-02 20:21:09,329 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2022-11-02 20:21:09,329 INFO L119 BuchiIsEmpty]: Starting construction of run
[2022-11-02 20:21:09,330 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1]
[2022-11-02 20:21:09,330 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1]
[2022-11-02 20:21:09,352 INFO L748 eck$LassoCheckResult]: Stem: 4#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 10#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~mem6#1, main_#t~mem5#1, main_#t~mem7#1, main_#t~mem4#1, main_~x1~0#1.base, main_~x1~0#1.offset, main_~x2~0#1.base, main_~x2~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~x1~0#1.base, main_~x1~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~x2~0#1.base, main_~x2~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset; 6#L549-3true
[2022-11-02 20:21:09,353 INFO L750 eck$LassoCheckResult]: Loop: 6#L549-3true call main_#t~mem4#1 := read~int(main_~x1~0#1.base, main_~x1~0#1.offset, 4); 2#L549-1true assume !!(main_#t~mem4#1 <= 10);havoc main_#t~mem4#1;call write~int(1000, main_~x2~0#1.base, main_~x2~0#1.offset, 4); 7#L551-3true assume !true; 11#L551-4true call main_#t~mem7#1 := read~int(main_~x1~0#1.base, main_~x1~0#1.offset, 4);call write~int(1 + main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, 4);havoc main_#t~mem7#1; 6#L549-3true
[2022-11-02 20:21:09,359 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2022-11-02 20:21:09,360 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 1 times
[2022-11-02 20:21:09,387 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2022-11-02 20:21:09,388 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1492266459]
[2022-11-02 20:21:09,388 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2022-11-02 20:21:09,389 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2022-11-02 20:21:09,570 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2022-11-02 20:21:09,571 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2022-11-02 20:21:09,604 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2022-11-02 20:21:09,633 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2022-11-02 20:21:09,641 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2022-11-02 20:21:09,641 INFO L85 PathProgramCache]: Analyzing trace with hash 1144360, now seen corresponding path program 1 times
[2022-11-02 20:21:09,642 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2022-11-02 20:21:09,644 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [721778917]
[2022-11-02 20:21:09,644 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2022-11-02 20:21:09,645 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2022-11-02 20:21:09,678 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2022-11-02 20:21:09,746 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2022-11-02 20:21:09,747 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2022-11-02 20:21:09,747 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [721778917]
[2022-11-02 20:21:09,748 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [721778917] provided 1 perfect and 0 imperfect interpolant sequences
[2022-11-02 20:21:09,748 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2022-11-02 20:21:09,749 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2
[2022-11-02 20:21:09,749 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2011552218]
[2022-11-02 20:21:09,750 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2022-11-02 20:21:09,756 INFO L765 eck$LassoCheckResult]: loop already infeasible
[2022-11-02 20:21:09,759 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2022-11-02 20:21:09,804 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants.
[2022-11-02 20:21:09,805 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2
[2022-11-02 20:21:09,807 INFO L87 Difference]: Start difference. First operand has 11 states, 10 states have (on average 1.4) internal successors, (14), 10 states have internal predecessors, (14), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 2.0) internal successors, (4), 2 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2022-11-02 20:21:09,815 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2022-11-02 20:21:09,815 INFO L93 Difference]: Finished difference Result 11 states and 12 transitions.
[2022-11-02 20:21:09,817 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11 states and 12 transitions.
[2022-11-02 20:21:09,820 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5
[2022-11-02 20:21:09,824 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11 states to 7 states and 8 transitions.
[2022-11-02 20:21:09,825 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7
[2022-11-02 20:21:09,826 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7
[2022-11-02 20:21:09,827 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7 states and 8 transitions.
[2022-11-02 20:21:09,827 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2022-11-02 20:21:09,827 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7 states and 8 transitions.
[2022-11-02 20:21:09,848 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7 states and 8 transitions.
[2022-11-02 20:21:09,858 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7 to 7.
[2022-11-02 20:21:09,859 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7 states, 7 states have (on average 1.1428571428571428) internal successors, (8), 6 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2022-11-02 20:21:09,859 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7 states to 7 states and 8 transitions.
[2022-11-02 20:21:09,861 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7 states and 8 transitions.
[2022-11-02 20:21:09,862 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states.
[2022-11-02 20:21:09,870 INFO L428 stractBuchiCegarLoop]: Abstraction has 7 states and 8 transitions.
[2022-11-02 20:21:09,871 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============
[2022-11-02 20:21:09,871 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7 states and 8 transitions.
[2022-11-02 20:21:09,872 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5
[2022-11-02 20:21:09,873 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2022-11-02 20:21:09,873 INFO L119 BuchiIsEmpty]: Starting construction of run
[2022-11-02 20:21:09,873 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1]
[2022-11-02 20:21:09,874 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1]
[2022-11-02 20:21:09,874 INFO L748 eck$LassoCheckResult]: Stem: 32#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 33#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~mem6#1, main_#t~mem5#1, main_#t~mem7#1, main_#t~mem4#1, main_~x1~0#1.base, main_~x1~0#1.offset, main_~x2~0#1.base, main_~x2~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~x1~0#1.base, main_~x1~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~x2~0#1.base, main_~x2~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset; 34#L549-3
[2022-11-02 20:21:09,874 INFO L750 eck$LassoCheckResult]: Loop: 34#L549-3 call main_#t~mem4#1 := read~int(main_~x1~0#1.base, main_~x1~0#1.offset, 4); 30#L549-1 assume !!(main_#t~mem4#1 <= 10);havoc main_#t~mem4#1;call write~int(1000, main_~x2~0#1.base, main_~x2~0#1.offset, 4); 31#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 35#L551-1 assume !(main_#t~mem5#1 > 1);havoc main_#t~mem5#1; 36#L551-4 call main_#t~mem7#1 := read~int(main_~x1~0#1.base, main_~x1~0#1.offset, 4);call write~int(1 + main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, 4);havoc main_#t~mem7#1; 34#L549-3
[2022-11-02 20:21:09,875 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2022-11-02 20:21:09,876 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 2 times
[2022-11-02 20:21:09,876 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2022-11-02 20:21:09,876 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2093439255]
[2022-11-02 20:21:09,877 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2022-11-02 20:21:09,878 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2022-11-02 20:21:09,919 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2022-11-02 20:21:09,919 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2022-11-02 20:21:09,926 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2022-11-02 20:21:09,929 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2022-11-02 20:21:09,934 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2022-11-02 20:21:09,934 INFO L85 PathProgramCache]: Analyzing trace with hash 35468273, now seen corresponding path program 1 times
[2022-11-02 20:21:09,934 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2022-11-02 20:21:09,935 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [511840234]
[2022-11-02 20:21:09,935 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2022-11-02 20:21:09,936 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2022-11-02 20:21:09,972 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2022-11-02 20:21:10,213 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2022-11-02 20:21:10,214 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2022-11-02 20:21:10,214 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [511840234]
[2022-11-02 20:21:10,215 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [511840234] provided 1 perfect and 0 imperfect interpolant sequences
[2022-11-02 20:21:10,215 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2022-11-02 20:21:10,215 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4
[2022-11-02 20:21:10,216 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [509083909]
[2022-11-02 20:21:10,216 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2022-11-02 20:21:10,216 INFO L765 eck$LassoCheckResult]: loop already infeasible
[2022-11-02 20:21:10,217 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2022-11-02 20:21:10,217 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants.
[2022-11-02 20:21:10,218 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12
[2022-11-02 20:21:10,218 INFO L87 Difference]: Start difference. First operand 7 states and 8 transitions. cyclomatic complexity: 2 Second operand has 4 states, 4 states have (on average 1.25) internal successors, (5), 4 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2022-11-02 20:21:10,261 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2022-11-02 20:21:10,262 INFO L93 Difference]: Finished difference Result 9 states and 10 transitions.
[2022-11-02 20:21:10,262 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9 states and 10 transitions.
[2022-11-02 20:21:10,263 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 7
[2022-11-02 20:21:10,263 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9 states to 9 states and 10 transitions.
[2022-11-02 20:21:10,263 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9
[2022-11-02 20:21:10,264 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9
[2022-11-02 20:21:10,264 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9 states and 10 transitions.
[2022-11-02 20:21:10,264 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2022-11-02 20:21:10,265 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9 states and 10 transitions.
[2022-11-02 20:21:10,265 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9 states and 10 transitions.
[2022-11-02 20:21:10,266 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9 to 9.
[2022-11-02 20:21:10,266 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9 states, 9 states have (on average 1.1111111111111112) internal successors, (10), 8 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2022-11-02 20:21:10,267 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9 states to 9 states and 10 transitions.
[2022-11-02 20:21:10,267 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9 states and 10 transitions.
[2022-11-02 20:21:10,268 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states.
[2022-11-02 20:21:10,269 INFO L428 stractBuchiCegarLoop]: Abstraction has 9 states and 10 transitions.
[2022-11-02 20:21:10,269 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============
[2022-11-02 20:21:10,269 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9 states and 10 transitions.
[2022-11-02 20:21:10,270 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 7
[2022-11-02 20:21:10,270 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2022-11-02 20:21:10,270 INFO L119 BuchiIsEmpty]: Starting construction of run
[2022-11-02 20:21:10,271 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1]
[2022-11-02 20:21:10,271 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 1, 1, 1, 1, 1]
[2022-11-02 20:21:10,272 INFO L748 eck$LassoCheckResult]: Stem: 57#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 58#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~mem6#1, main_#t~mem5#1, main_#t~mem7#1, main_#t~mem4#1, main_~x1~0#1.base, main_~x1~0#1.offset, main_~x2~0#1.base, main_~x2~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~x1~0#1.base, main_~x1~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~x2~0#1.base, main_~x2~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset; 59#L549-3
[2022-11-02 20:21:10,272 INFO L750 eck$LassoCheckResult]: Loop: 59#L549-3 call main_#t~mem4#1 := read~int(main_~x1~0#1.base, main_~x1~0#1.offset, 4); 55#L549-1 assume !!(main_#t~mem4#1 <= 10);havoc main_#t~mem4#1;call write~int(1000, main_~x2~0#1.base, main_~x2~0#1.offset, 4); 56#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 60#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 61#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 63#L551-1 assume !(main_#t~mem5#1 > 1);havoc main_#t~mem5#1; 62#L551-4 call main_#t~mem7#1 := read~int(main_~x1~0#1.base, main_~x1~0#1.offset, 4);call write~int(1 + main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, 4);havoc main_#t~mem7#1; 59#L549-3
[2022-11-02 20:21:10,273 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2022-11-02 20:21:10,273 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 3 times
[2022-11-02 20:21:10,273 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2022-11-02 20:21:10,274 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1276695023]
[2022-11-02 20:21:10,274 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2022-11-02 20:21:10,274 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2022-11-02 20:21:10,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2022-11-02 20:21:10,288 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2022-11-02 20:21:10,294 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2022-11-02 20:21:10,297 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2022-11-02 20:21:10,298 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2022-11-02 20:21:10,298 INFO L85 PathProgramCache]: Analyzing trace with hash -274676436, now seen corresponding path program 1 times
[2022-11-02 20:21:10,299 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2022-11-02 20:21:10,299 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [761331606]
[2022-11-02 20:21:10,299 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2022-11-02 20:21:10,300 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2022-11-02 20:21:10,316 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2022-11-02 20:21:10,530 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2022-11-02 20:21:10,530 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2022-11-02 20:21:10,531 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [761331606]
[2022-11-02 20:21:10,531 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [761331606] provided 0 perfect and 1 imperfect interpolant sequences
[2022-11-02 20:21:10,531 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1412053313]
[2022-11-02 20:21:10,532 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2022-11-02 20:21:10,532 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true
[2022-11-02 20:21:10,532 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96df67be-2121-48b2-a4fd-9c987158c42d/bin/uautomizer-Dbtcem3rbc/z3
[2022-11-02 20:21:10,535 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96df67be-2121-48b2-a4fd-9c987158c42d/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null)
[2022-11-02 20:21:10,543 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96df67be-2121-48b2-a4fd-9c987158c42d/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process
[2022-11-02 20:21:10,629 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2022-11-02 20:21:10,631 INFO L263 TraceCheckSpWp]: Trace formula consists of 47 conjuncts, 8 conjunts are in the unsatisfiable core
[2022-11-02 20:21:10,634 INFO L286 TraceCheckSpWp]: Computing forward predicates...
[2022-11-02 20:21:10,714 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7
[2022-11-02 20:21:10,755 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:10,774 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7
[2022-11-02 20:21:10,781 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2022-11-02 20:21:10,781 INFO L328 TraceCheckSpWp]: Computing backward predicates...
[2022-11-02 20:21:10,835 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2022-11-02 20:21:10,836 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1412053313] provided 0 perfect and 2 imperfect interpolant sequences
[2022-11-02 20:21:10,836 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences.
[2022-11-02 20:21:10,837 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 5, 5] total 10
[2022-11-02 20:21:10,837 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1818922640]
[2022-11-02 20:21:10,837 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton
[2022-11-02 20:21:10,838 INFO L765 eck$LassoCheckResult]: loop already infeasible
[2022-11-02 20:21:10,838 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2022-11-02 20:21:10,839 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants.
[2022-11-02 20:21:10,839 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=35, Invalid=55, Unknown=0, NotChecked=0, Total=90
[2022-11-02 20:21:10,840 INFO L87 Difference]: Start difference. First operand 9 states and 10 transitions. cyclomatic complexity: 2 Second operand has 10 states, 10 states have (on average 1.5) internal successors, (15), 10 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2022-11-02 20:21:10,928 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2022-11-02 20:21:10,928 INFO L93 Difference]: Finished difference Result 15 states and 16 transitions.
[2022-11-02 20:21:10,929 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 15 states and 16 transitions.
[2022-11-02 20:21:10,930 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 13
[2022-11-02 20:21:10,930 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 15 states to 15 states and 16 transitions.
[2022-11-02 20:21:10,931 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15
[2022-11-02 20:21:10,931 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15
[2022-11-02 20:21:10,931 INFO L73 IsDeterministic]: Start isDeterministic. Operand 15 states and 16 transitions.
[2022-11-02 20:21:10,931 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2022-11-02 20:21:10,932 INFO L218 hiAutomatonCegarLoop]: Abstraction has 15 states and 16 transitions.
[2022-11-02 20:21:10,932 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15 states and 16 transitions.
[2022-11-02 20:21:10,933 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15 to 15.
[2022-11-02 20:21:10,934 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15 states, 15 states have (on average 1.0666666666666667) internal successors, (16), 14 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2022-11-02 20:21:10,934 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15 states to 15 states and 16 transitions.
[2022-11-02 20:21:10,934 INFO L240 hiAutomatonCegarLoop]: Abstraction has 15 states and 16 transitions.
[2022-11-02 20:21:10,935 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states.
[2022-11-02 20:21:10,936 INFO L428 stractBuchiCegarLoop]: Abstraction has 15 states and 16 transitions.
[2022-11-02 20:21:10,936 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============
[2022-11-02 20:21:10,937 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 15 states and 16 transitions.
[2022-11-02 20:21:10,937 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 13
[2022-11-02 20:21:10,938 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2022-11-02 20:21:10,938 INFO L119 BuchiIsEmpty]: Starting construction of run
[2022-11-02 20:21:10,938 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1]
[2022-11-02 20:21:10,939 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [5, 4, 1, 1, 1, 1]
[2022-11-02 20:21:10,939 INFO L748 eck$LassoCheckResult]: Stem: 136#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 137#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~mem6#1, main_#t~mem5#1, main_#t~mem7#1, main_#t~mem4#1, main_~x1~0#1.base, main_~x1~0#1.offset, main_~x2~0#1.base, main_~x2~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~x1~0#1.base, main_~x1~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~x2~0#1.base, main_~x2~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset; 138#L549-3
[2022-11-02 20:21:10,939 INFO L750 eck$LassoCheckResult]: Loop: 138#L549-3 call main_#t~mem4#1 := read~int(main_~x1~0#1.base, main_~x1~0#1.offset, 4); 134#L549-1 assume !!(main_#t~mem4#1 <= 10);havoc main_#t~mem4#1;call write~int(1000, main_~x2~0#1.base, main_~x2~0#1.offset, 4); 135#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 139#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 140#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 141#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 148#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 147#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 146#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 145#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 144#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 143#L551-1 assume !(main_#t~mem5#1 > 1);havoc main_#t~mem5#1; 142#L551-4 call main_#t~mem7#1 := read~int(main_~x1~0#1.base, main_~x1~0#1.offset, 4);call write~int(1 + main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, 4);havoc main_#t~mem7#1; 138#L549-3
[2022-11-02 20:21:10,940 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2022-11-02 20:21:10,940 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 4 times
[2022-11-02 20:21:10,940 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2022-11-02 20:21:10,941 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1942461085]
[2022-11-02 20:21:10,941 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2022-11-02 20:21:10,941 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2022-11-02 20:21:10,950 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2022-11-02 20:21:10,951 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2022-11-02 20:21:10,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2022-11-02 20:21:10,957 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2022-11-02 20:21:10,958 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2022-11-02 20:21:10,958 INFO L85 PathProgramCache]: Analyzing trace with hash 351922269, now seen corresponding path program 2 times
[2022-11-02 20:21:10,959 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2022-11-02 20:21:10,959 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [285234377]
[2022-11-02 20:21:10,959 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2022-11-02 20:21:10,960 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2022-11-02 20:21:10,977 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2022-11-02 20:21:11,624 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2022-11-02 20:21:11,628 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2022-11-02 20:21:11,629 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [285234377]
[2022-11-02 20:21:11,629 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [285234377] provided 0 perfect and 1 imperfect interpolant sequences
[2022-11-02 20:21:11,631 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1630778716]
[2022-11-02 20:21:11,631 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1
[2022-11-02 20:21:11,632 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true
[2022-11-02 20:21:11,632 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96df67be-2121-48b2-a4fd-9c987158c42d/bin/uautomizer-Dbtcem3rbc/z3
[2022-11-02 20:21:11,636 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96df67be-2121-48b2-a4fd-9c987158c42d/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null)
[2022-11-02 20:21:11,659 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96df67be-2121-48b2-a4fd-9c987158c42d/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process
[2022-11-02 20:21:11,774 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s)
[2022-11-02 20:21:11,774 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat
[2022-11-02 20:21:11,776 INFO L263 TraceCheckSpWp]: Trace formula consists of 92 conjuncts, 17 conjunts are in the unsatisfiable core
[2022-11-02 20:21:11,785 INFO L286 TraceCheckSpWp]: Computing forward predicates...
[2022-11-02 20:21:11,805 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7
[2022-11-02 20:21:11,861 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:11,902 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:11,942 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:11,983 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:12,010 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7
[2022-11-02 20:21:12,017 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2022-11-02 20:21:12,017 INFO L328 TraceCheckSpWp]: Computing backward predicates...
[2022-11-02 20:21:12,176 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2022-11-02 20:21:12,176 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1630778716] provided 0 perfect and 2 imperfect interpolant sequences
[2022-11-02 20:21:12,177 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences.
[2022-11-02 20:21:12,177 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 8, 8] total 19
[2022-11-02 20:21:12,177 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1481602764]
[2022-11-02 20:21:12,177 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton
[2022-11-02 20:21:12,178 INFO L765 eck$LassoCheckResult]: loop already infeasible
[2022-11-02 20:21:12,178 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2022-11-02 20:21:12,179 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants.
[2022-11-02 20:21:12,179 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=140, Invalid=202, Unknown=0, NotChecked=0, Total=342
[2022-11-02 20:21:12,180 INFO L87 Difference]: Start difference. First operand 15 states and 16 transitions. cyclomatic complexity: 2 Second operand has 19 states, 19 states have (on average 1.736842105263158) internal successors, (33), 19 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2022-11-02 20:21:12,403 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2022-11-02 20:21:12,403 INFO L93 Difference]: Finished difference Result 27 states and 28 transitions.
[2022-11-02 20:21:12,403 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27 states and 28 transitions.
[2022-11-02 20:21:12,404 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 25
[2022-11-02 20:21:12,405 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27 states to 27 states and 28 transitions.
[2022-11-02 20:21:12,405 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27
[2022-11-02 20:21:12,411 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27
[2022-11-02 20:21:12,412 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27 states and 28 transitions.
[2022-11-02 20:21:12,412 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2022-11-02 20:21:12,412 INFO L218 hiAutomatonCegarLoop]: Abstraction has 27 states and 28 transitions.
[2022-11-02 20:21:12,413 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27 states and 28 transitions.
[2022-11-02 20:21:12,415 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27 to 27.
[2022-11-02 20:21:12,416 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27 states, 27 states have (on average 1.037037037037037) internal successors, (28), 26 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2022-11-02 20:21:12,422 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 28 transitions.
[2022-11-02 20:21:12,423 INFO L240 hiAutomatonCegarLoop]: Abstraction has 27 states and 28 transitions.
[2022-11-02 20:21:12,423 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states.
[2022-11-02 20:21:12,424 INFO L428 stractBuchiCegarLoop]: Abstraction has 27 states and 28 transitions.
[2022-11-02 20:21:12,426 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============
[2022-11-02 20:21:12,427 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27 states and 28 transitions.
[2022-11-02 20:21:12,431 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 25
[2022-11-02 20:21:12,431 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2022-11-02 20:21:12,432 INFO L119 BuchiIsEmpty]: Starting construction of run
[2022-11-02 20:21:12,433 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1]
[2022-11-02 20:21:12,433 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [11, 10, 1, 1, 1, 1]
[2022-11-02 20:21:12,434 INFO L748 eck$LassoCheckResult]: Stem: 284#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 285#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~mem6#1, main_#t~mem5#1, main_#t~mem7#1, main_#t~mem4#1, main_~x1~0#1.base, main_~x1~0#1.offset, main_~x2~0#1.base, main_~x2~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~x1~0#1.base, main_~x1~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~x2~0#1.base, main_~x2~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset; 286#L549-3
[2022-11-02 20:21:12,434 INFO L750 eck$LassoCheckResult]: Loop: 286#L549-3 call main_#t~mem4#1 := read~int(main_~x1~0#1.base, main_~x1~0#1.offset, 4); 282#L549-1 assume !!(main_#t~mem4#1 <= 10);havoc main_#t~mem4#1;call write~int(1000, main_~x2~0#1.base, main_~x2~0#1.offset, 4); 283#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 287#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 288#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 289#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 308#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 307#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 306#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 305#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 304#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 303#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 302#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 301#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 300#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 299#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 298#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 297#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 296#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 295#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 294#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 293#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 292#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 291#L551-1 assume !(main_#t~mem5#1 > 1);havoc main_#t~mem5#1; 290#L551-4 call main_#t~mem7#1 := read~int(main_~x1~0#1.base, main_~x1~0#1.offset, 4);call write~int(1 + main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, 4);havoc main_#t~mem7#1; 286#L549-3
[2022-11-02 20:21:12,435 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2022-11-02 20:21:12,435 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 5 times
[2022-11-02 20:21:12,435 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2022-11-02 20:21:12,435 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [696879041]
[2022-11-02 20:21:12,436 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2022-11-02 20:21:12,436 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2022-11-02 20:21:12,448 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2022-11-02 20:21:12,448 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2022-11-02 20:21:12,452 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2022-11-02 20:21:12,460 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2022-11-02 20:21:12,461 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2022-11-02 20:21:12,462 INFO L85 PathProgramCache]: Analyzing trace with hash 646907007, now seen corresponding path program 3 times
[2022-11-02 20:21:12,462 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2022-11-02 20:21:12,462 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1889769352]
[2022-11-02 20:21:12,462 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2022-11-02 20:21:12,463 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2022-11-02 20:21:12,512 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2022-11-02 20:21:14,338 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2022-11-02 20:21:14,338 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2022-11-02 20:21:14,338 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1889769352]
[2022-11-02 20:21:14,339 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1889769352] provided 0 perfect and 1 imperfect interpolant sequences
[2022-11-02 20:21:14,339 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [85793457]
[2022-11-02 20:21:14,339 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2
[2022-11-02 20:21:14,339 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true
[2022-11-02 20:21:14,339 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96df67be-2121-48b2-a4fd-9c987158c42d/bin/uautomizer-Dbtcem3rbc/z3
[2022-11-02 20:21:14,365 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96df67be-2121-48b2-a4fd-9c987158c42d/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null)
[2022-11-02 20:21:14,394 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96df67be-2121-48b2-a4fd-9c987158c42d/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process
[2022-11-02 20:21:14,563 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s)
[2022-11-02 20:21:14,563 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat
[2022-11-02 20:21:14,565 INFO L263 TraceCheckSpWp]: Trace formula consists of 182 conjuncts, 35 conjunts are in the unsatisfiable core
[2022-11-02 20:21:14,573 INFO L286 TraceCheckSpWp]: Computing forward predicates...
[2022-11-02 20:21:14,587 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7
[2022-11-02 20:21:14,607 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:14,623 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:14,639 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:14,657 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:14,687 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:14,708 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:14,742 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:14,760 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:14,779 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:14,822 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:14,835 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7
[2022-11-02 20:21:14,840 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2022-11-02 20:21:14,841 INFO L328 TraceCheckSpWp]: Computing backward predicates...
[2022-11-02 20:21:15,287 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2022-11-02 20:21:15,287 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [85793457] provided 0 perfect and 2 imperfect interpolant sequences
[2022-11-02 20:21:15,288 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences.
[2022-11-02 20:21:15,288 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 14, 14] total 36
[2022-11-02 20:21:15,288 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1723259713]
[2022-11-02 20:21:15,288 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton
[2022-11-02 20:21:15,291 INFO L765 eck$LassoCheckResult]: loop already infeasible
[2022-11-02 20:21:15,291 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2022-11-02 20:21:15,293 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants.
[2022-11-02 20:21:15,295 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=541, Invalid=719, Unknown=0, NotChecked=0, Total=1260
[2022-11-02 20:21:15,295 INFO L87 Difference]: Start difference. First operand 27 states and 28 transitions. cyclomatic complexity: 2 Second operand has 36 states, 36 states have (on average 1.8888888888888888) internal successors, (68), 36 states have internal predecessors, (68), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2022-11-02 20:21:15,794 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2022-11-02 20:21:15,795 INFO L93 Difference]: Finished difference Result 51 states and 52 transitions.
[2022-11-02 20:21:15,795 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 51 states and 52 transitions.
[2022-11-02 20:21:15,796 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 49
[2022-11-02 20:21:15,797 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 51 states to 51 states and 52 transitions.
[2022-11-02 20:21:15,797 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 51
[2022-11-02 20:21:15,797 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 51
[2022-11-02 20:21:15,797 INFO L73 IsDeterministic]: Start isDeterministic. Operand 51 states and 52 transitions.
[2022-11-02 20:21:15,798 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2022-11-02 20:21:15,798 INFO L218 hiAutomatonCegarLoop]: Abstraction has 51 states and 52 transitions.
[2022-11-02 20:21:15,798 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51 states and 52 transitions.
[2022-11-02 20:21:15,801 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51 to 51.
[2022-11-02 20:21:15,802 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 51 states, 51 states have (on average 1.0196078431372548) internal successors, (52), 50 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2022-11-02 20:21:15,803 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51 states to 51 states and 52 transitions.
[2022-11-02 20:21:15,803 INFO L240 hiAutomatonCegarLoop]: Abstraction has 51 states and 52 transitions.
[2022-11-02 20:21:15,808 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states.
[2022-11-02 20:21:15,809 INFO L428 stractBuchiCegarLoop]: Abstraction has 51 states and 52 transitions.
[2022-11-02 20:21:15,809 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============
[2022-11-02 20:21:15,809 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 51 states and 52 transitions.
[2022-11-02 20:21:15,810 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 49
[2022-11-02 20:21:15,810 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2022-11-02 20:21:15,810 INFO L119 BuchiIsEmpty]: Starting construction of run
[2022-11-02 20:21:15,811 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1]
[2022-11-02 20:21:15,811 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [23, 22, 1, 1, 1, 1]
[2022-11-02 20:21:15,812 INFO L748 eck$LassoCheckResult]: Stem: 569#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 570#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~mem6#1, main_#t~mem5#1, main_#t~mem7#1, main_#t~mem4#1, main_~x1~0#1.base, main_~x1~0#1.offset, main_~x2~0#1.base, main_~x2~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~x1~0#1.base, main_~x1~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~x2~0#1.base, main_~x2~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset; 571#L549-3
[2022-11-02 20:21:15,812 INFO L750 eck$LassoCheckResult]: Loop: 571#L549-3 call main_#t~mem4#1 := read~int(main_~x1~0#1.base, main_~x1~0#1.offset, 4); 567#L549-1 assume !!(main_#t~mem4#1 <= 10);havoc main_#t~mem4#1;call write~int(1000, main_~x2~0#1.base, main_~x2~0#1.offset, 4); 568#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 574#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 572#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 573#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 617#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 616#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 615#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 614#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 613#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 612#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 611#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 610#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 609#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 608#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 607#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 606#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 605#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 604#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 603#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 602#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 601#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 600#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 599#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 598#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 597#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 596#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 595#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 594#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 593#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 592#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 591#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 590#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 589#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 588#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 587#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 586#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 585#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 584#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 583#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 582#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 581#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 580#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 579#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 578#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 577#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 576#L551-1 assume !(main_#t~mem5#1 > 1);havoc main_#t~mem5#1; 575#L551-4 call main_#t~mem7#1 := read~int(main_~x1~0#1.base, main_~x1~0#1.offset, 4);call write~int(1 + main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, 4);havoc main_#t~mem7#1; 571#L549-3
[2022-11-02 20:21:15,812 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2022-11-02 20:21:15,812 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 6 times
[2022-11-02 20:21:15,813 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2022-11-02 20:21:15,813 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1930966960]
[2022-11-02 20:21:15,813 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2022-11-02 20:21:15,813 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2022-11-02 20:21:15,823 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2022-11-02 20:21:15,823 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2022-11-02 20:21:15,826 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2022-11-02 20:21:15,828 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2022-11-02 20:21:15,829 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2022-11-02 20:21:15,829 INFO L85 PathProgramCache]: Analyzing trace with hash 1009537987, now seen corresponding path program 4 times
[2022-11-02 20:21:15,830 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2022-11-02 20:21:15,830 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2095381280]
[2022-11-02 20:21:15,830 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2022-11-02 20:21:15,830 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2022-11-02 20:21:15,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2022-11-02 20:21:20,444 INFO L134 CoverageAnalysis]: Checked inductivity of 506 backedges. 0 proven. 506 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2022-11-02 20:21:20,444 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2022-11-02 20:21:20,445 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2095381280]
[2022-11-02 20:21:20,445 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2095381280] provided 0 perfect and 1 imperfect interpolant sequences
[2022-11-02 20:21:20,445 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1357838615]
[2022-11-02 20:21:20,445 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST
[2022-11-02 20:21:20,445 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true
[2022-11-02 20:21:20,446 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96df67be-2121-48b2-a4fd-9c987158c42d/bin/uautomizer-Dbtcem3rbc/z3
[2022-11-02 20:21:20,452 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96df67be-2121-48b2-a4fd-9c987158c42d/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null)
[2022-11-02 20:21:20,482 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96df67be-2121-48b2-a4fd-9c987158c42d/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process
[2022-11-02 20:21:20,930 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s)
[2022-11-02 20:21:20,931 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat
[2022-11-02 20:21:20,935 INFO L263 TraceCheckSpWp]: Trace formula consists of 362 conjuncts, 71 conjunts are in the unsatisfiable core
[2022-11-02 20:21:20,949 INFO L286 TraceCheckSpWp]: Computing forward predicates...
[2022-11-02 20:21:20,955 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7
[2022-11-02 20:21:20,994 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:21,011 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:21,028 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:21,048 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:21,080 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:21,099 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:21,113 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:21,128 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:21,146 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:21,159 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:21,173 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:21,186 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:21,199 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:21,222 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:21,248 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:21,262 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:21,277 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:21,291 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:21,311 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:21,325 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:21,345 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:21,358 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:21,367 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7
[2022-11-02 20:21:21,370 INFO L134 CoverageAnalysis]: Checked inductivity of 506 backedges. 0 proven. 506 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2022-11-02 20:21:21,371 INFO L328 TraceCheckSpWp]: Computing backward predicates...
[2022-11-02 20:21:22,800 INFO L134 CoverageAnalysis]: Checked inductivity of 506 backedges. 0 proven. 506 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2022-11-02 20:21:22,801 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1357838615] provided 0 perfect and 2 imperfect interpolant sequences
[2022-11-02 20:21:22,801 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences.
[2022-11-02 20:21:22,802 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 26, 26] total 73
[2022-11-02 20:21:22,803 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1590749797]
[2022-11-02 20:21:22,804 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton
[2022-11-02 20:21:22,807 INFO L765 eck$LassoCheckResult]: loop already infeasible
[2022-11-02 20:21:22,808 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2022-11-02 20:21:22,812 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 73 interpolants.
[2022-11-02 20:21:22,819 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=2282, Invalid=2974, Unknown=0, NotChecked=0, Total=5256
[2022-11-02 20:21:22,820 INFO L87 Difference]: Start difference. First operand 51 states and 52 transitions. cyclomatic complexity: 2 Second operand has 73 states, 73 states have (on average 1.9315068493150684) internal successors, (141), 73 states have internal predecessors, (141), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2022-11-02 20:21:24,329 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2022-11-02 20:21:24,330 INFO L93 Difference]: Finished difference Result 99 states and 100 transitions.
[2022-11-02 20:21:24,330 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 99 states and 100 transitions.
[2022-11-02 20:21:24,332 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 97
[2022-11-02 20:21:24,333 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 99 states to 99 states and 100 transitions.
[2022-11-02 20:21:24,333 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 99
[2022-11-02 20:21:24,333 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 99
[2022-11-02 20:21:24,333 INFO L73 IsDeterministic]: Start isDeterministic. Operand 99 states and 100 transitions.
[2022-11-02 20:21:24,334 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2022-11-02 20:21:24,334 INFO L218 hiAutomatonCegarLoop]: Abstraction has 99 states and 100 transitions.
[2022-11-02 20:21:24,335 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 99 states and 100 transitions.
[2022-11-02 20:21:24,340 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 99 to 99.
[2022-11-02 20:21:24,341 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 99 states, 99 states have (on average 1.0101010101010102) internal successors, (100), 98 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2022-11-02 20:21:24,342 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99 states to 99 states and 100 transitions.
[2022-11-02 20:21:24,343 INFO L240 hiAutomatonCegarLoop]: Abstraction has 99 states and 100 transitions.
[2022-11-02 20:21:24,343 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 94 states.
[2022-11-02 20:21:24,344 INFO L428 stractBuchiCegarLoop]: Abstraction has 99 states and 100 transitions.
[2022-11-02 20:21:24,344 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============
[2022-11-02 20:21:24,345 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 99 states and 100 transitions.
[2022-11-02 20:21:24,346 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 97
[2022-11-02 20:21:24,346 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2022-11-02 20:21:24,346 INFO L119 BuchiIsEmpty]: Starting construction of run
[2022-11-02 20:21:24,348 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1]
[2022-11-02 20:21:24,348 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [47, 46, 1, 1, 1, 1]
[2022-11-02 20:21:24,348 INFO L748 eck$LassoCheckResult]: Stem: 1131#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1132#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~mem6#1, main_#t~mem5#1, main_#t~mem7#1, main_#t~mem4#1, main_~x1~0#1.base, main_~x1~0#1.offset, main_~x2~0#1.base, main_~x2~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~x1~0#1.base, main_~x1~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~x2~0#1.base, main_~x2~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset; 1133#L549-3
[2022-11-02 20:21:24,349 INFO L750 eck$LassoCheckResult]: Loop: 1133#L549-3 call main_#t~mem4#1 := read~int(main_~x1~0#1.base, main_~x1~0#1.offset, 4); 1129#L549-1 assume !!(main_#t~mem4#1 <= 10);havoc main_#t~mem4#1;call write~int(1000, main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1130#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1136#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1134#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1135#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1227#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1226#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1225#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1224#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1223#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1222#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1221#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1220#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1219#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1218#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1217#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1216#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1215#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1214#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1213#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1212#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1211#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1210#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1209#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1208#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1207#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1206#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1205#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1204#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1203#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1202#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1201#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1200#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1199#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1198#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1197#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1196#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1195#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1194#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1193#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1192#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1191#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1190#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1189#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1188#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1187#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1186#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1185#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1184#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1183#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1182#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1181#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1180#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1179#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1178#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1177#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1176#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1175#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1174#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1173#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1172#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1171#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1170#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1169#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1168#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1167#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1166#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1165#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1164#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1163#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1162#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1161#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1160#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1159#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1158#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1157#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1156#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1155#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1154#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1153#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1152#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1151#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1150#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1149#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1148#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1147#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1146#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1145#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1144#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1143#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1142#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1141#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1140#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1139#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1138#L551-1 assume !(main_#t~mem5#1 > 1);havoc main_#t~mem5#1; 1137#L551-4 call main_#t~mem7#1 := read~int(main_~x1~0#1.base, main_~x1~0#1.offset, 4);call write~int(1 + main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, 4);havoc main_#t~mem7#1; 1133#L549-3
[2022-11-02 20:21:24,350 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2022-11-02 20:21:24,350 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 7 times
[2022-11-02 20:21:24,350 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2022-11-02 20:21:24,351 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [960846213]
[2022-11-02 20:21:24,351 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2022-11-02 20:21:24,351 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2022-11-02 20:21:24,359 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2022-11-02 20:21:24,360 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2022-11-02 20:21:24,362 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2022-11-02 20:21:24,365 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2022-11-02 20:21:24,365 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2022-11-02 20:21:24,366 INFO L85 PathProgramCache]: Analyzing trace with hash 1846627915, now seen corresponding path program 5 times
[2022-11-02 20:21:24,366 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2022-11-02 20:21:24,366 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2118229275]
[2022-11-02 20:21:24,366 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2022-11-02 20:21:24,367 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2022-11-02 20:21:24,453 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2022-11-02 20:21:38,266 INFO L134 CoverageAnalysis]: Checked inductivity of 2162 backedges. 0 proven. 2162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2022-11-02 20:21:38,267 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2022-11-02 20:21:38,267 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2118229275]
[2022-11-02 20:21:38,267 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2118229275] provided 0 perfect and 1 imperfect interpolant sequences
[2022-11-02 20:21:38,268 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1382166790]
[2022-11-02 20:21:38,268 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1
[2022-11-02 20:21:38,268 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true
[2022-11-02 20:21:38,268 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96df67be-2121-48b2-a4fd-9c987158c42d/bin/uautomizer-Dbtcem3rbc/z3
[2022-11-02 20:21:38,274 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96df67be-2121-48b2-a4fd-9c987158c42d/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null)
[2022-11-02 20:21:38,302 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96df67be-2121-48b2-a4fd-9c987158c42d/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process
[2022-11-02 20:21:53,026 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 47 check-sat command(s)
[2022-11-02 20:21:53,027 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat
[2022-11-02 20:21:53,047 INFO L263 TraceCheckSpWp]: Trace formula consists of 722 conjuncts, 143 conjunts are in the unsatisfiable core
[2022-11-02 20:21:53,079 INFO L286 TraceCheckSpWp]: Computing forward predicates...
[2022-11-02 20:21:53,087 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7
[2022-11-02 20:21:53,151 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:53,171 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:53,184 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:53,198 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:53,210 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:53,226 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:53,248 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:53,261 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:53,276 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:53,288 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:53,303 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:53,326 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:53,338 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:53,351 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:53,369 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:53,381 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:53,393 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:53,408 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:53,423 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:53,436 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:53,448 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:53,461 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:53,475 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:53,487 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:53,502 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:53,516 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:53,528 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:53,564 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:53,577 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:53,589 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:53,600 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:53,616 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:53,630 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:53,643 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:53,654 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:53,666 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:53,683 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:53,695 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:53,708 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:53,720 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:53,733 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:53,744 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:53,758 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:53,770 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:53,782 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:53,795 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16
[2022-11-02 20:21:53,814 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7
[2022-11-02 20:21:53,820 INFO L134 CoverageAnalysis]: Checked inductivity of 2162 backedges. 0 proven. 2162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2022-11-02 20:21:53,821 INFO L328 TraceCheckSpWp]: Computing backward predicates...
[2022-11-02 20:21:58,186 INFO L134 CoverageAnalysis]: Checked inductivity of 2162 backedges. 0 proven. 2162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2022-11-02 20:21:58,186 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1382166790] provided 0 perfect and 2 imperfect interpolant sequences
[2022-11-02 20:21:58,187 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences.
[2022-11-02 20:21:58,187 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [96, 50, 50] total 145
[2022-11-02 20:21:58,187 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1557571082]
[2022-11-02 20:21:58,187 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton
[2022-11-02 20:21:58,188 INFO L765 eck$LassoCheckResult]: loop already infeasible
[2022-11-02 20:21:58,189 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2022-11-02 20:21:58,193 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 145 interpolants.
[2022-11-02 20:21:58,202 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=9170, Invalid=11710, Unknown=0, NotChecked=0, Total=20880
[2022-11-02 20:21:58,203 INFO L87 Difference]: Start difference. First operand 99 states and 100 transitions. cyclomatic complexity: 2 Second operand has 145 states, 145 states have (on average 1.9655172413793103) internal successors, (285), 145 states have internal predecessors, (285), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2022-11-02 20:22:02,553 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2022-11-02 20:22:02,553 INFO L93 Difference]: Finished difference Result 195 states and 196 transitions.
[2022-11-02 20:22:02,553 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 195 states and 196 transitions.
[2022-11-02 20:22:02,556 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 193
[2022-11-02 20:22:02,558 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 195 states to 195 states and 196 transitions.
[2022-11-02 20:22:02,558 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 195
[2022-11-02 20:22:02,559 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 195
[2022-11-02 20:22:02,559 INFO L73 IsDeterministic]: Start isDeterministic. Operand 195 states and 196 transitions.
[2022-11-02 20:22:02,560 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2022-11-02 20:22:02,560 INFO L218 hiAutomatonCegarLoop]: Abstraction has 195 states and 196 transitions.
[2022-11-02 20:22:02,561 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 195 states and 196 transitions.
[2022-11-02 20:22:02,569 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 195 to 195.
[2022-11-02 20:22:02,570 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 195 states, 195 states have (on average 1.005128205128205) internal successors, (196), 194 states have internal predecessors, (196), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2022-11-02 20:22:02,572 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 195 states to 195 states and 196 transitions.
[2022-11-02 20:22:02,572 INFO L240 hiAutomatonCegarLoop]: Abstraction has 195 states and 196 transitions.
[2022-11-02 20:22:02,573 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 190 states.
[2022-11-02 20:22:02,574 INFO L428 stractBuchiCegarLoop]: Abstraction has 195 states and 196 transitions.
[2022-11-02 20:22:02,574 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============
[2022-11-02 20:22:02,574 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 195 states and 196 transitions.
[2022-11-02 20:22:02,576 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 193
[2022-11-02 20:22:02,576 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2022-11-02 20:22:02,576 INFO L119 BuchiIsEmpty]: Starting construction of run
[2022-11-02 20:22:02,579 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1]
[2022-11-02 20:22:02,579 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [95, 94, 1, 1, 1, 1]
[2022-11-02 20:22:02,579 INFO L748 eck$LassoCheckResult]: Stem: 2245#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 2246#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~mem6#1, main_#t~mem5#1, main_#t~mem7#1, main_#t~mem4#1, main_~x1~0#1.base, main_~x1~0#1.offset, main_~x2~0#1.base, main_~x2~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~x1~0#1.base, main_~x1~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~x2~0#1.base, main_~x2~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset; 2247#L549-3
[2022-11-02 20:22:02,580 INFO L750 eck$LassoCheckResult]: Loop: 2247#L549-3 call main_#t~mem4#1 := read~int(main_~x1~0#1.base, main_~x1~0#1.offset, 4); 2243#L549-1 assume !!(main_#t~mem4#1 <= 10);havoc main_#t~mem4#1;call write~int(1000, main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2244#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2250#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2248#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2249#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2437#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2436#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2435#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2434#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2433#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2432#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2431#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2430#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2429#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2428#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2427#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2426#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2425#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2424#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2423#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2422#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2421#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2420#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2419#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2418#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2417#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2416#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2415#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2414#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2413#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2412#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2411#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2410#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2409#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2408#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2407#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2406#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2405#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2404#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2403#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2402#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2401#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2400#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2399#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2398#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2397#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2396#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2395#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2394#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2393#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2392#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2391#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2390#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2389#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2388#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2387#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2386#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2385#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2384#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2383#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2382#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2381#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2380#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2379#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2378#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2377#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2376#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2375#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2374#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2373#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2372#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2371#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2370#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2369#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2368#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2367#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2366#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2365#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2364#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2363#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2362#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2361#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2360#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2359#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2358#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2357#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2356#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2355#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2354#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2353#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2352#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2351#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2350#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2349#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2348#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2347#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2346#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2345#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2344#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2343#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2342#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2341#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2340#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2339#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2338#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2337#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2336#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2335#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2334#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2333#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2332#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2331#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2330#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2329#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2328#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2327#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2326#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2325#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2324#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2323#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2322#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2321#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2320#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2319#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2318#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2317#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2316#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2315#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2314#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2313#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2312#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2311#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2310#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2309#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2308#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2307#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2306#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2305#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2304#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2303#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2302#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2301#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2300#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2299#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2298#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2297#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2296#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2295#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2294#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2293#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2292#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2291#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2290#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2289#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2288#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2287#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2286#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2285#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2284#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2283#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2282#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2281#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2280#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2279#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2278#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2277#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2276#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2275#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2274#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2273#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2272#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2271#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2270#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2269#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2268#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2267#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2266#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2265#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2264#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2263#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2262#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2261#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2260#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2259#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2258#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2257#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2256#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2255#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2254#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2253#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2252#L551-1 assume !(main_#t~mem5#1 > 1);havoc main_#t~mem5#1; 2251#L551-4 call main_#t~mem7#1 := read~int(main_~x1~0#1.base, main_~x1~0#1.offset, 4);call write~int(1 + main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, 4);havoc main_#t~mem7#1; 2247#L549-3
[2022-11-02 20:22:02,581 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2022-11-02 20:22:02,581 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 8 times
[2022-11-02 20:22:02,581 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2022-11-02 20:22:02,582 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [926671164]
[2022-11-02 20:22:02,582 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2022-11-02 20:22:02,582 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2022-11-02 20:22:02,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2022-11-02 20:22:02,590 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2022-11-02 20:22:02,592 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2022-11-02 20:22:02,595 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2022-11-02 20:22:02,596 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2022-11-02 20:22:02,596 INFO L85 PathProgramCache]: Analyzing trace with hash -1384860837, now seen corresponding path program 6 times
[2022-11-02 20:22:02,596 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2022-11-02 20:22:02,596 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1953498907]
[2022-11-02 20:22:02,597 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2022-11-02 20:22:02,597 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2022-11-02 20:22:02,828 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2022-11-02 20:22:43,514 INFO L134 CoverageAnalysis]: Checked inductivity of 8930 backedges. 0 proven. 8930 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2022-11-02 20:22:43,514 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2022-11-02 20:22:43,515 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1953498907]
[2022-11-02 20:22:43,515 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1953498907] provided 0 perfect and 1 imperfect interpolant sequences
[2022-11-02 20:22:43,515 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [435967637]
[2022-11-02 20:22:43,515 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE
[2022-11-02 20:22:43,515 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true
[2022-11-02 20:22:43,516 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96df67be-2121-48b2-a4fd-9c987158c42d/bin/uautomizer-Dbtcem3rbc/z3
[2022-11-02 20:22:43,522 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96df67be-2121-48b2-a4fd-9c987158c42d/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null)
[2022-11-02 20:22:43,542 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96df67be-2121-48b2-a4fd-9c987158c42d/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process