./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/loop-invgen/string_concat-noarr.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 5e519f3a Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/loop-invgen/string_concat-noarr.i -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 30a4b942034eaa47a8fcc8fdf4549d1d63a9a60d59b585da2a353c9626604750 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-5e519f3 [2022-11-02 20:54:24,890 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-11-02 20:54:24,892 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-11-02 20:54:24,932 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-11-02 20:54:24,933 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-11-02 20:54:24,934 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-11-02 20:54:24,940 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-11-02 20:54:24,943 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-11-02 20:54:24,945 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-11-02 20:54:24,952 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-11-02 20:54:24,953 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-11-02 20:54:24,954 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-11-02 20:54:24,955 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-11-02 20:54:24,957 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-11-02 20:54:24,959 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-11-02 20:54:24,960 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-11-02 20:54:24,962 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-11-02 20:54:24,962 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-11-02 20:54:24,964 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-11-02 20:54:24,967 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-11-02 20:54:24,973 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-11-02 20:54:24,974 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-11-02 20:54:24,975 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-11-02 20:54:24,976 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-11-02 20:54:24,979 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-11-02 20:54:24,979 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-11-02 20:54:24,979 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-11-02 20:54:24,980 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-11-02 20:54:24,980 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-11-02 20:54:24,981 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-11-02 20:54:24,981 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-11-02 20:54:24,982 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-11-02 20:54:24,983 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-11-02 20:54:24,984 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-11-02 20:54:24,984 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-11-02 20:54:24,985 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-11-02 20:54:24,985 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-11-02 20:54:24,991 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-11-02 20:54:24,993 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-11-02 20:54:24,993 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-11-02 20:54:24,994 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-11-02 20:54:24,995 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-11-02 20:54:25,032 INFO L113 SettingsManager]: Loading preferences was successful [2022-11-02 20:54:25,032 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-11-02 20:54:25,033 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-11-02 20:54:25,033 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-11-02 20:54:25,037 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-11-02 20:54:25,038 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-11-02 20:54:25,038 INFO L138 SettingsManager]: * Use SBE=true [2022-11-02 20:54:25,038 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-11-02 20:54:25,038 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-11-02 20:54:25,038 INFO L138 SettingsManager]: * Use old map elimination=false [2022-11-02 20:54:25,039 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-11-02 20:54:25,040 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-11-02 20:54:25,040 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-11-02 20:54:25,040 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-11-02 20:54:25,040 INFO L138 SettingsManager]: * sizeof long=4 [2022-11-02 20:54:25,040 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-11-02 20:54:25,041 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-11-02 20:54:25,041 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-11-02 20:54:25,041 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-11-02 20:54:25,041 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-11-02 20:54:25,041 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-11-02 20:54:25,041 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-11-02 20:54:25,042 INFO L138 SettingsManager]: * sizeof long double=12 [2022-11-02 20:54:25,043 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-11-02 20:54:25,044 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-11-02 20:54:25,044 INFO L138 SettingsManager]: * Use constant arrays=true [2022-11-02 20:54:25,044 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-11-02 20:54:25,044 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-11-02 20:54:25,044 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-11-02 20:54:25,045 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-11-02 20:54:25,045 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-11-02 20:54:25,046 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-11-02 20:54:25,046 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 30a4b942034eaa47a8fcc8fdf4549d1d63a9a60d59b585da2a353c9626604750 [2022-11-02 20:54:25,325 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-11-02 20:54:25,360 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-11-02 20:54:25,363 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-11-02 20:54:25,364 INFO L271 PluginConnector]: Initializing CDTParser... [2022-11-02 20:54:25,365 INFO L275 PluginConnector]: CDTParser initialized [2022-11-02 20:54:25,366 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/../../sv-benchmarks/c/loop-invgen/string_concat-noarr.i [2022-11-02 20:54:25,447 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/data/769677682/a4dec12090ed4abd9896f3be8ca948a9/FLAGc9c590c3d [2022-11-02 20:54:25,909 INFO L306 CDTParser]: Found 1 translation units. [2022-11-02 20:54:25,910 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/sv-benchmarks/c/loop-invgen/string_concat-noarr.i [2022-11-02 20:54:25,921 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/data/769677682/a4dec12090ed4abd9896f3be8ca948a9/FLAGc9c590c3d [2022-11-02 20:54:26,269 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/data/769677682/a4dec12090ed4abd9896f3be8ca948a9 [2022-11-02 20:54:26,272 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-11-02 20:54:26,273 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-11-02 20:54:26,275 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-11-02 20:54:26,275 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-11-02 20:54:26,279 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-11-02 20:54:26,279 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.11 08:54:26" (1/1) ... [2022-11-02 20:54:26,281 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5aebc314 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 08:54:26, skipping insertion in model container [2022-11-02 20:54:26,281 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.11 08:54:26" (1/1) ... [2022-11-02 20:54:26,288 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-11-02 20:54:26,303 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-11-02 20:54:26,464 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/sv-benchmarks/c/loop-invgen/string_concat-noarr.i[893,906] [2022-11-02 20:54:26,479 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-02 20:54:26,491 INFO L203 MainTranslator]: Completed pre-run [2022-11-02 20:54:26,506 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/sv-benchmarks/c/loop-invgen/string_concat-noarr.i[893,906] [2022-11-02 20:54:26,509 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-02 20:54:26,523 INFO L208 MainTranslator]: Completed translation [2022-11-02 20:54:26,523 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 08:54:26 WrapperNode [2022-11-02 20:54:26,523 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-11-02 20:54:26,525 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-11-02 20:54:26,525 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-11-02 20:54:26,525 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-11-02 20:54:26,533 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 08:54:26" (1/1) ... [2022-11-02 20:54:26,539 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 08:54:26" (1/1) ... [2022-11-02 20:54:26,556 INFO L138 Inliner]: procedures = 16, calls = 7, calls flagged for inlining = 3, calls inlined = 3, statements flattened = 51 [2022-11-02 20:54:26,556 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-11-02 20:54:26,557 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-11-02 20:54:26,557 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-11-02 20:54:26,557 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-11-02 20:54:26,566 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 08:54:26" (1/1) ... [2022-11-02 20:54:26,566 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 08:54:26" (1/1) ... [2022-11-02 20:54:26,567 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 08:54:26" (1/1) ... [2022-11-02 20:54:26,567 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 08:54:26" (1/1) ... [2022-11-02 20:54:26,569 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 08:54:26" (1/1) ... [2022-11-02 20:54:26,573 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 08:54:26" (1/1) ... [2022-11-02 20:54:26,574 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 08:54:26" (1/1) ... [2022-11-02 20:54:26,574 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 08:54:26" (1/1) ... [2022-11-02 20:54:26,576 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-11-02 20:54:26,576 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-11-02 20:54:26,577 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-11-02 20:54:26,577 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-11-02 20:54:26,578 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 08:54:26" (1/1) ... [2022-11-02 20:54:26,584 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-02 20:54:26,596 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 20:54:26,610 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-02 20:54:26,612 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-11-02 20:54:26,648 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-11-02 20:54:26,648 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-11-02 20:54:26,648 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-11-02 20:54:26,648 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-11-02 20:54:26,712 INFO L235 CfgBuilder]: Building ICFG [2022-11-02 20:54:26,714 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-11-02 20:54:26,826 INFO L276 CfgBuilder]: Performing block encoding [2022-11-02 20:54:26,831 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-11-02 20:54:26,832 INFO L300 CfgBuilder]: Removed 2 assume(true) statements. [2022-11-02 20:54:26,834 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.11 08:54:26 BoogieIcfgContainer [2022-11-02 20:54:26,834 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-11-02 20:54:26,835 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-11-02 20:54:26,835 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-11-02 20:54:26,839 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-11-02 20:54:26,840 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-02 20:54:26,840 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 02.11 08:54:26" (1/3) ... [2022-11-02 20:54:26,841 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@41efb162 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 02.11 08:54:26, skipping insertion in model container [2022-11-02 20:54:26,841 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-02 20:54:26,841 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 08:54:26" (2/3) ... [2022-11-02 20:54:26,841 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@41efb162 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 02.11 08:54:26, skipping insertion in model container [2022-11-02 20:54:26,842 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-02 20:54:26,842 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.11 08:54:26" (3/3) ... [2022-11-02 20:54:26,843 INFO L332 chiAutomizerObserver]: Analyzing ICFG string_concat-noarr.i [2022-11-02 20:54:26,914 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-11-02 20:54:26,914 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-11-02 20:54:26,914 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-11-02 20:54:26,915 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-11-02 20:54:26,915 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-11-02 20:54:26,915 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-11-02 20:54:26,915 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-11-02 20:54:26,915 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-11-02 20:54:26,927 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 14 states, 13 states have (on average 1.5384615384615385) internal successors, (20), 13 states have internal predecessors, (20), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:54:26,965 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3 [2022-11-02 20:54:26,965 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 20:54:26,966 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 20:54:26,971 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1] [2022-11-02 20:54:26,971 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2022-11-02 20:54:26,971 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-11-02 20:54:26,971 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 14 states, 13 states have (on average 1.5384615384615385) internal successors, (20), 13 states have internal predecessors, (20), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:54:26,973 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3 [2022-11-02 20:54:26,973 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 20:54:26,973 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 20:54:26,974 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1] [2022-11-02 20:54:26,974 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2022-11-02 20:54:26,997 INFO L748 eck$LassoCheckResult]: Stem: 3#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 6#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 5#L26true main_~i~0#1 := 0; 4#L29-1true [2022-11-02 20:54:26,998 INFO L750 eck$LassoCheckResult]: Loop: 4#L29-1true assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4#L29-1true [2022-11-02 20:54:27,003 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:54:27,003 INFO L85 PathProgramCache]: Analyzing trace with hash 29857, now seen corresponding path program 1 times [2022-11-02 20:54:27,029 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:54:27,031 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [596957036] [2022-11-02 20:54:27,031 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:54:27,032 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:54:27,146 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:54:27,147 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:54:27,168 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:54:27,190 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:54:27,195 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:54:27,195 INFO L85 PathProgramCache]: Analyzing trace with hash 44, now seen corresponding path program 1 times [2022-11-02 20:54:27,197 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:54:27,198 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1737435374] [2022-11-02 20:54:27,198 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:54:27,198 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:54:27,217 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:54:27,218 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:54:27,224 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:54:27,227 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:54:27,240 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:54:27,241 INFO L85 PathProgramCache]: Analyzing trace with hash 925580, now seen corresponding path program 1 times [2022-11-02 20:54:27,241 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:54:27,242 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1287041326] [2022-11-02 20:54:27,242 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:54:27,242 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:54:27,255 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:54:27,259 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:54:27,274 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:54:27,277 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:54:27,381 INFO L210 LassoAnalysis]: Preferences: [2022-11-02 20:54:27,382 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2022-11-02 20:54:27,382 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2022-11-02 20:54:27,382 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2022-11-02 20:54:27,382 INFO L129 ssoRankerPreferences]: Use exernal solver: true [2022-11-02 20:54:27,383 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-02 20:54:27,383 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2022-11-02 20:54:27,383 INFO L132 ssoRankerPreferences]: Path of dumped script: [2022-11-02 20:54:27,384 INFO L133 ssoRankerPreferences]: Filename of dumped script: string_concat-noarr.i_Iteration1_Loop [2022-11-02 20:54:27,384 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2022-11-02 20:54:27,384 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2022-11-02 20:54:27,402 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-02 20:54:27,420 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-02 20:54:27,429 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-02 20:54:27,508 INFO L294 LassoAnalysis]: Preprocessing complete. [2022-11-02 20:54:27,508 INFO L404 LassoAnalysis]: Checking for nontermination... [2022-11-02 20:54:27,510 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-02 20:54:27,511 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 20:54:27,514 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-02 20:54:27,517 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2022-11-02 20:54:27,517 INFO L160 nArgumentSynthesizer]: Using integer mode. [2022-11-02 20:54:27,529 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2022-11-02 20:54:27,544 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2022-11-02 20:54:27,545 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_main_#t~post2#1=0} Honda state: {ULTIMATE.start_main_#t~post2#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2022-11-02 20:54:27,582 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Forceful destruction successful, exit code 0 [2022-11-02 20:54:27,583 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-02 20:54:27,583 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 20:54:27,584 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-02 20:54:27,599 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2022-11-02 20:54:27,599 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2022-11-02 20:54:27,600 INFO L160 nArgumentSynthesizer]: Using integer mode. [2022-11-02 20:54:27,623 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2022-11-02 20:54:27,623 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_main_#t~nondet1#1=-1} Honda state: {ULTIMATE.start_main_#t~nondet1#1=-1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2022-11-02 20:54:27,662 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Forceful destruction successful, exit code 0 [2022-11-02 20:54:27,663 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-02 20:54:27,663 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 20:54:27,665 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-02 20:54:27,672 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2022-11-02 20:54:27,672 INFO L160 nArgumentSynthesizer]: Using integer mode. [2022-11-02 20:54:27,675 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2022-11-02 20:54:27,731 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Forceful destruction successful, exit code 0 [2022-11-02 20:54:27,731 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-02 20:54:27,732 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 20:54:27,734 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-02 20:54:27,741 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2022-11-02 20:54:27,742 INFO L160 nArgumentSynthesizer]: Using integer mode. [2022-11-02 20:54:27,758 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2022-11-02 20:54:27,810 INFO L444 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2022-11-02 20:54:27,819 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Forceful destruction successful, exit code 0 [2022-11-02 20:54:27,820 INFO L210 LassoAnalysis]: Preferences: [2022-11-02 20:54:27,820 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2022-11-02 20:54:27,820 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2022-11-02 20:54:27,820 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2022-11-02 20:54:27,820 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2022-11-02 20:54:27,820 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-02 20:54:27,820 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2022-11-02 20:54:27,821 INFO L132 ssoRankerPreferences]: Path of dumped script: [2022-11-02 20:54:27,821 INFO L133 ssoRankerPreferences]: Filename of dumped script: string_concat-noarr.i_Iteration1_Loop [2022-11-02 20:54:27,821 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2022-11-02 20:54:27,821 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2022-11-02 20:54:27,822 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-02 20:54:27,825 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-02 20:54:27,833 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-02 20:54:27,911 INFO L294 LassoAnalysis]: Preprocessing complete. [2022-11-02 20:54:27,928 INFO L490 LassoAnalysis]: Using template 'affine'. [2022-11-02 20:54:27,929 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-02 20:54:27,930 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 20:54:27,941 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-02 20:54:27,950 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-02 20:54:27,962 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2022-11-02 20:54:27,963 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-02 20:54:27,964 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-02 20:54:27,964 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-02 20:54:27,964 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-02 20:54:27,964 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-02 20:54:27,966 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-02 20:54:27,966 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-02 20:54:27,976 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-02 20:54:28,009 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Forceful destruction successful, exit code 0 [2022-11-02 20:54:28,009 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-02 20:54:28,010 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 20:54:28,016 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-02 20:54:28,018 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2022-11-02 20:54:28,019 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-02 20:54:28,032 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-02 20:54:28,032 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-02 20:54:28,032 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-02 20:54:28,032 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-02 20:54:28,032 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-02 20:54:28,034 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-02 20:54:28,034 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-02 20:54:28,045 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2022-11-02 20:54:28,049 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2022-11-02 20:54:28,049 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2022-11-02 20:54:28,051 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-02 20:54:28,051 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 20:54:28,055 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-02 20:54:28,078 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2022-11-02 20:54:28,078 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2022-11-02 20:54:28,079 INFO L513 LassoAnalysis]: Proved termination. [2022-11-02 20:54:28,079 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~i~0#1) = -2*ULTIMATE.start_main_~i~0#1 + 1999999 Supporting invariants [] [2022-11-02 20:54:28,094 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2022-11-02 20:54:28,113 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Ended with exit code 0 [2022-11-02 20:54:28,116 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2022-11-02 20:54:28,154 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:54:28,175 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:54:28,177 INFO L263 TraceCheckSpWp]: Trace formula consists of 24 conjuncts, 2 conjunts are in the unsatisfiable core [2022-11-02 20:54:28,179 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 20:54:28,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:54:28,198 WARN L261 TraceCheckSpWp]: Trace formula consists of 6 conjuncts, 4 conjunts are in the unsatisfiable core [2022-11-02 20:54:28,198 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 20:54:28,198 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:54:28,244 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 1 loop predicates [2022-11-02 20:54:28,247 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand has 14 states, 13 states have (on average 1.5384615384615385) internal successors, (20), 13 states have internal predecessors, (20), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 2.0) internal successors, (4), 2 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:54:28,295 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand has 14 states, 13 states have (on average 1.5384615384615385) internal successors, (20), 13 states have internal predecessors, (20), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0). Second operand has 2 states, 2 states have (on average 2.0) internal successors, (4), 2 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 37 states and 56 transitions. Complement of second has 5 states. [2022-11-02 20:54:28,298 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 4 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2022-11-02 20:54:28,303 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2 states, 2 states have (on average 2.0) internal successors, (4), 2 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:54:28,303 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 37 transitions. [2022-11-02 20:54:28,305 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 37 transitions. Stem has 3 letters. Loop has 1 letters. [2022-11-02 20:54:28,306 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-02 20:54:28,306 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 37 transitions. Stem has 4 letters. Loop has 1 letters. [2022-11-02 20:54:28,306 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-02 20:54:28,306 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 37 transitions. Stem has 3 letters. Loop has 2 letters. [2022-11-02 20:54:28,306 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-02 20:54:28,307 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 37 states and 56 transitions. [2022-11-02 20:54:28,310 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-11-02 20:54:28,330 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 37 states to 13 states and 19 transitions. [2022-11-02 20:54:28,331 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7 [2022-11-02 20:54:28,332 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2022-11-02 20:54:28,332 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13 states and 19 transitions. [2022-11-02 20:54:28,333 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-02 20:54:28,333 INFO L218 hiAutomatonCegarLoop]: Abstraction has 13 states and 19 transitions. [2022-11-02 20:54:28,349 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13 states and 19 transitions. [2022-11-02 20:54:28,359 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13 to 12. [2022-11-02 20:54:28,360 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12 states, 12 states have (on average 1.5) internal successors, (18), 11 states have internal predecessors, (18), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:54:28,360 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 18 transitions. [2022-11-02 20:54:28,361 INFO L240 hiAutomatonCegarLoop]: Abstraction has 12 states and 18 transitions. [2022-11-02 20:54:28,361 INFO L428 stractBuchiCegarLoop]: Abstraction has 12 states and 18 transitions. [2022-11-02 20:54:28,362 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-11-02 20:54:28,362 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12 states and 18 transitions. [2022-11-02 20:54:28,364 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-11-02 20:54:28,364 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 20:54:28,364 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 20:54:28,365 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1] [2022-11-02 20:54:28,365 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2022-11-02 20:54:28,365 INFO L748 eck$LassoCheckResult]: Stem: 89#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 90#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 96#L26 main_~i~0#1 := 0; 91#L29-1 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 93#L29-2 assume main_~i~0#1 >= 100; 95#L39 [2022-11-02 20:54:28,365 INFO L750 eck$LassoCheckResult]: Loop: 95#L39 assume true; 95#L39 [2022-11-02 20:54:28,367 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:54:28,367 INFO L85 PathProgramCache]: Analyzing trace with hash 28692937, now seen corresponding path program 1 times [2022-11-02 20:54:28,368 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:54:28,368 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [257072229] [2022-11-02 20:54:28,368 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:54:28,369 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:54:28,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:54:28,470 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:54:28,470 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 20:54:28,471 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [257072229] [2022-11-02 20:54:28,471 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [257072229] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-02 20:54:28,471 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-02 20:54:28,472 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-02 20:54:28,472 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1838958081] [2022-11-02 20:54:28,473 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-02 20:54:28,474 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-02 20:54:28,475 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:54:28,475 INFO L85 PathProgramCache]: Analyzing trace with hash 84, now seen corresponding path program 1 times [2022-11-02 20:54:28,475 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:54:28,475 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1249158855] [2022-11-02 20:54:28,475 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:54:28,476 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:54:28,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:54:28,478 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:54:28,479 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:54:28,480 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:54:28,487 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 20:54:28,489 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-02 20:54:28,489 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-02 20:54:28,491 INFO L87 Difference]: Start difference. First operand 12 states and 18 transitions. cyclomatic complexity: 9 Second operand has 3 states, 2 states have (on average 2.5) internal successors, (5), 3 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:54:28,519 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 20:54:28,524 INFO L93 Difference]: Finished difference Result 18 states and 24 transitions. [2022-11-02 20:54:28,525 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18 states and 24 transitions. [2022-11-02 20:54:28,529 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2 [2022-11-02 20:54:28,530 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18 states to 18 states and 24 transitions. [2022-11-02 20:54:28,530 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12 [2022-11-02 20:54:28,530 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12 [2022-11-02 20:54:28,530 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18 states and 24 transitions. [2022-11-02 20:54:28,530 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-02 20:54:28,530 INFO L218 hiAutomatonCegarLoop]: Abstraction has 18 states and 24 transitions. [2022-11-02 20:54:28,531 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18 states and 24 transitions. [2022-11-02 20:54:28,532 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18 to 13. [2022-11-02 20:54:28,532 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13 states, 13 states have (on average 1.4615384615384615) internal successors, (19), 12 states have internal predecessors, (19), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:54:28,532 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 19 transitions. [2022-11-02 20:54:28,533 INFO L240 hiAutomatonCegarLoop]: Abstraction has 13 states and 19 transitions. [2022-11-02 20:54:28,534 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-02 20:54:28,535 INFO L428 stractBuchiCegarLoop]: Abstraction has 13 states and 19 transitions. [2022-11-02 20:54:28,535 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-11-02 20:54:28,535 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13 states and 19 transitions. [2022-11-02 20:54:28,535 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-11-02 20:54:28,535 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 20:54:28,536 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 20:54:28,536 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1] [2022-11-02 20:54:28,536 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2022-11-02 20:54:28,536 INFO L748 eck$LassoCheckResult]: Stem: 125#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 126#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 133#L26 main_~i~0#1 := 0; 127#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 130#L29-1 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 131#L29-2 assume main_~i~0#1 >= 100; 132#L39 [2022-11-02 20:54:28,536 INFO L750 eck$LassoCheckResult]: Loop: 132#L39 assume true; 132#L39 [2022-11-02 20:54:28,537 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:54:28,537 INFO L85 PathProgramCache]: Analyzing trace with hash 889482740, now seen corresponding path program 1 times [2022-11-02 20:54:28,537 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:54:28,538 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1816625889] [2022-11-02 20:54:28,538 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:54:28,538 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:54:28,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:54:28,607 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:54:28,608 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 20:54:28,608 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1816625889] [2022-11-02 20:54:28,608 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1816625889] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 20:54:28,608 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1129253840] [2022-11-02 20:54:28,609 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:54:28,609 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 20:54:28,609 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 20:54:28,610 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 20:54:28,615 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2022-11-02 20:54:28,650 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:54:28,651 INFO L263 TraceCheckSpWp]: Trace formula consists of 30 conjuncts, 3 conjunts are in the unsatisfiable core [2022-11-02 20:54:28,651 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 20:54:28,679 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:54:28,679 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 20:54:28,700 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:54:28,701 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1129253840] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 20:54:28,701 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 20:54:28,701 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 6 [2022-11-02 20:54:28,701 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1212191313] [2022-11-02 20:54:28,701 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 20:54:28,702 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-02 20:54:28,702 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:54:28,702 INFO L85 PathProgramCache]: Analyzing trace with hash 84, now seen corresponding path program 2 times [2022-11-02 20:54:28,703 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:54:28,703 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1116671050] [2022-11-02 20:54:28,703 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:54:28,703 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:54:28,705 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:54:28,705 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:54:28,706 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:54:28,707 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:54:28,710 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 20:54:28,710 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-11-02 20:54:28,710 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=21, Unknown=0, NotChecked=0, Total=42 [2022-11-02 20:54:28,711 INFO L87 Difference]: Start difference. First operand 13 states and 19 transitions. cyclomatic complexity: 9 Second operand has 7 states, 6 states have (on average 2.0) internal successors, (12), 7 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:54:28,770 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 20:54:28,771 INFO L93 Difference]: Finished difference Result 40 states and 55 transitions. [2022-11-02 20:54:28,772 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 40 states and 55 transitions. [2022-11-02 20:54:28,773 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 5 [2022-11-02 20:54:28,776 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 40 states to 40 states and 55 transitions. [2022-11-02 20:54:28,776 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 23 [2022-11-02 20:54:28,777 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23 [2022-11-02 20:54:28,777 INFO L73 IsDeterministic]: Start isDeterministic. Operand 40 states and 55 transitions. [2022-11-02 20:54:28,779 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-02 20:54:28,780 INFO L218 hiAutomatonCegarLoop]: Abstraction has 40 states and 55 transitions. [2022-11-02 20:54:28,780 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40 states and 55 transitions. [2022-11-02 20:54:28,781 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40 to 16. [2022-11-02 20:54:28,782 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16 states, 16 states have (on average 1.75) internal successors, (28), 15 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:54:28,782 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16 states to 16 states and 28 transitions. [2022-11-02 20:54:28,783 INFO L240 hiAutomatonCegarLoop]: Abstraction has 16 states and 28 transitions. [2022-11-02 20:54:28,783 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-11-02 20:54:28,784 INFO L428 stractBuchiCegarLoop]: Abstraction has 16 states and 28 transitions. [2022-11-02 20:54:28,786 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-11-02 20:54:28,786 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16 states and 28 transitions. [2022-11-02 20:54:28,786 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-11-02 20:54:28,787 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 20:54:28,787 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 20:54:28,787 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1] [2022-11-02 20:54:28,788 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2022-11-02 20:54:28,788 INFO L748 eck$LassoCheckResult]: Stem: 218#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 219#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 226#L26 main_~i~0#1 := 0; 220#L29-1 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 222#L29-2 assume !(main_~i~0#1 >= 100);main_~j~0#1 := 0; 214#L35-1 assume !(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1; 215#L35-2 assume main_~j~0#1 >= 100; 225#L39 [2022-11-02 20:54:28,788 INFO L750 eck$LassoCheckResult]: Loop: 225#L39 assume true; 225#L39 [2022-11-02 20:54:28,789 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:54:28,789 INFO L85 PathProgramCache]: Analyzing trace with hash 1804112500, now seen corresponding path program 1 times [2022-11-02 20:54:28,789 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:54:28,789 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [295096394] [2022-11-02 20:54:28,790 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:54:28,790 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:54:28,802 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:54:28,840 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:54:28,840 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 20:54:28,841 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [295096394] [2022-11-02 20:54:28,841 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [295096394] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-02 20:54:28,841 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-02 20:54:28,841 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-02 20:54:28,841 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [554829098] [2022-11-02 20:54:28,841 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-02 20:54:28,842 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-02 20:54:28,842 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:54:28,842 INFO L85 PathProgramCache]: Analyzing trace with hash 84, now seen corresponding path program 3 times [2022-11-02 20:54:28,842 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:54:28,843 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [741645794] [2022-11-02 20:54:28,843 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:54:28,843 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:54:28,847 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:54:28,847 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:54:28,849 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:54:28,855 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:54:28,857 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 20:54:28,858 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-02 20:54:28,858 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-02 20:54:28,859 INFO L87 Difference]: Start difference. First operand 16 states and 28 transitions. cyclomatic complexity: 15 Second operand has 3 states, 2 states have (on average 3.5) internal successors, (7), 3 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:54:28,870 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 20:54:28,870 INFO L93 Difference]: Finished difference Result 17 states and 28 transitions. [2022-11-02 20:54:28,870 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17 states and 28 transitions. [2022-11-02 20:54:28,871 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-11-02 20:54:28,871 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17 states to 14 states and 21 transitions. [2022-11-02 20:54:28,871 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7 [2022-11-02 20:54:28,872 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7 [2022-11-02 20:54:28,872 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14 states and 21 transitions. [2022-11-02 20:54:28,872 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-02 20:54:28,872 INFO L218 hiAutomatonCegarLoop]: Abstraction has 14 states and 21 transitions. [2022-11-02 20:54:28,872 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14 states and 21 transitions. [2022-11-02 20:54:28,873 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14 to 14. [2022-11-02 20:54:28,873 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14 states, 14 states have (on average 1.5) internal successors, (21), 13 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:54:28,878 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14 states to 14 states and 21 transitions. [2022-11-02 20:54:28,878 INFO L240 hiAutomatonCegarLoop]: Abstraction has 14 states and 21 transitions. [2022-11-02 20:54:28,878 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-02 20:54:28,879 INFO L428 stractBuchiCegarLoop]: Abstraction has 14 states and 21 transitions. [2022-11-02 20:54:28,879 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-11-02 20:54:28,880 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14 states and 21 transitions. [2022-11-02 20:54:28,880 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-11-02 20:54:28,880 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 20:54:28,880 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 20:54:28,881 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 20:54:28,881 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2022-11-02 20:54:28,881 INFO L748 eck$LassoCheckResult]: Stem: 255#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 256#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 263#L26 main_~i~0#1 := 0; 257#L29-1 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 258#L29-2 assume !(main_~i~0#1 >= 100);main_~j~0#1 := 0; 253#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 254#L35-1 assume !(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1; 261#L35-2 assume main_~j~0#1 >= 100; 262#L39 [2022-11-02 20:54:28,881 INFO L750 eck$LassoCheckResult]: Loop: 262#L39 assume true; 262#L39 [2022-11-02 20:54:28,882 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:54:28,887 INFO L85 PathProgramCache]: Analyzing trace with hash 92914363, now seen corresponding path program 1 times [2022-11-02 20:54:28,887 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:54:28,887 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1921151575] [2022-11-02 20:54:28,887 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:54:28,888 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:54:28,895 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:54:28,933 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:54:28,933 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 20:54:28,933 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1921151575] [2022-11-02 20:54:28,934 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1921151575] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 20:54:28,934 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [371429429] [2022-11-02 20:54:28,934 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:54:28,934 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 20:54:28,935 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 20:54:28,937 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 20:54:28,946 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2022-11-02 20:54:28,980 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:54:28,981 INFO L263 TraceCheckSpWp]: Trace formula consists of 36 conjuncts, 3 conjunts are in the unsatisfiable core [2022-11-02 20:54:28,982 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 20:54:28,997 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:54:28,997 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 20:54:29,017 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:54:29,017 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [371429429] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 20:54:29,018 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 20:54:29,018 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 6 [2022-11-02 20:54:29,018 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [627108068] [2022-11-02 20:54:29,018 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 20:54:29,019 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-02 20:54:29,019 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:54:29,019 INFO L85 PathProgramCache]: Analyzing trace with hash 84, now seen corresponding path program 4 times [2022-11-02 20:54:29,019 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:54:29,020 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [490116857] [2022-11-02 20:54:29,020 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:54:29,020 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:54:29,022 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:54:29,022 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:54:29,023 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:54:29,024 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:54:29,027 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 20:54:29,028 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-11-02 20:54:29,028 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=21, Unknown=0, NotChecked=0, Total=42 [2022-11-02 20:54:29,028 INFO L87 Difference]: Start difference. First operand 14 states and 21 transitions. cyclomatic complexity: 10 Second operand has 7 states, 6 states have (on average 2.3333333333333335) internal successors, (14), 7 states have internal predecessors, (14), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:54:29,066 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 20:54:29,067 INFO L93 Difference]: Finished difference Result 20 states and 27 transitions. [2022-11-02 20:54:29,067 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 20 states and 27 transitions. [2022-11-02 20:54:29,067 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-11-02 20:54:29,068 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 20 states to 17 states and 24 transitions. [2022-11-02 20:54:29,068 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7 [2022-11-02 20:54:29,068 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7 [2022-11-02 20:54:29,068 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17 states and 24 transitions. [2022-11-02 20:54:29,068 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-02 20:54:29,068 INFO L218 hiAutomatonCegarLoop]: Abstraction has 17 states and 24 transitions. [2022-11-02 20:54:29,069 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17 states and 24 transitions. [2022-11-02 20:54:29,072 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17 to 17. [2022-11-02 20:54:29,079 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17 states, 17 states have (on average 1.411764705882353) internal successors, (24), 16 states have internal predecessors, (24), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:54:29,079 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17 states to 17 states and 24 transitions. [2022-11-02 20:54:29,080 INFO L240 hiAutomatonCegarLoop]: Abstraction has 17 states and 24 transitions. [2022-11-02 20:54:29,095 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-11-02 20:54:29,096 INFO L428 stractBuchiCegarLoop]: Abstraction has 17 states and 24 transitions. [2022-11-02 20:54:29,096 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-11-02 20:54:29,096 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17 states and 24 transitions. [2022-11-02 20:54:29,097 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-11-02 20:54:29,097 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 20:54:29,097 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 20:54:29,097 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 1, 1, 1, 1, 1] [2022-11-02 20:54:29,097 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2022-11-02 20:54:29,097 INFO L748 eck$LassoCheckResult]: Stem: 341#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 342#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 349#L26 main_~i~0#1 := 0; 343#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 345#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 346#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 354#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 352#L29-1 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 350#L29-2 assume main_~i~0#1 >= 100; 348#L39 [2022-11-02 20:54:29,097 INFO L750 eck$LassoCheckResult]: Loop: 348#L39 assume true; 348#L39 [2022-11-02 20:54:29,098 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:54:29,098 INFO L85 PathProgramCache]: Analyzing trace with hash -1366227831, now seen corresponding path program 2 times [2022-11-02 20:54:29,098 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:54:29,098 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [467641986] [2022-11-02 20:54:29,098 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:54:29,099 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:54:29,107 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:54:29,111 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Forceful destruction successful, exit code 0 [2022-11-02 20:54:29,181 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:54:29,181 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 20:54:29,181 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [467641986] [2022-11-02 20:54:29,181 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [467641986] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 20:54:29,182 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [685348613] [2022-11-02 20:54:29,182 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-02 20:54:29,182 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 20:54:29,182 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 20:54:29,183 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 20:54:29,190 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process [2022-11-02 20:54:29,227 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-02 20:54:29,227 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-02 20:54:29,228 INFO L263 TraceCheckSpWp]: Trace formula consists of 42 conjuncts, 6 conjunts are in the unsatisfiable core [2022-11-02 20:54:29,229 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 20:54:29,253 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:54:29,253 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 20:54:29,317 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:54:29,318 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [685348613] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 20:54:29,318 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 20:54:29,318 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6] total 12 [2022-11-02 20:54:29,318 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1950596763] [2022-11-02 20:54:29,318 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 20:54:29,319 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-02 20:54:29,319 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:54:29,319 INFO L85 PathProgramCache]: Analyzing trace with hash 84, now seen corresponding path program 5 times [2022-11-02 20:54:29,319 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:54:29,319 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1820932528] [2022-11-02 20:54:29,319 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:54:29,320 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:54:29,321 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:54:29,322 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:54:29,322 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:54:29,323 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:54:29,325 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 20:54:29,326 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2022-11-02 20:54:29,326 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=78, Unknown=0, NotChecked=0, Total=156 [2022-11-02 20:54:29,326 INFO L87 Difference]: Start difference. First operand 17 states and 24 transitions. cyclomatic complexity: 10 Second operand has 13 states, 12 states have (on average 1.5) internal successors, (18), 13 states have internal predecessors, (18), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:54:29,417 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 20:54:29,418 INFO L93 Difference]: Finished difference Result 90 states and 109 transitions. [2022-11-02 20:54:29,418 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 90 states and 109 transitions. [2022-11-02 20:54:29,420 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 7 [2022-11-02 20:54:29,420 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 90 states to 84 states and 103 transitions. [2022-11-02 20:54:29,421 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19 [2022-11-02 20:54:29,421 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19 [2022-11-02 20:54:29,421 INFO L73 IsDeterministic]: Start isDeterministic. Operand 84 states and 103 transitions. [2022-11-02 20:54:29,421 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-02 20:54:29,421 INFO L218 hiAutomatonCegarLoop]: Abstraction has 84 states and 103 transitions. [2022-11-02 20:54:29,422 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 84 states and 103 transitions. [2022-11-02 20:54:29,424 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 84 to 23. [2022-11-02 20:54:29,424 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 23 states, 23 states have (on average 1.565217391304348) internal successors, (36), 22 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:54:29,424 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23 states to 23 states and 36 transitions. [2022-11-02 20:54:29,425 INFO L240 hiAutomatonCegarLoop]: Abstraction has 23 states and 36 transitions. [2022-11-02 20:54:29,425 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2022-11-02 20:54:29,426 INFO L428 stractBuchiCegarLoop]: Abstraction has 23 states and 36 transitions. [2022-11-02 20:54:29,426 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-11-02 20:54:29,426 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 23 states and 36 transitions. [2022-11-02 20:54:29,426 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-11-02 20:54:29,427 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 20:54:29,427 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 20:54:29,427 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 20:54:29,427 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2022-11-02 20:54:29,427 INFO L748 eck$LassoCheckResult]: Stem: 512#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 513#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 520#L26 main_~i~0#1 := 0; 514#L29-1 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 515#L29-2 assume !(main_~i~0#1 >= 100);main_~j~0#1 := 0; 510#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 511#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 532#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 531#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 530#L35-1 assume !(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1; 518#L35-2 assume main_~j~0#1 >= 100; 519#L39 [2022-11-02 20:54:29,428 INFO L750 eck$LassoCheckResult]: Loop: 519#L39 assume true; 519#L39 [2022-11-02 20:54:29,428 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:54:29,428 INFO L85 PathProgramCache]: Analyzing trace with hash 2054548532, now seen corresponding path program 2 times [2022-11-02 20:54:29,428 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:54:29,428 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1725754126] [2022-11-02 20:54:29,428 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:54:29,429 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:54:29,436 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:54:29,508 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:54:29,508 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 20:54:29,508 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1725754126] [2022-11-02 20:54:29,508 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1725754126] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 20:54:29,508 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1913588631] [2022-11-02 20:54:29,509 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-02 20:54:29,509 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 20:54:29,509 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 20:54:29,514 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 20:54:29,534 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Waiting until timeout for monitored process [2022-11-02 20:54:29,558 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-02 20:54:29,558 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-02 20:54:29,559 INFO L263 TraceCheckSpWp]: Trace formula consists of 54 conjuncts, 6 conjunts are in the unsatisfiable core [2022-11-02 20:54:29,561 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 20:54:29,593 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:54:29,593 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 20:54:29,675 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:54:29,676 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1913588631] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 20:54:29,676 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 20:54:29,676 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6] total 12 [2022-11-02 20:54:29,678 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1747881492] [2022-11-02 20:54:29,679 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 20:54:29,679 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-02 20:54:29,680 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:54:29,680 INFO L85 PathProgramCache]: Analyzing trace with hash 84, now seen corresponding path program 6 times [2022-11-02 20:54:29,680 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:54:29,680 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1304174973] [2022-11-02 20:54:29,680 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:54:29,681 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:54:29,683 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:54:29,683 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:54:29,683 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:54:29,684 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:54:29,687 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 20:54:29,688 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2022-11-02 20:54:29,688 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=78, Unknown=0, NotChecked=0, Total=156 [2022-11-02 20:54:29,689 INFO L87 Difference]: Start difference. First operand 23 states and 36 transitions. cyclomatic complexity: 16 Second operand has 13 states, 12 states have (on average 1.6666666666666667) internal successors, (20), 13 states have internal predecessors, (20), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:54:29,721 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 20:54:29,721 INFO L93 Difference]: Finished difference Result 35 states and 48 transitions. [2022-11-02 20:54:29,721 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 35 states and 48 transitions. [2022-11-02 20:54:29,725 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-11-02 20:54:29,727 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 35 states to 29 states and 42 transitions. [2022-11-02 20:54:29,727 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7 [2022-11-02 20:54:29,727 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7 [2022-11-02 20:54:29,728 INFO L73 IsDeterministic]: Start isDeterministic. Operand 29 states and 42 transitions. [2022-11-02 20:54:29,728 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-02 20:54:29,728 INFO L218 hiAutomatonCegarLoop]: Abstraction has 29 states and 42 transitions. [2022-11-02 20:54:29,728 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29 states and 42 transitions. [2022-11-02 20:54:29,733 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29 to 29. [2022-11-02 20:54:29,734 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 29 states, 29 states have (on average 1.4482758620689655) internal successors, (42), 28 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:54:29,735 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29 states to 29 states and 42 transitions. [2022-11-02 20:54:29,735 INFO L240 hiAutomatonCegarLoop]: Abstraction has 29 states and 42 transitions. [2022-11-02 20:54:29,736 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2022-11-02 20:54:29,738 INFO L428 stractBuchiCegarLoop]: Abstraction has 29 states and 42 transitions. [2022-11-02 20:54:29,738 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-11-02 20:54:29,738 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 29 states and 42 transitions. [2022-11-02 20:54:29,739 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-11-02 20:54:29,739 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 20:54:29,740 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 20:54:29,740 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [10, 1, 1, 1, 1, 1] [2022-11-02 20:54:29,740 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2022-11-02 20:54:29,741 INFO L748 eck$LassoCheckResult]: Stem: 646#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 647#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 654#L26 main_~i~0#1 := 0; 648#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 650#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 651#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 669#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 667#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 665#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 663#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 661#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 660#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 659#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 657#L29-1 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 655#L29-2 assume main_~i~0#1 >= 100; 653#L39 [2022-11-02 20:54:29,741 INFO L750 eck$LassoCheckResult]: Loop: 653#L39 assume true; 653#L39 [2022-11-02 20:54:29,741 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:54:29,741 INFO L85 PathProgramCache]: Analyzing trace with hash 1329396905, now seen corresponding path program 3 times [2022-11-02 20:54:29,743 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:54:29,745 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [597178772] [2022-11-02 20:54:29,745 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:54:29,745 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:54:29,763 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:54:29,967 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:54:29,967 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 20:54:29,967 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [597178772] [2022-11-02 20:54:29,967 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [597178772] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 20:54:29,968 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [431201265] [2022-11-02 20:54:29,968 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-02 20:54:29,968 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 20:54:29,968 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 20:54:29,974 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 20:54:29,986 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2022-11-02 20:54:30,030 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2022-11-02 20:54:30,030 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-02 20:54:30,031 INFO L263 TraceCheckSpWp]: Trace formula consists of 66 conjuncts, 12 conjunts are in the unsatisfiable core [2022-11-02 20:54:30,033 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 20:54:30,075 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:54:30,075 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 20:54:30,321 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:54:30,321 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [431201265] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 20:54:30,321 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 20:54:30,321 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12] total 24 [2022-11-02 20:54:30,322 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1486223844] [2022-11-02 20:54:30,322 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 20:54:30,322 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-02 20:54:30,322 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:54:30,323 INFO L85 PathProgramCache]: Analyzing trace with hash 84, now seen corresponding path program 7 times [2022-11-02 20:54:30,323 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:54:30,323 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [277779469] [2022-11-02 20:54:30,323 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:54:30,323 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:54:30,325 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:54:30,325 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:54:30,326 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:54:30,327 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:54:30,329 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 20:54:30,329 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2022-11-02 20:54:30,330 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=300, Invalid=300, Unknown=0, NotChecked=0, Total=600 [2022-11-02 20:54:30,330 INFO L87 Difference]: Start difference. First operand 29 states and 42 transitions. cyclomatic complexity: 16 Second operand has 25 states, 24 states have (on average 1.25) internal successors, (30), 25 states have internal predecessors, (30), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:54:30,548 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 20:54:30,549 INFO L93 Difference]: Finished difference Result 285 states and 322 transitions. [2022-11-02 20:54:30,549 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 285 states and 322 transitions. [2022-11-02 20:54:30,555 INFO L131 ngComponentsAnalysis]: Automaton has 13 accepting balls. 13 [2022-11-02 20:54:30,563 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 285 states to 273 states and 310 transitions. [2022-11-02 20:54:30,563 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 31 [2022-11-02 20:54:30,563 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 31 [2022-11-02 20:54:30,563 INFO L73 IsDeterministic]: Start isDeterministic. Operand 273 states and 310 transitions. [2022-11-02 20:54:30,564 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-02 20:54:30,564 INFO L218 hiAutomatonCegarLoop]: Abstraction has 273 states and 310 transitions. [2022-11-02 20:54:30,568 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 273 states and 310 transitions. [2022-11-02 20:54:30,573 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 273 to 41. [2022-11-02 20:54:30,573 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 41 states, 41 states have (on average 1.6097560975609757) internal successors, (66), 40 states have internal predecessors, (66), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:54:30,574 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41 states to 41 states and 66 transitions. [2022-11-02 20:54:30,574 INFO L240 hiAutomatonCegarLoop]: Abstraction has 41 states and 66 transitions. [2022-11-02 20:54:30,574 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2022-11-02 20:54:30,575 INFO L428 stractBuchiCegarLoop]: Abstraction has 41 states and 66 transitions. [2022-11-02 20:54:30,575 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-11-02 20:54:30,575 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 41 states and 66 transitions. [2022-11-02 20:54:30,576 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-11-02 20:54:30,576 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 20:54:30,576 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 20:54:30,577 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [10, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 20:54:30,577 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2022-11-02 20:54:30,577 INFO L748 eck$LassoCheckResult]: Stem: 1072#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 1073#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 1080#L26 main_~i~0#1 := 0; 1074#L29-1 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 1075#L29-2 assume !(main_~i~0#1 >= 100);main_~j~0#1 := 0; 1070#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1071#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1110#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1109#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1108#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1107#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1106#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1105#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1104#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1103#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1102#L35-1 assume !(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1; 1078#L35-2 assume main_~j~0#1 >= 100; 1079#L39 [2022-11-02 20:54:30,577 INFO L750 eck$LassoCheckResult]: Loop: 1079#L39 assume true; 1079#L39 [2022-11-02 20:54:30,578 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:54:30,578 INFO L85 PathProgramCache]: Analyzing trace with hash -719352108, now seen corresponding path program 3 times [2022-11-02 20:54:30,578 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:54:30,578 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1199654802] [2022-11-02 20:54:30,578 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:54:30,579 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:54:30,596 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:54:30,804 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:54:30,804 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 20:54:30,804 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1199654802] [2022-11-02 20:54:30,804 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1199654802] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 20:54:30,805 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [474509600] [2022-11-02 20:54:30,805 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-02 20:54:30,805 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 20:54:30,805 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 20:54:30,810 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 20:54:30,818 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Waiting until timeout for monitored process [2022-11-02 20:54:30,876 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2022-11-02 20:54:30,877 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-02 20:54:30,878 INFO L263 TraceCheckSpWp]: Trace formula consists of 90 conjuncts, 12 conjunts are in the unsatisfiable core [2022-11-02 20:54:30,880 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 20:54:30,932 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:54:30,932 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 20:54:31,187 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:54:31,188 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [474509600] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 20:54:31,188 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 20:54:31,188 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12] total 24 [2022-11-02 20:54:31,188 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2025923356] [2022-11-02 20:54:31,188 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 20:54:31,189 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-02 20:54:31,189 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:54:31,189 INFO L85 PathProgramCache]: Analyzing trace with hash 84, now seen corresponding path program 8 times [2022-11-02 20:54:31,189 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:54:31,189 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1715366466] [2022-11-02 20:54:31,189 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:54:31,190 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:54:31,193 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:54:31,193 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:54:31,195 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:54:31,198 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:54:31,202 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 20:54:31,203 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2022-11-02 20:54:31,205 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=300, Invalid=300, Unknown=0, NotChecked=0, Total=600 [2022-11-02 20:54:31,205 INFO L87 Difference]: Start difference. First operand 41 states and 66 transitions. cyclomatic complexity: 28 Second operand has 25 states, 24 states have (on average 1.3333333333333333) internal successors, (32), 25 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:54:31,246 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 20:54:31,246 INFO L93 Difference]: Finished difference Result 65 states and 90 transitions. [2022-11-02 20:54:31,247 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 65 states and 90 transitions. [2022-11-02 20:54:31,247 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-11-02 20:54:31,248 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 65 states to 53 states and 78 transitions. [2022-11-02 20:54:31,248 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7 [2022-11-02 20:54:31,248 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7 [2022-11-02 20:54:31,248 INFO L73 IsDeterministic]: Start isDeterministic. Operand 53 states and 78 transitions. [2022-11-02 20:54:31,249 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-02 20:54:31,249 INFO L218 hiAutomatonCegarLoop]: Abstraction has 53 states and 78 transitions. [2022-11-02 20:54:31,249 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53 states and 78 transitions. [2022-11-02 20:54:31,257 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53 to 53. [2022-11-02 20:54:31,258 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 53 states, 53 states have (on average 1.471698113207547) internal successors, (78), 52 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:54:31,262 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53 states to 53 states and 78 transitions. [2022-11-02 20:54:31,262 INFO L240 hiAutomatonCegarLoop]: Abstraction has 53 states and 78 transitions. [2022-11-02 20:54:31,263 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2022-11-02 20:54:31,264 INFO L428 stractBuchiCegarLoop]: Abstraction has 53 states and 78 transitions. [2022-11-02 20:54:31,265 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-11-02 20:54:31,265 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 53 states and 78 transitions. [2022-11-02 20:54:31,266 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-11-02 20:54:31,266 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 20:54:31,266 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 20:54:31,267 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [22, 1, 1, 1, 1, 1] [2022-11-02 20:54:31,268 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2022-11-02 20:54:31,268 INFO L748 eck$LassoCheckResult]: Stem: 1302#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 1303#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 1310#L26 main_~i~0#1 := 0; 1304#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1306#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1307#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1352#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1351#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1349#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1347#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1345#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1343#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1341#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1339#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1337#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1335#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1333#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1331#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1329#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1327#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1325#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1323#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1321#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1319#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1315#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1313#L29-1 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 1311#L29-2 assume main_~i~0#1 >= 100; 1309#L39 [2022-11-02 20:54:31,268 INFO L750 eck$LassoCheckResult]: Loop: 1309#L39 assume true; 1309#L39 [2022-11-02 20:54:31,268 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:54:31,268 INFO L85 PathProgramCache]: Analyzing trace with hash -525392663, now seen corresponding path program 4 times [2022-11-02 20:54:31,269 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:54:31,269 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2093634282] [2022-11-02 20:54:31,269 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:54:31,269 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:54:31,300 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:54:31,816 INFO L134 CoverageAnalysis]: Checked inductivity of 253 backedges. 0 proven. 253 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:54:31,816 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 20:54:31,816 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2093634282] [2022-11-02 20:54:31,817 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2093634282] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 20:54:31,817 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [108115247] [2022-11-02 20:54:31,817 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-02 20:54:31,817 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 20:54:31,817 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 20:54:31,822 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 20:54:31,843 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Waiting until timeout for monitored process [2022-11-02 20:54:31,880 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-02 20:54:31,881 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-02 20:54:31,882 INFO L263 TraceCheckSpWp]: Trace formula consists of 114 conjuncts, 24 conjunts are in the unsatisfiable core [2022-11-02 20:54:31,885 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 20:54:31,987 INFO L134 CoverageAnalysis]: Checked inductivity of 253 backedges. 0 proven. 253 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:54:31,988 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 20:54:32,863 INFO L134 CoverageAnalysis]: Checked inductivity of 253 backedges. 0 proven. 253 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:54:32,863 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [108115247] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 20:54:32,863 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 20:54:32,863 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24, 24] total 48 [2022-11-02 20:54:32,864 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [643948622] [2022-11-02 20:54:32,864 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 20:54:32,864 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-02 20:54:32,864 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:54:32,865 INFO L85 PathProgramCache]: Analyzing trace with hash 84, now seen corresponding path program 9 times [2022-11-02 20:54:32,865 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:54:32,865 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2145995169] [2022-11-02 20:54:32,865 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:54:32,865 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:54:32,867 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:54:32,870 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:54:32,871 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:54:32,872 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:54:32,874 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 20:54:32,876 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2022-11-02 20:54:32,877 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1176, Invalid=1176, Unknown=0, NotChecked=0, Total=2352 [2022-11-02 20:54:32,880 INFO L87 Difference]: Start difference. First operand 53 states and 78 transitions. cyclomatic complexity: 28 Second operand has 49 states, 48 states have (on average 1.125) internal successors, (54), 49 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:54:33,439 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 20:54:33,439 INFO L93 Difference]: Finished difference Result 999 states and 1072 transitions. [2022-11-02 20:54:33,439 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 999 states and 1072 transitions. [2022-11-02 20:54:33,446 INFO L131 ngComponentsAnalysis]: Automaton has 25 accepting balls. 25 [2022-11-02 20:54:33,451 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 999 states to 975 states and 1048 transitions. [2022-11-02 20:54:33,451 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 55 [2022-11-02 20:54:33,451 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 55 [2022-11-02 20:54:33,451 INFO L73 IsDeterministic]: Start isDeterministic. Operand 975 states and 1048 transitions. [2022-11-02 20:54:33,453 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-02 20:54:33,453 INFO L218 hiAutomatonCegarLoop]: Abstraction has 975 states and 1048 transitions. [2022-11-02 20:54:33,454 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 975 states and 1048 transitions. [2022-11-02 20:54:33,461 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 975 to 77. [2022-11-02 20:54:33,462 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 77 states, 77 states have (on average 1.6363636363636365) internal successors, (126), 76 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:54:33,463 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 77 states to 77 states and 126 transitions. [2022-11-02 20:54:33,463 INFO L240 hiAutomatonCegarLoop]: Abstraction has 77 states and 126 transitions. [2022-11-02 20:54:33,463 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2022-11-02 20:54:33,464 INFO L428 stractBuchiCegarLoop]: Abstraction has 77 states and 126 transitions. [2022-11-02 20:54:33,464 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-11-02 20:54:33,464 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 77 states and 126 transitions. [2022-11-02 20:54:33,465 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-11-02 20:54:33,465 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 20:54:33,465 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 20:54:33,466 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [22, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 20:54:33,466 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2022-11-02 20:54:33,466 INFO L748 eck$LassoCheckResult]: Stem: 2562#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 2563#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 2570#L26 main_~i~0#1 := 0; 2564#L29-1 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 2565#L29-2 assume !(main_~i~0#1 >= 100);main_~j~0#1 := 0; 2560#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 2561#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 2636#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 2635#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 2634#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 2633#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 2632#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 2631#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 2630#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 2629#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 2628#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 2627#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 2626#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 2625#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 2624#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 2623#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 2622#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 2621#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 2620#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 2619#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 2618#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 2617#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 2616#L35-1 assume !(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1; 2568#L35-2 assume main_~j~0#1 >= 100; 2569#L39 [2022-11-02 20:54:33,466 INFO L750 eck$LassoCheckResult]: Loop: 2569#L39 assume true; 2569#L39 [2022-11-02 20:54:33,467 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:54:33,467 INFO L85 PathProgramCache]: Analyzing trace with hash 798452756, now seen corresponding path program 4 times [2022-11-02 20:54:33,467 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:54:33,467 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [833203679] [2022-11-02 20:54:33,467 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:54:33,468 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:54:33,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:54:33,920 INFO L134 CoverageAnalysis]: Checked inductivity of 253 backedges. 0 proven. 253 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:54:33,920 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 20:54:33,920 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [833203679] [2022-11-02 20:54:33,920 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [833203679] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 20:54:33,921 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2136217931] [2022-11-02 20:54:33,921 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-02 20:54:33,921 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 20:54:33,921 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 20:54:33,923 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 20:54:33,939 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Waiting until timeout for monitored process [2022-11-02 20:54:33,984 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-02 20:54:33,984 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-02 20:54:33,986 INFO L263 TraceCheckSpWp]: Trace formula consists of 162 conjuncts, 24 conjunts are in the unsatisfiable core [2022-11-02 20:54:33,988 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 20:54:34,053 INFO L134 CoverageAnalysis]: Checked inductivity of 253 backedges. 0 proven. 253 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:54:34,053 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 20:54:34,882 INFO L134 CoverageAnalysis]: Checked inductivity of 253 backedges. 0 proven. 253 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:54:34,882 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2136217931] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 20:54:34,883 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 20:54:34,883 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24, 24] total 48 [2022-11-02 20:54:34,883 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [254189420] [2022-11-02 20:54:34,883 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 20:54:34,884 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-02 20:54:34,884 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:54:34,884 INFO L85 PathProgramCache]: Analyzing trace with hash 84, now seen corresponding path program 10 times [2022-11-02 20:54:34,884 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:54:34,884 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [498967428] [2022-11-02 20:54:34,885 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:54:34,885 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:54:34,886 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:54:34,887 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:54:34,887 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:54:34,888 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:54:34,893 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 20:54:34,894 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2022-11-02 20:54:34,895 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1176, Invalid=1176, Unknown=0, NotChecked=0, Total=2352 [2022-11-02 20:54:34,896 INFO L87 Difference]: Start difference. First operand 77 states and 126 transitions. cyclomatic complexity: 52 Second operand has 49 states, 48 states have (on average 1.1666666666666667) internal successors, (56), 49 states have internal predecessors, (56), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:54:34,975 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 20:54:34,975 INFO L93 Difference]: Finished difference Result 125 states and 174 transitions. [2022-11-02 20:54:34,975 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 125 states and 174 transitions. [2022-11-02 20:54:34,976 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-11-02 20:54:34,977 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 125 states to 101 states and 150 transitions. [2022-11-02 20:54:34,977 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7 [2022-11-02 20:54:34,977 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7 [2022-11-02 20:54:34,978 INFO L73 IsDeterministic]: Start isDeterministic. Operand 101 states and 150 transitions. [2022-11-02 20:54:34,979 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-02 20:54:34,980 INFO L218 hiAutomatonCegarLoop]: Abstraction has 101 states and 150 transitions. [2022-11-02 20:54:34,980 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 101 states and 150 transitions. [2022-11-02 20:54:34,992 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 101 to 101. [2022-11-02 20:54:34,992 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 101 states, 101 states have (on average 1.4851485148514851) internal successors, (150), 100 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:54:34,993 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 101 states to 101 states and 150 transitions. [2022-11-02 20:54:34,994 INFO L240 hiAutomatonCegarLoop]: Abstraction has 101 states and 150 transitions. [2022-11-02 20:54:34,994 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2022-11-02 20:54:34,995 INFO L428 stractBuchiCegarLoop]: Abstraction has 101 states and 150 transitions. [2022-11-02 20:54:34,995 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-11-02 20:54:34,995 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 101 states and 150 transitions. [2022-11-02 20:54:34,996 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-11-02 20:54:34,996 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 20:54:34,996 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 20:54:35,000 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [46, 1, 1, 1, 1, 1] [2022-11-02 20:54:35,000 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2022-11-02 20:54:35,000 INFO L748 eck$LassoCheckResult]: Stem: 2984#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 2985#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 2992#L26 main_~i~0#1 := 0; 2986#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2988#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2989#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3082#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3081#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3079#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3077#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3075#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3073#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3071#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3069#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3067#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3065#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3063#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3061#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3059#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3057#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3055#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3053#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3051#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3049#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3047#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3045#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3043#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3041#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3039#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3037#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3035#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3033#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3031#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3029#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3027#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3025#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3023#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3021#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3019#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3017#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3015#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3013#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3011#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3009#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3007#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3005#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3003#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3001#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2997#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2995#L29-1 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 2993#L29-2 assume main_~i~0#1 >= 100; 2991#L39 [2022-11-02 20:54:35,004 INFO L750 eck$LassoCheckResult]: Loop: 2991#L39 assume true; 2991#L39 [2022-11-02 20:54:35,004 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:54:35,004 INFO L85 PathProgramCache]: Analyzing trace with hash 1685345641, now seen corresponding path program 5 times [2022-11-02 20:54:35,005 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:54:35,005 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [697637978] [2022-11-02 20:54:35,005 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:54:35,006 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:54:35,050 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:54:36,707 INFO L134 CoverageAnalysis]: Checked inductivity of 1081 backedges. 0 proven. 1081 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:54:36,707 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 20:54:36,707 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [697637978] [2022-11-02 20:54:36,707 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [697637978] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 20:54:36,708 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2133656128] [2022-11-02 20:54:36,708 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-02 20:54:36,708 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 20:54:36,708 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 20:54:36,714 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 20:54:36,740 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Waiting until timeout for monitored process [2022-11-02 20:54:36,799 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 24 check-sat command(s) [2022-11-02 20:54:36,799 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-02 20:54:36,802 INFO L263 TraceCheckSpWp]: Trace formula consists of 210 conjuncts, 48 conjunts are in the unsatisfiable core [2022-11-02 20:54:36,804 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 20:54:36,931 INFO L134 CoverageAnalysis]: Checked inductivity of 1081 backedges. 0 proven. 1081 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:54:36,931 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 20:54:39,823 INFO L134 CoverageAnalysis]: Checked inductivity of 1081 backedges. 0 proven. 1081 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:54:39,823 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2133656128] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 20:54:39,824 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 20:54:39,824 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 48, 48] total 96 [2022-11-02 20:54:39,826 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [53260349] [2022-11-02 20:54:39,826 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 20:54:39,830 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-02 20:54:39,831 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:54:39,831 INFO L85 PathProgramCache]: Analyzing trace with hash 84, now seen corresponding path program 11 times [2022-11-02 20:54:39,832 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:54:39,834 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1583614234] [2022-11-02 20:54:39,834 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:54:39,835 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:54:39,837 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:54:39,837 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:54:39,838 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:54:39,838 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:54:39,841 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 20:54:39,842 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 97 interpolants. [2022-11-02 20:54:39,846 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=4656, Invalid=4656, Unknown=0, NotChecked=0, Total=9312 [2022-11-02 20:54:39,847 INFO L87 Difference]: Start difference. First operand 101 states and 150 transitions. cyclomatic complexity: 52 Second operand has 97 states, 96 states have (on average 1.0625) internal successors, (102), 97 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:54:41,633 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 20:54:41,633 INFO L93 Difference]: Finished difference Result 3723 states and 3868 transitions. [2022-11-02 20:54:41,633 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3723 states and 3868 transitions. [2022-11-02 20:54:41,659 INFO L131 ngComponentsAnalysis]: Automaton has 49 accepting balls. 49 [2022-11-02 20:54:41,675 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3723 states to 3675 states and 3820 transitions. [2022-11-02 20:54:41,675 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 103 [2022-11-02 20:54:41,675 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 103 [2022-11-02 20:54:41,676 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3675 states and 3820 transitions. [2022-11-02 20:54:41,679 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-02 20:54:41,680 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3675 states and 3820 transitions. [2022-11-02 20:54:41,683 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3675 states and 3820 transitions. [2022-11-02 20:54:41,698 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3675 to 149. [2022-11-02 20:54:41,698 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 149 states, 149 states have (on average 1.651006711409396) internal successors, (246), 148 states have internal predecessors, (246), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:54:41,699 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 149 states to 149 states and 246 transitions. [2022-11-02 20:54:41,699 INFO L240 hiAutomatonCegarLoop]: Abstraction has 149 states and 246 transitions. [2022-11-02 20:54:41,700 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 96 states. [2022-11-02 20:54:41,700 INFO L428 stractBuchiCegarLoop]: Abstraction has 149 states and 246 transitions. [2022-11-02 20:54:41,700 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-11-02 20:54:41,701 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 149 states and 246 transitions. [2022-11-02 20:54:41,702 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-11-02 20:54:41,702 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 20:54:41,702 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 20:54:41,703 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [46, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 20:54:41,703 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2022-11-02 20:54:41,703 INFO L748 eck$LassoCheckResult]: Stem: 7208#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 7209#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 7216#L26 main_~i~0#1 := 0; 7210#L29-1 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 7211#L29-2 assume !(main_~i~0#1 >= 100);main_~j~0#1 := 0; 7206#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7207#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7354#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7353#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7352#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7351#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7350#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7349#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7348#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7347#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7346#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7345#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7344#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7343#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7342#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7341#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7340#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7339#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7338#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7337#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7336#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7335#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7334#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7333#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7332#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7331#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7330#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7329#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7328#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7327#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7326#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7325#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7324#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7323#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7322#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7321#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7320#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7319#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7318#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7317#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7316#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7315#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7314#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7313#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7312#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7311#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7310#L35-1 assume !(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1; 7214#L35-2 assume main_~j~0#1 >= 100; 7215#L39 [2022-11-02 20:54:41,704 INFO L750 eck$LassoCheckResult]: Loop: 7215#L39 assume true; 7215#L39 [2022-11-02 20:54:41,704 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:54:41,704 INFO L85 PathProgramCache]: Analyzing trace with hash 821134996, now seen corresponding path program 5 times [2022-11-02 20:54:41,704 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:54:41,705 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [245559521] [2022-11-02 20:54:41,705 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:54:41,705 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:54:41,729 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:54:43,124 INFO L134 CoverageAnalysis]: Checked inductivity of 1081 backedges. 0 proven. 1081 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:54:43,124 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 20:54:43,124 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [245559521] [2022-11-02 20:54:43,124 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [245559521] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 20:54:43,125 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [591834492] [2022-11-02 20:54:43,125 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-02 20:54:43,125 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 20:54:43,125 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 20:54:43,127 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 20:54:43,130 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Waiting until timeout for monitored process [2022-11-02 20:54:43,222 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 24 check-sat command(s) [2022-11-02 20:54:43,222 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-02 20:54:43,224 INFO L263 TraceCheckSpWp]: Trace formula consists of 306 conjuncts, 48 conjunts are in the unsatisfiable core [2022-11-02 20:54:43,227 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 20:54:43,363 INFO L134 CoverageAnalysis]: Checked inductivity of 1081 backedges. 0 proven. 1081 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:54:43,363 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 20:54:46,142 INFO L134 CoverageAnalysis]: Checked inductivity of 1081 backedges. 0 proven. 1081 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:54:46,143 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [591834492] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 20:54:46,143 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 20:54:46,143 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 48, 48] total 96 [2022-11-02 20:54:46,143 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [33285974] [2022-11-02 20:54:46,143 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 20:54:46,144 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-02 20:54:46,144 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:54:46,144 INFO L85 PathProgramCache]: Analyzing trace with hash 84, now seen corresponding path program 12 times [2022-11-02 20:54:46,145 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:54:46,145 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [671506906] [2022-11-02 20:54:46,145 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:54:46,145 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:54:46,147 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:54:46,147 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:54:46,148 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:54:46,149 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:54:46,156 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 20:54:46,158 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 97 interpolants. [2022-11-02 20:54:46,161 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=4656, Invalid=4656, Unknown=0, NotChecked=0, Total=9312 [2022-11-02 20:54:46,161 INFO L87 Difference]: Start difference. First operand 149 states and 246 transitions. cyclomatic complexity: 100 Second operand has 97 states, 96 states have (on average 1.0833333333333333) internal successors, (104), 97 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:54:46,391 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 20:54:46,391 INFO L93 Difference]: Finished difference Result 245 states and 342 transitions. [2022-11-02 20:54:46,391 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 245 states and 342 transitions. [2022-11-02 20:54:46,394 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-11-02 20:54:46,395 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 245 states to 197 states and 294 transitions. [2022-11-02 20:54:46,395 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7 [2022-11-02 20:54:46,395 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7 [2022-11-02 20:54:46,396 INFO L73 IsDeterministic]: Start isDeterministic. Operand 197 states and 294 transitions. [2022-11-02 20:54:46,396 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-02 20:54:46,396 INFO L218 hiAutomatonCegarLoop]: Abstraction has 197 states and 294 transitions. [2022-11-02 20:54:46,397 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 197 states and 294 transitions. [2022-11-02 20:54:46,399 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 197 to 197. [2022-11-02 20:54:46,400 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 197 states, 197 states have (on average 1.4923857868020305) internal successors, (294), 196 states have internal predecessors, (294), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:54:46,400 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 197 states to 197 states and 294 transitions. [2022-11-02 20:54:46,401 INFO L240 hiAutomatonCegarLoop]: Abstraction has 197 states and 294 transitions. [2022-11-02 20:54:46,401 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 96 states. [2022-11-02 20:54:46,402 INFO L428 stractBuchiCegarLoop]: Abstraction has 197 states and 294 transitions. [2022-11-02 20:54:46,402 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-11-02 20:54:46,402 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 197 states and 294 transitions. [2022-11-02 20:54:46,404 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-11-02 20:54:46,404 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 20:54:46,404 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 20:54:46,405 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [94, 1, 1, 1, 1, 1] [2022-11-02 20:54:46,406 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2022-11-02 20:54:46,406 INFO L748 eck$LassoCheckResult]: Stem: 8014#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 8015#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 8022#L26 main_~i~0#1 := 0; 8016#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8018#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8019#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8208#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8207#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8205#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8203#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8201#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8199#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8197#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8195#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8193#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8191#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8189#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8187#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8185#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8183#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8181#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8179#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8177#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8175#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8173#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8171#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8169#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8167#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8165#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8163#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8161#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8159#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8157#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8155#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8153#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8151#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8149#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8147#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8145#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8143#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8141#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8139#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8137#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8135#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8133#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8131#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8129#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8127#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8125#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8123#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8121#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8119#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8117#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8115#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8113#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8111#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8109#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8107#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8105#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8103#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8101#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8099#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8097#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8095#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8093#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8091#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8089#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8087#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8085#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8083#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8081#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8079#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8077#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8075#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8073#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8071#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8069#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8067#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8065#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8063#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8061#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8059#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8057#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8055#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8053#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8051#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8049#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8047#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8045#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8043#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8041#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8039#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8037#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8035#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8033#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8031#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8027#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8025#L29-1 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 8023#L29-2 assume main_~i~0#1 >= 100; 8021#L39 [2022-11-02 20:54:46,406 INFO L750 eck$LassoCheckResult]: Loop: 8021#L39 assume true; 8021#L39 [2022-11-02 20:54:46,407 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:54:46,407 INFO L85 PathProgramCache]: Analyzing trace with hash -415091095, now seen corresponding path program 6 times [2022-11-02 20:54:46,407 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:54:46,407 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [551203086] [2022-11-02 20:54:46,408 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:54:46,408 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:54:46,464 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:54:51,714 INFO L134 CoverageAnalysis]: Checked inductivity of 4465 backedges. 0 proven. 4465 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:54:51,714 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 20:54:51,714 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [551203086] [2022-11-02 20:54:51,714 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [551203086] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 20:54:51,714 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [815553705] [2022-11-02 20:54:51,715 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-11-02 20:54:51,715 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 20:54:51,715 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 20:54:51,717 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 20:54:51,719 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Waiting until timeout for monitored process [2022-11-02 20:54:51,851 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 48 check-sat command(s) [2022-11-02 20:54:51,851 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-02 20:54:51,854 INFO L263 TraceCheckSpWp]: Trace formula consists of 402 conjuncts, 96 conjunts are in the unsatisfiable core [2022-11-02 20:54:51,858 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 20:54:52,131 INFO L134 CoverageAnalysis]: Checked inductivity of 4465 backedges. 0 proven. 4465 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:54:52,131 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 20:54:56,553 INFO L134 CoverageAnalysis]: Checked inductivity of 4465 backedges. 0 proven. 4465 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:54:56,553 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [815553705] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 20:54:56,553 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 20:54:56,553 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [96, 96, 96] total 102 [2022-11-02 20:54:56,553 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1966334349] [2022-11-02 20:54:56,554 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 20:54:56,554 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-02 20:54:56,554 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:54:56,554 INFO L85 PathProgramCache]: Analyzing trace with hash 84, now seen corresponding path program 13 times [2022-11-02 20:54:56,554 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:54:56,554 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [767835604] [2022-11-02 20:54:56,555 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:54:56,555 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:54:56,556 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:54:56,557 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:54:56,557 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:54:56,558 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:54:56,568 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 20:54:56,570 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 103 interpolants. [2022-11-02 20:54:56,572 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5253, Invalid=5253, Unknown=0, NotChecked=0, Total=10506 [2022-11-02 20:54:56,572 INFO L87 Difference]: Start difference. First operand 197 states and 294 transitions. cyclomatic complexity: 100 Second operand has 103 states, 102 states have (on average 1.0686274509803921) internal successors, (109), 103 states have internal predecessors, (109), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:54:58,574 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 20:54:58,575 INFO L93 Difference]: Finished difference Result 5355 states and 5464 transitions. [2022-11-02 20:54:58,575 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5355 states and 5464 transitions. [2022-11-02 20:54:58,616 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 7 [2022-11-02 20:54:58,639 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5355 states to 5349 states and 5458 transitions. [2022-11-02 20:54:58,639 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19 [2022-11-02 20:54:58,639 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19 [2022-11-02 20:54:58,639 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5349 states and 5458 transitions. [2022-11-02 20:54:58,645 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-02 20:54:58,645 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5349 states and 5458 transitions. [2022-11-02 20:54:58,650 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5349 states and 5458 transitions. [2022-11-02 20:54:58,673 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5349 to 203. [2022-11-02 20:54:58,674 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 203 states, 203 states have (on average 1.5073891625615763) internal successors, (306), 202 states have internal predecessors, (306), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:54:58,674 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 203 states to 203 states and 306 transitions. [2022-11-02 20:54:58,675 INFO L240 hiAutomatonCegarLoop]: Abstraction has 203 states and 306 transitions. [2022-11-02 20:54:58,675 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 102 states. [2022-11-02 20:54:58,676 INFO L428 stractBuchiCegarLoop]: Abstraction has 203 states and 306 transitions. [2022-11-02 20:54:58,676 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-11-02 20:54:58,676 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 203 states and 306 transitions. [2022-11-02 20:54:58,678 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-11-02 20:54:58,678 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 20:54:58,678 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 20:54:58,679 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [94, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 20:54:58,679 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2022-11-02 20:54:58,680 INFO L748 eck$LassoCheckResult]: Stem: 14260#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 14261#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 14268#L26 main_~i~0#1 := 0; 14262#L29-1 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 14263#L29-2 assume !(main_~i~0#1 >= 100);main_~j~0#1 := 0; 14258#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14259#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14460#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14459#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14458#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14457#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14456#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14455#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14454#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14453#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14452#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14451#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14450#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14449#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14448#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14447#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14446#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14445#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14444#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14443#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14442#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14441#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14440#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14439#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14438#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14437#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14436#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14435#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14434#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14433#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14432#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14431#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14430#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14429#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14428#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14427#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14426#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14425#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14424#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14423#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14422#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14421#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14420#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14419#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14418#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14417#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14416#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14415#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14414#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14413#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14412#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14411#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14410#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14409#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14408#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14407#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14406#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14405#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14404#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14403#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14402#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14401#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14400#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14399#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14398#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14397#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14396#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14395#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14394#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14393#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14392#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14391#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14390#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14389#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14388#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14387#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14386#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14385#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14384#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14383#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14382#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14381#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14380#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14379#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14378#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14377#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14376#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14375#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14374#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14373#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14372#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14371#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14370#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14369#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14368#L35-1 assume !(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1; 14266#L35-2 assume main_~j~0#1 >= 100; 14267#L39 [2022-11-02 20:54:58,680 INFO L750 eck$LassoCheckResult]: Loop: 14267#L39 assume true; 14267#L39 [2022-11-02 20:54:58,680 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:54:58,681 INFO L85 PathProgramCache]: Analyzing trace with hash 672086932, now seen corresponding path program 6 times [2022-11-02 20:54:58,681 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:54:58,681 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1014345544] [2022-11-02 20:54:58,681 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:54:58,681 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:54:58,757 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:55:03,924 INFO L134 CoverageAnalysis]: Checked inductivity of 4465 backedges. 0 proven. 4465 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:55:03,924 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 20:55:03,924 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1014345544] [2022-11-02 20:55:03,924 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1014345544] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 20:55:03,924 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [886306140] [2022-11-02 20:55:03,924 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-11-02 20:55:03,925 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 20:55:03,925 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 20:55:03,926 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 20:55:03,929 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Waiting until timeout for monitored process [2022-11-02 20:55:04,120 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 48 check-sat command(s) [2022-11-02 20:55:04,120 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-02 20:55:04,124 INFO L263 TraceCheckSpWp]: Trace formula consists of 594 conjuncts, 96 conjunts are in the unsatisfiable core [2022-11-02 20:55:04,128 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 20:55:04,337 INFO L134 CoverageAnalysis]: Checked inductivity of 4465 backedges. 0 proven. 4465 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:55:04,337 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 20:55:08,552 INFO L134 CoverageAnalysis]: Checked inductivity of 4465 backedges. 0 proven. 4465 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:55:08,552 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [886306140] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 20:55:08,552 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 20:55:08,553 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [96, 96, 96] total 102 [2022-11-02 20:55:08,553 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1042137453] [2022-11-02 20:55:08,553 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 20:55:08,553 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-02 20:55:08,554 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:55:08,554 INFO L85 PathProgramCache]: Analyzing trace with hash 84, now seen corresponding path program 14 times [2022-11-02 20:55:08,554 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:55:08,554 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [942471960] [2022-11-02 20:55:08,555 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:55:08,555 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:55:08,556 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:55:08,557 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:55:08,557 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:55:08,558 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:55:08,560 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 20:55:08,562 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 103 interpolants. [2022-11-02 20:55:08,564 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5253, Invalid=5253, Unknown=0, NotChecked=0, Total=10506 [2022-11-02 20:55:08,565 INFO L87 Difference]: Start difference. First operand 203 states and 306 transitions. cyclomatic complexity: 106 Second operand has 103 states, 102 states have (on average 1.088235294117647) internal successors, (111), 103 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:55:08,703 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 20:55:08,703 INFO L93 Difference]: Finished difference Result 215 states and 318 transitions. [2022-11-02 20:55:08,704 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 215 states and 318 transitions. [2022-11-02 20:55:08,705 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-11-02 20:55:08,706 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 215 states to 209 states and 312 transitions. [2022-11-02 20:55:08,707 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7 [2022-11-02 20:55:08,707 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7 [2022-11-02 20:55:08,707 INFO L73 IsDeterministic]: Start isDeterministic. Operand 209 states and 312 transitions. [2022-11-02 20:55:08,707 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-02 20:55:08,707 INFO L218 hiAutomatonCegarLoop]: Abstraction has 209 states and 312 transitions. [2022-11-02 20:55:08,707 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 209 states and 312 transitions. [2022-11-02 20:55:08,710 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 209 to 209. [2022-11-02 20:55:08,710 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 209 states, 209 states have (on average 1.492822966507177) internal successors, (312), 208 states have internal predecessors, (312), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:55:08,711 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 209 states to 209 states and 312 transitions. [2022-11-02 20:55:08,711 INFO L240 hiAutomatonCegarLoop]: Abstraction has 209 states and 312 transitions. [2022-11-02 20:55:08,712 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 102 states. [2022-11-02 20:55:08,712 INFO L428 stractBuchiCegarLoop]: Abstraction has 209 states and 312 transitions. [2022-11-02 20:55:08,712 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-11-02 20:55:08,712 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 209 states and 312 transitions. [2022-11-02 20:55:08,714 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-11-02 20:55:08,714 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 20:55:08,714 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 20:55:08,715 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [100, 1, 1, 1, 1, 1] [2022-11-02 20:55:08,715 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2022-11-02 20:55:08,715 INFO L748 eck$LassoCheckResult]: Stem: 15384#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 15385#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 15392#L26 main_~i~0#1 := 0; 15386#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15388#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15389#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15590#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15589#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15587#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15585#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15583#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15581#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15579#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15577#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15575#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15573#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15571#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15569#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15567#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15565#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15563#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15561#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15559#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15557#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15555#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15553#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15551#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15549#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15547#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15545#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15543#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15541#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15539#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15537#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15535#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15533#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15531#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15529#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15527#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15525#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15523#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15521#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15519#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15517#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15515#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15513#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15511#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15509#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15507#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15505#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15503#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15501#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15499#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15497#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15495#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15493#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15491#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15489#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15487#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15485#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15483#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15481#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15479#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15477#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15475#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15473#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15471#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15469#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15467#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15465#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15463#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15461#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15459#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15457#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15455#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15453#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15451#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15449#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15447#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15445#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15443#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15441#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15439#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15437#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15435#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15433#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15431#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15429#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15427#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15425#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15423#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15421#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15419#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15417#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15415#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15413#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15411#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15409#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15407#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15405#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15403#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15401#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15397#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15395#L29-1 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 15393#L29-2 assume main_~i~0#1 >= 100; 15391#L39 [2022-11-02 20:55:08,715 INFO L750 eck$LassoCheckResult]: Loop: 15391#L39 assume true; 15391#L39 [2022-11-02 20:55:08,716 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:55:08,716 INFO L85 PathProgramCache]: Analyzing trace with hash -637974903, now seen corresponding path program 7 times [2022-11-02 20:55:08,716 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:55:08,716 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [924438628] [2022-11-02 20:55:08,717 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:55:08,717 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:55:08,777 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:55:08,777 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:55:08,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:55:08,882 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:55:08,883 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:55:08,883 INFO L85 PathProgramCache]: Analyzing trace with hash 84, now seen corresponding path program 15 times [2022-11-02 20:55:08,883 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:55:08,883 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1931437114] [2022-11-02 20:55:08,884 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:55:08,884 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:55:08,885 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:55:08,886 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:55:08,886 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:55:08,887 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:55:08,888 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:55:08,889 INFO L85 PathProgramCache]: Analyzing trace with hash 1697614540, now seen corresponding path program 1 times [2022-11-02 20:55:08,889 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:55:08,889 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1648314442] [2022-11-02 20:55:08,889 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:55:08,889 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:55:08,941 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:55:08,942 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:55:08,992 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:55:09,004 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:55:16,220 WARN L234 SmtUtils]: Spent 7.18s on a formula simplification. DAG size of input: 740 DAG size of output: 634 (called from [L 278] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.cfg.transitions.TransFormulaUtils.sequentialComposition) [2022-11-02 20:55:18,383 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:55:18,384 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:55:18,437 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:55:18,618 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 02.11 08:55:18 BoogieIcfgContainer [2022-11-02 20:55:18,619 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2022-11-02 20:55:18,619 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-11-02 20:55:18,619 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-11-02 20:55:18,619 INFO L275 PluginConnector]: Witness Printer initialized [2022-11-02 20:55:18,620 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.11 08:54:26" (3/4) ... [2022-11-02 20:55:18,622 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2022-11-02 20:55:18,710 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/witness.graphml [2022-11-02 20:55:18,710 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-11-02 20:55:18,711 INFO L158 Benchmark]: Toolchain (without parser) took 52437.89ms. Allocated memory was 138.4MB in the beginning and 352.3MB in the end (delta: 213.9MB). Free memory was 105.5MB in the beginning and 193.3MB in the end (delta: -87.8MB). Peak memory consumption was 126.5MB. Max. memory is 16.1GB. [2022-11-02 20:55:18,711 INFO L158 Benchmark]: CDTParser took 0.24ms. Allocated memory is still 83.9MB. Free memory was 39.0MB in the beginning and 39.0MB in the end (delta: 40.5kB). There was no memory consumed. Max. memory is 16.1GB. [2022-11-02 20:55:18,712 INFO L158 Benchmark]: CACSL2BoogieTranslator took 248.79ms. Allocated memory is still 138.4MB. Free memory was 105.5MB in the beginning and 114.9MB in the end (delta: -9.5MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2022-11-02 20:55:18,712 INFO L158 Benchmark]: Boogie Procedure Inliner took 31.91ms. Allocated memory is still 138.4MB. Free memory was 114.9MB in the beginning and 113.3MB in the end (delta: 1.6MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-11-02 20:55:18,713 INFO L158 Benchmark]: Boogie Preprocessor took 18.79ms. Allocated memory is still 138.4MB. Free memory was 113.3MB in the beginning and 112.4MB in the end (delta: 883.7kB). There was no memory consumed. Max. memory is 16.1GB. [2022-11-02 20:55:18,713 INFO L158 Benchmark]: RCFGBuilder took 257.47ms. Allocated memory is still 138.4MB. Free memory was 112.4MB in the beginning and 102.8MB in the end (delta: 9.6MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. [2022-11-02 20:55:18,713 INFO L158 Benchmark]: BuchiAutomizer took 51784.07ms. Allocated memory was 138.4MB in the beginning and 352.3MB in the end (delta: 213.9MB). Free memory was 102.8MB in the beginning and 199.6MB in the end (delta: -96.7MB). Peak memory consumption was 119.1MB. Max. memory is 16.1GB. [2022-11-02 20:55:18,714 INFO L158 Benchmark]: Witness Printer took 91.10ms. Allocated memory is still 352.3MB. Free memory was 199.6MB in the beginning and 193.3MB in the end (delta: 6.3MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. [2022-11-02 20:55:18,716 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.24ms. Allocated memory is still 83.9MB. Free memory was 39.0MB in the beginning and 39.0MB in the end (delta: 40.5kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 248.79ms. Allocated memory is still 138.4MB. Free memory was 105.5MB in the beginning and 114.9MB in the end (delta: -9.5MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 31.91ms. Allocated memory is still 138.4MB. Free memory was 114.9MB in the beginning and 113.3MB in the end (delta: 1.6MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 18.79ms. Allocated memory is still 138.4MB. Free memory was 113.3MB in the beginning and 112.4MB in the end (delta: 883.7kB). There was no memory consumed. Max. memory is 16.1GB. * RCFGBuilder took 257.47ms. Allocated memory is still 138.4MB. Free memory was 112.4MB in the beginning and 102.8MB in the end (delta: 9.6MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. * BuchiAutomizer took 51784.07ms. Allocated memory was 138.4MB in the beginning and 352.3MB in the end (delta: 213.9MB). Free memory was 102.8MB in the beginning and 199.6MB in the end (delta: -96.7MB). Peak memory consumption was 119.1MB. Max. memory is 16.1GB. * Witness Printer took 91.10ms. Allocated memory is still 352.3MB. Free memory was 199.6MB in the beginning and 193.3MB in the end (delta: 6.3MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 15 terminating modules (14 trivial, 1 deterministic, 0 nondeterministic) and one nonterminating remainder module.One deterministic module has affine ranking function -2 * i + 1999999 and consists of 4 locations. 14 modules have a trivial ranking function, the largest among these consists of 103 locations. The remainder module has 209 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 51.6s and 16 iterations. TraceHistogramMax:100. Analysis of lassos took 45.5s. Construction of modules took 2.0s. Büchi inclusion checks took 3.8s. Highest rank in rank-based complementation 3. Minimization of det autom 0. Minimization of nondet autom 15. Automata minimization 0.1s AutomataMinimizationTime, 15 MinimizatonAttempts, 9893 StatesRemovedByMinimization, 8 NontrivialMinimizations. Non-live state removal took 0.1s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [1, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 3220 SdHoareTripleChecker+Valid, 2.5s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 3219 mSDsluCounter, 710 SdHoareTripleChecker+Invalid, 2.0s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 587 mSDsCounter, 1231 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 1691 IncrementalHoareTripleChecker+Invalid, 2922 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 1231 mSolverCounterUnsat, 123 mSDtfsCounter, 1691 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI0 SFLT1 conc0 concLT0 SILN14 SILU0 SILI0 SILT0 lasso0 LassoPreprocessingBenchmarks: Lassos: inital14 mio100 ax100 hnf100 lsp71 ukn100 mio100 lsp100 div100 bol100 ite100 ukn100 eq160 hnf93 smp100 dnf100 smp100 tf113 neg100 sie111 LassoTerminationAnalysisBenchmarks: ConstraintsSatisfiability: unsat Degree: 0 Time: 47ms VariablesStem: 0 VariablesLoop: 0 DisjunctsStem: 1 DisjunctsLoop: 1 SupportingInvariants: 0 MotzkinApplications: 2 LassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 2 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 1 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.2s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 24]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L25] int i, j; [L27] i = 0 VAL [i=0] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=1] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=2] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=3] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=4] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=5] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=6] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=7] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=8] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=9] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=10] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=11] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=12] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=13] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=14] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=15] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=16] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=17] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=18] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=19] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=20] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=21] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=22] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=23] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=24] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=25] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=26] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=27] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=28] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=29] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=30] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=31] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=32] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=33] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=34] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=35] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=36] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=37] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=38] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=39] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=40] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=41] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=42] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=43] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=44] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=45] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=46] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=47] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=48] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=49] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=50] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=51] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=52] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=53] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=54] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=55] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=56] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=57] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=58] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=59] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=60] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=61] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=62] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=63] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=64] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=65] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=66] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=67] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=68] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=69] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=70] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=71] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=72] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=73] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=74] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=75] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=76] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=77] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=78] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=79] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=80] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=81] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=82] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=83] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=84] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=85] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=86] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=87] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=88] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=89] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=90] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=91] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=92] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=93] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=94] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=95] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=96] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=97] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=98] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=99] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=100] [L29] COND FALSE !(__VERIFIER_nondet_int() && i < 1000000) [L32] COND TRUE i >= 100 VAL [i=100] Loop: [L32] STUCK: goto STUCK; End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 24]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int i, j; [L27] i = 0 VAL [i=0] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=1] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=2] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=3] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=4] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=5] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=6] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=7] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=8] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=9] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=10] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=11] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=12] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=13] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=14] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=15] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=16] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=17] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=18] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=19] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=20] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=21] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=22] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=23] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=24] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=25] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=26] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=27] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=28] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=29] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=30] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=31] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=32] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=33] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=34] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=35] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=36] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=37] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=38] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=39] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=40] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=41] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=42] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=43] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=44] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=45] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=46] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=47] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=48] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=49] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=50] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=51] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=52] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=53] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=54] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=55] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=56] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=57] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=58] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=59] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=60] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=61] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=62] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=63] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=64] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=65] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=66] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=67] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=68] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=69] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=70] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=71] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=72] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=73] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=74] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=75] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=76] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=77] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=78] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=79] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=80] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=81] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=82] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=83] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=84] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=85] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=86] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=87] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=88] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=89] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=90] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=91] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=92] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=93] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=94] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=95] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=96] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=97] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=98] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=99] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=100] [L29] COND FALSE !(__VERIFIER_nondet_int() && i < 1000000) [L32] COND TRUE i >= 100 VAL [i=100] Loop: [L32] STUCK: goto STUCK; End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2022-11-02 20:55:18,819 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Forceful destruction successful, exit code 0 [2022-11-02 20:55:19,027 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Forceful destruction successful, exit code 0 [2022-11-02 20:55:19,225 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Forceful destruction successful, exit code 0 [2022-11-02 20:55:19,426 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Forceful destruction successful, exit code 0 [2022-11-02 20:55:19,626 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Forceful destruction successful, exit code 0 [2022-11-02 20:55:19,825 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Forceful destruction successful, exit code 0 [2022-11-02 20:55:20,026 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Forceful destruction successful, exit code 0 [2022-11-02 20:55:20,225 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Forceful destruction successful, exit code 0 [2022-11-02 20:55:20,425 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Forceful destruction successful, exit code 0 [2022-11-02 20:55:20,626 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Forceful destruction successful, exit code 0 [2022-11-02 20:55:20,826 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Forceful destruction successful, exit code 0 [2022-11-02 20:55:21,026 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Forceful destruction successful, exit code 0 [2022-11-02 20:55:21,227 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a552613-a09e-4739-951f-a96dc9636b23/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)