./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/termination-15/array12_alloca.i --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 5e519f3a Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/termination-15/array12_alloca.i -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/config/svcomp-Termination-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash b994a1ec31b8c037535d8c99bc15e7231c0aea3fc6bbd2fe006bfaa61a5800c0 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-5e519f3 [2022-11-02 21:05:16,877 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-11-02 21:05:16,893 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-11-02 21:05:16,936 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-11-02 21:05:16,936 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-11-02 21:05:16,938 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-11-02 21:05:16,939 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-11-02 21:05:16,942 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-11-02 21:05:16,944 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-11-02 21:05:16,945 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-11-02 21:05:16,946 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-11-02 21:05:16,948 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-11-02 21:05:16,948 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-11-02 21:05:16,950 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-11-02 21:05:16,951 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-11-02 21:05:16,953 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-11-02 21:05:16,954 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-11-02 21:05:16,955 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-11-02 21:05:16,957 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-11-02 21:05:16,959 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-11-02 21:05:16,961 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-11-02 21:05:16,968 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-11-02 21:05:16,974 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-11-02 21:05:16,975 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-11-02 21:05:16,979 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-11-02 21:05:16,987 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-11-02 21:05:16,988 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-11-02 21:05:16,989 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-11-02 21:05:16,990 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-11-02 21:05:16,991 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-11-02 21:05:16,992 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-11-02 21:05:16,993 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-11-02 21:05:16,995 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-11-02 21:05:16,996 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-11-02 21:05:16,998 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-11-02 21:05:17,000 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-11-02 21:05:17,001 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-11-02 21:05:17,001 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-11-02 21:05:17,002 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-11-02 21:05:17,003 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-11-02 21:05:17,004 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-11-02 21:05:17,005 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/config/svcomp-Termination-64bit-Automizer_Default.epf [2022-11-02 21:05:17,039 INFO L113 SettingsManager]: Loading preferences was successful [2022-11-02 21:05:17,040 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-11-02 21:05:17,040 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-11-02 21:05:17,041 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-11-02 21:05:17,042 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-11-02 21:05:17,042 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-11-02 21:05:17,043 INFO L138 SettingsManager]: * Use SBE=true [2022-11-02 21:05:17,043 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-11-02 21:05:17,043 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-11-02 21:05:17,043 INFO L138 SettingsManager]: * Use old map elimination=false [2022-11-02 21:05:17,045 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-11-02 21:05:17,045 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-11-02 21:05:17,045 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-11-02 21:05:17,045 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-11-02 21:05:17,046 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-11-02 21:05:17,046 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-11-02 21:05:17,046 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-11-02 21:05:17,046 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-11-02 21:05:17,047 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-11-02 21:05:17,047 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-11-02 21:05:17,047 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-11-02 21:05:17,047 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-11-02 21:05:17,048 INFO L138 SettingsManager]: * Use constant arrays=true [2022-11-02 21:05:17,049 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-11-02 21:05:17,050 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-11-02 21:05:17,050 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-11-02 21:05:17,050 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-11-02 21:05:17,050 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-11-02 21:05:17,052 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-11-02 21:05:17,052 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> b994a1ec31b8c037535d8c99bc15e7231c0aea3fc6bbd2fe006bfaa61a5800c0 [2022-11-02 21:05:17,380 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-11-02 21:05:17,403 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-11-02 21:05:17,406 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-11-02 21:05:17,407 INFO L271 PluginConnector]: Initializing CDTParser... [2022-11-02 21:05:17,408 INFO L275 PluginConnector]: CDTParser initialized [2022-11-02 21:05:17,410 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/../../sv-benchmarks/c/termination-15/array12_alloca.i [2022-11-02 21:05:17,506 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/data/f93e0801a/b1024ef30c994c928c7026b2c1d038c0/FLAG035176cfe [2022-11-02 21:05:18,110 INFO L306 CDTParser]: Found 1 translation units. [2022-11-02 21:05:18,111 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/sv-benchmarks/c/termination-15/array12_alloca.i [2022-11-02 21:05:18,122 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/data/f93e0801a/b1024ef30c994c928c7026b2c1d038c0/FLAG035176cfe [2022-11-02 21:05:18,367 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/data/f93e0801a/b1024ef30c994c928c7026b2c1d038c0 [2022-11-02 21:05:18,371 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-11-02 21:05:18,374 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-11-02 21:05:18,377 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-11-02 21:05:18,377 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-11-02 21:05:18,381 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-11-02 21:05:18,382 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.11 09:05:18" (1/1) ... [2022-11-02 21:05:18,383 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@73762726 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 09:05:18, skipping insertion in model container [2022-11-02 21:05:18,384 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.11 09:05:18" (1/1) ... [2022-11-02 21:05:18,394 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-11-02 21:05:18,453 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-11-02 21:05:18,956 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-02 21:05:18,967 INFO L203 MainTranslator]: Completed pre-run [2022-11-02 21:05:19,027 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-02 21:05:19,055 INFO L208 MainTranslator]: Completed translation [2022-11-02 21:05:19,056 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 09:05:19 WrapperNode [2022-11-02 21:05:19,056 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-11-02 21:05:19,057 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-11-02 21:05:19,057 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-11-02 21:05:19,057 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-11-02 21:05:19,065 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 09:05:19" (1/1) ... [2022-11-02 21:05:19,077 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 09:05:19" (1/1) ... [2022-11-02 21:05:19,097 INFO L138 Inliner]: procedures = 151, calls = 10, calls flagged for inlining = 2, calls inlined = 2, statements flattened = 54 [2022-11-02 21:05:19,098 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-11-02 21:05:19,099 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-11-02 21:05:19,099 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-11-02 21:05:19,099 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-11-02 21:05:19,108 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 09:05:19" (1/1) ... [2022-11-02 21:05:19,109 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 09:05:19" (1/1) ... [2022-11-02 21:05:19,111 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 09:05:19" (1/1) ... [2022-11-02 21:05:19,111 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 09:05:19" (1/1) ... [2022-11-02 21:05:19,116 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 09:05:19" (1/1) ... [2022-11-02 21:05:19,120 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 09:05:19" (1/1) ... [2022-11-02 21:05:19,121 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 09:05:19" (1/1) ... [2022-11-02 21:05:19,122 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 09:05:19" (1/1) ... [2022-11-02 21:05:19,123 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-11-02 21:05:19,124 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-11-02 21:05:19,124 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-11-02 21:05:19,124 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-11-02 21:05:19,125 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 09:05:19" (1/1) ... [2022-11-02 21:05:19,132 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-02 21:05:19,146 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:05:19,159 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-02 21:05:19,183 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-11-02 21:05:19,210 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2022-11-02 21:05:19,211 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2022-11-02 21:05:19,211 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2022-11-02 21:05:19,212 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2022-11-02 21:05:19,212 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-11-02 21:05:19,212 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-11-02 21:05:19,298 INFO L235 CfgBuilder]: Building ICFG [2022-11-02 21:05:19,301 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-11-02 21:05:19,457 INFO L276 CfgBuilder]: Performing block encoding [2022-11-02 21:05:19,464 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-11-02 21:05:19,465 INFO L300 CfgBuilder]: Removed 2 assume(true) statements. [2022-11-02 21:05:19,467 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.11 09:05:19 BoogieIcfgContainer [2022-11-02 21:05:19,467 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-11-02 21:05:19,468 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-11-02 21:05:19,468 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-11-02 21:05:19,473 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-11-02 21:05:19,474 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-02 21:05:19,474 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 02.11 09:05:18" (1/3) ... [2022-11-02 21:05:19,475 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@45b65609 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 02.11 09:05:19, skipping insertion in model container [2022-11-02 21:05:19,476 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-02 21:05:19,476 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 09:05:19" (2/3) ... [2022-11-02 21:05:19,476 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@45b65609 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 02.11 09:05:19, skipping insertion in model container [2022-11-02 21:05:19,476 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-02 21:05:19,477 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.11 09:05:19" (3/3) ... [2022-11-02 21:05:19,478 INFO L332 chiAutomizerObserver]: Analyzing ICFG array12_alloca.i [2022-11-02 21:05:19,538 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-11-02 21:05:19,538 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-11-02 21:05:19,539 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-11-02 21:05:19,539 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-11-02 21:05:19,539 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-11-02 21:05:19,539 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-11-02 21:05:19,539 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-11-02 21:05:19,540 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-11-02 21:05:19,545 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 15 states, 14 states have (on average 1.5714285714285714) internal successors, (22), 14 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:05:19,567 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5 [2022-11-02 21:05:19,567 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 21:05:19,568 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 21:05:19,574 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1] [2022-11-02 21:05:19,574 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-11-02 21:05:19,575 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-11-02 21:05:19,575 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 15 states, 14 states have (on average 1.5714285714285714) internal successors, (22), 14 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:05:19,577 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5 [2022-11-02 21:05:19,577 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 21:05:19,577 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 21:05:19,578 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1] [2022-11-02 21:05:19,578 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-11-02 21:05:19,588 INFO L748 eck$LassoCheckResult]: Stem: 3#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 6#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 10#L367true assume !(main_~length~0#1 < 1); 7#L367-2true call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 4#L369true assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 5#L370-3true [2022-11-02 21:05:19,589 INFO L750 eck$LassoCheckResult]: Loop: 5#L370-3true assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12#L372true assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15#L370-2true main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5#L370-3true [2022-11-02 21:05:19,595 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:05:19,596 INFO L85 PathProgramCache]: Analyzing trace with hash 28695753, now seen corresponding path program 1 times [2022-11-02 21:05:19,606 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:05:19,607 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1807468472] [2022-11-02 21:05:19,607 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:05:19,608 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:05:19,723 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:05:19,723 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:05:19,739 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:05:19,761 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:05:19,765 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:05:19,765 INFO L85 PathProgramCache]: Analyzing trace with hash 51737, now seen corresponding path program 1 times [2022-11-02 21:05:19,765 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:05:19,766 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1985222070] [2022-11-02 21:05:19,766 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:05:19,766 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:05:19,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:05:19,789 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:05:19,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:05:19,814 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:05:19,816 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:05:19,817 INFO L85 PathProgramCache]: Analyzing trace with hash 176707665, now seen corresponding path program 1 times [2022-11-02 21:05:19,820 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:05:19,820 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [876929526] [2022-11-02 21:05:19,821 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:05:19,821 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:05:19,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:05:19,928 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:05:19,966 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:05:19,971 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:05:20,443 INFO L210 LassoAnalysis]: Preferences: [2022-11-02 21:05:20,443 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2022-11-02 21:05:20,444 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2022-11-02 21:05:20,444 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2022-11-02 21:05:20,444 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2022-11-02 21:05:20,444 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-02 21:05:20,444 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2022-11-02 21:05:20,444 INFO L132 ssoRankerPreferences]: Path of dumped script: [2022-11-02 21:05:20,445 INFO L133 ssoRankerPreferences]: Filename of dumped script: array12_alloca.i_Iteration1_Lasso [2022-11-02 21:05:20,445 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2022-11-02 21:05:20,445 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2022-11-02 21:05:20,469 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-02 21:05:20,481 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-02 21:05:20,488 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-02 21:05:20,493 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-02 21:05:20,501 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-02 21:05:20,506 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-02 21:05:20,747 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-02 21:05:20,752 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-02 21:05:20,755 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-02 21:05:20,759 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-02 21:05:20,764 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-02 21:05:20,771 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-02 21:05:21,141 INFO L294 LassoAnalysis]: Preprocessing complete. [2022-11-02 21:05:21,147 INFO L490 LassoAnalysis]: Using template 'affine'. [2022-11-02 21:05:21,149 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-02 21:05:21,149 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:05:21,152 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-02 21:05:21,171 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-02 21:05:21,185 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2022-11-02 21:05:21,187 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-02 21:05:21,188 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-02 21:05:21,188 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-02 21:05:21,188 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-02 21:05:21,188 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-02 21:05:21,191 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-02 21:05:21,191 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-02 21:05:21,201 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-02 21:05:21,239 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Ended with exit code 0 [2022-11-02 21:05:21,240 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-02 21:05:21,240 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:05:21,241 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-02 21:05:21,243 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2022-11-02 21:05:21,244 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-02 21:05:21,256 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-02 21:05:21,256 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-02 21:05:21,257 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-02 21:05:21,257 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-02 21:05:21,261 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-02 21:05:21,262 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-02 21:05:21,275 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-02 21:05:21,317 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Forceful destruction successful, exit code 0 [2022-11-02 21:05:21,318 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-02 21:05:21,318 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:05:21,321 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-02 21:05:21,322 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2022-11-02 21:05:21,330 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-02 21:05:21,342 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-02 21:05:21,342 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-02 21:05:21,342 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-02 21:05:21,342 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-02 21:05:21,342 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-02 21:05:21,344 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-02 21:05:21,344 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-02 21:05:21,365 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-02 21:05:21,401 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Ended with exit code 0 [2022-11-02 21:05:21,402 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-02 21:05:21,402 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:05:21,403 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-02 21:05:21,404 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2022-11-02 21:05:21,405 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-02 21:05:21,418 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-02 21:05:21,418 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-02 21:05:21,418 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-02 21:05:21,419 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-02 21:05:21,419 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-02 21:05:21,420 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-02 21:05:21,420 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-02 21:05:21,457 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-02 21:05:21,495 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Forceful destruction successful, exit code 0 [2022-11-02 21:05:21,496 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-02 21:05:21,496 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:05:21,497 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-02 21:05:21,498 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2022-11-02 21:05:21,499 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-02 21:05:21,511 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-02 21:05:21,512 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-02 21:05:21,512 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-02 21:05:21,512 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-02 21:05:21,512 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-02 21:05:21,514 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-02 21:05:21,514 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-02 21:05:21,515 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-02 21:05:21,540 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Forceful destruction successful, exit code 0 [2022-11-02 21:05:21,541 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-02 21:05:21,541 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:05:21,542 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-02 21:05:21,544 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2022-11-02 21:05:21,546 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-02 21:05:21,558 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-02 21:05:21,558 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-02 21:05:21,559 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-02 21:05:21,559 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-02 21:05:21,559 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-02 21:05:21,560 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-02 21:05:21,560 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-02 21:05:21,564 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-02 21:05:21,597 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Forceful destruction successful, exit code 0 [2022-11-02 21:05:21,598 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-02 21:05:21,598 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:05:21,599 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-02 21:05:21,600 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2022-11-02 21:05:21,601 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-02 21:05:21,613 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-02 21:05:21,613 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-02 21:05:21,614 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-02 21:05:21,614 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-02 21:05:21,619 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-02 21:05:21,619 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-02 21:05:21,633 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-02 21:05:21,673 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Forceful destruction successful, exit code 0 [2022-11-02 21:05:21,674 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-02 21:05:21,674 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:05:21,675 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-02 21:05:21,678 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-02 21:05:21,691 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2022-11-02 21:05:21,692 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-02 21:05:21,692 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-02 21:05:21,693 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-02 21:05:21,693 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-02 21:05:21,696 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-02 21:05:21,696 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-02 21:05:21,721 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-02 21:05:21,765 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Forceful destruction successful, exit code 0 [2022-11-02 21:05:21,765 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-02 21:05:21,766 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:05:21,767 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-02 21:05:21,776 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-02 21:05:21,789 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2022-11-02 21:05:21,792 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-02 21:05:21,792 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-02 21:05:21,792 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-02 21:05:21,792 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-02 21:05:21,804 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-02 21:05:21,804 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-02 21:05:21,833 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2022-11-02 21:05:21,881 INFO L443 ModelExtractionUtils]: Simplification made 12 calls to the SMT solver. [2022-11-02 21:05:21,881 INFO L444 ModelExtractionUtils]: 6 out of 22 variables were initially zero. Simplification set additionally 13 variables to zero. [2022-11-02 21:05:21,883 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-02 21:05:21,883 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:05:21,885 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-02 21:05:21,896 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2022-11-02 21:05:21,896 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2022-11-02 21:05:21,940 INFO L438 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2022-11-02 21:05:21,940 INFO L513 LassoAnalysis]: Proved termination. [2022-11-02 21:05:21,941 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~i~0#1, ULTIMATE.start_main_~length~0#1) = -1*ULTIMATE.start_main_~i~0#1 + 1*ULTIMATE.start_main_~length~0#1 Supporting invariants [] [2022-11-02 21:05:21,987 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Forceful destruction successful, exit code 0 [2022-11-02 21:05:22,000 INFO L156 tatePredicateManager]: 3 out of 3 supporting invariants were superfluous and have been removed [2022-11-02 21:05:22,027 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:05:22,055 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 21:05:22,059 INFO L263 TraceCheckSpWp]: Trace formula consists of 30 conjuncts, 2 conjunts are in the unsatisfiable core [2022-11-02 21:05:22,060 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 21:05:22,089 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 21:05:22,090 INFO L263 TraceCheckSpWp]: Trace formula consists of 24 conjuncts, 4 conjunts are in the unsatisfiable core [2022-11-02 21:05:22,090 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 21:05:22,127 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:05:22,183 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2022-11-02 21:05:22,186 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand has 15 states, 14 states have (on average 1.5714285714285714) internal successors, (22), 14 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 2.6666666666666665) internal successors, (8), 3 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:05:22,263 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand has 15 states, 14 states have (on average 1.5714285714285714) internal successors, (22), 14 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0). Second operand has 3 states, 3 states have (on average 2.6666666666666665) internal successors, (8), 3 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 35 states and 50 transitions. Complement of second has 7 states. [2022-11-02 21:05:22,266 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 5 states 1 stem states 2 non-accepting loop states 1 accepting loop states [2022-11-02 21:05:22,275 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 2.6666666666666665) internal successors, (8), 3 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:05:22,277 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 33 transitions. [2022-11-02 21:05:22,282 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 33 transitions. Stem has 5 letters. Loop has 3 letters. [2022-11-02 21:05:22,283 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-02 21:05:22,283 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 33 transitions. Stem has 8 letters. Loop has 3 letters. [2022-11-02 21:05:22,284 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-02 21:05:22,284 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 33 transitions. Stem has 5 letters. Loop has 6 letters. [2022-11-02 21:05:22,285 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-02 21:05:22,287 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 35 states and 50 transitions. [2022-11-02 21:05:22,292 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:05:22,295 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 35 states to 12 states and 17 transitions. [2022-11-02 21:05:22,297 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2022-11-02 21:05:22,297 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2022-11-02 21:05:22,297 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12 states and 17 transitions. [2022-11-02 21:05:22,298 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-02 21:05:22,298 INFO L218 hiAutomatonCegarLoop]: Abstraction has 12 states and 17 transitions. [2022-11-02 21:05:22,316 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12 states and 17 transitions. [2022-11-02 21:05:22,324 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12 to 12. [2022-11-02 21:05:22,325 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12 states, 12 states have (on average 1.4166666666666667) internal successors, (17), 11 states have internal predecessors, (17), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:05:22,325 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 17 transitions. [2022-11-02 21:05:22,326 INFO L240 hiAutomatonCegarLoop]: Abstraction has 12 states and 17 transitions. [2022-11-02 21:05:22,327 INFO L428 stractBuchiCegarLoop]: Abstraction has 12 states and 17 transitions. [2022-11-02 21:05:22,327 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-11-02 21:05:22,327 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12 states and 17 transitions. [2022-11-02 21:05:22,328 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:05:22,328 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 21:05:22,328 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 21:05:22,328 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1] [2022-11-02 21:05:22,328 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-02 21:05:22,329 INFO L748 eck$LassoCheckResult]: Stem: 112#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 113#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 120#L367 assume !(main_~length~0#1 < 1); 114#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 115#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 116#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 117#L370-4 main_~j~0#1 := 0; 118#L378-2 [2022-11-02 21:05:22,329 INFO L750 eck$LassoCheckResult]: Loop: 118#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 119#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 118#L378-2 [2022-11-02 21:05:22,330 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:05:22,330 INFO L85 PathProgramCache]: Analyzing trace with hash 1806815510, now seen corresponding path program 1 times [2022-11-02 21:05:22,330 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:05:22,330 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [314304426] [2022-11-02 21:05:22,330 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:05:22,331 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:05:22,342 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 21:05:22,419 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:05:22,419 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 21:05:22,419 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [314304426] [2022-11-02 21:05:22,420 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [314304426] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-02 21:05:22,420 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-02 21:05:22,420 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-11-02 21:05:22,420 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1652730241] [2022-11-02 21:05:22,421 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-02 21:05:22,423 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-02 21:05:22,424 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:05:22,424 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 1 times [2022-11-02 21:05:22,424 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:05:22,424 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [211960694] [2022-11-02 21:05:22,424 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:05:22,425 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:05:22,432 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:05:22,432 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:05:22,436 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:05:22,439 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:05:22,499 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 21:05:22,501 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-02 21:05:22,502 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2022-11-02 21:05:22,503 INFO L87 Difference]: Start difference. First operand 12 states and 17 transitions. cyclomatic complexity: 7 Second operand has 4 states, 4 states have (on average 1.75) internal successors, (7), 4 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:05:22,534 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 21:05:22,534 INFO L93 Difference]: Finished difference Result 14 states and 19 transitions. [2022-11-02 21:05:22,534 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14 states and 19 transitions. [2022-11-02 21:05:22,535 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:05:22,535 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14 states to 14 states and 19 transitions. [2022-11-02 21:05:22,536 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9 [2022-11-02 21:05:22,536 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2022-11-02 21:05:22,536 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14 states and 19 transitions. [2022-11-02 21:05:22,536 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-02 21:05:22,536 INFO L218 hiAutomatonCegarLoop]: Abstraction has 14 states and 19 transitions. [2022-11-02 21:05:22,536 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14 states and 19 transitions. [2022-11-02 21:05:22,537 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14 to 12. [2022-11-02 21:05:22,538 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12 states, 12 states have (on average 1.3333333333333333) internal successors, (16), 11 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:05:22,538 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 16 transitions. [2022-11-02 21:05:22,538 INFO L240 hiAutomatonCegarLoop]: Abstraction has 12 states and 16 transitions. [2022-11-02 21:05:22,539 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-02 21:05:22,539 INFO L428 stractBuchiCegarLoop]: Abstraction has 12 states and 16 transitions. [2022-11-02 21:05:22,540 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-11-02 21:05:22,540 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12 states and 16 transitions. [2022-11-02 21:05:22,540 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:05:22,540 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 21:05:22,540 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 21:05:22,541 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 21:05:22,541 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-02 21:05:22,541 INFO L748 eck$LassoCheckResult]: Stem: 145#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 146#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 153#L367 assume !(main_~length~0#1 < 1); 147#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 148#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 149#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 154#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 156#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 155#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 150#L370-4 main_~j~0#1 := 0; 151#L378-2 [2022-11-02 21:05:22,541 INFO L750 eck$LassoCheckResult]: Loop: 151#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 152#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 151#L378-2 [2022-11-02 21:05:22,542 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:05:22,542 INFO L85 PathProgramCache]: Analyzing trace with hash -1982565540, now seen corresponding path program 1 times [2022-11-02 21:05:22,542 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:05:22,543 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [756941068] [2022-11-02 21:05:22,543 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:05:22,543 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:05:22,593 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:05:22,593 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:05:22,608 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:05:22,627 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:05:22,628 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:05:22,628 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 2 times [2022-11-02 21:05:22,628 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:05:22,629 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [224026481] [2022-11-02 21:05:22,629 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:05:22,629 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:05:22,651 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:05:22,651 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:05:22,656 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:05:22,671 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:05:22,672 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:05:22,675 INFO L85 PathProgramCache]: Analyzing trace with hash 1719996831, now seen corresponding path program 1 times [2022-11-02 21:05:22,675 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:05:22,676 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2011508807] [2022-11-02 21:05:22,676 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:05:22,676 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:05:22,679 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Forceful destruction successful, exit code 0 [2022-11-02 21:05:22,702 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 21:05:23,262 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:05:23,263 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 21:05:23,263 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2011508807] [2022-11-02 21:05:23,265 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2011508807] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 21:05:23,267 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [187261078] [2022-11-02 21:05:23,267 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:05:23,268 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 21:05:23,268 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:05:23,276 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 21:05:23,282 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Waiting until timeout for monitored process [2022-11-02 21:05:23,348 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 21:05:23,349 INFO L263 TraceCheckSpWp]: Trace formula consists of 58 conjuncts, 14 conjunts are in the unsatisfiable core [2022-11-02 21:05:23,353 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 21:05:23,423 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2022-11-02 21:05:23,517 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-02 21:05:23,528 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:05:23,529 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 21:05:23,622 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 14 [2022-11-02 21:05:23,630 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 24 [2022-11-02 21:05:23,649 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:05:23,650 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [187261078] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 21:05:23,650 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 21:05:23,650 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 7, 6] total 14 [2022-11-02 21:05:23,650 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1172145974] [2022-11-02 21:05:23,652 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 21:05:23,717 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 21:05:23,718 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2022-11-02 21:05:23,720 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=52, Invalid=158, Unknown=0, NotChecked=0, Total=210 [2022-11-02 21:05:23,721 INFO L87 Difference]: Start difference. First operand 12 states and 16 transitions. cyclomatic complexity: 6 Second operand has 15 states, 14 states have (on average 1.7857142857142858) internal successors, (25), 15 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:05:23,928 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 21:05:23,928 INFO L93 Difference]: Finished difference Result 22 states and 30 transitions. [2022-11-02 21:05:23,929 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22 states and 30 transitions. [2022-11-02 21:05:23,930 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-02 21:05:23,930 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22 states to 22 states and 30 transitions. [2022-11-02 21:05:23,930 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14 [2022-11-02 21:05:23,931 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14 [2022-11-02 21:05:23,931 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22 states and 30 transitions. [2022-11-02 21:05:23,931 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-02 21:05:23,931 INFO L218 hiAutomatonCegarLoop]: Abstraction has 22 states and 30 transitions. [2022-11-02 21:05:23,932 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22 states and 30 transitions. [2022-11-02 21:05:23,934 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22 to 19. [2022-11-02 21:05:23,934 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19 states, 19 states have (on average 1.368421052631579) internal successors, (26), 18 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:05:23,935 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19 states to 19 states and 26 transitions. [2022-11-02 21:05:23,935 INFO L240 hiAutomatonCegarLoop]: Abstraction has 19 states and 26 transitions. [2022-11-02 21:05:23,935 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2022-11-02 21:05:23,936 INFO L428 stractBuchiCegarLoop]: Abstraction has 19 states and 26 transitions. [2022-11-02 21:05:23,937 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-11-02 21:05:23,937 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19 states and 26 transitions. [2022-11-02 21:05:23,937 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:05:23,938 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 21:05:23,938 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 21:05:23,939 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 21:05:23,940 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-02 21:05:23,940 INFO L748 eck$LassoCheckResult]: Stem: 269#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 270#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 277#L367 assume !(main_~length~0#1 < 1); 271#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 272#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 273#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 278#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 283#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 279#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 280#L370-4 main_~j~0#1 := 0; 284#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 274#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 275#L378-2 [2022-11-02 21:05:23,940 INFO L750 eck$LassoCheckResult]: Loop: 275#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 282#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 275#L378-2 [2022-11-02 21:05:23,941 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:05:23,941 INFO L85 PathProgramCache]: Analyzing trace with hash 1719996833, now seen corresponding path program 1 times [2022-11-02 21:05:23,941 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:05:23,941 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [825642977] [2022-11-02 21:05:23,941 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:05:23,942 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:05:23,953 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:05:23,954 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:05:23,961 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:05:23,965 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:05:23,965 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:05:23,966 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 3 times [2022-11-02 21:05:23,966 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:05:23,966 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [346934000] [2022-11-02 21:05:23,966 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:05:23,966 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:05:23,970 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:05:23,970 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:05:23,973 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:05:23,974 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:05:23,975 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:05:23,975 INFO L85 PathProgramCache]: Analyzing trace with hash -645451100, now seen corresponding path program 1 times [2022-11-02 21:05:23,975 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:05:23,975 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2040603364] [2022-11-02 21:05:23,976 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:05:23,976 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:05:23,987 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 21:05:24,060 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 1 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:05:24,060 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 21:05:24,060 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2040603364] [2022-11-02 21:05:24,061 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2040603364] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 21:05:24,061 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1247182477] [2022-11-02 21:05:24,061 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:05:24,061 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 21:05:24,062 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:05:24,063 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 21:05:24,064 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2022-11-02 21:05:24,161 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 21:05:24,162 INFO L263 TraceCheckSpWp]: Trace formula consists of 69 conjuncts, 6 conjunts are in the unsatisfiable core [2022-11-02 21:05:24,163 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 21:05:24,233 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 2 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:05:24,233 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 21:05:24,286 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 2 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:05:24,287 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1247182477] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 21:05:24,287 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 21:05:24,287 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7] total 11 [2022-11-02 21:05:24,288 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [792661261] [2022-11-02 21:05:24,288 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 21:05:24,355 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 21:05:24,355 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2022-11-02 21:05:24,356 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=32, Invalid=78, Unknown=0, NotChecked=0, Total=110 [2022-11-02 21:05:24,356 INFO L87 Difference]: Start difference. First operand 19 states and 26 transitions. cyclomatic complexity: 10 Second operand has 11 states, 11 states have (on average 2.272727272727273) internal successors, (25), 11 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:05:24,515 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 21:05:24,515 INFO L93 Difference]: Finished difference Result 43 states and 57 transitions. [2022-11-02 21:05:24,515 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 43 states and 57 transitions. [2022-11-02 21:05:24,516 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-02 21:05:24,517 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 43 states to 39 states and 51 transitions. [2022-11-02 21:05:24,517 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19 [2022-11-02 21:05:24,517 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19 [2022-11-02 21:05:24,518 INFO L73 IsDeterministic]: Start isDeterministic. Operand 39 states and 51 transitions. [2022-11-02 21:05:24,518 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-02 21:05:24,518 INFO L218 hiAutomatonCegarLoop]: Abstraction has 39 states and 51 transitions. [2022-11-02 21:05:24,518 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39 states and 51 transitions. [2022-11-02 21:05:24,521 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39 to 34. [2022-11-02 21:05:24,521 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 34 states, 34 states have (on average 1.3235294117647058) internal successors, (45), 33 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:05:24,522 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34 states to 34 states and 45 transitions. [2022-11-02 21:05:24,522 INFO L240 hiAutomatonCegarLoop]: Abstraction has 34 states and 45 transitions. [2022-11-02 21:05:24,526 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2022-11-02 21:05:24,527 INFO L428 stractBuchiCegarLoop]: Abstraction has 34 states and 45 transitions. [2022-11-02 21:05:24,527 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-11-02 21:05:24,527 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 34 states and 45 transitions. [2022-11-02 21:05:24,528 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-02 21:05:24,528 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 21:05:24,528 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 21:05:24,529 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 21:05:24,529 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-02 21:05:24,529 INFO L748 eck$LassoCheckResult]: Stem: 437#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 438#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 444#L367 assume main_~length~0#1 < 1;main_~length~0#1 := 1; 445#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 461#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 460#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 457#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 455#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 456#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 458#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 452#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 453#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 440#L370-4 main_~j~0#1 := 0; 441#L378-2 [2022-11-02 21:05:24,529 INFO L750 eck$LassoCheckResult]: Loop: 441#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 451#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 441#L378-2 [2022-11-02 21:05:24,530 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:05:24,530 INFO L85 PathProgramCache]: Analyzing trace with hash 1080825110, now seen corresponding path program 1 times [2022-11-02 21:05:24,530 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:05:24,530 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1571829793] [2022-11-02 21:05:24,531 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:05:24,531 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:05:24,547 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 21:05:24,633 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 4 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:05:24,633 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 21:05:24,634 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1571829793] [2022-11-02 21:05:24,634 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1571829793] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 21:05:24,634 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1362166566] [2022-11-02 21:05:24,634 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:05:24,635 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 21:05:24,635 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:05:24,637 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 21:05:24,665 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Waiting until timeout for monitored process [2022-11-02 21:05:24,710 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 21:05:24,712 INFO L263 TraceCheckSpWp]: Trace formula consists of 71 conjuncts, 4 conjunts are in the unsatisfiable core [2022-11-02 21:05:24,714 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 21:05:24,766 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:05:24,767 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-02 21:05:24,767 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1362166566] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-02 21:05:24,767 INFO L184 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2022-11-02 21:05:24,767 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [5] total 7 [2022-11-02 21:05:24,768 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1308611094] [2022-11-02 21:05:24,768 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-02 21:05:24,768 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-02 21:05:24,769 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:05:24,769 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 4 times [2022-11-02 21:05:24,769 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:05:24,769 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1071987619] [2022-11-02 21:05:24,769 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:05:24,770 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:05:24,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:05:24,774 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:05:24,775 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:05:24,777 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:05:24,845 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 21:05:24,846 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-02 21:05:24,846 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2022-11-02 21:05:24,846 INFO L87 Difference]: Start difference. First operand 34 states and 45 transitions. cyclomatic complexity: 17 Second operand has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:05:24,881 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 21:05:24,881 INFO L93 Difference]: Finished difference Result 27 states and 34 transitions. [2022-11-02 21:05:24,881 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27 states and 34 transitions. [2022-11-02 21:05:24,882 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:05:24,882 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27 states to 21 states and 27 transitions. [2022-11-02 21:05:24,882 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12 [2022-11-02 21:05:24,882 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12 [2022-11-02 21:05:24,883 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21 states and 27 transitions. [2022-11-02 21:05:24,883 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-02 21:05:24,883 INFO L218 hiAutomatonCegarLoop]: Abstraction has 21 states and 27 transitions. [2022-11-02 21:05:24,883 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21 states and 27 transitions. [2022-11-02 21:05:24,884 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21 to 21. [2022-11-02 21:05:24,885 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21 states, 21 states have (on average 1.2857142857142858) internal successors, (27), 20 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:05:24,886 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 27 transitions. [2022-11-02 21:05:24,886 INFO L240 hiAutomatonCegarLoop]: Abstraction has 21 states and 27 transitions. [2022-11-02 21:05:24,886 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-11-02 21:05:24,887 INFO L428 stractBuchiCegarLoop]: Abstraction has 21 states and 27 transitions. [2022-11-02 21:05:24,887 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-11-02 21:05:24,888 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21 states and 27 transitions. [2022-11-02 21:05:24,888 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:05:24,888 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 21:05:24,889 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 21:05:24,889 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 21:05:24,889 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-02 21:05:24,890 INFO L748 eck$LassoCheckResult]: Stem: 542#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 543#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 551#L367 assume !(main_~length~0#1 < 1); 544#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 545#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 546#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 552#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 555#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 553#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 554#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 561#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 558#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 557#L370-4 main_~j~0#1 := 0; 550#L378-2 [2022-11-02 21:05:24,890 INFO L750 eck$LassoCheckResult]: Loop: 550#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 556#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 550#L378-2 [2022-11-02 21:05:24,890 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:05:24,890 INFO L85 PathProgramCache]: Analyzing trace with hash 1781889688, now seen corresponding path program 1 times [2022-11-02 21:05:24,891 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:05:24,891 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1821562635] [2022-11-02 21:05:24,891 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:05:24,891 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:05:24,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:05:24,903 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:05:24,910 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:05:24,914 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:05:24,914 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:05:24,914 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 5 times [2022-11-02 21:05:24,915 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:05:24,915 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [449715905] [2022-11-02 21:05:24,915 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:05:24,915 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:05:24,919 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:05:24,919 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:05:24,921 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:05:24,922 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:05:24,923 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:05:24,923 INFO L85 PathProgramCache]: Analyzing trace with hash -1295959589, now seen corresponding path program 1 times [2022-11-02 21:05:24,923 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:05:24,924 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [911743279] [2022-11-02 21:05:24,924 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:05:24,924 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:05:24,940 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 21:05:25,290 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:05:25,290 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 21:05:25,291 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [911743279] [2022-11-02 21:05:25,291 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [911743279] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 21:05:25,291 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1372984323] [2022-11-02 21:05:25,291 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:05:25,291 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 21:05:25,292 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:05:25,295 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 21:05:25,303 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Waiting until timeout for monitored process [2022-11-02 21:05:25,370 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 21:05:25,371 INFO L263 TraceCheckSpWp]: Trace formula consists of 80 conjuncts, 19 conjunts are in the unsatisfiable core [2022-11-02 21:05:25,379 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 21:05:25,404 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-02 21:05:25,478 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-02 21:05:25,480 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2022-11-02 21:05:25,508 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-02 21:05:25,509 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2022-11-02 21:05:25,555 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-02 21:05:25,567 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:05:25,567 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 21:05:37,706 WARN L833 $PredicateComparison]: unable to prove that (forall ((|v_ULTIMATE.start_main_~i~0#1_36| Int)) (or (not (<= (+ |c_ULTIMATE.start_main_~i~0#1| 1) |v_ULTIMATE.start_main_~i~0#1_36|)) (forall ((v_ArrVal_92 Int)) (< 0 (+ (select (store (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |v_ULTIMATE.start_main_~i~0#1_36| 4)) v_ArrVal_92) |c_ULTIMATE.start_main_~arr~0#1.offset|) 1))))) is different from false [2022-11-02 21:05:37,793 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 21 [2022-11-02 21:05:37,802 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 64 treesize of output 62 [2022-11-02 21:05:37,883 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 1 not checked. [2022-11-02 21:05:37,884 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1372984323] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 21:05:37,884 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 21:05:37,884 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 8] total 18 [2022-11-02 21:05:37,884 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1254526211] [2022-11-02 21:05:37,884 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 21:05:37,959 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 21:05:37,960 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2022-11-02 21:05:37,960 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=70, Invalid=239, Unknown=1, NotChecked=32, Total=342 [2022-11-02 21:05:37,960 INFO L87 Difference]: Start difference. First operand 21 states and 27 transitions. cyclomatic complexity: 9 Second operand has 19 states, 18 states have (on average 1.8333333333333333) internal successors, (33), 19 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:05:50,018 WARN L833 $PredicateComparison]: unable to prove that (let ((.cse0 (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|))) (and (<= 0 (select .cse0 (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |c_ULTIMATE.start_main_~i~0#1| 4)))) (= |c_ULTIMATE.start_main_~i~0#1| 0) (forall ((|v_ULTIMATE.start_main_~i~0#1_36| Int)) (or (not (<= (+ |c_ULTIMATE.start_main_~i~0#1| 1) |v_ULTIMATE.start_main_~i~0#1_36|)) (forall ((v_ArrVal_92 Int)) (< 0 (+ (select (store .cse0 (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |v_ULTIMATE.start_main_~i~0#1_36| 4)) v_ArrVal_92) |c_ULTIMATE.start_main_~arr~0#1.offset|) 1))))) (= |c_ULTIMATE.start_main_~arr~0#1.offset| 0))) is different from false [2022-11-02 21:06:02,057 WARN L833 $PredicateComparison]: unable to prove that (let ((.cse0 (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|))) (and (forall ((|v_ULTIMATE.start_main_~i~0#1_36| Int)) (or (not (<= (+ |c_ULTIMATE.start_main_~i~0#1| 1) |v_ULTIMATE.start_main_~i~0#1_36|)) (forall ((v_ArrVal_92 Int)) (< 0 (+ (select (store .cse0 (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |v_ULTIMATE.start_main_~i~0#1_36| 4)) v_ArrVal_92) |c_ULTIMATE.start_main_~arr~0#1.offset|) 1))))) (<= 1 |c_ULTIMATE.start_main_~i~0#1|) (<= 0 (select .cse0 |c_ULTIMATE.start_main_~arr~0#1.offset|)) (= |c_ULTIMATE.start_main_~arr~0#1.offset| 0))) is different from false [2022-11-02 21:06:02,217 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 21:06:02,217 INFO L93 Difference]: Finished difference Result 29 states and 37 transitions. [2022-11-02 21:06:02,218 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 29 states and 37 transitions. [2022-11-02 21:06:02,219 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-02 21:06:02,219 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 29 states to 29 states and 37 transitions. [2022-11-02 21:06:02,219 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17 [2022-11-02 21:06:02,220 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17 [2022-11-02 21:06:02,220 INFO L73 IsDeterministic]: Start isDeterministic. Operand 29 states and 37 transitions. [2022-11-02 21:06:02,220 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-02 21:06:02,220 INFO L218 hiAutomatonCegarLoop]: Abstraction has 29 states and 37 transitions. [2022-11-02 21:06:02,220 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29 states and 37 transitions. [2022-11-02 21:06:02,222 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29 to 23. [2022-11-02 21:06:02,223 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 23 states, 23 states have (on average 1.3043478260869565) internal successors, (30), 22 states have internal predecessors, (30), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:06:02,223 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23 states to 23 states and 30 transitions. [2022-11-02 21:06:02,223 INFO L240 hiAutomatonCegarLoop]: Abstraction has 23 states and 30 transitions. [2022-11-02 21:06:02,225 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2022-11-02 21:06:02,226 INFO L428 stractBuchiCegarLoop]: Abstraction has 23 states and 30 transitions. [2022-11-02 21:06:02,226 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-11-02 21:06:02,226 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 23 states and 30 transitions. [2022-11-02 21:06:02,227 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:06:02,227 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 21:06:02,227 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 21:06:02,230 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 21:06:02,230 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-02 21:06:02,230 INFO L748 eck$LassoCheckResult]: Stem: 711#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 712#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 719#L367 assume !(main_~length~0#1 < 1); 713#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 714#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 715#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 720#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 729#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 721#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 722#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 724#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 726#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 727#L370-4 main_~j~0#1 := 0; 730#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 716#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 717#L378-2 [2022-11-02 21:06:02,231 INFO L750 eck$LassoCheckResult]: Loop: 717#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 723#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 717#L378-2 [2022-11-02 21:06:02,231 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:06:02,231 INFO L85 PathProgramCache]: Analyzing trace with hash -1295959587, now seen corresponding path program 1 times [2022-11-02 21:06:02,231 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:06:02,232 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [63973928] [2022-11-02 21:06:02,232 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:06:02,232 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:06:02,254 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:06:02,254 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:06:02,269 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:06:02,281 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:06:02,282 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:06:02,285 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 6 times [2022-11-02 21:06:02,285 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:06:02,286 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1443179410] [2022-11-02 21:06:02,286 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:06:02,286 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:06:02,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:06:02,291 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:06:02,293 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:06:02,296 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:06:02,296 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:06:02,297 INFO L85 PathProgramCache]: Analyzing trace with hash 123354080, now seen corresponding path program 1 times [2022-11-02 21:06:02,297 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:06:02,297 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [147059650] [2022-11-02 21:06:02,297 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:06:02,297 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:06:02,320 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 21:06:02,547 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:06:02,547 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 21:06:02,547 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [147059650] [2022-11-02 21:06:02,547 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [147059650] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 21:06:02,548 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1904377762] [2022-11-02 21:06:02,548 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:06:02,548 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 21:06:02,548 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:06:02,551 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 21:06:02,560 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Waiting until timeout for monitored process [2022-11-02 21:06:02,634 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 21:06:02,635 INFO L263 TraceCheckSpWp]: Trace formula consists of 91 conjuncts, 17 conjunts are in the unsatisfiable core [2022-11-02 21:06:02,637 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 21:06:02,717 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 9 [2022-11-02 21:06:02,825 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-02 21:06:02,844 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:06:02,844 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 21:06:02,946 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 16 [2022-11-02 21:06:02,950 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 24 [2022-11-02 21:06:02,975 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:06:02,975 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1904377762] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 21:06:02,975 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 21:06:02,975 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 7] total 18 [2022-11-02 21:06:02,976 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1300497893] [2022-11-02 21:06:02,976 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 21:06:03,037 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 21:06:03,038 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2022-11-02 21:06:03,039 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=58, Invalid=284, Unknown=0, NotChecked=0, Total=342 [2022-11-02 21:06:03,039 INFO L87 Difference]: Start difference. First operand 23 states and 30 transitions. cyclomatic complexity: 10 Second operand has 19 states, 18 states have (on average 2.111111111111111) internal successors, (38), 19 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:06:03,359 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 21:06:03,359 INFO L93 Difference]: Finished difference Result 34 states and 44 transitions. [2022-11-02 21:06:03,359 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 34 states and 44 transitions. [2022-11-02 21:06:03,360 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-02 21:06:03,361 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 34 states to 34 states and 44 transitions. [2022-11-02 21:06:03,361 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19 [2022-11-02 21:06:03,361 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19 [2022-11-02 21:06:03,361 INFO L73 IsDeterministic]: Start isDeterministic. Operand 34 states and 44 transitions. [2022-11-02 21:06:03,361 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-02 21:06:03,362 INFO L218 hiAutomatonCegarLoop]: Abstraction has 34 states and 44 transitions. [2022-11-02 21:06:03,362 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34 states and 44 transitions. [2022-11-02 21:06:03,364 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34 to 29. [2022-11-02 21:06:03,364 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 29 states, 29 states have (on average 1.3103448275862069) internal successors, (38), 28 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:06:03,365 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29 states to 29 states and 38 transitions. [2022-11-02 21:06:03,365 INFO L240 hiAutomatonCegarLoop]: Abstraction has 29 states and 38 transitions. [2022-11-02 21:06:03,369 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2022-11-02 21:06:03,370 INFO L428 stractBuchiCegarLoop]: Abstraction has 29 states and 38 transitions. [2022-11-02 21:06:03,371 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-11-02 21:06:03,371 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 29 states and 38 transitions. [2022-11-02 21:06:03,372 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:06:03,375 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 21:06:03,375 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 21:06:03,376 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 21:06:03,377 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-02 21:06:03,377 INFO L748 eck$LassoCheckResult]: Stem: 898#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 899#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 906#L367 assume !(main_~length~0#1 < 1); 900#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 901#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 902#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 907#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 917#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 908#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 909#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 912#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 913#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 905#L370-4 main_~j~0#1 := 0; 904#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 910#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 919#L378-2 [2022-11-02 21:06:03,377 INFO L750 eck$LassoCheckResult]: Loop: 919#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 918#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 919#L378-2 [2022-11-02 21:06:03,378 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:06:03,378 INFO L85 PathProgramCache]: Analyzing trace with hash -1238701285, now seen corresponding path program 2 times [2022-11-02 21:06:03,378 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:06:03,379 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [740160571] [2022-11-02 21:06:03,379 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:06:03,379 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:06:03,403 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:06:03,404 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:06:03,421 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:06:03,429 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:06:03,430 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:06:03,430 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 7 times [2022-11-02 21:06:03,431 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:06:03,431 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1088196118] [2022-11-02 21:06:03,431 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:06:03,431 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:06:03,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:06:03,439 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:06:03,445 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:06:03,447 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:06:03,449 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:06:03,449 INFO L85 PathProgramCache]: Analyzing trace with hash -685992546, now seen corresponding path program 2 times [2022-11-02 21:06:03,449 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:06:03,449 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [989719503] [2022-11-02 21:06:03,450 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:06:03,450 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:06:03,477 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 21:06:03,731 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:06:03,732 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 21:06:03,732 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [989719503] [2022-11-02 21:06:03,732 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [989719503] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 21:06:03,732 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1425873633] [2022-11-02 21:06:03,733 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-02 21:06:03,733 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 21:06:03,733 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:06:03,735 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 21:06:03,742 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Waiting until timeout for monitored process [2022-11-02 21:06:03,815 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-02 21:06:03,816 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-02 21:06:03,817 INFO L263 TraceCheckSpWp]: Trace formula consists of 83 conjuncts, 14 conjunts are in the unsatisfiable core [2022-11-02 21:06:03,818 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 21:06:03,841 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-02 21:06:03,947 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2022-11-02 21:06:03,950 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:06:03,951 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 21:06:04,041 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 14 [2022-11-02 21:06:04,045 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 20 [2022-11-02 21:06:04,064 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:06:04,064 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1425873633] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 21:06:04,064 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 21:06:04,065 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 8, 8] total 13 [2022-11-02 21:06:04,065 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [679853561] [2022-11-02 21:06:04,065 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 21:06:04,126 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 21:06:04,127 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2022-11-02 21:06:04,127 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=39, Invalid=143, Unknown=0, NotChecked=0, Total=182 [2022-11-02 21:06:04,127 INFO L87 Difference]: Start difference. First operand 29 states and 38 transitions. cyclomatic complexity: 12 Second operand has 14 states, 13 states have (on average 2.076923076923077) internal successors, (27), 14 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:06:04,295 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 21:06:04,295 INFO L93 Difference]: Finished difference Result 45 states and 58 transitions. [2022-11-02 21:06:04,295 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 45 states and 58 transitions. [2022-11-02 21:06:04,296 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-02 21:06:04,296 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 45 states to 45 states and 58 transitions. [2022-11-02 21:06:04,297 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27 [2022-11-02 21:06:04,297 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27 [2022-11-02 21:06:04,297 INFO L73 IsDeterministic]: Start isDeterministic. Operand 45 states and 58 transitions. [2022-11-02 21:06:04,297 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-02 21:06:04,297 INFO L218 hiAutomatonCegarLoop]: Abstraction has 45 states and 58 transitions. [2022-11-02 21:06:04,298 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 45 states and 58 transitions. [2022-11-02 21:06:04,300 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 45 to 35. [2022-11-02 21:06:04,300 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 35 states, 35 states have (on average 1.3428571428571427) internal successors, (47), 34 states have internal predecessors, (47), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:06:04,300 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35 states to 35 states and 47 transitions. [2022-11-02 21:06:04,301 INFO L240 hiAutomatonCegarLoop]: Abstraction has 35 states and 47 transitions. [2022-11-02 21:06:04,304 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2022-11-02 21:06:04,308 INFO L428 stractBuchiCegarLoop]: Abstraction has 35 states and 47 transitions. [2022-11-02 21:06:04,309 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-11-02 21:06:04,310 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 35 states and 47 transitions. [2022-11-02 21:06:04,310 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:06:04,310 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 21:06:04,311 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 21:06:04,311 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 21:06:04,311 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-02 21:06:04,312 INFO L748 eck$LassoCheckResult]: Stem: 1089#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1090#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 1097#L367 assume !(main_~length~0#1 < 1); 1091#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 1092#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 1093#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1098#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 1107#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1099#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1100#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1101#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1104#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1106#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1117#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1114#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 1111#L370-4 main_~j~0#1 := 0; 1109#L378-2 [2022-11-02 21:06:04,312 INFO L750 eck$LassoCheckResult]: Loop: 1109#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1110#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 1109#L378-2 [2022-11-02 21:06:04,312 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:06:04,312 INFO L85 PathProgramCache]: Analyzing trace with hash -1518446116, now seen corresponding path program 2 times [2022-11-02 21:06:04,313 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:06:04,313 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [717631732] [2022-11-02 21:06:04,313 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:06:04,313 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:06:04,325 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:06:04,326 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:06:04,346 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:06:04,349 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:06:04,349 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:06:04,349 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 8 times [2022-11-02 21:06:04,350 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:06:04,350 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2110024909] [2022-11-02 21:06:04,350 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:06:04,350 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:06:04,353 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:06:04,354 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:06:04,355 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:06:04,357 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:06:04,357 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:06:04,357 INFO L85 PathProgramCache]: Analyzing trace with hash 1062164511, now seen corresponding path program 2 times [2022-11-02 21:06:04,358 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:06:04,358 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1630168990] [2022-11-02 21:06:04,358 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:06:04,358 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:06:04,372 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 21:06:05,011 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:06:05,011 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 21:06:05,011 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1630168990] [2022-11-02 21:06:05,012 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1630168990] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 21:06:05,012 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1140994450] [2022-11-02 21:06:05,012 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-02 21:06:05,012 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 21:06:05,013 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:06:05,016 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 21:06:05,033 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Waiting until timeout for monitored process [2022-11-02 21:06:05,097 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-02 21:06:05,098 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-02 21:06:05,099 INFO L263 TraceCheckSpWp]: Trace formula consists of 102 conjuncts, 23 conjunts are in the unsatisfiable core [2022-11-02 21:06:05,102 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 21:06:05,133 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-02 21:06:05,225 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-02 21:06:05,226 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2022-11-02 21:06:05,239 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-02 21:06:05,240 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2022-11-02 21:06:05,282 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-02 21:06:05,283 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2022-11-02 21:06:05,300 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-02 21:06:05,301 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2022-11-02 21:06:05,365 INFO L173 IndexEqualityManager]: detected equality via solver [2022-11-02 21:06:05,368 INFO L356 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-02 21:06:05,369 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 19 treesize of output 10 [2022-11-02 21:06:05,384 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 2 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:06:05,384 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 21:06:54,991 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 25 [2022-11-02 21:06:55,000 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 80 treesize of output 74 [2022-11-02 21:06:55,083 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 1 proven. 10 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-02 21:06:55,083 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1140994450] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 21:06:55,083 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 21:06:55,083 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 9] total 26 [2022-11-02 21:06:55,086 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1330066731] [2022-11-02 21:06:55,086 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 21:06:55,148 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 21:06:55,148 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2022-11-02 21:06:55,149 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=143, Invalid=556, Unknown=3, NotChecked=0, Total=702 [2022-11-02 21:06:55,149 INFO L87 Difference]: Start difference. First operand 35 states and 47 transitions. cyclomatic complexity: 16 Second operand has 27 states, 26 states have (on average 1.8076923076923077) internal successors, (47), 27 states have internal predecessors, (47), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:06:55,411 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 21:06:55,411 INFO L93 Difference]: Finished difference Result 41 states and 52 transitions. [2022-11-02 21:06:55,411 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 41 states and 52 transitions. [2022-11-02 21:06:55,412 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:06:55,412 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 41 states to 41 states and 52 transitions. [2022-11-02 21:06:55,412 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22 [2022-11-02 21:06:55,412 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22 [2022-11-02 21:06:55,413 INFO L73 IsDeterministic]: Start isDeterministic. Operand 41 states and 52 transitions. [2022-11-02 21:06:55,413 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-02 21:06:55,413 INFO L218 hiAutomatonCegarLoop]: Abstraction has 41 states and 52 transitions. [2022-11-02 21:06:55,413 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41 states and 52 transitions. [2022-11-02 21:06:55,415 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41 to 24. [2022-11-02 21:06:55,415 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24 states, 24 states have (on average 1.2916666666666667) internal successors, (31), 23 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:06:55,416 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24 states to 24 states and 31 transitions. [2022-11-02 21:06:55,416 INFO L240 hiAutomatonCegarLoop]: Abstraction has 24 states and 31 transitions. [2022-11-02 21:06:55,423 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2022-11-02 21:06:55,423 INFO L428 stractBuchiCegarLoop]: Abstraction has 24 states and 31 transitions. [2022-11-02 21:06:55,424 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-11-02 21:06:55,424 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 24 states and 31 transitions. [2022-11-02 21:06:55,424 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:06:55,424 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 21:06:55,424 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 21:06:55,425 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 21:06:55,425 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-02 21:06:55,425 INFO L748 eck$LassoCheckResult]: Stem: 1308#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1309#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 1316#L367 assume !(main_~length~0#1 < 1); 1310#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 1311#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 1312#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1317#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 1325#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1318#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1319#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 1321#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1322#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 1323#L370-4 main_~j~0#1 := 0; 1328#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1313#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 1314#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1320#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 1327#L378-2 [2022-11-02 21:06:55,425 INFO L750 eck$LassoCheckResult]: Loop: 1327#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1326#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 1327#L378-2 [2022-11-02 21:06:55,426 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:06:55,426 INFO L85 PathProgramCache]: Analyzing trace with hash -685992544, now seen corresponding path program 3 times [2022-11-02 21:06:55,426 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:06:55,426 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2017977884] [2022-11-02 21:06:55,426 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:06:55,427 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:06:55,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:06:55,442 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:06:55,461 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:06:55,464 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:06:55,466 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:06:55,466 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 9 times [2022-11-02 21:06:55,467 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:06:55,467 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [81103935] [2022-11-02 21:06:55,468 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:06:55,468 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:06:55,471 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:06:55,471 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:06:55,473 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:06:55,475 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:06:55,475 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:06:55,475 INFO L85 PathProgramCache]: Analyzing trace with hash -2108837149, now seen corresponding path program 3 times [2022-11-02 21:06:55,476 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:06:55,476 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1808085300] [2022-11-02 21:06:55,476 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:06:55,476 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:06:55,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 21:06:55,602 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 3 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:06:55,602 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 21:06:55,602 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1808085300] [2022-11-02 21:06:55,605 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1808085300] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 21:06:55,605 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1494837169] [2022-11-02 21:06:55,605 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-02 21:06:55,605 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 21:06:55,606 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:06:55,611 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 21:06:55,619 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Waiting until timeout for monitored process [2022-11-02 21:06:55,691 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2022-11-02 21:06:55,691 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-02 21:06:55,692 INFO L263 TraceCheckSpWp]: Trace formula consists of 94 conjuncts, 8 conjunts are in the unsatisfiable core [2022-11-02 21:06:55,694 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 21:06:55,795 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 6 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:06:55,795 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 21:06:55,891 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 6 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:06:55,891 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1494837169] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 21:06:55,891 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 21:06:55,891 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9] total 14 [2022-11-02 21:06:55,891 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2134888942] [2022-11-02 21:06:55,892 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 21:06:55,948 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 21:06:55,949 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2022-11-02 21:06:55,949 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=49, Invalid=133, Unknown=0, NotChecked=0, Total=182 [2022-11-02 21:06:55,949 INFO L87 Difference]: Start difference. First operand 24 states and 31 transitions. cyclomatic complexity: 10 Second operand has 14 states, 14 states have (on average 2.2857142857142856) internal successors, (32), 14 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:06:56,087 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 21:06:56,087 INFO L93 Difference]: Finished difference Result 35 states and 43 transitions. [2022-11-02 21:06:56,088 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 35 states and 43 transitions. [2022-11-02 21:06:56,088 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:06:56,089 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 35 states to 29 states and 37 transitions. [2022-11-02 21:06:56,089 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14 [2022-11-02 21:06:56,089 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14 [2022-11-02 21:06:56,089 INFO L73 IsDeterministic]: Start isDeterministic. Operand 29 states and 37 transitions. [2022-11-02 21:06:56,091 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-02 21:06:56,091 INFO L218 hiAutomatonCegarLoop]: Abstraction has 29 states and 37 transitions. [2022-11-02 21:06:56,091 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29 states and 37 transitions. [2022-11-02 21:06:56,093 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29 to 26. [2022-11-02 21:06:56,093 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 26 states, 26 states have (on average 1.2692307692307692) internal successors, (33), 25 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:06:56,094 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26 states to 26 states and 33 transitions. [2022-11-02 21:06:56,094 INFO L240 hiAutomatonCegarLoop]: Abstraction has 26 states and 33 transitions. [2022-11-02 21:06:56,094 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2022-11-02 21:06:56,095 INFO L428 stractBuchiCegarLoop]: Abstraction has 26 states and 33 transitions. [2022-11-02 21:06:56,095 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-11-02 21:06:56,095 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 26 states and 33 transitions. [2022-11-02 21:06:56,096 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:06:56,096 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 21:06:56,096 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 21:06:56,097 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 21:06:56,097 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-02 21:06:56,097 INFO L748 eck$LassoCheckResult]: Stem: 1502#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1503#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 1511#L367 assume !(main_~length~0#1 < 1); 1504#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 1505#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 1506#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1512#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 1527#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1526#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1515#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 1516#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1513#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1514#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1524#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1522#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 1521#L370-4 main_~j~0#1 := 0; 1510#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1520#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 1519#L378-2 [2022-11-02 21:06:56,097 INFO L750 eck$LassoCheckResult]: Loop: 1519#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1518#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 1519#L378-2 [2022-11-02 21:06:56,098 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:06:56,098 INFO L85 PathProgramCache]: Analyzing trace with hash 1742222883, now seen corresponding path program 2 times [2022-11-02 21:06:56,098 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:06:56,098 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2144289290] [2022-11-02 21:06:56,099 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:06:56,099 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:06:56,111 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:06:56,111 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:06:56,118 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:06:56,122 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:06:56,123 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:06:56,123 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 10 times [2022-11-02 21:06:56,123 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:06:56,123 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [618430941] [2022-11-02 21:06:56,123 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:06:56,124 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:06:56,126 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:06:56,127 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:06:56,128 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:06:56,130 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:06:56,130 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:06:56,131 INFO L85 PathProgramCache]: Analyzing trace with hash -761053530, now seen corresponding path program 2 times [2022-11-02 21:06:56,131 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:06:56,131 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1883696566] [2022-11-02 21:06:56,131 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:06:56,131 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:06:56,144 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 21:06:56,441 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:06:56,441 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 21:06:56,441 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1883696566] [2022-11-02 21:06:56,442 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1883696566] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 21:06:56,442 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1379944516] [2022-11-02 21:06:56,442 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-02 21:06:56,442 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 21:06:56,442 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:06:56,445 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 21:06:56,481 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Waiting until timeout for monitored process [2022-11-02 21:06:56,551 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-02 21:06:56,551 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-02 21:06:56,553 INFO L263 TraceCheckSpWp]: Trace formula consists of 105 conjuncts, 19 conjunts are in the unsatisfiable core [2022-11-02 21:06:56,556 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 21:06:56,578 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-02 21:06:56,684 INFO L356 Elim1Store]: treesize reduction 29, result has 27.5 percent of original size [2022-11-02 21:06:56,684 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 26 [2022-11-02 21:06:56,721 INFO L356 Elim1Store]: treesize reduction 29, result has 27.5 percent of original size [2022-11-02 21:06:56,721 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 26 [2022-11-02 21:06:56,794 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2022-11-02 21:06:56,798 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:06:56,798 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 21:06:56,993 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 19 [2022-11-02 21:06:56,996 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 25 [2022-11-02 21:06:57,018 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:06:57,018 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1379944516] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 21:06:57,019 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 21:06:57,019 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10] total 16 [2022-11-02 21:06:57,019 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1668663081] [2022-11-02 21:06:57,019 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 21:06:57,073 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 21:06:57,074 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2022-11-02 21:06:57,074 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=51, Invalid=221, Unknown=0, NotChecked=0, Total=272 [2022-11-02 21:06:57,074 INFO L87 Difference]: Start difference. First operand 26 states and 33 transitions. cyclomatic complexity: 10 Second operand has 17 states, 16 states have (on average 2.0625) internal successors, (33), 17 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:06:57,299 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 21:06:57,299 INFO L93 Difference]: Finished difference Result 53 states and 67 transitions. [2022-11-02 21:06:57,299 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 53 states and 67 transitions. [2022-11-02 21:06:57,300 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 6 [2022-11-02 21:06:57,300 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 53 states to 53 states and 67 transitions. [2022-11-02 21:06:57,300 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 33 [2022-11-02 21:06:57,301 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 33 [2022-11-02 21:06:57,301 INFO L73 IsDeterministic]: Start isDeterministic. Operand 53 states and 67 transitions. [2022-11-02 21:06:57,301 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-02 21:06:57,301 INFO L218 hiAutomatonCegarLoop]: Abstraction has 53 states and 67 transitions. [2022-11-02 21:06:57,301 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53 states and 67 transitions. [2022-11-02 21:06:57,304 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53 to 32. [2022-11-02 21:06:57,304 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 32 states, 32 states have (on average 1.34375) internal successors, (43), 31 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:06:57,305 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32 states to 32 states and 43 transitions. [2022-11-02 21:06:57,305 INFO L240 hiAutomatonCegarLoop]: Abstraction has 32 states and 43 transitions. [2022-11-02 21:06:57,306 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2022-11-02 21:06:57,306 INFO L428 stractBuchiCegarLoop]: Abstraction has 32 states and 43 transitions. [2022-11-02 21:06:57,307 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-11-02 21:06:57,307 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 32 states and 43 transitions. [2022-11-02 21:06:57,307 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:06:57,307 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 21:06:57,307 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 21:06:57,308 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 21:06:57,308 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-02 21:06:57,309 INFO L748 eck$LassoCheckResult]: Stem: 1725#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1726#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 1733#L367 assume !(main_~length~0#1 < 1); 1727#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 1728#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 1729#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1734#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 1741#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1742#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1746#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 1747#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1735#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1736#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1738#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1755#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 1744#L370-4 main_~j~0#1 := 0; 1750#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1732#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 1731#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1740#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 1749#L378-2 [2022-11-02 21:06:57,309 INFO L750 eck$LassoCheckResult]: Loop: 1749#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1748#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 1749#L378-2 [2022-11-02 21:06:57,309 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:06:57,309 INFO L85 PathProgramCache]: Analyzing trace with hash -761053528, now seen corresponding path program 3 times [2022-11-02 21:06:57,310 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:06:57,310 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [811164453] [2022-11-02 21:06:57,310 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:06:57,310 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:06:57,324 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:06:57,324 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:06:57,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:06:57,336 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:06:57,337 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:06:57,337 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 11 times [2022-11-02 21:06:57,337 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:06:57,337 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1629086399] [2022-11-02 21:06:57,337 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:06:57,338 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:06:57,340 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:06:57,341 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:06:57,342 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:06:57,343 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:06:57,344 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:06:57,344 INFO L85 PathProgramCache]: Analyzing trace with hash -1227998741, now seen corresponding path program 3 times [2022-11-02 21:06:57,344 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:06:57,344 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [499189152] [2022-11-02 21:06:57,345 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:06:57,345 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:06:57,356 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 21:06:57,589 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:06:57,589 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 21:06:57,589 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [499189152] [2022-11-02 21:06:57,590 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [499189152] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 21:06:57,590 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1115540621] [2022-11-02 21:06:57,590 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-02 21:06:57,590 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 21:06:57,590 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:06:57,593 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 21:06:57,613 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Waiting until timeout for monitored process [2022-11-02 21:06:57,690 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2022-11-02 21:06:57,690 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-02 21:06:57,691 INFO L263 TraceCheckSpWp]: Trace formula consists of 116 conjuncts, 14 conjunts are in the unsatisfiable core [2022-11-02 21:06:57,719 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 21:06:57,784 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-02 21:06:58,076 INFO L356 Elim1Store]: treesize reduction 9, result has 25.0 percent of original size [2022-11-02 21:06:58,077 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 10 [2022-11-02 21:06:58,103 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 4 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:06:58,103 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 21:06:58,472 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2022-11-02 21:06:58,479 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 28 [2022-11-02 21:06:58,540 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 2 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:06:58,540 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1115540621] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 21:06:58,540 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 21:06:58,541 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 11, 11] total 26 [2022-11-02 21:06:58,541 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [19147857] [2022-11-02 21:06:58,541 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 21:06:58,604 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 21:06:58,604 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2022-11-02 21:06:58,605 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=103, Invalid=599, Unknown=0, NotChecked=0, Total=702 [2022-11-02 21:06:58,605 INFO L87 Difference]: Start difference. First operand 32 states and 43 transitions. cyclomatic complexity: 14 Second operand has 27 states, 26 states have (on average 1.8846153846153846) internal successors, (49), 27 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:06:58,981 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 21:06:58,981 INFO L93 Difference]: Finished difference Result 47 states and 59 transitions. [2022-11-02 21:06:58,981 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 47 states and 59 transitions. [2022-11-02 21:06:58,982 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-02 21:06:58,982 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 47 states to 47 states and 59 transitions. [2022-11-02 21:06:58,983 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 23 [2022-11-02 21:06:58,983 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23 [2022-11-02 21:06:58,983 INFO L73 IsDeterministic]: Start isDeterministic. Operand 47 states and 59 transitions. [2022-11-02 21:06:58,984 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-02 21:06:58,984 INFO L218 hiAutomatonCegarLoop]: Abstraction has 47 states and 59 transitions. [2022-11-02 21:06:58,984 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47 states and 59 transitions. [2022-11-02 21:06:58,986 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47 to 37. [2022-11-02 21:06:58,987 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 37 states, 37 states have (on average 1.3243243243243243) internal successors, (49), 36 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:06:58,987 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37 states to 37 states and 49 transitions. [2022-11-02 21:06:58,987 INFO L240 hiAutomatonCegarLoop]: Abstraction has 37 states and 49 transitions. [2022-11-02 21:06:58,988 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2022-11-02 21:06:58,988 INFO L428 stractBuchiCegarLoop]: Abstraction has 37 states and 49 transitions. [2022-11-02 21:06:58,988 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-11-02 21:06:58,988 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 37 states and 49 transitions. [2022-11-02 21:06:58,989 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-02 21:06:58,989 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 21:06:58,989 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 21:06:58,990 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 21:06:58,990 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-02 21:06:58,990 INFO L748 eck$LassoCheckResult]: Stem: 1986#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1987#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 1994#L367 assume !(main_~length~0#1 < 1); 1988#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 1989#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 1990#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1995#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 2007#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2006#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1998#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 1999#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1996#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1997#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2022#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2019#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 1993#L370-4 main_~j~0#1 := 0; 1992#L378-2 [2022-11-02 21:06:58,991 INFO L750 eck$LassoCheckResult]: Loop: 1992#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1991#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 1992#L378-2 [2022-11-02 21:06:58,991 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:06:58,991 INFO L85 PathProgramCache]: Analyzing trace with hash 256561246, now seen corresponding path program 3 times [2022-11-02 21:06:58,991 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:06:58,992 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [587606229] [2022-11-02 21:06:58,992 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:06:58,992 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:06:59,023 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:06:59,023 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:06:59,029 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:06:59,032 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:06:59,032 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:06:59,032 INFO L85 PathProgramCache]: Analyzing trace with hash 2310, now seen corresponding path program 1 times [2022-11-02 21:06:59,033 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:06:59,033 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1584296263] [2022-11-02 21:06:59,033 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:06:59,033 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:06:59,036 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:06:59,036 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:06:59,038 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:06:59,039 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:06:59,040 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:06:59,040 INFO L85 PathProgramCache]: Analyzing trace with hash 1742222883, now seen corresponding path program 4 times [2022-11-02 21:06:59,040 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:06:59,040 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1429976360] [2022-11-02 21:06:59,040 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:06:59,041 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:06:59,051 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:06:59,051 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:06:59,058 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:06:59,061 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:06:59,802 INFO L210 LassoAnalysis]: Preferences: [2022-11-02 21:06:59,802 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2022-11-02 21:06:59,802 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2022-11-02 21:06:59,802 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2022-11-02 21:06:59,803 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2022-11-02 21:06:59,803 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-02 21:06:59,803 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2022-11-02 21:06:59,803 INFO L132 ssoRankerPreferences]: Path of dumped script: [2022-11-02 21:06:59,803 INFO L133 ssoRankerPreferences]: Filename of dumped script: array12_alloca.i_Iteration13_Lasso [2022-11-02 21:06:59,803 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2022-11-02 21:06:59,803 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2022-11-02 21:06:59,806 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-02 21:06:59,812 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-02 21:06:59,814 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-02 21:06:59,817 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-02 21:06:59,820 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-02 21:06:59,823 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-02 21:06:59,826 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-02 21:06:59,828 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-02 21:06:59,831 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-02 21:06:59,833 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-02 21:07:00,114 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-02 21:07:00,116 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-02 21:07:00,459 INFO L294 LassoAnalysis]: Preprocessing complete. [2022-11-02 21:07:00,459 INFO L490 LassoAnalysis]: Using template 'affine'. [2022-11-02 21:07:00,459 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-02 21:07:00,459 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:07:00,467 INFO L229 MonitoredProcess]: Starting monitored process 22 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-02 21:07:00,477 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-02 21:07:00,492 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Waiting until timeout for monitored process [2022-11-02 21:07:00,493 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-02 21:07:00,493 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-02 21:07:00,493 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-02 21:07:00,493 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-02 21:07:00,501 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-02 21:07:00,501 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-02 21:07:00,511 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-02 21:07:00,537 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Forceful destruction successful, exit code 0 [2022-11-02 21:07:00,538 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-02 21:07:00,538 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:07:00,540 INFO L229 MonitoredProcess]: Starting monitored process 23 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-02 21:07:00,546 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Waiting until timeout for monitored process [2022-11-02 21:07:00,546 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-02 21:07:00,558 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-02 21:07:00,558 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-02 21:07:00,558 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-02 21:07:00,558 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-02 21:07:00,559 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-02 21:07:00,559 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-02 21:07:00,559 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-02 21:07:00,561 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-02 21:07:00,589 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Forceful destruction successful, exit code 0 [2022-11-02 21:07:00,590 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-02 21:07:00,590 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:07:00,591 INFO L229 MonitoredProcess]: Starting monitored process 24 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-02 21:07:00,592 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Waiting until timeout for monitored process [2022-11-02 21:07:00,593 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-02 21:07:00,605 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-02 21:07:00,605 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-02 21:07:00,605 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-02 21:07:00,605 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-02 21:07:00,605 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-02 21:07:00,606 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-02 21:07:00,606 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-02 21:07:00,607 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-02 21:07:00,633 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Forceful destruction successful, exit code 0 [2022-11-02 21:07:00,633 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-02 21:07:00,633 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:07:00,634 INFO L229 MonitoredProcess]: Starting monitored process 25 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-02 21:07:00,636 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Waiting until timeout for monitored process [2022-11-02 21:07:00,636 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-02 21:07:00,648 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-02 21:07:00,649 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-02 21:07:00,649 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-02 21:07:00,649 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-02 21:07:00,649 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-02 21:07:00,650 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-02 21:07:00,650 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-02 21:07:00,651 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-02 21:07:00,678 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Forceful destruction successful, exit code 0 [2022-11-02 21:07:00,678 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-02 21:07:00,678 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:07:00,679 INFO L229 MonitoredProcess]: Starting monitored process 26 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-02 21:07:00,680 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Waiting until timeout for monitored process [2022-11-02 21:07:00,681 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-02 21:07:00,693 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-02 21:07:00,693 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-02 21:07:00,693 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-02 21:07:00,693 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-02 21:07:00,696 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-02 21:07:00,696 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-02 21:07:00,721 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-02 21:07:00,751 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Forceful destruction successful, exit code 0 [2022-11-02 21:07:00,751 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-02 21:07:00,751 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:07:00,752 INFO L229 MonitoredProcess]: Starting monitored process 27 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-02 21:07:00,753 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Waiting until timeout for monitored process [2022-11-02 21:07:00,755 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-02 21:07:00,766 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-02 21:07:00,766 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-02 21:07:00,767 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-02 21:07:00,767 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-02 21:07:00,767 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-02 21:07:00,767 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-02 21:07:00,767 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-02 21:07:00,769 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-02 21:07:00,797 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Forceful destruction successful, exit code 0 [2022-11-02 21:07:00,797 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-02 21:07:00,798 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:07:00,799 INFO L229 MonitoredProcess]: Starting monitored process 28 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-02 21:07:00,800 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (28)] Waiting until timeout for monitored process [2022-11-02 21:07:00,801 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-02 21:07:00,814 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-02 21:07:00,814 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-02 21:07:00,814 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-02 21:07:00,814 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-02 21:07:00,814 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-02 21:07:00,814 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-02 21:07:00,815 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-02 21:07:00,816 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-02 21:07:00,841 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (28)] Forceful destruction successful, exit code 0 [2022-11-02 21:07:00,845 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-02 21:07:00,846 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:07:00,847 INFO L229 MonitoredProcess]: Starting monitored process 29 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-02 21:07:00,857 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Waiting until timeout for monitored process [2022-11-02 21:07:00,858 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-02 21:07:00,873 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-02 21:07:00,873 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-02 21:07:00,873 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-02 21:07:00,873 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-02 21:07:00,873 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-02 21:07:00,874 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-02 21:07:00,874 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-02 21:07:00,883 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-02 21:07:00,910 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Forceful destruction successful, exit code 0 [2022-11-02 21:07:00,911 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-02 21:07:00,911 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:07:00,912 INFO L229 MonitoredProcess]: Starting monitored process 30 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-02 21:07:00,913 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (30)] Waiting until timeout for monitored process [2022-11-02 21:07:00,914 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-02 21:07:00,926 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-02 21:07:00,926 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-02 21:07:00,926 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-02 21:07:00,926 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-02 21:07:00,926 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-02 21:07:00,926 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-02 21:07:00,927 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-02 21:07:00,928 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-02 21:07:00,953 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (30)] Forceful destruction successful, exit code 0 [2022-11-02 21:07:00,954 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-02 21:07:00,954 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:07:00,955 INFO L229 MonitoredProcess]: Starting monitored process 31 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-02 21:07:00,956 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (31)] Waiting until timeout for monitored process [2022-11-02 21:07:00,958 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-02 21:07:00,970 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-02 21:07:00,970 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-02 21:07:00,970 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-02 21:07:00,970 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-02 21:07:00,975 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-02 21:07:00,975 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-02 21:07:00,982 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-02 21:07:01,012 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (31)] Forceful destruction successful, exit code 0 [2022-11-02 21:07:01,013 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-02 21:07:01,013 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:07:01,014 INFO L229 MonitoredProcess]: Starting monitored process 32 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-02 21:07:01,015 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (32)] Waiting until timeout for monitored process [2022-11-02 21:07:01,016 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-02 21:07:01,029 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-02 21:07:01,029 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-02 21:07:01,029 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-02 21:07:01,029 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-02 21:07:01,041 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-02 21:07:01,041 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-02 21:07:01,057 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2022-11-02 21:07:01,088 INFO L443 ModelExtractionUtils]: Simplification made 10 calls to the SMT solver. [2022-11-02 21:07:01,089 INFO L444 ModelExtractionUtils]: 10 out of 25 variables were initially zero. Simplification set additionally 11 variables to zero. [2022-11-02 21:07:01,089 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-02 21:07:01,089 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:07:01,096 INFO L229 MonitoredProcess]: Starting monitored process 33 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-02 21:07:01,103 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2022-11-02 21:07:01,138 INFO L438 nArgumentSynthesizer]: Removed 1 redundant supporting invariants from a total of 2. [2022-11-02 21:07:01,138 INFO L513 LassoAnalysis]: Proved termination. [2022-11-02 21:07:01,138 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(v_rep(select #length ULTIMATE.start_main_~arr~0#1.base)_2, ULTIMATE.start_main_~j~0#1) = 1*v_rep(select #length ULTIMATE.start_main_~arr~0#1.base)_2 - 2*ULTIMATE.start_main_~j~0#1 Supporting invariants [1*ULTIMATE.start_main_~arr~0#1.offset >= 0] [2022-11-02 21:07:01,149 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (33)] Waiting until timeout for monitored process [2022-11-02 21:07:01,187 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (32)] Forceful destruction successful, exit code 0 [2022-11-02 21:07:01,215 INFO L156 tatePredicateManager]: 6 out of 7 supporting invariants were superfluous and have been removed [2022-11-02 21:07:01,247 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:07:01,282 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 21:07:01,283 INFO L263 TraceCheckSpWp]: Trace formula consists of 83 conjuncts, 4 conjunts are in the unsatisfiable core [2022-11-02 21:07:01,284 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 21:07:01,359 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 21:07:01,359 INFO L263 TraceCheckSpWp]: Trace formula consists of 14 conjuncts, 6 conjunts are in the unsatisfiable core [2022-11-02 21:07:01,360 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 21:07:01,389 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:07:01,389 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.2 stem predicates 2 loop predicates [2022-11-02 21:07:01,390 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 37 states and 49 transitions. cyclomatic complexity: 16 Second operand has 4 states, 4 states have (on average 3.25) internal successors, (13), 4 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:07:01,432 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 37 states and 49 transitions. cyclomatic complexity: 16. Second operand has 4 states, 4 states have (on average 3.25) internal successors, (13), 4 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 45 states and 60 transitions. Complement of second has 6 states. [2022-11-02 21:07:01,433 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 4 states 2 stem states 1 non-accepting loop states 1 accepting loop states [2022-11-02 21:07:01,433 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4 states, 4 states have (on average 3.25) internal successors, (13), 4 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:07:01,434 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 13 transitions. [2022-11-02 21:07:01,434 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 13 transitions. Stem has 16 letters. Loop has 2 letters. [2022-11-02 21:07:01,434 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-02 21:07:01,434 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 13 transitions. Stem has 18 letters. Loop has 2 letters. [2022-11-02 21:07:01,435 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-02 21:07:01,435 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 13 transitions. Stem has 16 letters. Loop has 4 letters. [2022-11-02 21:07:01,435 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-02 21:07:01,435 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 45 states and 60 transitions. [2022-11-02 21:07:01,436 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:07:01,437 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 45 states to 38 states and 50 transitions. [2022-11-02 21:07:01,437 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12 [2022-11-02 21:07:01,437 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-02 21:07:01,437 INFO L73 IsDeterministic]: Start isDeterministic. Operand 38 states and 50 transitions. [2022-11-02 21:07:01,437 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-02 21:07:01,438 INFO L218 hiAutomatonCegarLoop]: Abstraction has 38 states and 50 transitions. [2022-11-02 21:07:01,438 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38 states and 50 transitions. [2022-11-02 21:07:01,439 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38 to 37. [2022-11-02 21:07:01,440 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 37 states, 37 states have (on average 1.3243243243243243) internal successors, (49), 36 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:07:01,440 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37 states to 37 states and 49 transitions. [2022-11-02 21:07:01,440 INFO L240 hiAutomatonCegarLoop]: Abstraction has 37 states and 49 transitions. [2022-11-02 21:07:01,441 INFO L428 stractBuchiCegarLoop]: Abstraction has 37 states and 49 transitions. [2022-11-02 21:07:01,441 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-11-02 21:07:01,441 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 37 states and 49 transitions. [2022-11-02 21:07:01,441 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:07:01,442 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 21:07:01,442 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 21:07:01,442 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [3, 3, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 21:07:01,442 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-02 21:07:01,443 INFO L748 eck$LassoCheckResult]: Stem: 2177#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 2178#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 2188#L367 assume !(main_~length~0#1 < 1); 2179#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 2180#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 2181#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2189#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 2192#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2190#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2191#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 2213#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2212#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2210#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 2211#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2200#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 2199#L370-4 main_~j~0#1 := 0; 2198#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2197#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2193#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2184#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2185#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2182#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 2183#L378-2 [2022-11-02 21:07:01,443 INFO L750 eck$LassoCheckResult]: Loop: 2183#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2196#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 2183#L378-2 [2022-11-02 21:07:01,443 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:07:01,443 INFO L85 PathProgramCache]: Analyzing trace with hash -1621025751, now seen corresponding path program 4 times [2022-11-02 21:07:01,444 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:07:01,444 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1168494053] [2022-11-02 21:07:01,444 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:07:01,444 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:07:01,456 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 21:07:01,728 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:07:01,728 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 21:07:01,728 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1168494053] [2022-11-02 21:07:01,728 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1168494053] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 21:07:01,728 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [420700961] [2022-11-02 21:07:01,729 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-02 21:07:01,729 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 21:07:01,729 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:07:01,731 INFO L229 MonitoredProcess]: Starting monitored process 34 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 21:07:01,740 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (34)] Waiting until timeout for monitored process [2022-11-02 21:07:01,825 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-02 21:07:01,825 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-02 21:07:01,826 INFO L263 TraceCheckSpWp]: Trace formula consists of 92 conjuncts, 18 conjunts are in the unsatisfiable core [2022-11-02 21:07:01,831 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 21:07:01,863 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-02 21:07:02,013 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2022-11-02 21:07:02,016 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:07:02,016 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 21:07:02,115 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 14 [2022-11-02 21:07:02,121 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 20 [2022-11-02 21:07:02,156 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:07:02,156 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [420700961] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 21:07:02,156 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 21:07:02,156 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 10, 10] total 16 [2022-11-02 21:07:02,157 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1043663212] [2022-11-02 21:07:02,157 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 21:07:02,158 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-02 21:07:02,159 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:07:02,159 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 12 times [2022-11-02 21:07:02,159 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:07:02,159 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [678550003] [2022-11-02 21:07:02,159 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:07:02,159 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:07:02,164 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:07:02,164 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:07:02,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:07:02,170 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:07:02,223 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 21:07:02,226 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2022-11-02 21:07:02,226 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=48, Invalid=224, Unknown=0, NotChecked=0, Total=272 [2022-11-02 21:07:02,226 INFO L87 Difference]: Start difference. First operand 37 states and 49 transitions. cyclomatic complexity: 16 Second operand has 17 states, 16 states have (on average 2.125) internal successors, (34), 17 states have internal predecessors, (34), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:07:02,441 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 21:07:02,441 INFO L93 Difference]: Finished difference Result 64 states and 83 transitions. [2022-11-02 21:07:02,441 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 64 states and 83 transitions. [2022-11-02 21:07:02,442 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 8 [2022-11-02 21:07:02,442 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 64 states to 63 states and 82 transitions. [2022-11-02 21:07:02,443 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27 [2022-11-02 21:07:02,443 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27 [2022-11-02 21:07:02,443 INFO L73 IsDeterministic]: Start isDeterministic. Operand 63 states and 82 transitions. [2022-11-02 21:07:02,443 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-02 21:07:02,443 INFO L218 hiAutomatonCegarLoop]: Abstraction has 63 states and 82 transitions. [2022-11-02 21:07:02,443 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 63 states and 82 transitions. [2022-11-02 21:07:02,480 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 63 to 55. [2022-11-02 21:07:02,480 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 55 states, 55 states have (on average 1.309090909090909) internal successors, (72), 54 states have internal predecessors, (72), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:07:02,481 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55 states to 55 states and 72 transitions. [2022-11-02 21:07:02,481 INFO L240 hiAutomatonCegarLoop]: Abstraction has 55 states and 72 transitions. [2022-11-02 21:07:02,489 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2022-11-02 21:07:02,490 INFO L428 stractBuchiCegarLoop]: Abstraction has 55 states and 72 transitions. [2022-11-02 21:07:02,490 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-11-02 21:07:02,490 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 55 states and 72 transitions. [2022-11-02 21:07:02,491 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6 [2022-11-02 21:07:02,491 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 21:07:02,491 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 21:07:02,491 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 4, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 21:07:02,492 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-02 21:07:02,492 INFO L748 eck$LassoCheckResult]: Stem: 2426#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 2427#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 2437#L367 assume !(main_~length~0#1 < 1); 2428#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 2429#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 2430#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2438#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 2452#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2456#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2455#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 2454#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2453#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2451#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2446#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2439#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2440#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2470#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2477#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 2475#L370-4 main_~j~0#1 := 0; 2473#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2472#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2471#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2457#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 2434#L378-2 [2022-11-02 21:07:02,492 INFO L750 eck$LassoCheckResult]: Loop: 2434#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2444#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 2434#L378-2 [2022-11-02 21:07:02,492 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:07:02,492 INFO L85 PathProgramCache]: Analyzing trace with hash 775133342, now seen corresponding path program 4 times [2022-11-02 21:07:02,493 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:07:02,493 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [293422266] [2022-11-02 21:07:02,493 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:07:02,493 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:07:02,532 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 21:07:02,590 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (33)] Forceful destruction successful, exit code 0 [2022-11-02 21:07:02,980 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 24 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:07:02,980 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 21:07:02,981 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [293422266] [2022-11-02 21:07:02,981 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [293422266] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 21:07:02,981 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2004546576] [2022-11-02 21:07:02,981 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-02 21:07:02,981 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 21:07:02,981 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:07:02,986 INFO L229 MonitoredProcess]: Starting monitored process 35 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 21:07:02,995 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (35)] Waiting until timeout for monitored process [2022-11-02 21:07:03,082 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-02 21:07:03,082 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-02 21:07:03,084 INFO L263 TraceCheckSpWp]: Trace formula consists of 111 conjuncts, 24 conjunts are in the unsatisfiable core [2022-11-02 21:07:03,088 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 21:07:03,105 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-02 21:07:03,186 INFO L356 Elim1Store]: treesize reduction 23, result has 28.1 percent of original size [2022-11-02 21:07:03,186 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2022-11-02 21:07:03,208 INFO L356 Elim1Store]: treesize reduction 23, result has 28.1 percent of original size [2022-11-02 21:07:03,209 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2022-11-02 21:07:03,246 INFO L356 Elim1Store]: treesize reduction 23, result has 28.1 percent of original size [2022-11-02 21:07:03,247 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2022-11-02 21:07:03,267 INFO L356 Elim1Store]: treesize reduction 23, result has 28.1 percent of original size [2022-11-02 21:07:03,268 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2022-11-02 21:07:03,326 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2022-11-02 21:07:03,328 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 2 proven. 22 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:07:03,328 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 21:07:03,567 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 19 [2022-11-02 21:07:03,571 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 25 [2022-11-02 21:07:03,600 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 1 proven. 22 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-02 21:07:03,600 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2004546576] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 21:07:03,600 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 21:07:03,600 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11, 11] total 17 [2022-11-02 21:07:03,601 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2030032113] [2022-11-02 21:07:03,601 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 21:07:03,601 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-02 21:07:03,601 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:07:03,601 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 13 times [2022-11-02 21:07:03,602 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:07:03,602 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1761930855] [2022-11-02 21:07:03,602 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:07:03,602 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:07:03,606 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:07:03,607 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:07:03,608 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:07:03,610 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:07:03,665 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 21:07:03,666 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2022-11-02 21:07:03,666 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=58, Invalid=248, Unknown=0, NotChecked=0, Total=306 [2022-11-02 21:07:03,666 INFO L87 Difference]: Start difference. First operand 55 states and 72 transitions. cyclomatic complexity: 23 Second operand has 18 states, 17 states have (on average 2.235294117647059) internal successors, (38), 18 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:07:03,893 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 21:07:03,893 INFO L93 Difference]: Finished difference Result 55 states and 69 transitions. [2022-11-02 21:07:03,893 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 55 states and 69 transitions. [2022-11-02 21:07:03,894 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:07:03,894 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 55 states to 53 states and 67 transitions. [2022-11-02 21:07:03,894 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17 [2022-11-02 21:07:03,895 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17 [2022-11-02 21:07:03,895 INFO L73 IsDeterministic]: Start isDeterministic. Operand 53 states and 67 transitions. [2022-11-02 21:07:03,895 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-02 21:07:03,895 INFO L218 hiAutomatonCegarLoop]: Abstraction has 53 states and 67 transitions. [2022-11-02 21:07:03,895 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53 states and 67 transitions. [2022-11-02 21:07:03,896 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53 to 34. [2022-11-02 21:07:03,897 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 34 states, 34 states have (on average 1.2647058823529411) internal successors, (43), 33 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:07:03,897 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34 states to 34 states and 43 transitions. [2022-11-02 21:07:03,897 INFO L240 hiAutomatonCegarLoop]: Abstraction has 34 states and 43 transitions. [2022-11-02 21:07:03,898 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2022-11-02 21:07:03,898 INFO L428 stractBuchiCegarLoop]: Abstraction has 34 states and 43 transitions. [2022-11-02 21:07:03,898 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-11-02 21:07:03,899 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 34 states and 43 transitions. [2022-11-02 21:07:03,899 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:07:03,899 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 21:07:03,899 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 21:07:03,900 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 21:07:03,900 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-02 21:07:03,900 INFO L748 eck$LassoCheckResult]: Stem: 2695#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 2696#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 2706#L367 assume !(main_~length~0#1 < 1); 2697#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 2698#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 2699#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2707#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 2728#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2708#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2709#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 2712#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2713#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2727#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 2724#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2718#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 2704#L370-4 main_~j~0#1 := 0; 2705#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2702#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2703#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2711#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2717#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2715#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2714#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2700#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 2701#L378-2 [2022-11-02 21:07:03,900 INFO L750 eck$LassoCheckResult]: Loop: 2701#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2716#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 2701#L378-2 [2022-11-02 21:07:03,901 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:07:03,901 INFO L85 PathProgramCache]: Analyzing trace with hash 1267385006, now seen corresponding path program 5 times [2022-11-02 21:07:03,901 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:07:03,901 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [42709051] [2022-11-02 21:07:03,901 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:07:03,901 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:07:03,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 21:07:04,044 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 7 proven. 17 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:07:04,044 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 21:07:04,044 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [42709051] [2022-11-02 21:07:04,044 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [42709051] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 21:07:04,044 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1056595176] [2022-11-02 21:07:04,045 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-02 21:07:04,045 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 21:07:04,045 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:07:04,051 INFO L229 MonitoredProcess]: Starting monitored process 36 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 21:07:04,053 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (36)] Waiting until timeout for monitored process [2022-11-02 21:07:04,151 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 4 check-sat command(s) [2022-11-02 21:07:04,152 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-02 21:07:04,153 INFO L263 TraceCheckSpWp]: Trace formula consists of 119 conjuncts, 10 conjunts are in the unsatisfiable core [2022-11-02 21:07:04,154 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 21:07:04,282 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 12 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:07:04,282 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 21:07:04,384 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 9 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:07:04,384 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1056595176] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 21:07:04,384 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 21:07:04,385 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11, 11] total 17 [2022-11-02 21:07:04,385 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [18902215] [2022-11-02 21:07:04,385 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 21:07:04,385 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-02 21:07:04,385 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:07:04,385 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 14 times [2022-11-02 21:07:04,386 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:07:04,386 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [699399480] [2022-11-02 21:07:04,386 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:07:04,386 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:07:04,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:07:04,389 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:07:04,391 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:07:04,392 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:07:04,447 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 21:07:04,448 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2022-11-02 21:07:04,448 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=70, Invalid=202, Unknown=0, NotChecked=0, Total=272 [2022-11-02 21:07:04,448 INFO L87 Difference]: Start difference. First operand 34 states and 43 transitions. cyclomatic complexity: 13 Second operand has 17 states, 17 states have (on average 2.235294117647059) internal successors, (38), 17 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:07:04,592 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 21:07:04,592 INFO L93 Difference]: Finished difference Result 47 states and 57 transitions. [2022-11-02 21:07:04,592 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 47 states and 57 transitions. [2022-11-02 21:07:04,593 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:07:04,593 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 47 states to 39 states and 49 transitions. [2022-11-02 21:07:04,593 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-02 21:07:04,593 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-02 21:07:04,594 INFO L73 IsDeterministic]: Start isDeterministic. Operand 39 states and 49 transitions. [2022-11-02 21:07:04,594 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-02 21:07:04,594 INFO L218 hiAutomatonCegarLoop]: Abstraction has 39 states and 49 transitions. [2022-11-02 21:07:04,594 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39 states and 49 transitions. [2022-11-02 21:07:04,595 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39 to 34. [2022-11-02 21:07:04,595 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 34 states, 34 states have (on average 1.2647058823529411) internal successors, (43), 33 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:07:04,596 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34 states to 34 states and 43 transitions. [2022-11-02 21:07:04,596 INFO L240 hiAutomatonCegarLoop]: Abstraction has 34 states and 43 transitions. [2022-11-02 21:07:04,602 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2022-11-02 21:07:04,603 INFO L428 stractBuchiCegarLoop]: Abstraction has 34 states and 43 transitions. [2022-11-02 21:07:04,603 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-11-02 21:07:04,603 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 34 states and 43 transitions. [2022-11-02 21:07:04,603 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:07:04,603 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 21:07:04,604 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 21:07:04,604 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 4, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 21:07:04,604 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-02 21:07:04,604 INFO L748 eck$LassoCheckResult]: Stem: 2944#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 2945#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 2955#L367 assume !(main_~length~0#1 < 1); 2946#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 2947#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 2948#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2956#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 2977#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2957#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2958#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 2959#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2961#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2976#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 2975#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2974#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2971#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2973#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2962#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 2963#L370-4 main_~j~0#1 := 0; 2969#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2960#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2968#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2966#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2965#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2951#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 2952#L378-2 [2022-11-02 21:07:04,604 INFO L750 eck$LassoCheckResult]: Loop: 2952#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2967#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 2952#L378-2 [2022-11-02 21:07:04,605 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:07:04,605 INFO L85 PathProgramCache]: Analyzing trace with hash 1286996709, now seen corresponding path program 5 times [2022-11-02 21:07:04,605 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:07:04,605 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1792327928] [2022-11-02 21:07:04,605 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:07:04,605 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:07:04,632 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 21:07:05,016 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:07:05,016 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 21:07:05,016 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1792327928] [2022-11-02 21:07:05,016 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1792327928] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 21:07:05,016 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2068397445] [2022-11-02 21:07:05,016 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-02 21:07:05,017 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 21:07:05,017 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:07:05,023 INFO L229 MonitoredProcess]: Starting monitored process 37 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 21:07:05,032 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (37)] Waiting until timeout for monitored process [2022-11-02 21:07:05,143 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 5 check-sat command(s) [2022-11-02 21:07:05,144 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-02 21:07:05,145 INFO L263 TraceCheckSpWp]: Trace formula consists of 130 conjuncts, 25 conjunts are in the unsatisfiable core [2022-11-02 21:07:05,147 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 21:07:05,304 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-02 21:07:05,478 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-02 21:07:05,481 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 26 [2022-11-02 21:07:05,516 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-02 21:07:05,517 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 26 [2022-11-02 21:07:05,924 INFO L173 IndexEqualityManager]: detected equality via solver [2022-11-02 21:07:05,927 INFO L356 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-02 21:07:05,928 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 10 [2022-11-02 21:07:05,933 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:07:05,933 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 21:07:06,231 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 19 [2022-11-02 21:07:06,240 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 25 [2022-11-02 21:07:06,333 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:07:06,333 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2068397445] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 21:07:06,333 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 21:07:06,333 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 15, 15] total 31 [2022-11-02 21:07:06,334 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2134855017] [2022-11-02 21:07:06,334 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 21:07:06,334 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-02 21:07:06,334 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:07:06,334 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 15 times [2022-11-02 21:07:06,335 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:07:06,335 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1857165047] [2022-11-02 21:07:06,335 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:07:06,335 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:07:06,338 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:07:06,338 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:07:06,340 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:07:06,341 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:07:06,398 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 21:07:06,398 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2022-11-02 21:07:06,399 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=137, Invalid=855, Unknown=0, NotChecked=0, Total=992 [2022-11-02 21:07:06,399 INFO L87 Difference]: Start difference. First operand 34 states and 43 transitions. cyclomatic complexity: 13 Second operand has 32 states, 31 states have (on average 1.7741935483870968) internal successors, (55), 32 states have internal predecessors, (55), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:07:06,706 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 21:07:06,706 INFO L93 Difference]: Finished difference Result 70 states and 86 transitions. [2022-11-02 21:07:06,706 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 70 states and 86 transitions. [2022-11-02 21:07:06,707 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:07:06,707 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 70 states to 69 states and 84 transitions. [2022-11-02 21:07:06,707 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21 [2022-11-02 21:07:06,708 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21 [2022-11-02 21:07:06,708 INFO L73 IsDeterministic]: Start isDeterministic. Operand 69 states and 84 transitions. [2022-11-02 21:07:06,708 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-02 21:07:06,708 INFO L218 hiAutomatonCegarLoop]: Abstraction has 69 states and 84 transitions. [2022-11-02 21:07:06,708 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69 states and 84 transitions. [2022-11-02 21:07:06,710 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69 to 40. [2022-11-02 21:07:06,710 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 40 states, 40 states have (on average 1.325) internal successors, (53), 39 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:07:06,710 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40 states to 40 states and 53 transitions. [2022-11-02 21:07:06,710 INFO L240 hiAutomatonCegarLoop]: Abstraction has 40 states and 53 transitions. [2022-11-02 21:07:06,711 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2022-11-02 21:07:06,711 INFO L428 stractBuchiCegarLoop]: Abstraction has 40 states and 53 transitions. [2022-11-02 21:07:06,712 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2022-11-02 21:07:06,712 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 40 states and 53 transitions. [2022-11-02 21:07:06,712 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:07:06,712 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 21:07:06,712 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 21:07:06,713 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 4, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 21:07:06,713 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-02 21:07:06,713 INFO L748 eck$LassoCheckResult]: Stem: 3234#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 3235#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 3245#L367 assume !(main_~length~0#1 < 1); 3236#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 3237#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 3238#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3246#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 3273#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3247#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3248#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 3250#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3251#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3272#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 3271#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3270#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3269#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3265#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3264#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 3239#L370-4 main_~j~0#1 := 0; 3240#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3243#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 3244#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3249#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 3255#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3253#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 3252#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3241#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 3242#L378-2 [2022-11-02 21:07:06,714 INFO L750 eck$LassoCheckResult]: Loop: 3242#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3254#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 3242#L378-2 [2022-11-02 21:07:06,714 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:07:06,714 INFO L85 PathProgramCache]: Analyzing trace with hash -146740630, now seen corresponding path program 6 times [2022-11-02 21:07:06,714 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:07:06,715 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1752558415] [2022-11-02 21:07:06,715 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:07:06,715 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:07:06,728 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 21:07:07,047 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 0 proven. 34 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:07:07,048 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 21:07:07,048 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1752558415] [2022-11-02 21:07:07,048 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1752558415] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 21:07:07,048 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [78714459] [2022-11-02 21:07:07,048 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-11-02 21:07:07,048 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 21:07:07,048 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:07:07,051 INFO L229 MonitoredProcess]: Starting monitored process 38 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 21:07:07,073 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (38)] Waiting until timeout for monitored process [2022-11-02 21:07:07,169 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 5 check-sat command(s) [2022-11-02 21:07:07,169 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-02 21:07:07,171 INFO L263 TraceCheckSpWp]: Trace formula consists of 141 conjuncts, 16 conjunts are in the unsatisfiable core [2022-11-02 21:07:07,173 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 21:07:07,258 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-02 21:07:07,658 INFO L356 Elim1Store]: treesize reduction 9, result has 25.0 percent of original size [2022-11-02 21:07:07,658 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 10 [2022-11-02 21:07:07,687 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 9 proven. 25 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:07:07,687 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 21:07:08,176 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2022-11-02 21:07:08,184 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 28 [2022-11-02 21:07:08,273 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 6 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:07:08,273 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [78714459] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 21:07:08,273 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 21:07:08,273 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 13, 13] total 31 [2022-11-02 21:07:08,273 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [424659829] [2022-11-02 21:07:08,273 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 21:07:08,274 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-02 21:07:08,274 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:07:08,274 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 16 times [2022-11-02 21:07:08,274 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:07:08,274 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [872609259] [2022-11-02 21:07:08,274 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:07:08,275 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:07:08,277 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:07:08,278 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:07:08,279 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:07:08,280 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:07:08,335 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 21:07:08,335 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2022-11-02 21:07:08,336 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=135, Invalid=857, Unknown=0, NotChecked=0, Total=992 [2022-11-02 21:07:08,336 INFO L87 Difference]: Start difference. First operand 40 states and 53 transitions. cyclomatic complexity: 17 Second operand has 32 states, 31 states have (on average 1.967741935483871) internal successors, (61), 32 states have internal predecessors, (61), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:07:08,932 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 21:07:08,932 INFO L93 Difference]: Finished difference Result 61 states and 75 transitions. [2022-11-02 21:07:08,932 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 61 states and 75 transitions. [2022-11-02 21:07:08,933 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:07:08,933 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 61 states to 48 states and 61 transitions. [2022-11-02 21:07:08,934 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-02 21:07:08,934 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-02 21:07:08,934 INFO L73 IsDeterministic]: Start isDeterministic. Operand 48 states and 61 transitions. [2022-11-02 21:07:08,934 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-02 21:07:08,934 INFO L218 hiAutomatonCegarLoop]: Abstraction has 48 states and 61 transitions. [2022-11-02 21:07:08,934 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 48 states and 61 transitions. [2022-11-02 21:07:08,935 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 48 to 42. [2022-11-02 21:07:08,936 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 42 states, 42 states have (on average 1.3095238095238095) internal successors, (55), 41 states have internal predecessors, (55), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:07:08,936 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42 states to 42 states and 55 transitions. [2022-11-02 21:07:08,936 INFO L240 hiAutomatonCegarLoop]: Abstraction has 42 states and 55 transitions. [2022-11-02 21:07:08,936 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2022-11-02 21:07:08,937 INFO L428 stractBuchiCegarLoop]: Abstraction has 42 states and 55 transitions. [2022-11-02 21:07:08,937 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2022-11-02 21:07:08,937 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 42 states and 55 transitions. [2022-11-02 21:07:08,937 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:07:08,937 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 21:07:08,938 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 21:07:08,938 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 4, 4, 4, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 21:07:08,938 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-02 21:07:08,938 INFO L748 eck$LassoCheckResult]: Stem: 3557#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 3558#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 3568#L367 assume !(main_~length~0#1 < 1); 3559#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 3560#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 3561#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3569#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 3573#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3570#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3571#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 3598#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3597#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3596#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 3595#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3594#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3592#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 3593#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3582#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 3579#L370-4 main_~j~0#1 := 0; 3578#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3577#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 3572#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3564#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 3565#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3575#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 3574#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3562#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 3563#L378-2 [2022-11-02 21:07:08,938 INFO L750 eck$LassoCheckResult]: Loop: 3563#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3576#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 3563#L378-2 [2022-11-02 21:07:08,939 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:07:08,939 INFO L85 PathProgramCache]: Analyzing trace with hash 111424808, now seen corresponding path program 6 times [2022-11-02 21:07:08,939 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:07:08,939 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [212917139] [2022-11-02 21:07:08,939 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:07:08,939 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:07:08,952 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 21:07:09,277 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 0 proven. 34 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:07:09,277 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 21:07:09,277 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [212917139] [2022-11-02 21:07:09,277 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [212917139] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 21:07:09,277 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [424518002] [2022-11-02 21:07:09,277 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-11-02 21:07:09,278 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 21:07:09,278 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:07:09,280 INFO L229 MonitoredProcess]: Starting monitored process 39 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 21:07:09,282 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (39)] Waiting until timeout for monitored process [2022-11-02 21:07:09,395 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 5 check-sat command(s) [2022-11-02 21:07:09,395 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-02 21:07:09,397 INFO L263 TraceCheckSpWp]: Trace formula consists of 133 conjuncts, 17 conjunts are in the unsatisfiable core [2022-11-02 21:07:09,398 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 21:07:09,490 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-02 21:07:09,895 INFO L356 Elim1Store]: treesize reduction 9, result has 25.0 percent of original size [2022-11-02 21:07:09,896 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 10 [2022-11-02 21:07:09,900 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 9 proven. 25 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:07:09,900 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 21:07:10,459 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2022-11-02 21:07:10,465 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 28 [2022-11-02 21:07:10,554 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 6 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:07:10,554 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [424518002] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 21:07:10,554 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 21:07:10,554 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 14, 14] total 33 [2022-11-02 21:07:10,555 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1701696575] [2022-11-02 21:07:10,555 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 21:07:10,555 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-02 21:07:10,555 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:07:10,556 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 17 times [2022-11-02 21:07:10,556 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:07:10,556 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1377535036] [2022-11-02 21:07:10,556 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:07:10,556 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:07:10,559 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:07:10,560 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:07:10,561 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:07:10,562 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:07:10,620 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 21:07:10,621 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2022-11-02 21:07:10,621 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=155, Invalid=967, Unknown=0, NotChecked=0, Total=1122 [2022-11-02 21:07:10,622 INFO L87 Difference]: Start difference. First operand 42 states and 55 transitions. cyclomatic complexity: 17 Second operand has 34 states, 33 states have (on average 1.8484848484848484) internal successors, (61), 34 states have internal predecessors, (61), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:07:11,278 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 21:07:11,278 INFO L93 Difference]: Finished difference Result 68 states and 86 transitions. [2022-11-02 21:07:11,278 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 68 states and 86 transitions. [2022-11-02 21:07:11,282 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:07:11,282 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 68 states to 57 states and 73 transitions. [2022-11-02 21:07:11,283 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-02 21:07:11,283 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-02 21:07:11,283 INFO L73 IsDeterministic]: Start isDeterministic. Operand 57 states and 73 transitions. [2022-11-02 21:07:11,283 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-02 21:07:11,283 INFO L218 hiAutomatonCegarLoop]: Abstraction has 57 states and 73 transitions. [2022-11-02 21:07:11,284 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 57 states and 73 transitions. [2022-11-02 21:07:11,291 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 57 to 53. [2022-11-02 21:07:11,292 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 53 states, 53 states have (on average 1.3018867924528301) internal successors, (69), 52 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:07:11,296 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53 states to 53 states and 69 transitions. [2022-11-02 21:07:11,296 INFO L240 hiAutomatonCegarLoop]: Abstraction has 53 states and 69 transitions. [2022-11-02 21:07:11,297 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2022-11-02 21:07:11,299 INFO L428 stractBuchiCegarLoop]: Abstraction has 53 states and 69 transitions. [2022-11-02 21:07:11,299 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2022-11-02 21:07:11,299 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 53 states and 69 transitions. [2022-11-02 21:07:11,300 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:07:11,300 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 21:07:11,300 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 21:07:11,301 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 4, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 21:07:11,301 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-02 21:07:11,301 INFO L748 eck$LassoCheckResult]: Stem: 3895#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 3896#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 3906#L367 assume !(main_~length~0#1 < 1); 3897#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 3898#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 3899#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3907#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3946#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3947#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3910#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 3911#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3908#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3909#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 3936#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3934#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3931#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 3929#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3921#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 3920#L370-4 main_~j~0#1 := 0; 3912#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3904#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 3905#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3913#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 3919#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3918#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 3917#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3902#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 3903#L378-2 [2022-11-02 21:07:11,301 INFO L750 eck$LassoCheckResult]: Loop: 3903#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3916#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 3903#L378-2 [2022-11-02 21:07:11,302 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:07:11,302 INFO L85 PathProgramCache]: Analyzing trace with hash -311277018, now seen corresponding path program 7 times [2022-11-02 21:07:11,302 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:07:11,302 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1218817997] [2022-11-02 21:07:11,303 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:07:11,303 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:07:11,316 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 21:07:11,643 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 0 proven. 34 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:07:11,644 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 21:07:11,644 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1218817997] [2022-11-02 21:07:11,644 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1218817997] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 21:07:11,644 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1267406280] [2022-11-02 21:07:11,644 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-11-02 21:07:11,644 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 21:07:11,644 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:07:11,647 INFO L229 MonitoredProcess]: Starting monitored process 40 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 21:07:11,649 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (40)] Waiting until timeout for monitored process [2022-11-02 21:07:11,745 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 21:07:11,746 INFO L263 TraceCheckSpWp]: Trace formula consists of 141 conjuncts, 26 conjunts are in the unsatisfiable core [2022-11-02 21:07:11,748 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 21:07:11,891 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 9 [2022-11-02 21:07:12,138 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-02 21:07:12,147 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 0 proven. 34 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:07:12,147 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 21:07:12,265 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 14 [2022-11-02 21:07:12,268 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 20 [2022-11-02 21:07:12,307 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 0 proven. 34 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:07:12,307 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1267406280] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 21:07:12,307 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 21:07:12,307 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 12] total 26 [2022-11-02 21:07:12,307 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [966219556] [2022-11-02 21:07:12,307 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 21:07:12,308 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-02 21:07:12,308 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:07:12,308 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 18 times [2022-11-02 21:07:12,308 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:07:12,308 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1763747660] [2022-11-02 21:07:12,308 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:07:12,308 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:07:12,311 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:07:12,311 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:07:12,312 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:07:12,314 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:07:12,366 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 21:07:12,366 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2022-11-02 21:07:12,366 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=94, Invalid=608, Unknown=0, NotChecked=0, Total=702 [2022-11-02 21:07:12,367 INFO L87 Difference]: Start difference. First operand 53 states and 69 transitions. cyclomatic complexity: 20 Second operand has 27 states, 26 states have (on average 2.1538461538461537) internal successors, (56), 27 states have internal predecessors, (56), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:07:12,783 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 21:07:12,783 INFO L93 Difference]: Finished difference Result 86 states and 110 transitions. [2022-11-02 21:07:12,783 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 86 states and 110 transitions. [2022-11-02 21:07:12,784 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 10 [2022-11-02 21:07:12,784 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 86 states to 85 states and 109 transitions. [2022-11-02 21:07:12,784 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 29 [2022-11-02 21:07:12,785 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 29 [2022-11-02 21:07:12,785 INFO L73 IsDeterministic]: Start isDeterministic. Operand 85 states and 109 transitions. [2022-11-02 21:07:12,785 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-02 21:07:12,785 INFO L218 hiAutomatonCegarLoop]: Abstraction has 85 states and 109 transitions. [2022-11-02 21:07:12,785 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 85 states and 109 transitions. [2022-11-02 21:07:12,787 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 85 to 75. [2022-11-02 21:07:12,787 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 75 states, 75 states have (on average 1.2933333333333332) internal successors, (97), 74 states have internal predecessors, (97), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:07:12,787 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 75 states to 75 states and 97 transitions. [2022-11-02 21:07:12,788 INFO L240 hiAutomatonCegarLoop]: Abstraction has 75 states and 97 transitions. [2022-11-02 21:07:12,788 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2022-11-02 21:07:12,789 INFO L428 stractBuchiCegarLoop]: Abstraction has 75 states and 97 transitions. [2022-11-02 21:07:12,789 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2022-11-02 21:07:12,789 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 75 states and 97 transitions. [2022-11-02 21:07:12,790 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 8 [2022-11-02 21:07:12,790 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 21:07:12,790 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 21:07:12,791 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 5, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 21:07:12,791 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-02 21:07:12,791 INFO L748 eck$LassoCheckResult]: Stem: 4228#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 4229#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 4239#L367 assume !(main_~length~0#1 < 1); 4230#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 4231#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 4232#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4240#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4269#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4267#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4265#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 4263#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4261#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4259#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 4256#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4255#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4253#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4244#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4246#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4285#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4287#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4292#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 4290#L370-4 main_~j~0#1 := 0; 4288#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4273#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4278#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4275#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4276#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4277#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 4234#L378-2 [2022-11-02 21:07:12,791 INFO L750 eck$LassoCheckResult]: Loop: 4234#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4271#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 4234#L378-2 [2022-11-02 21:07:12,792 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:07:12,792 INFO L85 PathProgramCache]: Analyzing trace with hash 179920235, now seen corresponding path program 8 times [2022-11-02 21:07:12,792 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:07:12,792 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [211194102] [2022-11-02 21:07:12,792 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:07:12,793 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:07:12,807 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 21:07:13,347 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 0 proven. 41 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:07:13,348 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 21:07:13,348 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [211194102] [2022-11-02 21:07:13,348 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [211194102] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 21:07:13,348 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [804741055] [2022-11-02 21:07:13,348 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-02 21:07:13,348 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 21:07:13,348 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:07:13,351 INFO L229 MonitoredProcess]: Starting monitored process 41 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 21:07:13,384 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (41)] Waiting until timeout for monitored process [2022-11-02 21:07:13,473 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-02 21:07:13,473 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-02 21:07:13,475 INFO L263 TraceCheckSpWp]: Trace formula consists of 160 conjuncts, 28 conjunts are in the unsatisfiable core [2022-11-02 21:07:13,477 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 21:07:13,509 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-02 21:07:13,588 INFO L356 Elim1Store]: treesize reduction 23, result has 28.1 percent of original size [2022-11-02 21:07:13,589 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2022-11-02 21:07:13,610 INFO L356 Elim1Store]: treesize reduction 23, result has 28.1 percent of original size [2022-11-02 21:07:13,610 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2022-11-02 21:07:13,652 INFO L356 Elim1Store]: treesize reduction 23, result has 28.1 percent of original size [2022-11-02 21:07:13,653 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2022-11-02 21:07:13,677 INFO L356 Elim1Store]: treesize reduction 23, result has 28.1 percent of original size [2022-11-02 21:07:13,678 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2022-11-02 21:07:13,754 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2022-11-02 21:07:13,756 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 2 proven. 39 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:07:13,757 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 21:07:14,044 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 19 [2022-11-02 21:07:14,048 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 25 [2022-11-02 21:07:14,084 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 1 proven. 39 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-02 21:07:14,084 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [804741055] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 21:07:14,084 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 21:07:14,084 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13] total 20 [2022-11-02 21:07:14,085 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [294435978] [2022-11-02 21:07:14,085 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 21:07:14,085 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-02 21:07:14,085 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:07:14,086 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 19 times [2022-11-02 21:07:14,086 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:07:14,086 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1496559281] [2022-11-02 21:07:14,086 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:07:14,086 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:07:14,089 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:07:14,093 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:07:14,096 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:07:14,099 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:07:14,149 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 21:07:14,149 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2022-11-02 21:07:14,150 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=354, Unknown=0, NotChecked=0, Total=420 [2022-11-02 21:07:14,150 INFO L87 Difference]: Start difference. First operand 75 states and 97 transitions. cyclomatic complexity: 28 Second operand has 21 states, 20 states have (on average 2.25) internal successors, (45), 21 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:07:14,443 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 21:07:14,444 INFO L93 Difference]: Finished difference Result 77 states and 95 transitions. [2022-11-02 21:07:14,444 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 77 states and 95 transitions. [2022-11-02 21:07:14,444 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:07:14,445 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 77 states to 75 states and 93 transitions. [2022-11-02 21:07:14,445 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17 [2022-11-02 21:07:14,445 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17 [2022-11-02 21:07:14,445 INFO L73 IsDeterministic]: Start isDeterministic. Operand 75 states and 93 transitions. [2022-11-02 21:07:14,446 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-02 21:07:14,446 INFO L218 hiAutomatonCegarLoop]: Abstraction has 75 states and 93 transitions. [2022-11-02 21:07:14,446 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 75 states and 93 transitions. [2022-11-02 21:07:14,447 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 75 to 48. [2022-11-02 21:07:14,448 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 48 states, 48 states have (on average 1.2708333333333333) internal successors, (61), 47 states have internal predecessors, (61), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:07:14,448 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48 states to 48 states and 61 transitions. [2022-11-02 21:07:14,448 INFO L240 hiAutomatonCegarLoop]: Abstraction has 48 states and 61 transitions. [2022-11-02 21:07:14,448 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2022-11-02 21:07:14,449 INFO L428 stractBuchiCegarLoop]: Abstraction has 48 states and 61 transitions. [2022-11-02 21:07:14,449 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2022-11-02 21:07:14,449 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 48 states and 61 transitions. [2022-11-02 21:07:14,449 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:07:14,450 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 21:07:14,450 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 21:07:14,450 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 4, 4, 4, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 21:07:14,450 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-02 21:07:14,451 INFO L748 eck$LassoCheckResult]: Stem: 4574#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 4575#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 4585#L367 assume !(main_~length~0#1 < 1); 4576#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 4577#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 4578#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4586#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4589#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4587#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4588#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 4619#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4617#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4615#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 4612#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4610#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4608#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 4605#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4597#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 4598#L370-4 main_~j~0#1 := 0; 4601#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4600#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4591#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4583#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4584#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4596#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4595#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4593#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4592#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4581#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 4582#L378-2 [2022-11-02 21:07:14,451 INFO L750 eck$LassoCheckResult]: Loop: 4582#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4594#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 4582#L378-2 [2022-11-02 21:07:14,451 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:07:14,451 INFO L85 PathProgramCache]: Analyzing trace with hash 1510499691, now seen corresponding path program 9 times [2022-11-02 21:07:14,451 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:07:14,452 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [392698234] [2022-11-02 21:07:14,452 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:07:14,452 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:07:14,477 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 21:07:14,645 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 13 proven. 29 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:07:14,645 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 21:07:14,646 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [392698234] [2022-11-02 21:07:14,646 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [392698234] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 21:07:14,646 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [190710850] [2022-11-02 21:07:14,646 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-02 21:07:14,646 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 21:07:14,647 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:07:14,649 INFO L229 MonitoredProcess]: Starting monitored process 42 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 21:07:14,681 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (42)] Waiting until timeout for monitored process [2022-11-02 21:07:14,803 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 5 check-sat command(s) [2022-11-02 21:07:14,804 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-02 21:07:14,805 INFO L263 TraceCheckSpWp]: Trace formula consists of 152 conjuncts, 12 conjunts are in the unsatisfiable core [2022-11-02 21:07:14,806 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 21:07:14,954 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 20 proven. 22 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:07:14,955 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 21:07:15,075 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 20 proven. 22 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:07:15,075 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [190710850] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 21:07:15,076 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 21:07:15,076 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13] total 20 [2022-11-02 21:07:15,076 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2019510671] [2022-11-02 21:07:15,076 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 21:07:15,077 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-02 21:07:15,078 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:07:15,078 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 20 times [2022-11-02 21:07:15,078 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:07:15,078 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [46341576] [2022-11-02 21:07:15,078 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:07:15,079 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:07:15,082 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:07:15,082 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:07:15,083 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:07:15,085 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:07:15,143 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 21:07:15,144 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2022-11-02 21:07:15,144 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=95, Invalid=285, Unknown=0, NotChecked=0, Total=380 [2022-11-02 21:07:15,145 INFO L87 Difference]: Start difference. First operand 48 states and 61 transitions. cyclomatic complexity: 17 Second operand has 20 states, 20 states have (on average 2.3) internal successors, (46), 20 states have internal predecessors, (46), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:07:15,333 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 21:07:15,333 INFO L93 Difference]: Finished difference Result 63 states and 77 transitions. [2022-11-02 21:07:15,333 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 63 states and 77 transitions. [2022-11-02 21:07:15,334 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:07:15,334 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 63 states to 53 states and 67 transitions. [2022-11-02 21:07:15,334 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-02 21:07:15,334 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-02 21:07:15,334 INFO L73 IsDeterministic]: Start isDeterministic. Operand 53 states and 67 transitions. [2022-11-02 21:07:15,335 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-02 21:07:15,335 INFO L218 hiAutomatonCegarLoop]: Abstraction has 53 states and 67 transitions. [2022-11-02 21:07:15,335 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53 states and 67 transitions. [2022-11-02 21:07:15,336 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53 to 39. [2022-11-02 21:07:15,336 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 39 states, 39 states have (on average 1.2564102564102564) internal successors, (49), 38 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:07:15,336 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39 states to 39 states and 49 transitions. [2022-11-02 21:07:15,336 INFO L240 hiAutomatonCegarLoop]: Abstraction has 39 states and 49 transitions. [2022-11-02 21:07:15,338 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2022-11-02 21:07:15,338 INFO L428 stractBuchiCegarLoop]: Abstraction has 39 states and 49 transitions. [2022-11-02 21:07:15,338 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2022-11-02 21:07:15,338 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 39 states and 49 transitions. [2022-11-02 21:07:15,339 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:07:15,339 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 21:07:15,339 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 21:07:15,340 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 5, 4, 4, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 21:07:15,340 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-02 21:07:15,340 INFO L748 eck$LassoCheckResult]: Stem: 4888#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 4889#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 4899#L367 assume !(main_~length~0#1 < 1); 4890#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 4891#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 4892#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4900#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 4905#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4901#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4902#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 4926#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4925#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4924#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 4923#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4922#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4921#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 4920#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4919#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4912#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4918#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4915#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 4914#L370-4 main_~j~0#1 := 0; 4903#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4895#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4896#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4910#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4909#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4907#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4906#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4893#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 4894#L378-2 [2022-11-02 21:07:15,340 INFO L750 eck$LassoCheckResult]: Loop: 4894#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4908#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 4894#L378-2 [2022-11-02 21:07:15,341 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:07:15,341 INFO L85 PathProgramCache]: Analyzing trace with hash -309219920, now seen corresponding path program 10 times [2022-11-02 21:07:15,341 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:07:15,341 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [296864348] [2022-11-02 21:07:15,341 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:07:15,342 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:07:15,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 21:07:15,813 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 0 proven. 47 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:07:15,813 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 21:07:15,813 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [296864348] [2022-11-02 21:07:15,814 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [296864348] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 21:07:15,814 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [448499605] [2022-11-02 21:07:15,814 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-02 21:07:15,814 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 21:07:15,814 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:07:15,819 INFO L229 MonitoredProcess]: Starting monitored process 43 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 21:07:15,827 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (43)] Waiting until timeout for monitored process [2022-11-02 21:07:15,936 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-02 21:07:15,936 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-02 21:07:15,938 INFO L263 TraceCheckSpWp]: Trace formula consists of 139 conjuncts, 27 conjunts are in the unsatisfiable core [2022-11-02 21:07:15,940 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 21:07:15,978 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-02 21:07:16,083 INFO L356 Elim1Store]: treesize reduction 29, result has 27.5 percent of original size [2022-11-02 21:07:16,083 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 26 [2022-11-02 21:07:16,114 INFO L356 Elim1Store]: treesize reduction 29, result has 27.5 percent of original size [2022-11-02 21:07:16,114 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 26 [2022-11-02 21:07:16,259 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2022-11-02 21:07:16,262 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 0 proven. 47 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:07:16,263 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 21:07:16,468 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 19 [2022-11-02 21:07:16,472 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 25 [2022-11-02 21:07:16,558 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 0 proven. 47 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:07:16,558 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [448499605] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 21:07:16,558 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 21:07:16,559 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 14] total 22 [2022-11-02 21:07:16,559 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1174668027] [2022-11-02 21:07:16,559 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 21:07:16,559 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-02 21:07:16,560 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:07:16,560 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 21 times [2022-11-02 21:07:16,560 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:07:16,560 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [923481479] [2022-11-02 21:07:16,560 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:07:16,561 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:07:16,563 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:07:16,564 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:07:16,565 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:07:16,567 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:07:16,624 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 21:07:16,625 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2022-11-02 21:07:16,625 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=67, Invalid=439, Unknown=0, NotChecked=0, Total=506 [2022-11-02 21:07:16,625 INFO L87 Difference]: Start difference. First operand 39 states and 49 transitions. cyclomatic complexity: 14 Second operand has 23 states, 22 states have (on average 2.1363636363636362) internal successors, (47), 23 states have internal predecessors, (47), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:07:17,174 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 21:07:17,174 INFO L93 Difference]: Finished difference Result 84 states and 103 transitions. [2022-11-02 21:07:17,174 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 84 states and 103 transitions. [2022-11-02 21:07:17,175 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 6 [2022-11-02 21:07:17,176 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 84 states to 83 states and 102 transitions. [2022-11-02 21:07:17,176 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 25 [2022-11-02 21:07:17,176 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 25 [2022-11-02 21:07:17,176 INFO L73 IsDeterministic]: Start isDeterministic. Operand 83 states and 102 transitions. [2022-11-02 21:07:17,176 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-02 21:07:17,177 INFO L218 hiAutomatonCegarLoop]: Abstraction has 83 states and 102 transitions. [2022-11-02 21:07:17,177 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 83 states and 102 transitions. [2022-11-02 21:07:17,178 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 83 to 45. [2022-11-02 21:07:17,178 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 45 states, 45 states have (on average 1.3111111111111111) internal successors, (59), 44 states have internal predecessors, (59), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:07:17,178 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 59 transitions. [2022-11-02 21:07:17,179 INFO L240 hiAutomatonCegarLoop]: Abstraction has 45 states and 59 transitions. [2022-11-02 21:07:17,179 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2022-11-02 21:07:17,180 INFO L428 stractBuchiCegarLoop]: Abstraction has 45 states and 59 transitions. [2022-11-02 21:07:17,180 INFO L335 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2022-11-02 21:07:17,180 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 45 states and 59 transitions. [2022-11-02 21:07:17,181 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:07:17,181 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 21:07:17,181 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 21:07:17,181 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 5, 5, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 21:07:17,182 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-02 21:07:17,182 INFO L748 eck$LassoCheckResult]: Stem: 5223#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 5224#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 5234#L367 assume !(main_~length~0#1 < 1); 5225#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 5226#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 5227#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5235#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 5249#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5250#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5251#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 5242#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5243#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5256#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 5255#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5254#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5253#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 5252#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5236#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5237#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5239#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5266#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 5228#L370-4 main_~j~0#1 := 0; 5229#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5232#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5233#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5241#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5259#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5258#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5257#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5248#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5247#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5230#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 5231#L378-2 [2022-11-02 21:07:17,182 INFO L750 eck$LassoCheckResult]: Loop: 5231#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5246#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 5231#L378-2 [2022-11-02 21:07:17,182 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:07:17,183 INFO L85 PathProgramCache]: Analyzing trace with hash -807596427, now seen corresponding path program 11 times [2022-11-02 21:07:17,183 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:07:17,183 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [583349835] [2022-11-02 21:07:17,183 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:07:17,183 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:07:17,198 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 21:07:17,544 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:07:17,544 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 21:07:17,544 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [583349835] [2022-11-02 21:07:17,545 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [583349835] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 21:07:17,545 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1613124808] [2022-11-02 21:07:17,545 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-02 21:07:17,545 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 21:07:17,545 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:07:17,548 INFO L229 MonitoredProcess]: Starting monitored process 44 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 21:07:17,565 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (44)] Waiting until timeout for monitored process [2022-11-02 21:07:17,681 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 6 check-sat command(s) [2022-11-02 21:07:17,682 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-02 21:07:17,683 INFO L263 TraceCheckSpWp]: Trace formula consists of 166 conjuncts, 25 conjunts are in the unsatisfiable core [2022-11-02 21:07:17,685 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 21:07:17,743 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-02 21:07:18,211 INFO L356 Elim1Store]: treesize reduction 9, result has 25.0 percent of original size [2022-11-02 21:07:18,212 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 10 [2022-11-02 21:07:18,239 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:07:18,240 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 21:07:18,567 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 19 [2022-11-02 21:07:18,571 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 39 treesize of output 32 [2022-11-02 21:07:18,638 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:07:18,639 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1613124808] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 21:07:18,639 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 21:07:18,639 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 14] total 29 [2022-11-02 21:07:18,639 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1722402748] [2022-11-02 21:07:18,640 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 21:07:18,640 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-02 21:07:18,640 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:07:18,640 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 22 times [2022-11-02 21:07:18,641 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:07:18,641 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [357919830] [2022-11-02 21:07:18,641 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:07:18,641 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:07:18,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:07:18,652 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:07:18,654 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:07:18,655 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:07:18,709 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 21:07:18,709 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2022-11-02 21:07:18,709 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=98, Invalid=772, Unknown=0, NotChecked=0, Total=870 [2022-11-02 21:07:18,710 INFO L87 Difference]: Start difference. First operand 45 states and 59 transitions. cyclomatic complexity: 18 Second operand has 30 states, 29 states have (on average 2.0344827586206895) internal successors, (59), 30 states have internal predecessors, (59), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:07:19,217 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 21:07:19,217 INFO L93 Difference]: Finished difference Result 59 states and 74 transitions. [2022-11-02 21:07:19,217 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 59 states and 74 transitions. [2022-11-02 21:07:19,218 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:07:19,219 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 59 states to 58 states and 73 transitions. [2022-11-02 21:07:19,219 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15 [2022-11-02 21:07:19,219 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15 [2022-11-02 21:07:19,219 INFO L73 IsDeterministic]: Start isDeterministic. Operand 58 states and 73 transitions. [2022-11-02 21:07:19,219 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-02 21:07:19,219 INFO L218 hiAutomatonCegarLoop]: Abstraction has 58 states and 73 transitions. [2022-11-02 21:07:19,219 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 58 states and 73 transitions. [2022-11-02 21:07:19,220 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 58 to 51. [2022-11-02 21:07:19,220 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 51 states, 51 states have (on average 1.2941176470588236) internal successors, (66), 50 states have internal predecessors, (66), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:07:19,221 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51 states to 51 states and 66 transitions. [2022-11-02 21:07:19,221 INFO L240 hiAutomatonCegarLoop]: Abstraction has 51 states and 66 transitions. [2022-11-02 21:07:19,225 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2022-11-02 21:07:19,226 INFO L428 stractBuchiCegarLoop]: Abstraction has 51 states and 66 transitions. [2022-11-02 21:07:19,226 INFO L335 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2022-11-02 21:07:19,227 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 51 states and 66 transitions. [2022-11-02 21:07:19,231 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:07:19,232 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 21:07:19,232 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 21:07:19,234 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 5, 5, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 21:07:19,234 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-02 21:07:19,234 INFO L748 eck$LassoCheckResult]: Stem: 5556#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 5557#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 5567#L367 assume !(main_~length~0#1 < 1); 5558#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 5559#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 5560#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5568#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 5571#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5569#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5570#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 5606#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5605#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5604#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 5603#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5602#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5601#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 5600#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5599#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5596#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 5597#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5589#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 5561#L370-4 main_~j~0#1 := 0; 5562#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5565#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5566#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5579#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5578#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5577#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5576#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5575#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5574#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5563#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 5564#L378-2 [2022-11-02 21:07:19,235 INFO L750 eck$LassoCheckResult]: Loop: 5564#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5573#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 5564#L378-2 [2022-11-02 21:07:19,235 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:07:19,235 INFO L85 PathProgramCache]: Analyzing trace with hash -1818713677, now seen corresponding path program 7 times [2022-11-02 21:07:19,235 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:07:19,235 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1849573199] [2022-11-02 21:07:19,235 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:07:19,235 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:07:19,250 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 21:07:19,629 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:07:19,629 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 21:07:19,629 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1849573199] [2022-11-02 21:07:19,629 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1849573199] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 21:07:19,630 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [695643734] [2022-11-02 21:07:19,630 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-11-02 21:07:19,630 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 21:07:19,630 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:07:19,633 INFO L229 MonitoredProcess]: Starting monitored process 45 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 21:07:19,651 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (45)] Waiting until timeout for monitored process [2022-11-02 21:07:19,748 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 21:07:19,750 INFO L263 TraceCheckSpWp]: Trace formula consists of 158 conjuncts, 30 conjunts are in the unsatisfiable core [2022-11-02 21:07:19,752 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 21:07:19,953 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 9 [2022-11-02 21:07:20,268 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-02 21:07:20,271 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:07:20,272 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 21:07:20,412 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 14 [2022-11-02 21:07:20,417 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 20 [2022-11-02 21:07:20,470 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:07:20,470 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [695643734] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 21:07:20,470 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 21:07:20,470 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 14] total 30 [2022-11-02 21:07:20,471 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [169789172] [2022-11-02 21:07:20,471 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 21:07:20,471 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-02 21:07:20,471 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:07:20,472 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 23 times [2022-11-02 21:07:20,472 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:07:20,472 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1788905948] [2022-11-02 21:07:20,472 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:07:20,472 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:07:20,475 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:07:20,476 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:07:20,477 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:07:20,478 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:07:20,532 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 21:07:20,533 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2022-11-02 21:07:20,533 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=109, Invalid=821, Unknown=0, NotChecked=0, Total=930 [2022-11-02 21:07:20,534 INFO L87 Difference]: Start difference. First operand 51 states and 66 transitions. cyclomatic complexity: 19 Second operand has 31 states, 30 states have (on average 2.2) internal successors, (66), 31 states have internal predecessors, (66), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:07:21,089 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 21:07:21,090 INFO L93 Difference]: Finished difference Result 96 states and 120 transitions. [2022-11-02 21:07:21,090 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 96 states and 120 transitions. [2022-11-02 21:07:21,093 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 12 [2022-11-02 21:07:21,095 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 96 states to 95 states and 119 transitions. [2022-11-02 21:07:21,095 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 33 [2022-11-02 21:07:21,095 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 33 [2022-11-02 21:07:21,096 INFO L73 IsDeterministic]: Start isDeterministic. Operand 95 states and 119 transitions. [2022-11-02 21:07:21,096 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-02 21:07:21,096 INFO L218 hiAutomatonCegarLoop]: Abstraction has 95 states and 119 transitions. [2022-11-02 21:07:21,096 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 95 states and 119 transitions. [2022-11-02 21:07:21,098 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 95 to 73. [2022-11-02 21:07:21,098 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 73 states, 73 states have (on average 1.3013698630136987) internal successors, (95), 72 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:07:21,098 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 73 states to 73 states and 95 transitions. [2022-11-02 21:07:21,099 INFO L240 hiAutomatonCegarLoop]: Abstraction has 73 states and 95 transitions. [2022-11-02 21:07:21,101 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2022-11-02 21:07:21,102 INFO L428 stractBuchiCegarLoop]: Abstraction has 73 states and 95 transitions. [2022-11-02 21:07:21,102 INFO L335 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2022-11-02 21:07:21,102 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 73 states and 95 transitions. [2022-11-02 21:07:21,103 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2022-11-02 21:07:21,103 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 21:07:21,103 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 21:07:21,105 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [6, 6, 4, 4, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 21:07:21,105 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-02 21:07:21,105 INFO L748 eck$LassoCheckResult]: Stem: 5931#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 5932#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 5942#L367 assume !(main_~length~0#1 < 1); 5933#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 5934#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 5935#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5943#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 5955#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5956#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5957#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 5951#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5952#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5962#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 5961#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5960#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5959#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 5958#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5944#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5945#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5983#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5982#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5979#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5981#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5989#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 5988#L370-4 main_~j~0#1 := 0; 5987#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5986#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5985#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5965#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5969#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5967#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5968#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5970#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 5937#L378-2 [2022-11-02 21:07:21,105 INFO L750 eck$LassoCheckResult]: Loop: 5937#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5963#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 5937#L378-2 [2022-11-02 21:07:21,105 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:07:21,106 INFO L85 PathProgramCache]: Analyzing trace with hash 978257960, now seen corresponding path program 12 times [2022-11-02 21:07:21,106 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:07:21,106 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1587154302] [2022-11-02 21:07:21,106 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:07:21,106 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:07:21,122 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 21:07:21,661 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 0 proven. 63 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:07:21,661 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 21:07:21,661 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1587154302] [2022-11-02 21:07:21,661 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1587154302] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 21:07:21,662 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1266263605] [2022-11-02 21:07:21,662 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-11-02 21:07:21,662 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 21:07:21,662 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:07:21,667 INFO L229 MonitoredProcess]: Starting monitored process 46 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 21:07:21,682 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (46)] Waiting until timeout for monitored process [2022-11-02 21:07:21,828 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) [2022-11-02 21:07:21,828 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-02 21:07:21,830 INFO L263 TraceCheckSpWp]: Trace formula consists of 177 conjuncts, 32 conjunts are in the unsatisfiable core [2022-11-02 21:07:21,842 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 21:07:21,882 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-02 21:07:21,961 INFO L356 Elim1Store]: treesize reduction 23, result has 28.1 percent of original size [2022-11-02 21:07:21,961 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2022-11-02 21:07:21,980 INFO L356 Elim1Store]: treesize reduction 23, result has 28.1 percent of original size [2022-11-02 21:07:21,981 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2022-11-02 21:07:22,003 INFO L356 Elim1Store]: treesize reduction 17, result has 46.9 percent of original size [2022-11-02 21:07:22,003 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 30 [2022-11-02 21:07:22,047 INFO L356 Elim1Store]: treesize reduction 17, result has 46.9 percent of original size [2022-11-02 21:07:22,047 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 31 treesize of output 36 [2022-11-02 21:07:25,366 INFO L356 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-02 21:07:25,366 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 30 treesize of output 20 [2022-11-02 21:07:25,372 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 2 proven. 61 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:07:25,372 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 21:07:37,961 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 19 [2022-11-02 21:07:37,964 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 25 [2022-11-02 21:07:38,028 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 0 proven. 61 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-11-02 21:07:38,028 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1266263605] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 21:07:38,029 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 21:07:38,029 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 16, 15] total 25 [2022-11-02 21:07:38,029 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1133325108] [2022-11-02 21:07:38,029 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 21:07:38,030 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-02 21:07:38,030 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:07:38,031 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 24 times [2022-11-02 21:07:38,031 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:07:38,031 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1662855438] [2022-11-02 21:07:38,031 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:07:38,031 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:07:38,037 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:07:38,038 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:07:38,039 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:07:38,040 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:07:38,096 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 21:07:38,096 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2022-11-02 21:07:38,097 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=97, Invalid=548, Unknown=5, NotChecked=0, Total=650 [2022-11-02 21:07:38,097 INFO L87 Difference]: Start difference. First operand 73 states and 95 transitions. cyclomatic complexity: 28 Second operand has 26 states, 25 states have (on average 2.2) internal successors, (55), 26 states have internal predecessors, (55), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:07:39,264 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 21:07:39,265 INFO L93 Difference]: Finished difference Result 78 states and 95 transitions. [2022-11-02 21:07:39,265 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 78 states and 95 transitions. [2022-11-02 21:07:39,266 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:07:39,267 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 78 states to 76 states and 93 transitions. [2022-11-02 21:07:39,267 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17 [2022-11-02 21:07:39,267 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17 [2022-11-02 21:07:39,267 INFO L73 IsDeterministic]: Start isDeterministic. Operand 76 states and 93 transitions. [2022-11-02 21:07:39,267 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-02 21:07:39,268 INFO L218 hiAutomatonCegarLoop]: Abstraction has 76 states and 93 transitions. [2022-11-02 21:07:39,268 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 76 states and 93 transitions. [2022-11-02 21:07:39,269 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 76 to 42. [2022-11-02 21:07:39,269 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 42 states, 42 states have (on average 1.2619047619047619) internal successors, (53), 41 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:07:39,270 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42 states to 42 states and 53 transitions. [2022-11-02 21:07:39,270 INFO L240 hiAutomatonCegarLoop]: Abstraction has 42 states and 53 transitions. [2022-11-02 21:07:39,270 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2022-11-02 21:07:39,271 INFO L428 stractBuchiCegarLoop]: Abstraction has 42 states and 53 transitions. [2022-11-02 21:07:39,271 INFO L335 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2022-11-02 21:07:39,271 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 42 states and 53 transitions. [2022-11-02 21:07:39,272 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:07:39,272 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 21:07:39,272 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 21:07:39,272 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [6, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 21:07:39,272 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-02 21:07:39,273 INFO L748 eck$LassoCheckResult]: Stem: 6307#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 6308#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 6318#L367 assume !(main_~length~0#1 < 1); 6309#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 6310#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 6311#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6319#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 6348#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6320#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6321#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 6335#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6336#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6347#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 6346#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6345#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6344#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 6343#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6342#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6324#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 6325#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6326#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 6316#L370-4 main_~j~0#1 := 0; 6317#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6314#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6315#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6323#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6337#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6334#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6332#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6331#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6330#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6329#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6328#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6312#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 6313#L378-2 [2022-11-02 21:07:39,273 INFO L750 eck$LassoCheckResult]: Loop: 6313#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6327#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 6313#L378-2 [2022-11-02 21:07:39,273 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:07:39,273 INFO L85 PathProgramCache]: Analyzing trace with hash 267849144, now seen corresponding path program 8 times [2022-11-02 21:07:39,274 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:07:39,274 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1231336642] [2022-11-02 21:07:39,274 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:07:39,274 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:07:39,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 21:07:39,497 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 21 proven. 44 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:07:39,498 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 21:07:39,498 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1231336642] [2022-11-02 21:07:39,498 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1231336642] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 21:07:39,498 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [355341757] [2022-11-02 21:07:39,498 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-02 21:07:39,498 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 21:07:39,499 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:07:39,505 INFO L229 MonitoredProcess]: Starting monitored process 47 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 21:07:39,521 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (47)] Waiting until timeout for monitored process [2022-11-02 21:07:39,623 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-02 21:07:39,623 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-02 21:07:39,625 INFO L263 TraceCheckSpWp]: Trace formula consists of 169 conjuncts, 14 conjunts are in the unsatisfiable core [2022-11-02 21:07:39,626 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 21:07:39,806 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 30 proven. 35 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:07:39,806 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 21:07:39,943 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 30 proven. 35 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:07:39,943 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [355341757] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 21:07:39,943 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 21:07:39,943 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15] total 23 [2022-11-02 21:07:39,944 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [75732254] [2022-11-02 21:07:39,944 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 21:07:39,944 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-02 21:07:39,944 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:07:39,945 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 25 times [2022-11-02 21:07:39,945 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:07:39,945 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [354137315] [2022-11-02 21:07:39,945 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:07:39,945 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:07:39,948 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:07:39,948 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:07:39,950 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:07:39,951 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:07:40,013 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 21:07:40,013 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2022-11-02 21:07:40,014 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=124, Invalid=382, Unknown=0, NotChecked=0, Total=506 [2022-11-02 21:07:40,014 INFO L87 Difference]: Start difference. First operand 42 states and 53 transitions. cyclomatic complexity: 15 Second operand has 23 states, 23 states have (on average 2.3043478260869565) internal successors, (53), 23 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:07:40,224 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 21:07:40,224 INFO L93 Difference]: Finished difference Result 59 states and 71 transitions. [2022-11-02 21:07:40,224 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 59 states and 71 transitions. [2022-11-02 21:07:40,225 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:07:40,226 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 59 states to 47 states and 59 transitions. [2022-11-02 21:07:40,226 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-02 21:07:40,226 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-02 21:07:40,226 INFO L73 IsDeterministic]: Start isDeterministic. Operand 47 states and 59 transitions. [2022-11-02 21:07:40,226 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-02 21:07:40,226 INFO L218 hiAutomatonCegarLoop]: Abstraction has 47 states and 59 transitions. [2022-11-02 21:07:40,227 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47 states and 59 transitions. [2022-11-02 21:07:40,227 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47 to 44. [2022-11-02 21:07:40,228 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 44 states, 44 states have (on average 1.25) internal successors, (55), 43 states have internal predecessors, (55), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:07:40,228 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44 states to 44 states and 55 transitions. [2022-11-02 21:07:40,228 INFO L240 hiAutomatonCegarLoop]: Abstraction has 44 states and 55 transitions. [2022-11-02 21:07:40,233 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2022-11-02 21:07:40,234 INFO L428 stractBuchiCegarLoop]: Abstraction has 44 states and 55 transitions. [2022-11-02 21:07:40,234 INFO L335 stractBuchiCegarLoop]: ======== Iteration 28 ============ [2022-11-02 21:07:40,234 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 44 states and 55 transitions. [2022-11-02 21:07:40,234 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:07:40,234 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 21:07:40,235 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 21:07:40,235 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [6, 6, 5, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 21:07:40,235 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-02 21:07:40,235 INFO L748 eck$LassoCheckResult]: Stem: 6646#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 6647#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 6657#L367 assume !(main_~length~0#1 < 1); 6648#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 6649#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 6650#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6658#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 6689#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6659#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6660#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 6661#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6663#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6688#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 6687#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6686#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6685#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 6684#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6683#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6682#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 6681#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6680#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6678#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6674#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6664#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 6651#L370-4 main_~j~0#1 := 0; 6652#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6662#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6673#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6672#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6671#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6670#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6669#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6667#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6666#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6653#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 6654#L378-2 [2022-11-02 21:07:40,235 INFO L750 eck$LassoCheckResult]: Loop: 6654#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6668#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 6654#L378-2 [2022-11-02 21:07:40,236 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:07:40,236 INFO L85 PathProgramCache]: Analyzing trace with hash -2080282897, now seen corresponding path program 13 times [2022-11-02 21:07:40,236 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:07:40,236 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [78057667] [2022-11-02 21:07:40,236 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:07:40,236 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:07:40,263 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 21:07:40,800 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 71 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:07:40,800 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 21:07:40,800 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [78057667] [2022-11-02 21:07:40,800 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [78057667] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 21:07:40,800 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [919620761] [2022-11-02 21:07:40,801 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-11-02 21:07:40,801 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 21:07:40,801 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:07:40,807 INFO L229 MonitoredProcess]: Starting monitored process 48 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 21:07:40,831 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (48)] Waiting until timeout for monitored process [2022-11-02 21:07:40,929 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 21:07:40,931 INFO L263 TraceCheckSpWp]: Trace formula consists of 180 conjuncts, 35 conjunts are in the unsatisfiable core [2022-11-02 21:07:40,933 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 21:07:41,134 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-02 21:07:41,265 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-02 21:07:41,266 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-02 21:07:41,282 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-02 21:07:41,283 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-02 21:07:41,537 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-02 21:07:41,541 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 71 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:07:41,541 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 21:07:41,767 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 19 [2022-11-02 21:07:41,770 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 25 [2022-11-02 21:07:41,839 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 71 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:07:41,840 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [919620761] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 21:07:41,840 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 21:07:41,840 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 17, 16] total 34 [2022-11-02 21:07:41,840 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1769340042] [2022-11-02 21:07:41,840 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 21:07:41,841 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-02 21:07:41,841 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:07:41,841 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 26 times [2022-11-02 21:07:41,841 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:07:41,841 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [541371179] [2022-11-02 21:07:41,842 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:07:41,842 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:07:41,845 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:07:41,845 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:07:41,847 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:07:41,848 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:07:41,901 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 21:07:41,901 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2022-11-02 21:07:41,902 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=129, Invalid=1061, Unknown=0, NotChecked=0, Total=1190 [2022-11-02 21:07:41,902 INFO L87 Difference]: Start difference. First operand 44 states and 55 transitions. cyclomatic complexity: 15 Second operand has 35 states, 34 states have (on average 2.1176470588235294) internal successors, (72), 35 states have internal predecessors, (72), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:07:42,616 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 21:07:42,616 INFO L93 Difference]: Finished difference Result 54 states and 65 transitions. [2022-11-02 21:07:42,616 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 54 states and 65 transitions. [2022-11-02 21:07:42,617 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:07:42,617 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 54 states to 53 states and 64 transitions. [2022-11-02 21:07:42,618 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-02 21:07:42,618 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-02 21:07:42,618 INFO L73 IsDeterministic]: Start isDeterministic. Operand 53 states and 64 transitions. [2022-11-02 21:07:42,618 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-02 21:07:42,618 INFO L218 hiAutomatonCegarLoop]: Abstraction has 53 states and 64 transitions. [2022-11-02 21:07:42,618 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53 states and 64 transitions. [2022-11-02 21:07:42,619 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53 to 39. [2022-11-02 21:07:42,619 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 39 states, 39 states have (on average 1.2307692307692308) internal successors, (48), 38 states have internal predecessors, (48), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:07:42,620 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39 states to 39 states and 48 transitions. [2022-11-02 21:07:42,620 INFO L240 hiAutomatonCegarLoop]: Abstraction has 39 states and 48 transitions. [2022-11-02 21:07:42,620 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2022-11-02 21:07:42,621 INFO L428 stractBuchiCegarLoop]: Abstraction has 39 states and 48 transitions. [2022-11-02 21:07:42,621 INFO L335 stractBuchiCegarLoop]: ======== Iteration 29 ============ [2022-11-02 21:07:42,621 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 39 states and 48 transitions. [2022-11-02 21:07:42,622 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:07:42,622 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 21:07:42,622 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 21:07:42,622 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [6, 6, 6, 6, 5, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 21:07:42,622 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-02 21:07:42,623 INFO L748 eck$LassoCheckResult]: Stem: 7000#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 7001#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 7011#L367 assume !(main_~length~0#1 < 1); 7002#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 7003#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 7004#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7012#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7036#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7013#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7014#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7015#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7017#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7035#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7034#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7033#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7032#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7031#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7030#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7029#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7028#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7027#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7019#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7024#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7018#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 7005#L370-4 main_~j~0#1 := 0; 7006#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7009#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7010#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7016#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7038#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7037#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7026#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7025#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7023#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7021#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7020#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7007#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 7008#L378-2 [2022-11-02 21:07:42,623 INFO L750 eck$LassoCheckResult]: Loop: 7008#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7022#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 7008#L378-2 [2022-11-02 21:07:42,623 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:07:42,624 INFO L85 PathProgramCache]: Analyzing trace with hash 1281830834, now seen corresponding path program 9 times [2022-11-02 21:07:42,624 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:07:42,624 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [874420887] [2022-11-02 21:07:42,624 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:07:42,624 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:07:42,642 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 21:07:43,046 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 0 proven. 81 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:07:43,046 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 21:07:43,046 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [874420887] [2022-11-02 21:07:43,047 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [874420887] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 21:07:43,047 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1728396215] [2022-11-02 21:07:43,047 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-02 21:07:43,047 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 21:07:43,047 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:07:43,048 INFO L229 MonitoredProcess]: Starting monitored process 49 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 21:07:43,051 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (49)] Waiting until timeout for monitored process [2022-11-02 21:07:43,223 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 7 check-sat command(s) [2022-11-02 21:07:43,223 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-02 21:07:43,225 INFO L263 TraceCheckSpWp]: Trace formula consists of 183 conjuncts, 21 conjunts are in the unsatisfiable core [2022-11-02 21:07:43,226 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 21:07:43,382 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-02 21:07:44,034 INFO L356 Elim1Store]: treesize reduction 9, result has 25.0 percent of original size [2022-11-02 21:07:44,034 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 10 [2022-11-02 21:07:44,039 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 25 proven. 56 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:07:44,040 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 21:07:44,823 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2022-11-02 21:07:44,828 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 28 [2022-11-02 21:07:45,000 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 20 proven. 61 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:07:45,000 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1728396215] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 21:07:45,001 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 21:07:45,001 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 18, 18] total 43 [2022-11-02 21:07:45,001 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [635191166] [2022-11-02 21:07:45,001 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 21:07:45,001 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-02 21:07:45,002 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:07:45,002 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 27 times [2022-11-02 21:07:45,002 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:07:45,002 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1273963821] [2022-11-02 21:07:45,002 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:07:45,002 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:07:45,005 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:07:45,006 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:07:45,007 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:07:45,009 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:07:45,064 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 21:07:45,064 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2022-11-02 21:07:45,065 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=238, Invalid=1654, Unknown=0, NotChecked=0, Total=1892 [2022-11-02 21:07:45,066 INFO L87 Difference]: Start difference. First operand 39 states and 48 transitions. cyclomatic complexity: 12 Second operand has 44 states, 43 states have (on average 1.9767441860465116) internal successors, (85), 44 states have internal predecessors, (85), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:07:46,266 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 21:07:46,266 INFO L93 Difference]: Finished difference Result 73 states and 88 transitions. [2022-11-02 21:07:46,266 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 73 states and 88 transitions. [2022-11-02 21:07:46,267 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:07:46,267 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 73 states to 56 states and 70 transitions. [2022-11-02 21:07:46,267 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11 [2022-11-02 21:07:46,268 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11 [2022-11-02 21:07:46,268 INFO L73 IsDeterministic]: Start isDeterministic. Operand 56 states and 70 transitions. [2022-11-02 21:07:46,268 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-02 21:07:46,268 INFO L218 hiAutomatonCegarLoop]: Abstraction has 56 states and 70 transitions. [2022-11-02 21:07:46,268 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 56 states and 70 transitions. [2022-11-02 21:07:46,269 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 56 to 51. [2022-11-02 21:07:46,269 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 51 states, 51 states have (on average 1.2549019607843137) internal successors, (64), 50 states have internal predecessors, (64), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:07:46,269 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51 states to 51 states and 64 transitions. [2022-11-02 21:07:46,270 INFO L240 hiAutomatonCegarLoop]: Abstraction has 51 states and 64 transitions. [2022-11-02 21:07:46,270 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2022-11-02 21:07:46,271 INFO L428 stractBuchiCegarLoop]: Abstraction has 51 states and 64 transitions. [2022-11-02 21:07:46,271 INFO L335 stractBuchiCegarLoop]: ======== Iteration 30 ============ [2022-11-02 21:07:46,271 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 51 states and 64 transitions. [2022-11-02 21:07:46,271 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:07:46,271 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 21:07:46,271 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 21:07:46,272 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [6, 6, 6, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 21:07:46,272 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-02 21:07:46,272 INFO L748 eck$LassoCheckResult]: Stem: 7430#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 7431#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 7441#L367 assume !(main_~length~0#1 < 1); 7432#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 7433#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 7434#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7442#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7476#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7480#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7445#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7446#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7443#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7444#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7470#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7479#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7478#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7462#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7477#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7463#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7460#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7451#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7449#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7450#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7448#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 7439#L370-4 main_~j~0#1 := 0; 7440#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7437#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7438#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7447#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7459#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7458#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7457#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7456#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7455#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7453#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7452#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7435#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 7436#L378-2 [2022-11-02 21:07:46,272 INFO L750 eck$LassoCheckResult]: Loop: 7436#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7454#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 7436#L378-2 [2022-11-02 21:07:46,272 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:07:46,273 INFO L85 PathProgramCache]: Analyzing trace with hash 580230960, now seen corresponding path program 14 times [2022-11-02 21:07:46,273 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:07:46,273 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [9304181] [2022-11-02 21:07:46,273 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:07:46,273 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:07:46,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 21:07:46,699 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 0 proven. 81 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:07:46,699 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 21:07:46,700 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [9304181] [2022-11-02 21:07:46,700 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [9304181] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 21:07:46,700 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [835609664] [2022-11-02 21:07:46,700 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-02 21:07:46,700 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 21:07:46,700 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:07:46,703 INFO L229 MonitoredProcess]: Starting monitored process 50 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 21:07:46,725 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (50)] Waiting until timeout for monitored process [2022-11-02 21:07:46,843 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-02 21:07:46,843 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-02 21:07:46,845 INFO L263 TraceCheckSpWp]: Trace formula consists of 191 conjuncts, 30 conjunts are in the unsatisfiable core [2022-11-02 21:07:46,858 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 21:07:46,916 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-02 21:07:47,189 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2022-11-02 21:07:47,195 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 0 proven. 81 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:07:47,196 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 21:07:47,324 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 14 [2022-11-02 21:07:47,327 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 20 [2022-11-02 21:07:47,381 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 0 proven. 81 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:07:47,381 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [835609664] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 21:07:47,381 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 21:07:47,381 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 16, 16] total 25 [2022-11-02 21:07:47,382 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [393431266] [2022-11-02 21:07:47,382 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 21:07:47,384 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-02 21:07:47,384 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:07:47,384 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 28 times [2022-11-02 21:07:47,384 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:07:47,384 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1370868105] [2022-11-02 21:07:47,384 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:07:47,384 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:07:47,388 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:07:47,388 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:07:47,392 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:07:47,396 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:07:47,452 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 21:07:47,453 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2022-11-02 21:07:47,453 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=75, Invalid=575, Unknown=0, NotChecked=0, Total=650 [2022-11-02 21:07:47,453 INFO L87 Difference]: Start difference. First operand 51 states and 64 transitions. cyclomatic complexity: 16 Second operand has 26 states, 25 states have (on average 2.2) internal successors, (55), 26 states have internal predecessors, (55), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:07:47,924 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 21:07:47,924 INFO L93 Difference]: Finished difference Result 80 states and 99 transitions. [2022-11-02 21:07:47,924 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 80 states and 99 transitions. [2022-11-02 21:07:47,925 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-02 21:07:47,929 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 80 states to 79 states and 98 transitions. [2022-11-02 21:07:47,929 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16 [2022-11-02 21:07:47,930 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16 [2022-11-02 21:07:47,930 INFO L73 IsDeterministic]: Start isDeterministic. Operand 79 states and 98 transitions. [2022-11-02 21:07:47,930 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-02 21:07:47,930 INFO L218 hiAutomatonCegarLoop]: Abstraction has 79 states and 98 transitions. [2022-11-02 21:07:47,931 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 79 states and 98 transitions. [2022-11-02 21:07:47,932 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 79 to 64. [2022-11-02 21:07:47,932 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 64 states, 64 states have (on average 1.265625) internal successors, (81), 63 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:07:47,932 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 64 states to 64 states and 81 transitions. [2022-11-02 21:07:47,933 INFO L240 hiAutomatonCegarLoop]: Abstraction has 64 states and 81 transitions. [2022-11-02 21:07:47,933 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2022-11-02 21:07:47,933 INFO L428 stractBuchiCegarLoop]: Abstraction has 64 states and 81 transitions. [2022-11-02 21:07:47,933 INFO L335 stractBuchiCegarLoop]: ======== Iteration 31 ============ [2022-11-02 21:07:47,934 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 64 states and 81 transitions. [2022-11-02 21:07:47,934 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:07:47,934 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 21:07:47,934 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 21:07:47,934 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [7, 6, 6, 6, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 21:07:47,935 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-02 21:07:47,935 INFO L748 eck$LassoCheckResult]: Stem: 7808#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 7809#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 7819#L367 assume !(main_~length~0#1 < 1); 7810#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 7811#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 7812#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7820#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7850#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7821#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7822#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7823#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7826#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7854#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7844#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7853#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7852#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7840#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7871#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7870#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7834#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7869#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7830#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7829#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7827#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 7813#L370-4 main_~j~0#1 := 0; 7814#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7864#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7825#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7817#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7818#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7863#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7862#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7861#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7860#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7859#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7858#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7856#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7855#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7815#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 7816#L378-2 [2022-11-02 21:07:47,935 INFO L750 eck$LassoCheckResult]: Loop: 7816#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7857#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 7816#L378-2 [2022-11-02 21:07:47,935 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:07:47,935 INFO L85 PathProgramCache]: Analyzing trace with hash -743792651, now seen corresponding path program 15 times [2022-11-02 21:07:47,935 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:07:47,935 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1677384995] [2022-11-02 21:07:47,936 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:07:47,936 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:07:47,961 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 21:07:48,292 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 31 proven. 62 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:07:48,292 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 21:07:48,292 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1677384995] [2022-11-02 21:07:48,292 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1677384995] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 21:07:48,292 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [140288246] [2022-11-02 21:07:48,292 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-02 21:07:48,293 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 21:07:48,293 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:07:48,299 INFO L229 MonitoredProcess]: Starting monitored process 51 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 21:07:48,323 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (51)] Waiting until timeout for monitored process [2022-11-02 21:07:48,521 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 7 check-sat command(s) [2022-11-02 21:07:48,521 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-02 21:07:48,523 INFO L263 TraceCheckSpWp]: Trace formula consists of 202 conjuncts, 16 conjunts are in the unsatisfiable core [2022-11-02 21:07:48,524 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 21:07:48,772 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 42 proven. 51 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:07:48,772 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 21:07:48,971 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 42 proven. 51 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:07:48,971 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [140288246] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 21:07:48,971 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 21:07:48,972 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17] total 26 [2022-11-02 21:07:48,972 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1795679536] [2022-11-02 21:07:48,972 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 21:07:48,972 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-02 21:07:48,972 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:07:48,973 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 29 times [2022-11-02 21:07:48,973 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:07:48,973 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1082639699] [2022-11-02 21:07:48,973 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:07:48,973 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:07:48,976 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:07:48,976 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:07:48,977 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:07:48,979 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:07:49,035 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 21:07:49,035 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2022-11-02 21:07:49,036 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=157, Invalid=493, Unknown=0, NotChecked=0, Total=650 [2022-11-02 21:07:49,036 INFO L87 Difference]: Start difference. First operand 64 states and 81 transitions. cyclomatic complexity: 21 Second operand has 26 states, 26 states have (on average 2.3076923076923075) internal successors, (60), 26 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:07:49,264 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 21:07:49,264 INFO L93 Difference]: Finished difference Result 83 states and 101 transitions. [2022-11-02 21:07:49,264 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 83 states and 101 transitions. [2022-11-02 21:07:49,265 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:07:49,265 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 83 states to 69 states and 87 transitions. [2022-11-02 21:07:49,265 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-02 21:07:49,266 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-02 21:07:49,266 INFO L73 IsDeterministic]: Start isDeterministic. Operand 69 states and 87 transitions. [2022-11-02 21:07:49,266 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-02 21:07:49,266 INFO L218 hiAutomatonCegarLoop]: Abstraction has 69 states and 87 transitions. [2022-11-02 21:07:49,266 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69 states and 87 transitions. [2022-11-02 21:07:49,267 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69 to 49. [2022-11-02 21:07:49,268 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 49 states, 49 states have (on average 1.2448979591836735) internal successors, (61), 48 states have internal predecessors, (61), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:07:49,268 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49 states to 49 states and 61 transitions. [2022-11-02 21:07:49,268 INFO L240 hiAutomatonCegarLoop]: Abstraction has 49 states and 61 transitions. [2022-11-02 21:07:49,275 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2022-11-02 21:07:49,276 INFO L428 stractBuchiCegarLoop]: Abstraction has 49 states and 61 transitions. [2022-11-02 21:07:49,276 INFO L335 stractBuchiCegarLoop]: ======== Iteration 32 ============ [2022-11-02 21:07:49,276 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 49 states and 61 transitions. [2022-11-02 21:07:49,276 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:07:49,277 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 21:07:49,277 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 21:07:49,277 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [7, 7, 6, 6, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 21:07:49,277 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-02 21:07:49,277 INFO L748 eck$LassoCheckResult]: Stem: 8228#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 8229#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 8239#L367 assume !(main_~length~0#1 < 1); 8230#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 8231#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 8232#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8240#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 8245#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8241#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8242#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 8276#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8275#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8274#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 8273#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8272#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8271#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 8270#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8269#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8268#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 8267#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8266#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8265#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 8264#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8263#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8256#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8262#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8259#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 8258#L370-4 main_~j~0#1 := 0; 8243#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8235#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8236#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8254#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8253#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8252#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8251#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8250#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8249#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8247#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8246#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8233#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 8234#L378-2 [2022-11-02 21:07:49,277 INFO L750 eck$LassoCheckResult]: Loop: 8234#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8248#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 8234#L378-2 [2022-11-02 21:07:49,278 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:07:49,278 INFO L85 PathProgramCache]: Analyzing trace with hash -968534086, now seen corresponding path program 16 times [2022-11-02 21:07:49,278 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:07:49,278 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [905494869] [2022-11-02 21:07:49,278 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:07:49,278 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:07:49,299 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 21:07:49,886 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:07:49,887 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 21:07:49,887 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [905494869] [2022-11-02 21:07:49,887 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [905494869] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 21:07:49,887 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2078360389] [2022-11-02 21:07:49,887 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-02 21:07:49,887 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 21:07:49,888 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:07:49,889 INFO L229 MonitoredProcess]: Starting monitored process 52 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 21:07:49,910 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (52)] Waiting until timeout for monitored process [2022-11-02 21:07:50,034 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-02 21:07:50,034 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-02 21:07:50,036 INFO L263 TraceCheckSpWp]: Trace formula consists of 189 conjuncts, 35 conjunts are in the unsatisfiable core [2022-11-02 21:07:50,039 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 21:07:50,099 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-02 21:07:50,214 INFO L356 Elim1Store]: treesize reduction 29, result has 27.5 percent of original size [2022-11-02 21:07:50,214 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 26 [2022-11-02 21:07:50,243 INFO L356 Elim1Store]: treesize reduction 29, result has 27.5 percent of original size [2022-11-02 21:07:50,243 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 26 [2022-11-02 21:07:50,479 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2022-11-02 21:07:50,482 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:07:50,483 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 21:07:50,742 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 19 [2022-11-02 21:07:50,745 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 25 [2022-11-02 21:07:50,820 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:07:50,820 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2078360389] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 21:07:50,820 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 21:07:50,820 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18, 18] total 28 [2022-11-02 21:07:50,821 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1304399701] [2022-11-02 21:07:50,821 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 21:07:50,821 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-02 21:07:50,822 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:07:50,822 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 30 times [2022-11-02 21:07:50,822 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:07:50,822 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1967483963] [2022-11-02 21:07:50,822 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:07:50,822 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:07:50,825 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:07:50,826 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:07:50,827 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:07:50,829 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:07:50,889 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 21:07:50,890 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2022-11-02 21:07:50,890 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=83, Invalid=729, Unknown=0, NotChecked=0, Total=812 [2022-11-02 21:07:50,891 INFO L87 Difference]: Start difference. First operand 49 states and 61 transitions. cyclomatic complexity: 16 Second operand has 29 states, 28 states have (on average 2.1785714285714284) internal successors, (61), 29 states have internal predecessors, (61), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:07:51,671 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 21:07:51,671 INFO L93 Difference]: Finished difference Result 106 states and 127 transitions. [2022-11-02 21:07:51,671 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 106 states and 127 transitions. [2022-11-02 21:07:51,674 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 6 [2022-11-02 21:07:51,675 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 106 states to 105 states and 126 transitions. [2022-11-02 21:07:51,675 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 25 [2022-11-02 21:07:51,675 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 25 [2022-11-02 21:07:51,675 INFO L73 IsDeterministic]: Start isDeterministic. Operand 105 states and 126 transitions. [2022-11-02 21:07:51,675 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-02 21:07:51,676 INFO L218 hiAutomatonCegarLoop]: Abstraction has 105 states and 126 transitions. [2022-11-02 21:07:51,676 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 105 states and 126 transitions. [2022-11-02 21:07:51,680 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 105 to 55. [2022-11-02 21:07:51,681 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 55 states, 55 states have (on average 1.290909090909091) internal successors, (71), 54 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:07:51,681 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55 states to 55 states and 71 transitions. [2022-11-02 21:07:51,681 INFO L240 hiAutomatonCegarLoop]: Abstraction has 55 states and 71 transitions. [2022-11-02 21:07:51,685 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2022-11-02 21:07:51,686 INFO L428 stractBuchiCegarLoop]: Abstraction has 55 states and 71 transitions. [2022-11-02 21:07:51,686 INFO L335 stractBuchiCegarLoop]: ======== Iteration 33 ============ [2022-11-02 21:07:51,686 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 55 states and 71 transitions. [2022-11-02 21:07:51,687 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:07:51,687 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 21:07:51,687 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 21:07:51,688 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [7, 7, 7, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 21:07:51,688 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-02 21:07:51,688 INFO L748 eck$LassoCheckResult]: Stem: 8665#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 8666#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 8676#L367 assume !(main_~length~0#1 < 1); 8667#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 8668#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 8669#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8677#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 8702#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8678#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8679#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 8680#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8683#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8701#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 8700#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8699#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8698#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 8697#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8696#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8695#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 8694#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8693#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8692#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 8691#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8689#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8690#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8688#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8718#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 8670#L370-4 main_~j~0#1 := 0; 8671#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8712#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8682#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8674#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8675#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8711#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8710#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8709#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8708#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8707#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8706#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8705#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8704#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8672#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 8673#L378-2 [2022-11-02 21:07:51,688 INFO L750 eck$LassoCheckResult]: Loop: 8673#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8703#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 8673#L378-2 [2022-11-02 21:07:51,689 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:07:51,689 INFO L85 PathProgramCache]: Analyzing trace with hash 1246649855, now seen corresponding path program 17 times [2022-11-02 21:07:51,689 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:07:51,689 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [437716452] [2022-11-02 21:07:51,689 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:07:51,689 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:07:51,710 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 21:07:52,246 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 0 proven. 112 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:07:52,246 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 21:07:52,246 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [437716452] [2022-11-02 21:07:52,246 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [437716452] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 21:07:52,246 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1357519785] [2022-11-02 21:07:52,246 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-02 21:07:52,247 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 21:07:52,247 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:07:52,253 INFO L229 MonitoredProcess]: Starting monitored process 53 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 21:07:52,269 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (53)] Waiting until timeout for monitored process [2022-11-02 21:07:52,442 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 8 check-sat command(s) [2022-11-02 21:07:52,442 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-02 21:07:52,445 INFO L263 TraceCheckSpWp]: Trace formula consists of 216 conjuncts, 33 conjunts are in the unsatisfiable core [2022-11-02 21:07:52,447 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 21:07:52,533 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-02 21:07:53,140 INFO L356 Elim1Store]: treesize reduction 9, result has 25.0 percent of original size [2022-11-02 21:07:53,140 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 10 [2022-11-02 21:07:53,175 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 0 proven. 112 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:07:53,176 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 21:07:53,609 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 19 [2022-11-02 21:07:53,615 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 39 treesize of output 32 [2022-11-02 21:07:53,726 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 0 proven. 112 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:07:53,726 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1357519785] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 21:07:53,727 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 21:07:53,727 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18, 18] total 37 [2022-11-02 21:07:53,727 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [235097179] [2022-11-02 21:07:53,727 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 21:07:53,728 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-02 21:07:53,728 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:07:53,728 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 31 times [2022-11-02 21:07:53,728 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:07:53,728 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1853756930] [2022-11-02 21:07:53,729 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:07:53,729 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:07:53,739 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:07:53,739 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:07:53,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:07:53,743 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:07:53,797 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 21:07:53,798 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2022-11-02 21:07:53,798 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=122, Invalid=1284, Unknown=0, NotChecked=0, Total=1406 [2022-11-02 21:07:53,799 INFO L87 Difference]: Start difference. First operand 55 states and 71 transitions. cyclomatic complexity: 20 Second operand has 38 states, 37 states have (on average 2.081081081081081) internal successors, (77), 38 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:07:54,651 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 21:07:54,651 INFO L93 Difference]: Finished difference Result 78 states and 97 transitions. [2022-11-02 21:07:54,652 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 78 states and 97 transitions. [2022-11-02 21:07:54,652 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-02 21:07:54,653 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 78 states to 77 states and 96 transitions. [2022-11-02 21:07:54,653 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18 [2022-11-02 21:07:54,653 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18 [2022-11-02 21:07:54,653 INFO L73 IsDeterministic]: Start isDeterministic. Operand 77 states and 96 transitions. [2022-11-02 21:07:54,653 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-02 21:07:54,653 INFO L218 hiAutomatonCegarLoop]: Abstraction has 77 states and 96 transitions. [2022-11-02 21:07:54,653 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 77 states and 96 transitions. [2022-11-02 21:07:54,654 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 77 to 61. [2022-11-02 21:07:54,655 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 61 states, 61 states have (on average 1.278688524590164) internal successors, (78), 60 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:07:54,655 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 61 states to 61 states and 78 transitions. [2022-11-02 21:07:54,655 INFO L240 hiAutomatonCegarLoop]: Abstraction has 61 states and 78 transitions. [2022-11-02 21:07:54,656 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2022-11-02 21:07:54,656 INFO L428 stractBuchiCegarLoop]: Abstraction has 61 states and 78 transitions. [2022-11-02 21:07:54,656 INFO L335 stractBuchiCegarLoop]: ======== Iteration 34 ============ [2022-11-02 21:07:54,656 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 61 states and 78 transitions. [2022-11-02 21:07:54,657 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:07:54,657 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 21:07:54,657 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 21:07:54,657 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [7, 7, 7, 7, 6, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 21:07:54,657 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-02 21:07:54,658 INFO L748 eck$LassoCheckResult]: Stem: 9099#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 9100#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 9110#L367 assume !(main_~length~0#1 < 1); 9101#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 9102#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 9103#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9111#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 9116#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9112#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9113#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 9159#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9158#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9157#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 9156#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9155#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9154#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 9153#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9152#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9151#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 9150#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9149#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9148#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 9147#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9146#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9143#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 9144#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9136#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 9135#L370-4 main_~j~0#1 := 0; 9114#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9106#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9107#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9130#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9129#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9128#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9127#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9126#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9125#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9124#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9123#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9121#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9120#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9104#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 9105#L378-2 [2022-11-02 21:07:54,658 INFO L750 eck$LassoCheckResult]: Loop: 9105#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9122#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 9105#L378-2 [2022-11-02 21:07:54,658 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:07:54,658 INFO L85 PathProgramCache]: Analyzing trace with hash -747494851, now seen corresponding path program 10 times [2022-11-02 21:07:54,658 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:07:54,658 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [265302385] [2022-11-02 21:07:54,658 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:07:54,658 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:07:54,679 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 21:07:55,196 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 0 proven. 112 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:07:55,196 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 21:07:55,197 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [265302385] [2022-11-02 21:07:55,197 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [265302385] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 21:07:55,197 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1023789774] [2022-11-02 21:07:55,197 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-02 21:07:55,197 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 21:07:55,197 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:07:55,205 INFO L229 MonitoredProcess]: Starting monitored process 54 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 21:07:55,223 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (54)] Waiting until timeout for monitored process [2022-11-02 21:07:55,355 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-02 21:07:55,355 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-02 21:07:55,357 INFO L263 TraceCheckSpWp]: Trace formula consists of 192 conjuncts, 34 conjunts are in the unsatisfiable core [2022-11-02 21:07:55,359 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 21:07:55,437 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-02 21:07:55,832 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2022-11-02 21:07:55,835 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 0 proven. 112 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:07:55,835 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 21:07:55,975 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 14 [2022-11-02 21:07:55,979 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 20 [2022-11-02 21:07:56,068 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 0 proven. 112 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:07:56,068 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1023789774] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 21:07:56,068 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 21:07:56,069 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 18, 18] total 28 [2022-11-02 21:07:56,069 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2097588285] [2022-11-02 21:07:56,069 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 21:07:56,069 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-02 21:07:56,070 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:07:56,070 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 32 times [2022-11-02 21:07:56,070 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:07:56,070 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1019967247] [2022-11-02 21:07:56,070 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:07:56,071 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:07:56,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:07:56,074 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:07:56,075 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:07:56,077 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:07:56,131 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 21:07:56,132 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2022-11-02 21:07:56,132 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=84, Invalid=728, Unknown=0, NotChecked=0, Total=812 [2022-11-02 21:07:56,133 INFO L87 Difference]: Start difference. First operand 61 states and 78 transitions. cyclomatic complexity: 21 Second operand has 29 states, 28 states have (on average 2.2142857142857144) internal successors, (62), 29 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:07:56,736 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 21:07:56,736 INFO L93 Difference]: Finished difference Result 92 states and 111 transitions. [2022-11-02 21:07:56,736 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 92 states and 111 transitions. [2022-11-02 21:07:56,737 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-02 21:07:56,738 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 92 states to 91 states and 110 transitions. [2022-11-02 21:07:56,738 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 20 [2022-11-02 21:07:56,738 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 20 [2022-11-02 21:07:56,738 INFO L73 IsDeterministic]: Start isDeterministic. Operand 91 states and 110 transitions. [2022-11-02 21:07:56,738 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-02 21:07:56,739 INFO L218 hiAutomatonCegarLoop]: Abstraction has 91 states and 110 transitions. [2022-11-02 21:07:56,739 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 91 states and 110 transitions. [2022-11-02 21:07:56,740 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 91 to 61. [2022-11-02 21:07:56,740 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 61 states, 61 states have (on average 1.278688524590164) internal successors, (78), 60 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:07:56,741 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 61 states to 61 states and 78 transitions. [2022-11-02 21:07:56,741 INFO L240 hiAutomatonCegarLoop]: Abstraction has 61 states and 78 transitions. [2022-11-02 21:07:56,741 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2022-11-02 21:07:56,742 INFO L428 stractBuchiCegarLoop]: Abstraction has 61 states and 78 transitions. [2022-11-02 21:07:56,742 INFO L335 stractBuchiCegarLoop]: ======== Iteration 35 ============ [2022-11-02 21:07:56,742 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 61 states and 78 transitions. [2022-11-02 21:07:56,742 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:07:56,743 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 21:07:56,743 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 21:07:56,743 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [8, 8, 7, 6, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 21:07:56,743 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-02 21:07:56,744 INFO L748 eck$LassoCheckResult]: Stem: 9532#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 9533#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 9543#L367 assume !(main_~length~0#1 < 1); 9534#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 9535#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 9536#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9544#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 9549#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9545#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9546#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 9591#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9590#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9589#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 9588#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9587#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9586#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 9585#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9584#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9583#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 9582#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9581#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9580#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 9579#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9578#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9576#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9577#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9572#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9566#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 9567#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9565#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 9564#L370-4 main_~j~0#1 := 0; 9563#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9562#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9561#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9560#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9559#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9558#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9557#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9556#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9555#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9553#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9552#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9537#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 9538#L378-2 [2022-11-02 21:07:56,744 INFO L750 eck$LassoCheckResult]: Loop: 9538#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9554#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 9538#L378-2 [2022-11-02 21:07:56,744 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:07:56,744 INFO L85 PathProgramCache]: Analyzing trace with hash 1828556400, now seen corresponding path program 18 times [2022-11-02 21:07:56,745 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:07:56,745 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [992561982] [2022-11-02 21:07:56,745 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:07:56,745 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:07:56,767 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 21:07:57,464 INFO L134 CoverageAnalysis]: Checked inductivity of 122 backedges. 0 proven. 122 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:07:57,464 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 21:07:57,464 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [992561982] [2022-11-02 21:07:57,464 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [992561982] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 21:07:57,465 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1986166331] [2022-11-02 21:07:57,465 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-11-02 21:07:57,465 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 21:07:57,465 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:07:57,468 INFO L229 MonitoredProcess]: Starting monitored process 55 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 21:07:57,496 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (55)] Waiting until timeout for monitored process [2022-11-02 21:07:57,947 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 9 check-sat command(s) [2022-11-02 21:07:57,948 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-02 21:07:57,950 INFO L263 TraceCheckSpWp]: Trace formula consists of 219 conjuncts, 44 conjunts are in the unsatisfiable core [2022-11-02 21:07:57,952 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 21:07:58,005 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-02 21:07:58,097 INFO L356 Elim1Store]: treesize reduction 23, result has 28.1 percent of original size [2022-11-02 21:07:58,098 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2022-11-02 21:07:58,117 INFO L356 Elim1Store]: treesize reduction 23, result has 28.1 percent of original size [2022-11-02 21:07:58,117 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2022-11-02 21:07:58,196 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-02 21:07:58,226 INFO L356 Elim1Store]: treesize reduction 36, result has 49.3 percent of original size [2022-11-02 21:07:58,226 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 2 case distinctions, treesize of input 36 treesize of output 52 [2022-11-02 21:07:59,879 INFO L356 Elim1Store]: treesize reduction 9, result has 10.0 percent of original size [2022-11-02 21:07:59,879 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 31 treesize of output 11 [2022-11-02 21:07:59,882 INFO L134 CoverageAnalysis]: Checked inductivity of 122 backedges. 0 proven. 122 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:07:59,882 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 21:08:02,702 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 14 [2022-11-02 21:08:02,705 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 20 [2022-11-02 21:08:02,769 INFO L134 CoverageAnalysis]: Checked inductivity of 122 backedges. 2 proven. 115 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2022-11-02 21:08:02,770 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1986166331] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 21:08:02,770 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 21:08:02,770 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 20, 17] total 32 [2022-11-02 21:08:02,770 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1826561747] [2022-11-02 21:08:02,770 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 21:08:02,771 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-02 21:08:02,771 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:08:02,771 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 33 times [2022-11-02 21:08:02,771 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:08:02,771 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1386043174] [2022-11-02 21:08:02,771 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:08:02,771 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:08:02,774 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:08:02,775 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:08:02,775 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:08:02,777 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:08:02,855 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 21:08:02,856 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2022-11-02 21:08:02,857 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=127, Invalid=929, Unknown=0, NotChecked=0, Total=1056 [2022-11-02 21:08:02,857 INFO L87 Difference]: Start difference. First operand 61 states and 78 transitions. cyclomatic complexity: 21 Second operand has 33 states, 32 states have (on average 2.25) internal successors, (72), 33 states have internal predecessors, (72), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:08:04,251 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 21:08:04,251 INFO L93 Difference]: Finished difference Result 110 states and 130 transitions. [2022-11-02 21:08:04,251 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 110 states and 130 transitions. [2022-11-02 21:08:04,252 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:08:04,253 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 110 states to 109 states and 128 transitions. [2022-11-02 21:08:04,253 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19 [2022-11-02 21:08:04,253 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19 [2022-11-02 21:08:04,253 INFO L73 IsDeterministic]: Start isDeterministic. Operand 109 states and 128 transitions. [2022-11-02 21:08:04,253 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-02 21:08:04,253 INFO L218 hiAutomatonCegarLoop]: Abstraction has 109 states and 128 transitions. [2022-11-02 21:08:04,254 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 109 states and 128 transitions. [2022-11-02 21:08:04,255 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 109 to 51. [2022-11-02 21:08:04,255 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 51 states, 51 states have (on average 1.2352941176470589) internal successors, (63), 50 states have internal predecessors, (63), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:08:04,255 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51 states to 51 states and 63 transitions. [2022-11-02 21:08:04,255 INFO L240 hiAutomatonCegarLoop]: Abstraction has 51 states and 63 transitions. [2022-11-02 21:08:04,258 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2022-11-02 21:08:04,258 INFO L428 stractBuchiCegarLoop]: Abstraction has 51 states and 63 transitions. [2022-11-02 21:08:04,258 INFO L335 stractBuchiCegarLoop]: ======== Iteration 36 ============ [2022-11-02 21:08:04,258 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 51 states and 63 transitions. [2022-11-02 21:08:04,259 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:08:04,259 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 21:08:04,259 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 21:08:04,259 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [8, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 21:08:04,259 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-02 21:08:04,260 INFO L748 eck$LassoCheckResult]: Stem: 9999#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 10000#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 10010#L367 assume !(main_~length~0#1 < 1); 10001#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 10002#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 10003#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10011#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 10017#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10012#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10013#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 10016#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10049#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10048#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 10047#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10046#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10045#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 10044#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10043#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10042#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 10041#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10040#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10039#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 10038#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10037#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10036#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 10032#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10024#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 10008#L370-4 main_~j~0#1 := 0; 10009#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10006#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10007#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10015#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10031#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10030#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10029#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10028#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10027#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10026#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10023#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10022#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10021#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10019#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10018#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10004#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 10005#L378-2 [2022-11-02 21:08:04,260 INFO L750 eck$LassoCheckResult]: Loop: 10005#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10020#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 10005#L378-2 [2022-11-02 21:08:04,260 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:08:04,260 INFO L85 PathProgramCache]: Analyzing trace with hash -1083010110, now seen corresponding path program 11 times [2022-11-02 21:08:04,260 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:08:04,261 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [103996486] [2022-11-02 21:08:04,261 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:08:04,261 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:08:04,278 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 21:08:04,582 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 43 proven. 83 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:08:04,582 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 21:08:04,582 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [103996486] [2022-11-02 21:08:04,583 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [103996486] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 21:08:04,583 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1800328460] [2022-11-02 21:08:04,583 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-02 21:08:04,583 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 21:08:04,583 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:08:04,587 INFO L229 MonitoredProcess]: Starting monitored process 56 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 21:08:04,617 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (56)] Waiting until timeout for monitored process [2022-11-02 21:08:04,835 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 8 check-sat command(s) [2022-11-02 21:08:04,836 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-02 21:08:04,838 INFO L263 TraceCheckSpWp]: Trace formula consists of 219 conjuncts, 18 conjunts are in the unsatisfiable core [2022-11-02 21:08:04,839 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 21:08:05,143 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 56 proven. 70 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:08:05,143 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 21:08:05,375 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 49 proven. 77 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:08:05,376 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1800328460] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 21:08:05,376 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 21:08:05,376 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19] total 29 [2022-11-02 21:08:05,376 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [618206339] [2022-11-02 21:08:05,376 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 21:08:05,377 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-02 21:08:05,377 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:08:05,377 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 34 times [2022-11-02 21:08:05,377 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:08:05,377 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [994683082] [2022-11-02 21:08:05,377 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:08:05,377 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:08:05,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:08:05,382 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:08:05,383 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:08:05,386 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:08:05,435 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 21:08:05,435 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2022-11-02 21:08:05,436 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=194, Invalid=618, Unknown=0, NotChecked=0, Total=812 [2022-11-02 21:08:05,436 INFO L87 Difference]: Start difference. First operand 51 states and 63 transitions. cyclomatic complexity: 15 Second operand has 29 states, 29 states have (on average 2.2758620689655173) internal successors, (66), 29 states have internal predecessors, (66), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:08:05,680 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 21:08:05,680 INFO L93 Difference]: Finished difference Result 65 states and 77 transitions. [2022-11-02 21:08:05,680 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 65 states and 77 transitions. [2022-11-02 21:08:05,681 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:08:05,681 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 65 states to 49 states and 61 transitions. [2022-11-02 21:08:05,681 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11 [2022-11-02 21:08:05,681 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11 [2022-11-02 21:08:05,682 INFO L73 IsDeterministic]: Start isDeterministic. Operand 49 states and 61 transitions. [2022-11-02 21:08:05,682 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-02 21:08:05,682 INFO L218 hiAutomatonCegarLoop]: Abstraction has 49 states and 61 transitions. [2022-11-02 21:08:05,682 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49 states and 61 transitions. [2022-11-02 21:08:05,683 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49 to 47. [2022-11-02 21:08:05,683 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 47 states, 47 states have (on average 1.2340425531914894) internal successors, (58), 46 states have internal predecessors, (58), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:08:05,684 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47 states to 47 states and 58 transitions. [2022-11-02 21:08:05,684 INFO L240 hiAutomatonCegarLoop]: Abstraction has 47 states and 58 transitions. [2022-11-02 21:08:05,689 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2022-11-02 21:08:05,690 INFO L428 stractBuchiCegarLoop]: Abstraction has 47 states and 58 transitions. [2022-11-02 21:08:05,690 INFO L335 stractBuchiCegarLoop]: ======== Iteration 37 ============ [2022-11-02 21:08:05,690 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 47 states and 58 transitions. [2022-11-02 21:08:05,692 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:08:05,692 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 21:08:05,692 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 21:08:05,692 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [8, 8, 8, 7, 6, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 21:08:05,693 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-02 21:08:05,693 INFO L748 eck$LassoCheckResult]: Stem: 10423#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 10424#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 10434#L367 assume !(main_~length~0#1 < 1); 10425#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 10426#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 10427#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10435#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 10438#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10436#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10437#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 10469#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10468#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10467#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 10466#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10465#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10464#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 10463#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10462#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10461#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 10460#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10459#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10458#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 10457#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10456#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10455#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 10454#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10453#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10441#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 10442#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10440#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 10428#L370-4 main_~j~0#1 := 0; 10429#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10432#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10433#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10439#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10452#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10451#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10450#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10449#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10448#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10447#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10446#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10445#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10444#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10430#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 10431#L378-2 [2022-11-02 21:08:05,693 INFO L750 eck$LassoCheckResult]: Loop: 10431#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10443#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 10431#L378-2 [2022-11-02 21:08:05,693 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:08:05,694 INFO L85 PathProgramCache]: Analyzing trace with hash 1023781431, now seen corresponding path program 12 times [2022-11-02 21:08:05,694 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:08:05,694 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1338134700] [2022-11-02 21:08:05,694 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:08:05,696 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:08:05,719 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 21:08:06,336 INFO L134 CoverageAnalysis]: Checked inductivity of 134 backedges. 0 proven. 134 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:08:06,337 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 21:08:06,337 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1338134700] [2022-11-02 21:08:06,337 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1338134700] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 21:08:06,337 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [87079539] [2022-11-02 21:08:06,337 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-11-02 21:08:06,337 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 21:08:06,337 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:08:06,339 INFO L229 MonitoredProcess]: Starting monitored process 57 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 21:08:06,340 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (57)] Waiting until timeout for monitored process [2022-11-02 21:08:06,568 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 9 check-sat command(s) [2022-11-02 21:08:06,568 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-02 21:08:06,571 INFO L263 TraceCheckSpWp]: Trace formula consists of 222 conjuncts, 37 conjunts are in the unsatisfiable core [2022-11-02 21:08:06,572 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 21:08:06,634 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-02 21:08:06,748 INFO L356 Elim1Store]: treesize reduction 29, result has 27.5 percent of original size [2022-11-02 21:08:06,749 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 26 [2022-11-02 21:08:07,031 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2022-11-02 21:08:07,033 INFO L134 CoverageAnalysis]: Checked inductivity of 134 backedges. 0 proven. 134 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:08:07,034 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 21:08:07,284 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 19 [2022-11-02 21:08:07,287 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 25 [2022-11-02 21:08:07,366 INFO L134 CoverageAnalysis]: Checked inductivity of 134 backedges. 0 proven. 134 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:08:07,366 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [87079539] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 21:08:07,366 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 21:08:07,367 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20, 20] total 31 [2022-11-02 21:08:07,367 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1916927752] [2022-11-02 21:08:07,367 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 21:08:07,367 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-02 21:08:07,367 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:08:07,367 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 35 times [2022-11-02 21:08:07,368 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:08:07,368 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [791965119] [2022-11-02 21:08:07,368 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:08:07,368 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:08:07,371 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:08:07,371 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:08:07,373 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:08:07,375 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:08:07,426 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 21:08:07,426 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2022-11-02 21:08:07,427 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=91, Invalid=901, Unknown=0, NotChecked=0, Total=992 [2022-11-02 21:08:07,427 INFO L87 Difference]: Start difference. First operand 47 states and 58 transitions. cyclomatic complexity: 14 Second operand has 32 states, 31 states have (on average 2.161290322580645) internal successors, (67), 32 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:08:08,033 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 21:08:08,033 INFO L93 Difference]: Finished difference Result 71 states and 86 transitions. [2022-11-02 21:08:08,033 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 71 states and 86 transitions. [2022-11-02 21:08:08,034 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-02 21:08:08,034 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 71 states to 70 states and 85 transitions. [2022-11-02 21:08:08,034 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16 [2022-11-02 21:08:08,034 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16 [2022-11-02 21:08:08,035 INFO L73 IsDeterministic]: Start isDeterministic. Operand 70 states and 85 transitions. [2022-11-02 21:08:08,035 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-02 21:08:08,035 INFO L218 hiAutomatonCegarLoop]: Abstraction has 70 states and 85 transitions. [2022-11-02 21:08:08,035 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 70 states and 85 transitions. [2022-11-02 21:08:08,036 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 70 to 54. [2022-11-02 21:08:08,036 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 54 states, 54 states have (on average 1.2407407407407407) internal successors, (67), 53 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:08:08,037 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54 states to 54 states and 67 transitions. [2022-11-02 21:08:08,037 INFO L240 hiAutomatonCegarLoop]: Abstraction has 54 states and 67 transitions. [2022-11-02 21:08:08,045 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2022-11-02 21:08:08,046 INFO L428 stractBuchiCegarLoop]: Abstraction has 54 states and 67 transitions. [2022-11-02 21:08:08,047 INFO L335 stractBuchiCegarLoop]: ======== Iteration 38 ============ [2022-11-02 21:08:08,047 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 54 states and 67 transitions. [2022-11-02 21:08:08,047 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:08:08,047 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 21:08:08,047 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 21:08:08,048 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [8, 8, 8, 8, 7, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 21:08:08,048 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-02 21:08:08,048 INFO L748 eck$LassoCheckResult]: Stem: 10843#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 10844#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 10854#L367 assume !(main_~length~0#1 < 1); 10845#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 10846#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 10847#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10855#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 10881#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10856#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10857#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 10858#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10861#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10880#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 10879#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10878#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10877#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 10876#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10875#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10874#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 10873#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10872#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10871#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 10870#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10869#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10868#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 10867#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10866#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10865#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 10864#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10862#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 10848#L370-4 main_~j~0#1 := 0; 10849#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10893#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10860#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10852#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10853#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10892#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10891#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10890#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10889#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10888#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10887#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10886#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10885#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10884#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10883#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10850#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 10851#L378-2 [2022-11-02 21:08:08,049 INFO L750 eck$LassoCheckResult]: Loop: 10851#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10882#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 10851#L378-2 [2022-11-02 21:08:08,049 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:08:08,049 INFO L85 PathProgramCache]: Analyzing trace with hash 306447676, now seen corresponding path program 13 times [2022-11-02 21:08:08,049 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:08:08,049 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [199449072] [2022-11-02 21:08:08,049 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:08:08,050 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:08:08,069 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 21:08:08,650 INFO L134 CoverageAnalysis]: Checked inductivity of 148 backedges. 0 proven. 148 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:08:08,650 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 21:08:08,650 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [199449072] [2022-11-02 21:08:08,650 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [199449072] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 21:08:08,650 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [808498932] [2022-11-02 21:08:08,650 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-11-02 21:08:08,651 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 21:08:08,651 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:08:08,657 INFO L229 MonitoredProcess]: Starting monitored process 58 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 21:08:08,678 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (58)] Waiting until timeout for monitored process [2022-11-02 21:08:08,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 21:08:08,839 INFO L263 TraceCheckSpWp]: Trace formula consists of 233 conjuncts, 42 conjunts are in the unsatisfiable core [2022-11-02 21:08:08,841 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 21:08:09,221 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 9 [2022-11-02 21:08:09,791 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-02 21:08:09,793 INFO L134 CoverageAnalysis]: Checked inductivity of 148 backedges. 0 proven. 148 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:08:09,793 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 21:08:09,964 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 14 [2022-11-02 21:08:09,967 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 20 [2022-11-02 21:08:10,059 INFO L134 CoverageAnalysis]: Checked inductivity of 148 backedges. 0 proven. 148 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:08:10,059 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [808498932] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 21:08:10,060 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 21:08:10,060 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21, 20] total 42 [2022-11-02 21:08:10,060 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1074708436] [2022-11-02 21:08:10,060 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 21:08:10,060 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-02 21:08:10,061 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:08:10,061 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 36 times [2022-11-02 21:08:10,061 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:08:10,061 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [299170354] [2022-11-02 21:08:10,061 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:08:10,061 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:08:10,064 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:08:10,064 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:08:10,066 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:08:10,067 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:08:10,122 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 21:08:10,123 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 43 interpolants. [2022-11-02 21:08:10,123 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=154, Invalid=1652, Unknown=0, NotChecked=0, Total=1806 [2022-11-02 21:08:10,123 INFO L87 Difference]: Start difference. First operand 54 states and 67 transitions. cyclomatic complexity: 16 Second operand has 43 states, 42 states have (on average 2.2857142857142856) internal successors, (96), 43 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:08:11,116 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 21:08:11,116 INFO L93 Difference]: Finished difference Result 107 states and 132 transitions. [2022-11-02 21:08:11,116 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 107 states and 132 transitions. [2022-11-02 21:08:11,117 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 18 [2022-11-02 21:08:11,118 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 107 states to 106 states and 131 transitions. [2022-11-02 21:08:11,118 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 35 [2022-11-02 21:08:11,118 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 35 [2022-11-02 21:08:11,118 INFO L73 IsDeterministic]: Start isDeterministic. Operand 106 states and 131 transitions. [2022-11-02 21:08:11,118 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-02 21:08:11,118 INFO L218 hiAutomatonCegarLoop]: Abstraction has 106 states and 131 transitions. [2022-11-02 21:08:11,119 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 106 states and 131 transitions. [2022-11-02 21:08:11,121 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 106 to 90. [2022-11-02 21:08:11,121 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 90 states, 90 states have (on average 1.2555555555555555) internal successors, (113), 89 states have internal predecessors, (113), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:08:11,121 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 90 states to 90 states and 113 transitions. [2022-11-02 21:08:11,121 INFO L240 hiAutomatonCegarLoop]: Abstraction has 90 states and 113 transitions. [2022-11-02 21:08:11,122 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2022-11-02 21:08:11,122 INFO L428 stractBuchiCegarLoop]: Abstraction has 90 states and 113 transitions. [2022-11-02 21:08:11,122 INFO L335 stractBuchiCegarLoop]: ======== Iteration 39 ============ [2022-11-02 21:08:11,123 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 90 states and 113 transitions. [2022-11-02 21:08:11,123 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 16 [2022-11-02 21:08:11,123 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 21:08:11,123 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 21:08:11,124 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [9, 9, 8, 7, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 21:08:11,124 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-02 21:08:11,124 INFO L748 eck$LassoCheckResult]: Stem: 11334#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 11335#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 11345#L367 assume !(main_~length~0#1 < 1); 11336#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 11337#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 11338#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11346#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 11349#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11347#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11348#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 11352#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11353#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11372#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 11371#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11370#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11369#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 11368#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11367#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11366#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 11365#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11364#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11363#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 11362#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11361#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11360#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 11359#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11357#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11358#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 11399#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11397#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11395#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11356#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11354#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 11339#L370-4 main_~j~0#1 := 0; 11340#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11407#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11406#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11405#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11404#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11403#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11402#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11401#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11400#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11376#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11379#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11377#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11378#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11380#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 11342#L378-2 [2022-11-02 21:08:11,125 INFO L750 eck$LassoCheckResult]: Loop: 11342#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11373#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 11342#L378-2 [2022-11-02 21:08:11,125 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:08:11,125 INFO L85 PathProgramCache]: Analyzing trace with hash -1153522753, now seen corresponding path program 19 times [2022-11-02 21:08:11,125 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:08:11,126 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1114960280] [2022-11-02 21:08:11,126 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:08:11,126 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:08:11,156 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 21:08:11,964 INFO L134 CoverageAnalysis]: Checked inductivity of 159 backedges. 0 proven. 159 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:08:11,964 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 21:08:11,964 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1114960280] [2022-11-02 21:08:11,965 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1114960280] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 21:08:11,965 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1429620547] [2022-11-02 21:08:11,965 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-11-02 21:08:11,965 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 21:08:11,965 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:08:11,973 INFO L229 MonitoredProcess]: Starting monitored process 59 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 21:08:11,997 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (59)] Waiting until timeout for monitored process [2022-11-02 21:08:12,155 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 21:08:12,158 INFO L263 TraceCheckSpWp]: Trace formula consists of 244 conjuncts, 46 conjunts are in the unsatisfiable core [2022-11-02 21:08:12,161 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 21:08:12,502 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-02 21:08:12,657 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-02 21:08:12,658 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-02 21:08:12,726 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-02 21:08:12,726 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-02 21:08:12,741 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-02 21:08:12,742 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-02 21:08:13,261 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-02 21:08:13,264 INFO L134 CoverageAnalysis]: Checked inductivity of 159 backedges. 2 proven. 157 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:08:13,264 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 21:08:13,603 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 19 [2022-11-02 21:08:13,606 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 25 [2022-11-02 21:08:13,675 INFO L134 CoverageAnalysis]: Checked inductivity of 159 backedges. 1 proven. 157 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-02 21:08:13,675 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1429620547] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 21:08:13,675 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 21:08:13,676 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 22, 21] total 44 [2022-11-02 21:08:13,676 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [88193401] [2022-11-02 21:08:13,676 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 21:08:13,676 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-02 21:08:13,677 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:08:13,677 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 37 times [2022-11-02 21:08:13,677 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:08:13,677 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1436570270] [2022-11-02 21:08:13,677 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:08:13,677 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:08:13,680 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:08:13,680 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:08:13,681 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:08:13,682 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:08:13,731 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 21:08:13,732 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 45 interpolants. [2022-11-02 21:08:13,733 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=174, Invalid=1806, Unknown=0, NotChecked=0, Total=1980 [2022-11-02 21:08:13,733 INFO L87 Difference]: Start difference. First operand 90 states and 113 transitions. cyclomatic complexity: 28 Second operand has 45 states, 44 states have (on average 2.2954545454545454) internal successors, (101), 45 states have internal predecessors, (101), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:08:14,625 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 21:08:14,625 INFO L93 Difference]: Finished difference Result 88 states and 103 transitions. [2022-11-02 21:08:14,625 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 88 states and 103 transitions. [2022-11-02 21:08:14,626 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:08:14,626 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 88 states to 86 states and 101 transitions. [2022-11-02 21:08:14,626 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15 [2022-11-02 21:08:14,627 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15 [2022-11-02 21:08:14,627 INFO L73 IsDeterministic]: Start isDeterministic. Operand 86 states and 101 transitions. [2022-11-02 21:08:14,627 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-02 21:08:14,627 INFO L218 hiAutomatonCegarLoop]: Abstraction has 86 states and 101 transitions. [2022-11-02 21:08:14,627 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 86 states and 101 transitions. [2022-11-02 21:08:14,628 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 86 to 57. [2022-11-02 21:08:14,629 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 57 states, 57 states have (on average 1.2456140350877194) internal successors, (71), 56 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:08:14,629 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 57 states to 57 states and 71 transitions. [2022-11-02 21:08:14,629 INFO L240 hiAutomatonCegarLoop]: Abstraction has 57 states and 71 transitions. [2022-11-02 21:08:14,631 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2022-11-02 21:08:14,631 INFO L428 stractBuchiCegarLoop]: Abstraction has 57 states and 71 transitions. [2022-11-02 21:08:14,631 INFO L335 stractBuchiCegarLoop]: ======== Iteration 40 ============ [2022-11-02 21:08:14,631 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 57 states and 71 transitions. [2022-11-02 21:08:14,632 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:08:14,632 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 21:08:14,632 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 21:08:14,633 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [9, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 21:08:14,633 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-02 21:08:14,633 INFO L748 eck$LassoCheckResult]: Stem: 11860#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 11861#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 11871#L367 assume !(main_~length~0#1 < 1); 11862#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 11863#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 11864#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11872#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 11907#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11873#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11874#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 11875#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11878#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11906#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 11905#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11904#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11903#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 11902#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11901#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11900#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 11899#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11898#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11897#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 11896#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11895#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11894#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 11893#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11892#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11890#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 11888#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11885#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 11865#L370-4 main_~j~0#1 := 0; 11866#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11912#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11877#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11869#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11870#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11911#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11910#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11909#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11908#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11891#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11889#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11887#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11884#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11883#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11882#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11881#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11880#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11867#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 11868#L378-2 [2022-11-02 21:08:14,633 INFO L750 eck$LassoCheckResult]: Loop: 11868#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11879#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 11868#L378-2 [2022-11-02 21:08:14,634 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:08:14,634 INFO L85 PathProgramCache]: Analyzing trace with hash -1856523519, now seen corresponding path program 14 times [2022-11-02 21:08:14,634 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:08:14,634 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1270998420] [2022-11-02 21:08:14,634 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:08:14,635 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:08:14,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 21:08:15,014 INFO L134 CoverageAnalysis]: Checked inductivity of 164 backedges. 57 proven. 107 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:08:15,014 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 21:08:15,014 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1270998420] [2022-11-02 21:08:15,014 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1270998420] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 21:08:15,014 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1731940288] [2022-11-02 21:08:15,015 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-02 21:08:15,015 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 21:08:15,015 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:08:15,021 INFO L229 MonitoredProcess]: Starting monitored process 60 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 21:08:15,041 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (60)] Waiting until timeout for monitored process [2022-11-02 21:08:15,207 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-02 21:08:15,207 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-02 21:08:15,208 INFO L263 TraceCheckSpWp]: Trace formula consists of 244 conjuncts, 20 conjunts are in the unsatisfiable core [2022-11-02 21:08:15,209 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 21:08:15,537 INFO L134 CoverageAnalysis]: Checked inductivity of 164 backedges. 72 proven. 92 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:08:15,538 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 21:08:15,780 INFO L134 CoverageAnalysis]: Checked inductivity of 164 backedges. 72 proven. 92 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:08:15,781 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1731940288] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 21:08:15,781 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 21:08:15,781 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21, 21] total 32 [2022-11-02 21:08:15,781 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [215088271] [2022-11-02 21:08:15,781 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 21:08:15,781 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-02 21:08:15,782 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:08:15,782 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 38 times [2022-11-02 21:08:15,782 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:08:15,782 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1579036652] [2022-11-02 21:08:15,782 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:08:15,782 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:08:15,785 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:08:15,786 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:08:15,787 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:08:15,789 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:08:15,836 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 21:08:15,837 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2022-11-02 21:08:15,837 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=235, Invalid=757, Unknown=0, NotChecked=0, Total=992 [2022-11-02 21:08:15,837 INFO L87 Difference]: Start difference. First operand 57 states and 71 transitions. cyclomatic complexity: 18 Second operand has 32 states, 32 states have (on average 2.3125) internal successors, (74), 32 states have internal predecessors, (74), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:08:16,113 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 21:08:16,113 INFO L93 Difference]: Finished difference Result 80 states and 95 transitions. [2022-11-02 21:08:16,113 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 80 states and 95 transitions. [2022-11-02 21:08:16,113 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:08:16,114 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 80 states to 62 states and 77 transitions. [2022-11-02 21:08:16,114 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-02 21:08:16,114 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-02 21:08:16,114 INFO L73 IsDeterministic]: Start isDeterministic. Operand 62 states and 77 transitions. [2022-11-02 21:08:16,114 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-02 21:08:16,114 INFO L218 hiAutomatonCegarLoop]: Abstraction has 62 states and 77 transitions. [2022-11-02 21:08:16,114 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 62 states and 77 transitions. [2022-11-02 21:08:16,115 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 62 to 59. [2022-11-02 21:08:16,116 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 59 states, 59 states have (on average 1.2372881355932204) internal successors, (73), 58 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:08:16,116 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 59 states to 59 states and 73 transitions. [2022-11-02 21:08:16,116 INFO L240 hiAutomatonCegarLoop]: Abstraction has 59 states and 73 transitions. [2022-11-02 21:08:16,119 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2022-11-02 21:08:16,120 INFO L428 stractBuchiCegarLoop]: Abstraction has 59 states and 73 transitions. [2022-11-02 21:08:16,120 INFO L335 stractBuchiCegarLoop]: ======== Iteration 41 ============ [2022-11-02 21:08:16,120 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 59 states and 73 transitions. [2022-11-02 21:08:16,120 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:08:16,120 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 21:08:16,120 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 21:08:16,121 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [9, 9, 8, 8, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 21:08:16,121 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-02 21:08:16,121 INFO L748 eck$LassoCheckResult]: Stem: 12340#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 12341#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 12351#L367 assume !(main_~length~0#1 < 1); 12342#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 12343#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 12344#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12352#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12355#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12353#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12354#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12398#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12397#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12396#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12395#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12394#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12393#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12392#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12391#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12390#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12389#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12388#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12387#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12386#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12385#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12384#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12383#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12382#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12381#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12380#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12379#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12374#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12378#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12375#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 12372#L370-4 main_~j~0#1 := 0; 12371#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12356#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12370#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12369#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12368#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12367#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12366#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12365#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12364#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12363#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12362#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12361#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12360#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12358#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12357#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12345#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 12346#L378-2 [2022-11-02 21:08:16,122 INFO L750 eck$LassoCheckResult]: Loop: 12346#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12359#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 12346#L378-2 [2022-11-02 21:08:16,122 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:08:16,122 INFO L85 PathProgramCache]: Analyzing trace with hash -433799996, now seen corresponding path program 20 times [2022-11-02 21:08:16,122 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:08:16,122 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [57591485] [2022-11-02 21:08:16,123 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:08:16,123 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:08:16,147 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 21:08:16,872 INFO L134 CoverageAnalysis]: Checked inductivity of 173 backedges. 0 proven. 173 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:08:16,872 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 21:08:16,872 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [57591485] [2022-11-02 21:08:16,873 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [57591485] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 21:08:16,873 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [341626454] [2022-11-02 21:08:16,873 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-02 21:08:16,873 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 21:08:16,873 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:08:16,879 INFO L229 MonitoredProcess]: Starting monitored process 61 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 21:08:16,885 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (61)] Waiting until timeout for monitored process [2022-11-02 21:08:17,046 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-02 21:08:17,047 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-02 21:08:17,049 INFO L263 TraceCheckSpWp]: Trace formula consists of 255 conjuncts, 43 conjunts are in the unsatisfiable core [2022-11-02 21:08:17,051 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 21:08:17,132 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-02 21:08:17,248 INFO L356 Elim1Store]: treesize reduction 29, result has 27.5 percent of original size [2022-11-02 21:08:17,249 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 26 [2022-11-02 21:08:17,273 INFO L356 Elim1Store]: treesize reduction 29, result has 27.5 percent of original size [2022-11-02 21:08:17,274 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 26 [2022-11-02 21:08:17,593 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2022-11-02 21:08:17,596 INFO L134 CoverageAnalysis]: Checked inductivity of 173 backedges. 0 proven. 173 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:08:17,596 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 21:08:17,882 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 19 [2022-11-02 21:08:17,885 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 25 [2022-11-02 21:08:17,961 INFO L134 CoverageAnalysis]: Checked inductivity of 173 backedges. 0 proven. 173 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:08:17,962 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [341626454] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 21:08:17,962 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 21:08:17,962 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 22, 22] total 34 [2022-11-02 21:08:17,962 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [529880147] [2022-11-02 21:08:17,962 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 21:08:17,962 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-02 21:08:17,962 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:08:17,962 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 39 times [2022-11-02 21:08:17,963 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:08:17,963 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1898773917] [2022-11-02 21:08:17,963 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:08:17,963 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:08:17,966 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:08:17,966 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:08:17,967 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:08:17,969 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:08:18,016 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 21:08:18,017 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2022-11-02 21:08:18,017 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=99, Invalid=1091, Unknown=0, NotChecked=0, Total=1190 [2022-11-02 21:08:18,018 INFO L87 Difference]: Start difference. First operand 59 states and 73 transitions. cyclomatic complexity: 18 Second operand has 35 states, 34 states have (on average 2.2058823529411766) internal successors, (75), 35 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:08:18,939 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 21:08:18,939 INFO L93 Difference]: Finished difference Result 128 states and 151 transitions. [2022-11-02 21:08:18,939 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 128 states and 151 transitions. [2022-11-02 21:08:18,940 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 6 [2022-11-02 21:08:18,941 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 128 states to 127 states and 150 transitions. [2022-11-02 21:08:18,941 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 25 [2022-11-02 21:08:18,941 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 25 [2022-11-02 21:08:18,942 INFO L73 IsDeterministic]: Start isDeterministic. Operand 127 states and 150 transitions. [2022-11-02 21:08:18,942 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-02 21:08:18,942 INFO L218 hiAutomatonCegarLoop]: Abstraction has 127 states and 150 transitions. [2022-11-02 21:08:18,942 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 127 states and 150 transitions. [2022-11-02 21:08:18,944 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 127 to 65. [2022-11-02 21:08:18,944 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 65 states, 65 states have (on average 1.2769230769230768) internal successors, (83), 64 states have internal predecessors, (83), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:08:18,944 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 65 states to 65 states and 83 transitions. [2022-11-02 21:08:18,945 INFO L240 hiAutomatonCegarLoop]: Abstraction has 65 states and 83 transitions. [2022-11-02 21:08:18,949 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2022-11-02 21:08:18,950 INFO L428 stractBuchiCegarLoop]: Abstraction has 65 states and 83 transitions. [2022-11-02 21:08:18,950 INFO L335 stractBuchiCegarLoop]: ======== Iteration 42 ============ [2022-11-02 21:08:18,950 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 65 states and 83 transitions. [2022-11-02 21:08:18,951 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:08:18,951 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 21:08:18,951 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 21:08:18,951 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [9, 9, 9, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 21:08:18,951 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-02 21:08:18,952 INFO L748 eck$LassoCheckResult]: Stem: 12879#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 12880#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 12890#L367 assume !(main_~length~0#1 < 1); 12881#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 12882#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 12883#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12891#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12922#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12892#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12893#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12896#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12897#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12921#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12920#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12919#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12918#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12917#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12916#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12915#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12914#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12913#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12912#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12911#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12910#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12909#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12908#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12907#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12906#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12905#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12903#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12904#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12902#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12942#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 12888#L370-4 main_~j~0#1 := 0; 12889#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12936#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12895#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12886#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12887#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12935#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12934#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12933#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12932#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12931#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12930#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12929#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12928#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12927#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12926#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12924#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12923#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12884#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 12885#L378-2 [2022-11-02 21:08:18,952 INFO L750 eck$LassoCheckResult]: Loop: 12885#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12925#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 12885#L378-2 [2022-11-02 21:08:18,952 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:08:18,953 INFO L85 PathProgramCache]: Analyzing trace with hash -269965175, now seen corresponding path program 21 times [2022-11-02 21:08:18,953 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:08:18,953 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1905971529] [2022-11-02 21:08:18,953 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:08:18,953 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:08:18,974 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 21:08:19,596 INFO L134 CoverageAnalysis]: Checked inductivity of 189 backedges. 0 proven. 189 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:08:19,597 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 21:08:19,597 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1905971529] [2022-11-02 21:08:19,597 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1905971529] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 21:08:19,597 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [933295993] [2022-11-02 21:08:19,597 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-02 21:08:19,597 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 21:08:19,597 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:08:19,600 INFO L229 MonitoredProcess]: Starting monitored process 62 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 21:08:19,628 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (62)] Waiting until timeout for monitored process [2022-11-02 21:08:20,249 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 10 check-sat command(s) [2022-11-02 21:08:20,249 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-02 21:08:20,251 INFO L263 TraceCheckSpWp]: Trace formula consists of 266 conjuncts, 26 conjunts are in the unsatisfiable core [2022-11-02 21:08:20,252 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 21:08:20,525 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-02 21:08:21,386 INFO L356 Elim1Store]: treesize reduction 9, result has 25.0 percent of original size [2022-11-02 21:08:21,386 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 10 [2022-11-02 21:08:21,430 INFO L134 CoverageAnalysis]: Checked inductivity of 189 backedges. 64 proven. 125 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:08:21,430 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 21:08:22,531 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2022-11-02 21:08:22,535 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 28 [2022-11-02 21:08:22,771 INFO L134 CoverageAnalysis]: Checked inductivity of 189 backedges. 56 proven. 133 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:08:22,772 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [933295993] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 21:08:22,772 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 21:08:22,772 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 23, 23] total 56 [2022-11-02 21:08:22,772 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [48443155] [2022-11-02 21:08:22,772 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 21:08:22,773 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-02 21:08:22,773 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:08:22,773 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 40 times [2022-11-02 21:08:22,773 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:08:22,773 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [953549175] [2022-11-02 21:08:22,774 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:08:22,774 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:08:22,776 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:08:22,777 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:08:22,778 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:08:22,780 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:08:22,824 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 21:08:22,825 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 57 interpolants. [2022-11-02 21:08:22,825 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=370, Invalid=2822, Unknown=0, NotChecked=0, Total=3192 [2022-11-02 21:08:22,826 INFO L87 Difference]: Start difference. First operand 65 states and 83 transitions. cyclomatic complexity: 22 Second operand has 57 states, 56 states have (on average 2.1607142857142856) internal successors, (121), 57 states have internal predecessors, (121), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:08:24,187 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 21:08:24,187 INFO L93 Difference]: Finished difference Result 106 states and 125 transitions. [2022-11-02 21:08:24,187 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 106 states and 125 transitions. [2022-11-02 21:08:24,187 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:08:24,188 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 106 states to 83 states and 101 transitions. [2022-11-02 21:08:24,188 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-02 21:08:24,188 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-02 21:08:24,188 INFO L73 IsDeterministic]: Start isDeterministic. Operand 83 states and 101 transitions. [2022-11-02 21:08:24,188 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-02 21:08:24,188 INFO L218 hiAutomatonCegarLoop]: Abstraction has 83 states and 101 transitions. [2022-11-02 21:08:24,189 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 83 states and 101 transitions. [2022-11-02 21:08:24,190 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 83 to 67. [2022-11-02 21:08:24,190 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 67 states, 67 states have (on average 1.2686567164179106) internal successors, (85), 66 states have internal predecessors, (85), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:08:24,190 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 67 states to 67 states and 85 transitions. [2022-11-02 21:08:24,190 INFO L240 hiAutomatonCegarLoop]: Abstraction has 67 states and 85 transitions. [2022-11-02 21:08:24,190 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2022-11-02 21:08:24,191 INFO L428 stractBuchiCegarLoop]: Abstraction has 67 states and 85 transitions. [2022-11-02 21:08:24,191 INFO L335 stractBuchiCegarLoop]: ======== Iteration 43 ============ [2022-11-02 21:08:24,191 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 67 states and 85 transitions. [2022-11-02 21:08:24,191 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:08:24,192 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 21:08:24,192 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 21:08:24,192 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [9, 9, 9, 9, 8, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 21:08:24,192 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-02 21:08:24,192 INFO L748 eck$LassoCheckResult]: Stem: 13484#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 13485#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 13493#L367 assume !(main_~length~0#1 < 1); 13482#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 13483#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 13486#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13494#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13498#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13495#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13496#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13548#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13547#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13546#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13545#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13544#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13543#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13542#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13541#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13540#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13539#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13538#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13537#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13536#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13535#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13534#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13533#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13532#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13531#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13530#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13529#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13528#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13526#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13517#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 13514#L370-4 main_~j~0#1 := 0; 13513#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13512#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13497#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13489#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13490#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13511#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13510#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13509#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13508#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13507#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13506#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13505#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13504#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13503#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13502#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13501#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13500#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13487#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 13488#L378-2 [2022-11-02 21:08:24,193 INFO L750 eck$LassoCheckResult]: Loop: 13488#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13499#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 13488#L378-2 [2022-11-02 21:08:24,193 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:08:24,193 INFO L85 PathProgramCache]: Analyzing trace with hash -51110457, now seen corresponding path program 15 times [2022-11-02 21:08:24,193 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:08:24,193 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [235949314] [2022-11-02 21:08:24,194 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:08:24,194 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:08:24,213 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 21:08:24,803 INFO L134 CoverageAnalysis]: Checked inductivity of 189 backedges. 0 proven. 189 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:08:24,804 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 21:08:24,804 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [235949314] [2022-11-02 21:08:24,804 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [235949314] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 21:08:24,804 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1948002818] [2022-11-02 21:08:24,804 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-02 21:08:24,804 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 21:08:24,805 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:08:24,806 INFO L229 MonitoredProcess]: Starting monitored process 63 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 21:08:24,807 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (63)] Waiting until timeout for monitored process [2022-11-02 21:08:25,134 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 10 check-sat command(s) [2022-11-02 21:08:25,134 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-02 21:08:25,137 INFO L263 TraceCheckSpWp]: Trace formula consists of 258 conjuncts, 27 conjunts are in the unsatisfiable core [2022-11-02 21:08:25,138 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 21:08:25,376 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-02 21:08:26,229 INFO L356 Elim1Store]: treesize reduction 9, result has 25.0 percent of original size [2022-11-02 21:08:26,229 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 10 [2022-11-02 21:08:26,233 INFO L134 CoverageAnalysis]: Checked inductivity of 189 backedges. 64 proven. 125 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:08:26,233 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 21:08:27,713 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2022-11-02 21:08:27,716 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 28 [2022-11-02 21:08:27,962 INFO L134 CoverageAnalysis]: Checked inductivity of 189 backedges. 56 proven. 133 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:08:27,963 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1948002818] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 21:08:27,963 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 21:08:27,963 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 24, 24] total 58 [2022-11-02 21:08:27,963 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1679714615] [2022-11-02 21:08:27,963 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 21:08:27,964 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-02 21:08:27,964 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:08:27,964 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 41 times [2022-11-02 21:08:27,964 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:08:27,964 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [438930701] [2022-11-02 21:08:27,965 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:08:27,965 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:08:27,968 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:08:27,968 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:08:27,969 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:08:27,971 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:08:28,015 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 21:08:28,016 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 59 interpolants. [2022-11-02 21:08:28,017 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=400, Invalid=3021, Unknown=1, NotChecked=0, Total=3422 [2022-11-02 21:08:28,017 INFO L87 Difference]: Start difference. First operand 67 states and 85 transitions. cyclomatic complexity: 22 Second operand has 59 states, 58 states have (on average 2.086206896551724) internal successors, (121), 59 states have internal predecessors, (121), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:08:29,814 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 21:08:29,814 INFO L93 Difference]: Finished difference Result 88 states and 107 transitions. [2022-11-02 21:08:29,814 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 88 states and 107 transitions. [2022-11-02 21:08:29,815 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:08:29,815 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 88 states to 67 states and 84 transitions. [2022-11-02 21:08:29,815 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-02 21:08:29,815 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-02 21:08:29,816 INFO L73 IsDeterministic]: Start isDeterministic. Operand 67 states and 84 transitions. [2022-11-02 21:08:29,816 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-02 21:08:29,816 INFO L218 hiAutomatonCegarLoop]: Abstraction has 67 states and 84 transitions. [2022-11-02 21:08:29,816 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67 states and 84 transitions. [2022-11-02 21:08:29,817 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67 to 67. [2022-11-02 21:08:29,817 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 67 states, 67 states have (on average 1.2537313432835822) internal successors, (84), 66 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:08:29,817 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 67 states to 67 states and 84 transitions. [2022-11-02 21:08:29,817 INFO L240 hiAutomatonCegarLoop]: Abstraction has 67 states and 84 transitions. [2022-11-02 21:08:29,818 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2022-11-02 21:08:29,818 INFO L428 stractBuchiCegarLoop]: Abstraction has 67 states and 84 transitions. [2022-11-02 21:08:29,818 INFO L335 stractBuchiCegarLoop]: ======== Iteration 44 ============ [2022-11-02 21:08:29,819 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 67 states and 84 transitions. [2022-11-02 21:08:29,819 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:08:29,819 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 21:08:29,819 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 21:08:29,820 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [10, 10, 9, 8, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 21:08:29,820 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-02 21:08:29,820 INFO L748 eck$LassoCheckResult]: Stem: 14093#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 14094#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 14104#L367 assume !(main_~length~0#1 < 1); 14095#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 14096#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 14097#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14105#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14159#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14106#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14107#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14108#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14110#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14158#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14157#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14156#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14155#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14154#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14153#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14152#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14151#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14150#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14149#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14148#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14147#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14146#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14145#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14144#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14143#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14142#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14141#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14138#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14136#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14133#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14130#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14131#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14129#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 14126#L370-4 main_~j~0#1 := 0; 14125#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14109#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14124#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14123#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14122#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14121#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14120#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14119#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14118#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14117#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14116#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14115#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14114#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14112#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14111#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14098#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 14099#L378-2 [2022-11-02 21:08:29,820 INFO L750 eck$LassoCheckResult]: Loop: 14099#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14113#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 14099#L378-2 [2022-11-02 21:08:29,820 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:08:29,821 INFO L85 PathProgramCache]: Analyzing trace with hash 687219962, now seen corresponding path program 22 times [2022-11-02 21:08:29,821 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:08:29,821 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1334916651] [2022-11-02 21:08:29,821 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:08:29,821 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:08:29,844 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 21:08:30,674 INFO L134 CoverageAnalysis]: Checked inductivity of 201 backedges. 0 proven. 201 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:08:30,674 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 21:08:30,674 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1334916651] [2022-11-02 21:08:30,674 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1334916651] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 21:08:30,674 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [882086366] [2022-11-02 21:08:30,674 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-02 21:08:30,674 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 21:08:30,675 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:08:30,680 INFO L229 MonitoredProcess]: Starting monitored process 64 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 21:08:30,701 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (64)] Waiting until timeout for monitored process [2022-11-02 21:08:30,857 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-02 21:08:30,858 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-02 21:08:30,860 INFO L263 TraceCheckSpWp]: Trace formula consists of 253 conjuncts, 46 conjunts are in the unsatisfiable core [2022-11-02 21:08:30,862 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 21:08:30,947 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-02 21:08:31,041 INFO L356 Elim1Store]: treesize reduction 23, result has 28.1 percent of original size [2022-11-02 21:08:31,041 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2022-11-02 21:08:31,059 INFO L356 Elim1Store]: treesize reduction 23, result has 28.1 percent of original size [2022-11-02 21:08:31,060 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2022-11-02 21:08:31,118 INFO L356 Elim1Store]: treesize reduction 23, result has 28.1 percent of original size [2022-11-02 21:08:31,119 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2022-11-02 21:08:31,425 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2022-11-02 21:08:31,427 INFO L134 CoverageAnalysis]: Checked inductivity of 201 backedges. 1 proven. 200 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:08:31,427 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 21:08:31,726 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 19 [2022-11-02 21:08:31,729 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 25 [2022-11-02 21:08:31,803 INFO L134 CoverageAnalysis]: Checked inductivity of 201 backedges. 1 proven. 199 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-02 21:08:31,803 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [882086366] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 21:08:31,803 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 21:08:31,803 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23, 23] total 35 [2022-11-02 21:08:31,804 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [495798485] [2022-11-02 21:08:31,804 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 21:08:31,804 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-02 21:08:31,804 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:08:31,804 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 42 times [2022-11-02 21:08:31,805 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:08:31,805 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1198233741] [2022-11-02 21:08:31,805 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:08:31,805 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:08:31,808 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:08:31,808 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:08:31,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:08:31,810 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:08:31,851 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 21:08:31,852 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2022-11-02 21:08:31,853 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=106, Invalid=1154, Unknown=0, NotChecked=0, Total=1260 [2022-11-02 21:08:31,853 INFO L87 Difference]: Start difference. First operand 67 states and 84 transitions. cyclomatic complexity: 21 Second operand has 36 states, 35 states have (on average 2.257142857142857) internal successors, (79), 36 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:08:32,705 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 21:08:32,705 INFO L93 Difference]: Finished difference Result 83 states and 100 transitions. [2022-11-02 21:08:32,705 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 83 states and 100 transitions. [2022-11-02 21:08:32,706 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:08:32,706 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 83 states to 82 states and 99 transitions. [2022-11-02 21:08:32,706 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-02 21:08:32,706 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-02 21:08:32,706 INFO L73 IsDeterministic]: Start isDeterministic. Operand 82 states and 99 transitions. [2022-11-02 21:08:32,707 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-02 21:08:32,707 INFO L218 hiAutomatonCegarLoop]: Abstraction has 82 states and 99 transitions. [2022-11-02 21:08:32,707 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 82 states and 99 transitions. [2022-11-02 21:08:32,708 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 82 to 57. [2022-11-02 21:08:32,708 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 57 states, 57 states have (on average 1.2280701754385965) internal successors, (70), 56 states have internal predecessors, (70), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:08:32,708 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 57 states to 57 states and 70 transitions. [2022-11-02 21:08:32,708 INFO L240 hiAutomatonCegarLoop]: Abstraction has 57 states and 70 transitions. [2022-11-02 21:08:32,713 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2022-11-02 21:08:32,714 INFO L428 stractBuchiCegarLoop]: Abstraction has 57 states and 70 transitions. [2022-11-02 21:08:32,714 INFO L335 stractBuchiCegarLoop]: ======== Iteration 45 ============ [2022-11-02 21:08:32,714 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 57 states and 70 transitions. [2022-11-02 21:08:32,714 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:08:32,714 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 21:08:32,714 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 21:08:32,715 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [10, 10, 10, 9, 8, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 21:08:32,715 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-02 21:08:32,715 INFO L748 eck$LassoCheckResult]: Stem: 14612#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 14613#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 14623#L367 assume !(main_~length~0#1 < 1); 14614#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 14615#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 14616#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14624#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14668#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14625#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14626#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14628#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14629#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14667#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14666#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14665#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14664#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14663#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14662#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14661#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14660#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14659#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14658#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14657#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14656#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14655#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14654#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14653#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14652#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14651#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14650#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14649#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14648#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14647#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14634#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14646#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14633#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 14621#L370-4 main_~j~0#1 := 0; 14622#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14619#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14620#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14627#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14645#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14644#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14643#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14642#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14641#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14640#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14639#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14638#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14637#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14636#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14635#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14632#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14631#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14617#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 14618#L378-2 [2022-11-02 21:08:32,715 INFO L750 eck$LassoCheckResult]: Loop: 14618#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14630#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 14618#L378-2 [2022-11-02 21:08:32,715 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:08:32,715 INFO L85 PathProgramCache]: Analyzing trace with hash -866028223, now seen corresponding path program 16 times [2022-11-02 21:08:32,715 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:08:32,716 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [866174861] [2022-11-02 21:08:32,716 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:08:32,716 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:08:32,736 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 21:08:33,497 INFO L134 CoverageAnalysis]: Checked inductivity of 217 backedges. 0 proven. 217 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:08:33,497 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 21:08:33,497 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [866174861] [2022-11-02 21:08:33,497 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [866174861] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 21:08:33,497 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1522128462] [2022-11-02 21:08:33,497 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-02 21:08:33,497 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 21:08:33,498 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:08:33,499 INFO L229 MonitoredProcess]: Starting monitored process 65 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 21:08:33,506 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (65)] Waiting until timeout for monitored process [2022-11-02 21:08:33,637 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-02 21:08:33,638 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-02 21:08:33,639 INFO L263 TraceCheckSpWp]: Trace formula consists of 256 conjuncts, 45 conjunts are in the unsatisfiable core [2022-11-02 21:08:33,641 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 21:08:33,724 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-02 21:08:33,840 INFO L356 Elim1Store]: treesize reduction 29, result has 27.5 percent of original size [2022-11-02 21:08:33,840 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 26 [2022-11-02 21:08:34,198 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2022-11-02 21:08:34,201 INFO L134 CoverageAnalysis]: Checked inductivity of 217 backedges. 0 proven. 217 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:08:34,201 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 21:08:34,437 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 19 [2022-11-02 21:08:34,440 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 25 [2022-11-02 21:08:34,529 INFO L134 CoverageAnalysis]: Checked inductivity of 217 backedges. 0 proven. 217 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:08:34,529 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1522128462] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 21:08:34,530 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 21:08:34,530 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24, 24] total 37 [2022-11-02 21:08:34,530 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [34707649] [2022-11-02 21:08:34,530 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 21:08:34,530 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-02 21:08:34,531 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:08:34,531 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 43 times [2022-11-02 21:08:34,531 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:08:34,531 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2080213039] [2022-11-02 21:08:34,531 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:08:34,532 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:08:34,534 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:08:34,535 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:08:34,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:08:34,537 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:08:34,580 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 21:08:34,580 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2022-11-02 21:08:34,581 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=107, Invalid=1299, Unknown=0, NotChecked=0, Total=1406 [2022-11-02 21:08:34,581 INFO L87 Difference]: Start difference. First operand 57 states and 70 transitions. cyclomatic complexity: 16 Second operand has 38 states, 37 states have (on average 2.189189189189189) internal successors, (81), 38 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:08:35,354 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 21:08:35,355 INFO L93 Difference]: Finished difference Result 85 states and 102 transitions. [2022-11-02 21:08:35,355 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 85 states and 102 transitions. [2022-11-02 21:08:35,355 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-02 21:08:35,356 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 85 states to 84 states and 101 transitions. [2022-11-02 21:08:35,356 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16 [2022-11-02 21:08:35,356 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16 [2022-11-02 21:08:35,356 INFO L73 IsDeterministic]: Start isDeterministic. Operand 84 states and 101 transitions. [2022-11-02 21:08:35,356 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-02 21:08:35,356 INFO L218 hiAutomatonCegarLoop]: Abstraction has 84 states and 101 transitions. [2022-11-02 21:08:35,356 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 84 states and 101 transitions. [2022-11-02 21:08:35,357 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 84 to 64. [2022-11-02 21:08:35,358 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 64 states, 64 states have (on average 1.234375) internal successors, (79), 63 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:08:35,358 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 64 states to 64 states and 79 transitions. [2022-11-02 21:08:35,358 INFO L240 hiAutomatonCegarLoop]: Abstraction has 64 states and 79 transitions. [2022-11-02 21:08:35,362 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2022-11-02 21:08:35,362 INFO L428 stractBuchiCegarLoop]: Abstraction has 64 states and 79 transitions. [2022-11-02 21:08:35,362 INFO L335 stractBuchiCegarLoop]: ======== Iteration 46 ============ [2022-11-02 21:08:35,363 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 64 states and 79 transitions. [2022-11-02 21:08:35,363 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:08:35,363 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 21:08:35,363 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 21:08:35,364 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [10, 10, 10, 10, 9, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 21:08:35,364 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-02 21:08:35,364 INFO L748 eck$LassoCheckResult]: Stem: 15121#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 15122#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 15132#L367 assume !(main_~length~0#1 < 1); 15123#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 15124#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 15125#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15133#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15165#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15134#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15135#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15138#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15139#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15164#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15163#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15162#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15161#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15160#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15159#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15158#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15157#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15156#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15155#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15154#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15153#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15152#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15151#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15150#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15149#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15148#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15147#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15146#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15145#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15144#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15143#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15142#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15140#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 15130#L370-4 main_~j~0#1 := 0; 15131#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15181#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15137#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15128#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15129#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15180#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15179#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15178#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15177#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15176#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15175#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15174#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15173#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15172#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15171#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15170#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15169#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15167#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15166#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15126#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 15127#L378-2 [2022-11-02 21:08:35,364 INFO L750 eck$LassoCheckResult]: Loop: 15127#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15168#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 15127#L378-2 [2022-11-02 21:08:35,364 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:08:35,365 INFO L85 PathProgramCache]: Analyzing trace with hash 970536390, now seen corresponding path program 17 times [2022-11-02 21:08:35,365 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:08:35,365 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [895800631] [2022-11-02 21:08:35,365 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:08:35,365 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:08:35,386 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 21:08:36,139 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 0 proven. 235 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:08:36,139 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 21:08:36,139 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [895800631] [2022-11-02 21:08:36,139 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [895800631] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 21:08:36,139 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [587168105] [2022-11-02 21:08:36,140 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-02 21:08:36,140 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 21:08:36,140 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:08:36,143 INFO L229 MonitoredProcess]: Starting monitored process 66 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 21:08:36,147 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (66)] Waiting until timeout for monitored process [2022-11-02 21:08:36,401 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 11 check-sat command(s) [2022-11-02 21:08:36,402 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-02 21:08:36,405 INFO L263 TraceCheckSpWp]: Trace formula consists of 283 conjuncts, 46 conjunts are in the unsatisfiable core [2022-11-02 21:08:36,406 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 21:08:36,490 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-02 21:08:37,045 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2022-11-02 21:08:37,048 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 0 proven. 235 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:08:37,048 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 21:08:37,281 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 14 [2022-11-02 21:08:37,285 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 20 [2022-11-02 21:08:37,377 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 0 proven. 235 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:08:37,378 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [587168105] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 21:08:37,378 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 21:08:37,378 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25] total 39 [2022-11-02 21:08:37,378 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [999416934] [2022-11-02 21:08:37,378 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 21:08:37,379 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-02 21:08:37,379 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:08:37,379 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 44 times [2022-11-02 21:08:37,379 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:08:37,380 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [899867853] [2022-11-02 21:08:37,380 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:08:37,380 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:08:37,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:08:37,383 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:08:37,383 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:08:37,385 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:08:37,441 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 21:08:37,442 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2022-11-02 21:08:37,443 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=121, Invalid=1439, Unknown=0, NotChecked=0, Total=1560 [2022-11-02 21:08:37,443 INFO L87 Difference]: Start difference. First operand 64 states and 79 transitions. cyclomatic complexity: 18 Second operand has 40 states, 39 states have (on average 2.1794871794871793) internal successors, (85), 40 states have internal predecessors, (85), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:08:38,372 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 21:08:38,372 INFO L93 Difference]: Finished difference Result 130 states and 159 transitions. [2022-11-02 21:08:38,372 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 130 states and 159 transitions. [2022-11-02 21:08:38,373 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 23 [2022-11-02 21:08:38,374 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 130 states to 129 states and 158 transitions. [2022-11-02 21:08:38,374 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 40 [2022-11-02 21:08:38,374 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 40 [2022-11-02 21:08:38,374 INFO L73 IsDeterministic]: Start isDeterministic. Operand 129 states and 158 transitions. [2022-11-02 21:08:38,375 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-02 21:08:38,375 INFO L218 hiAutomatonCegarLoop]: Abstraction has 129 states and 158 transitions. [2022-11-02 21:08:38,375 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 129 states and 158 transitions. [2022-11-02 21:08:38,377 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 129 to 108. [2022-11-02 21:08:38,377 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 108 states, 108 states have (on average 1.25) internal successors, (135), 107 states have internal predecessors, (135), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:08:38,377 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 108 states to 108 states and 135 transitions. [2022-11-02 21:08:38,377 INFO L240 hiAutomatonCegarLoop]: Abstraction has 108 states and 135 transitions. [2022-11-02 21:08:38,381 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2022-11-02 21:08:38,382 INFO L428 stractBuchiCegarLoop]: Abstraction has 108 states and 135 transitions. [2022-11-02 21:08:38,382 INFO L335 stractBuchiCegarLoop]: ======== Iteration 47 ============ [2022-11-02 21:08:38,382 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 108 states and 135 transitions. [2022-11-02 21:08:38,383 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 20 [2022-11-02 21:08:38,383 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 21:08:38,383 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 21:08:38,385 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [11, 11, 10, 9, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 21:08:38,385 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-02 21:08:38,385 INFO L748 eck$LassoCheckResult]: Stem: 15696#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 15697#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 15707#L367 assume !(main_~length~0#1 < 1); 15698#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 15699#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 15700#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15708#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15740#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15709#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15710#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15713#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15714#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15739#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15738#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15737#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15736#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15735#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15734#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15733#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15732#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15731#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15730#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15729#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15728#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15727#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15726#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15725#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15724#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15723#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15722#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15721#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15720#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15718#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15719#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15771#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15769#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15767#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15717#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15715#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 15705#L370-4 main_~j~0#1 := 0; 15706#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15783#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15782#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15781#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15780#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15779#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15778#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15777#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15776#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15775#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15774#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15773#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15772#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15744#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15748#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15745#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15746#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15747#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 15702#L378-2 [2022-11-02 21:08:38,386 INFO L750 eck$LassoCheckResult]: Loop: 15702#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15741#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 15702#L378-2 [2022-11-02 21:08:38,386 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:08:38,386 INFO L85 PathProgramCache]: Analyzing trace with hash 1150074441, now seen corresponding path program 23 times [2022-11-02 21:08:38,386 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:08:38,386 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1491498854] [2022-11-02 21:08:38,387 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:08:38,387 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:08:38,427 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 21:08:39,230 INFO L134 CoverageAnalysis]: Checked inductivity of 248 backedges. 0 proven. 248 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:08:39,230 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 21:08:39,230 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1491498854] [2022-11-02 21:08:39,230 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1491498854] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 21:08:39,230 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [166918353] [2022-11-02 21:08:39,230 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-02 21:08:39,230 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 21:08:39,230 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:08:39,232 INFO L229 MonitoredProcess]: Starting monitored process 67 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 21:08:39,233 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (67)] Waiting until timeout for monitored process [2022-11-02 21:08:39,465 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 12 check-sat command(s) [2022-11-02 21:08:39,465 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-02 21:08:39,468 INFO L263 TraceCheckSpWp]: Trace formula consists of 294 conjuncts, 50 conjunts are in the unsatisfiable core [2022-11-02 21:08:39,472 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 21:08:39,563 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-02 21:08:39,654 INFO L356 Elim1Store]: treesize reduction 23, result has 28.1 percent of original size [2022-11-02 21:08:39,654 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2022-11-02 21:08:39,711 INFO L356 Elim1Store]: treesize reduction 23, result has 28.1 percent of original size [2022-11-02 21:08:39,711 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2022-11-02 21:08:39,729 INFO L356 Elim1Store]: treesize reduction 23, result has 28.1 percent of original size [2022-11-02 21:08:39,729 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2022-11-02 21:08:40,089 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2022-11-02 21:08:40,091 INFO L134 CoverageAnalysis]: Checked inductivity of 248 backedges. 2 proven. 246 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:08:40,091 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 21:08:40,504 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 19 [2022-11-02 21:08:40,506 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 25 [2022-11-02 21:08:40,581 INFO L134 CoverageAnalysis]: Checked inductivity of 248 backedges. 1 proven. 246 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-02 21:08:40,581 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [166918353] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 21:08:40,582 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 21:08:40,582 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 26, 26] total 40 [2022-11-02 21:08:40,582 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [608442041] [2022-11-02 21:08:40,582 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 21:08:40,582 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-02 21:08:40,582 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:08:40,582 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 45 times [2022-11-02 21:08:40,583 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:08:40,583 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [311634280] [2022-11-02 21:08:40,583 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:08:40,583 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:08:40,585 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:08:40,586 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:08:40,586 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:08:40,588 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:08:40,642 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 21:08:40,643 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2022-11-02 21:08:40,643 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=123, Invalid=1517, Unknown=0, NotChecked=0, Total=1640 [2022-11-02 21:08:40,644 INFO L87 Difference]: Start difference. First operand 108 states and 135 transitions. cyclomatic complexity: 32 Second operand has 41 states, 40 states have (on average 2.25) internal successors, (90), 41 states have internal predecessors, (90), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:08:41,667 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 21:08:41,668 INFO L93 Difference]: Finished difference Result 106 states and 123 transitions. [2022-11-02 21:08:41,668 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 106 states and 123 transitions. [2022-11-02 21:08:41,669 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:08:41,669 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 106 states to 104 states and 121 transitions. [2022-11-02 21:08:41,669 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15 [2022-11-02 21:08:41,670 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15 [2022-11-02 21:08:41,670 INFO L73 IsDeterministic]: Start isDeterministic. Operand 104 states and 121 transitions. [2022-11-02 21:08:41,670 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-02 21:08:41,670 INFO L218 hiAutomatonCegarLoop]: Abstraction has 104 states and 121 transitions. [2022-11-02 21:08:41,670 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 104 states and 121 transitions. [2022-11-02 21:08:41,672 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 104 to 67. [2022-11-02 21:08:41,672 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 67 states, 67 states have (on average 1.2388059701492538) internal successors, (83), 66 states have internal predecessors, (83), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:08:41,672 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 67 states to 67 states and 83 transitions. [2022-11-02 21:08:41,673 INFO L240 hiAutomatonCegarLoop]: Abstraction has 67 states and 83 transitions. [2022-11-02 21:08:41,673 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2022-11-02 21:08:41,674 INFO L428 stractBuchiCegarLoop]: Abstraction has 67 states and 83 transitions. [2022-11-02 21:08:41,674 INFO L335 stractBuchiCegarLoop]: ======== Iteration 48 ============ [2022-11-02 21:08:41,674 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 67 states and 83 transitions. [2022-11-02 21:08:41,675 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:08:41,675 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 21:08:41,675 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 21:08:41,675 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [11, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 21:08:41,675 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-02 21:08:41,676 INFO L748 eck$LassoCheckResult]: Stem: 16316#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 16317#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 16327#L367 assume !(main_~length~0#1 < 1); 16318#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 16319#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 16320#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16328#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16369#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16329#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16330#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16331#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16334#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16368#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16367#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16366#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16365#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16364#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16363#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16362#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16361#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16360#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16359#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16358#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16357#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16356#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16355#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16354#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16353#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16352#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16351#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16350#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16349#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16348#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16346#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16344#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16341#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 16321#L370-4 main_~j~0#1 := 0; 16322#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16378#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16333#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16325#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16326#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16377#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16376#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16375#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16374#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16373#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16372#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16371#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16370#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16347#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16345#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16343#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16340#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16339#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16338#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16336#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16335#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16323#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 16324#L378-2 [2022-11-02 21:08:41,676 INFO L750 eck$LassoCheckResult]: Loop: 16324#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16337#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 16324#L378-2 [2022-11-02 21:08:41,676 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:08:41,677 INFO L85 PathProgramCache]: Analyzing trace with hash 677570827, now seen corresponding path program 18 times [2022-11-02 21:08:41,677 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:08:41,677 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1858923591] [2022-11-02 21:08:41,677 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:08:41,677 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:08:41,702 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 21:08:42,044 INFO L134 CoverageAnalysis]: Checked inductivity of 255 backedges. 91 proven. 164 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:08:42,044 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 21:08:42,044 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1858923591] [2022-11-02 21:08:42,044 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1858923591] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 21:08:42,045 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [807889360] [2022-11-02 21:08:42,045 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-11-02 21:08:42,045 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 21:08:42,045 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:08:42,078 INFO L229 MonitoredProcess]: Starting monitored process 68 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 21:08:42,082 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (68)] Waiting until timeout for monitored process [2022-11-02 21:08:42,598 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 11 check-sat command(s) [2022-11-02 21:08:42,598 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-02 21:08:42,600 INFO L263 TraceCheckSpWp]: Trace formula consists of 294 conjuncts, 24 conjunts are in the unsatisfiable core [2022-11-02 21:08:42,601 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 21:08:42,973 INFO L134 CoverageAnalysis]: Checked inductivity of 255 backedges. 110 proven. 145 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:08:42,973 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 21:08:43,259 INFO L134 CoverageAnalysis]: Checked inductivity of 255 backedges. 110 proven. 145 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:08:43,259 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [807889360] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 21:08:43,259 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 21:08:43,259 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25] total 38 [2022-11-02 21:08:43,260 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [328569913] [2022-11-02 21:08:43,260 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 21:08:43,260 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-02 21:08:43,260 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:08:43,260 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 46 times [2022-11-02 21:08:43,260 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:08:43,261 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [32949801] [2022-11-02 21:08:43,261 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:08:43,261 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:08:43,263 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:08:43,263 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:08:43,264 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:08:43,266 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:08:43,310 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 21:08:43,311 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2022-11-02 21:08:43,311 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=329, Invalid=1077, Unknown=0, NotChecked=0, Total=1406 [2022-11-02 21:08:43,312 INFO L87 Difference]: Start difference. First operand 67 states and 83 transitions. cyclomatic complexity: 20 Second operand has 38 states, 38 states have (on average 2.3157894736842106) internal successors, (88), 38 states have internal predecessors, (88), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:08:43,644 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 21:08:43,645 INFO L93 Difference]: Finished difference Result 94 states and 111 transitions. [2022-11-02 21:08:43,645 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 94 states and 111 transitions. [2022-11-02 21:08:43,645 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:08:43,645 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 94 states to 72 states and 89 transitions. [2022-11-02 21:08:43,645 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-02 21:08:43,646 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-02 21:08:43,646 INFO L73 IsDeterministic]: Start isDeterministic. Operand 72 states and 89 transitions. [2022-11-02 21:08:43,646 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-02 21:08:43,646 INFO L218 hiAutomatonCegarLoop]: Abstraction has 72 states and 89 transitions. [2022-11-02 21:08:43,646 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 72 states and 89 transitions. [2022-11-02 21:08:43,647 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 72 to 69. [2022-11-02 21:08:43,647 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 69 states, 69 states have (on average 1.2318840579710144) internal successors, (85), 68 states have internal predecessors, (85), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:08:43,647 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 69 states to 69 states and 85 transitions. [2022-11-02 21:08:43,647 INFO L240 hiAutomatonCegarLoop]: Abstraction has 69 states and 85 transitions. [2022-11-02 21:08:43,648 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2022-11-02 21:08:43,648 INFO L428 stractBuchiCegarLoop]: Abstraction has 69 states and 85 transitions. [2022-11-02 21:08:43,648 INFO L335 stractBuchiCegarLoop]: ======== Iteration 49 ============ [2022-11-02 21:08:43,648 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 69 states and 85 transitions. [2022-11-02 21:08:43,649 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:08:43,649 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 21:08:43,649 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 21:08:43,649 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [11, 11, 10, 10, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 21:08:43,649 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-02 21:08:43,649 INFO L748 eck$LassoCheckResult]: Stem: 16890#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 16891#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 16901#L367 assume !(main_~length~0#1 < 1); 16892#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 16893#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 16894#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16902#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16958#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16903#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16904#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16905#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16907#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16957#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16956#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16955#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16954#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16953#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16952#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16951#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16950#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16949#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16948#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16947#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16946#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16945#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16944#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16943#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16942#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16941#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16940#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16939#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16938#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16937#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16936#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16935#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16934#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16932#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16928#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16908#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 16895#L370-4 main_~j~0#1 := 0; 16896#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16906#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16927#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16926#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16925#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16924#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16923#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16922#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16921#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16920#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16919#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16918#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16917#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16916#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16915#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16914#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16913#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16911#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16910#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16897#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 16898#L378-2 [2022-11-02 21:08:43,650 INFO L750 eck$LassoCheckResult]: Loop: 16898#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16912#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 16898#L378-2 [2022-11-02 21:08:43,650 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:08:43,650 INFO L85 PathProgramCache]: Analyzing trace with hash 1414945998, now seen corresponding path program 24 times [2022-11-02 21:08:43,650 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:08:43,650 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [597016355] [2022-11-02 21:08:43,651 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:08:43,651 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:08:43,676 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 21:08:44,579 INFO L134 CoverageAnalysis]: Checked inductivity of 266 backedges. 0 proven. 266 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:08:44,579 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 21:08:44,579 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [597016355] [2022-11-02 21:08:44,579 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [597016355] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 21:08:44,579 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [414583589] [2022-11-02 21:08:44,579 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-11-02 21:08:44,580 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 21:08:44,580 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:08:44,583 INFO L229 MonitoredProcess]: Starting monitored process 69 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 21:08:44,601 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (69)] Waiting until timeout for monitored process [2022-11-02 21:08:46,708 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 12 check-sat command(s) [2022-11-02 21:08:46,708 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-02 21:08:46,711 INFO L263 TraceCheckSpWp]: Trace formula consists of 305 conjuncts, 51 conjunts are in the unsatisfiable core [2022-11-02 21:08:46,713 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 21:08:46,790 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-02 21:08:46,901 INFO L356 Elim1Store]: treesize reduction 29, result has 27.5 percent of original size [2022-11-02 21:08:46,901 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 26 [2022-11-02 21:08:46,925 INFO L356 Elim1Store]: treesize reduction 29, result has 27.5 percent of original size [2022-11-02 21:08:46,925 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 26 [2022-11-02 21:08:47,332 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2022-11-02 21:08:47,334 INFO L134 CoverageAnalysis]: Checked inductivity of 266 backedges. 0 proven. 266 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:08:47,334 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 21:08:47,641 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 19 [2022-11-02 21:08:47,644 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 25 [2022-11-02 21:08:47,750 INFO L134 CoverageAnalysis]: Checked inductivity of 266 backedges. 0 proven. 266 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:08:47,750 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [414583589] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 21:08:47,750 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 21:08:47,750 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 26, 26] total 40 [2022-11-02 21:08:47,751 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [366043047] [2022-11-02 21:08:47,751 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 21:08:47,751 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-02 21:08:47,751 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:08:47,751 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 47 times [2022-11-02 21:08:47,752 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:08:47,752 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1623933917] [2022-11-02 21:08:47,752 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:08:47,752 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:08:47,755 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:08:47,756 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:08:47,756 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:08:47,758 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:08:47,802 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 21:08:47,802 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2022-11-02 21:08:47,803 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=115, Invalid=1525, Unknown=0, NotChecked=0, Total=1640 [2022-11-02 21:08:47,803 INFO L87 Difference]: Start difference. First operand 69 states and 85 transitions. cyclomatic complexity: 20 Second operand has 41 states, 40 states have (on average 2.225) internal successors, (89), 41 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:08:48,600 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 21:08:48,600 INFO L93 Difference]: Finished difference Result 124 states and 147 transitions. [2022-11-02 21:08:48,600 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 124 states and 147 transitions. [2022-11-02 21:08:48,601 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-02 21:08:48,601 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 124 states to 123 states and 146 transitions. [2022-11-02 21:08:48,601 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 20 [2022-11-02 21:08:48,601 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 20 [2022-11-02 21:08:48,601 INFO L73 IsDeterministic]: Start isDeterministic. Operand 123 states and 146 transitions. [2022-11-02 21:08:48,602 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-02 21:08:48,602 INFO L218 hiAutomatonCegarLoop]: Abstraction has 123 states and 146 transitions. [2022-11-02 21:08:48,602 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 123 states and 146 transitions. [2022-11-02 21:08:48,603 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 123 to 75. [2022-11-02 21:08:48,603 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 75 states, 75 states have (on average 1.2666666666666666) internal successors, (95), 74 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:08:48,603 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 75 states to 75 states and 95 transitions. [2022-11-02 21:08:48,604 INFO L240 hiAutomatonCegarLoop]: Abstraction has 75 states and 95 transitions. [2022-11-02 21:08:48,613 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2022-11-02 21:08:48,614 INFO L428 stractBuchiCegarLoop]: Abstraction has 75 states and 95 transitions. [2022-11-02 21:08:48,614 INFO L335 stractBuchiCegarLoop]: ======== Iteration 50 ============ [2022-11-02 21:08:48,614 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 75 states and 95 transitions. [2022-11-02 21:08:48,615 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:08:48,615 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 21:08:48,615 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 21:08:48,615 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [11, 11, 11, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 21:08:48,615 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-02 21:08:48,616 INFO L748 eck$LassoCheckResult]: Stem: 17483#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 17484#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 17494#L367 assume !(main_~length~0#1 < 1); 17485#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 17486#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 17487#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17495#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 17557#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17496#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17497#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 17499#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17500#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17556#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 17555#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17554#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17553#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 17552#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17551#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17550#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 17549#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17548#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17547#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 17546#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17545#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17544#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 17543#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17542#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17541#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 17540#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17539#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17538#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 17537#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17536#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17535#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 17534#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17533#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17529#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17528#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17527#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 17492#L370-4 main_~j~0#1 := 0; 17493#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17490#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 17491#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17498#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 17518#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17517#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 17516#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17515#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 17514#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17513#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 17512#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17511#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 17510#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17509#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 17508#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17507#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 17506#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17505#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 17504#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17502#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 17501#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17488#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 17489#L378-2 [2022-11-02 21:08:48,616 INFO L750 eck$LassoCheckResult]: Loop: 17489#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17503#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 17489#L378-2 [2022-11-02 21:08:48,616 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:08:48,616 INFO L85 PathProgramCache]: Analyzing trace with hash -1741525485, now seen corresponding path program 25 times [2022-11-02 21:08:48,617 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:08:48,617 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1512617720] [2022-11-02 21:08:48,617 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:08:48,617 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:08:48,642 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 21:08:49,363 INFO L134 CoverageAnalysis]: Checked inductivity of 286 backedges. 0 proven. 286 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:08:49,363 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 21:08:49,363 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1512617720] [2022-11-02 21:08:49,363 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1512617720] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 21:08:49,363 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1315549569] [2022-11-02 21:08:49,363 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-11-02 21:08:49,364 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 21:08:49,364 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:08:49,366 INFO L229 MonitoredProcess]: Starting monitored process 70 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 21:08:49,367 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (70)] Waiting until timeout for monitored process [2022-11-02 21:08:49,525 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 21:08:49,527 INFO L263 TraceCheckSpWp]: Trace formula consists of 316 conjuncts, 53 conjunts are in the unsatisfiable core [2022-11-02 21:08:49,529 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 21:08:50,007 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 9 [2022-11-02 21:08:50,685 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-02 21:08:50,732 INFO L134 CoverageAnalysis]: Checked inductivity of 286 backedges. 0 proven. 286 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:08:50,732 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 21:08:51,344 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 16 [2022-11-02 21:08:51,350 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 24 [2022-11-02 21:08:51,464 INFO L134 CoverageAnalysis]: Checked inductivity of 286 backedges. 0 proven. 286 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:08:51,464 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1315549569] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 21:08:51,464 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 21:08:51,464 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 26, 25] total 63 [2022-11-02 21:08:51,465 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [149809199] [2022-11-02 21:08:51,465 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 21:08:51,465 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-02 21:08:51,465 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:08:51,465 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 48 times [2022-11-02 21:08:51,465 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:08:51,466 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1861974589] [2022-11-02 21:08:51,466 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:08:51,466 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:08:51,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:08:51,469 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:08:51,470 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:08:51,471 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:08:51,518 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 21:08:51,519 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 64 interpolants. [2022-11-02 21:08:51,521 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=211, Invalid=3821, Unknown=0, NotChecked=0, Total=4032 [2022-11-02 21:08:51,521 INFO L87 Difference]: Start difference. First operand 75 states and 95 transitions. cyclomatic complexity: 24 Second operand has 64 states, 63 states have (on average 2.3174603174603177) internal successors, (146), 64 states have internal predecessors, (146), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:08:53,579 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 21:08:53,579 INFO L93 Difference]: Finished difference Result 106 states and 129 transitions. [2022-11-02 21:08:53,579 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 106 states and 129 transitions. [2022-11-02 21:08:53,580 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-02 21:08:53,580 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 106 states to 105 states and 128 transitions. [2022-11-02 21:08:53,580 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18 [2022-11-02 21:08:53,581 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18 [2022-11-02 21:08:53,581 INFO L73 IsDeterministic]: Start isDeterministic. Operand 105 states and 128 transitions. [2022-11-02 21:08:53,581 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-02 21:08:53,581 INFO L218 hiAutomatonCegarLoop]: Abstraction has 105 states and 128 transitions. [2022-11-02 21:08:53,581 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 105 states and 128 transitions. [2022-11-02 21:08:53,583 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 105 to 81. [2022-11-02 21:08:53,583 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 81 states, 81 states have (on average 1.2592592592592593) internal successors, (102), 80 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:08:53,583 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 81 states to 81 states and 102 transitions. [2022-11-02 21:08:53,583 INFO L240 hiAutomatonCegarLoop]: Abstraction has 81 states and 102 transitions. [2022-11-02 21:08:53,589 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2022-11-02 21:08:53,590 INFO L428 stractBuchiCegarLoop]: Abstraction has 81 states and 102 transitions. [2022-11-02 21:08:53,590 INFO L335 stractBuchiCegarLoop]: ======== Iteration 51 ============ [2022-11-02 21:08:53,590 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 81 states and 102 transitions. [2022-11-02 21:08:53,591 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-02 21:08:53,591 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 21:08:53,591 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 21:08:53,591 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [11, 11, 11, 11, 10, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 21:08:53,591 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-02 21:08:53,592 INFO L748 eck$LassoCheckResult]: Stem: 18125#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 18126#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 18136#L367 assume !(main_~length~0#1 < 1); 18127#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 18128#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 18129#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18137#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18205#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18138#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18139#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18140#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18142#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18204#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18203#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18202#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18201#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18200#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18199#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18198#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18197#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18196#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18195#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18194#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18193#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18192#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18191#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18190#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18189#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18188#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18187#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18186#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18185#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18184#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18181#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18180#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18179#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18177#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18178#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18143#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 18130#L370-4 main_~j~0#1 := 0; 18131#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18141#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18164#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18163#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18162#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18161#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18160#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18159#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18158#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18157#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18156#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18155#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18154#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18153#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18152#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18151#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18150#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18149#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18148#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18146#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18145#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18132#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 18133#L378-2 [2022-11-02 21:08:53,592 INFO L750 eck$LassoCheckResult]: Loop: 18133#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18147#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 18133#L378-2 [2022-11-02 21:08:53,593 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:08:53,593 INFO L85 PathProgramCache]: Analyzing trace with hash -1679485871, now seen corresponding path program 19 times [2022-11-02 21:08:53,593 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:08:53,593 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [563776846] [2022-11-02 21:08:53,594 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:08:53,594 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:08:53,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 21:08:54,376 INFO L134 CoverageAnalysis]: Checked inductivity of 286 backedges. 0 proven. 286 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:08:54,377 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 21:08:54,377 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [563776846] [2022-11-02 21:08:54,377 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [563776846] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 21:08:54,377 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [418345667] [2022-11-02 21:08:54,377 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-11-02 21:08:54,378 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 21:08:54,378 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:08:54,389 INFO L229 MonitoredProcess]: Starting monitored process 71 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 21:08:54,393 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9fb342f5-b20e-4d54-a069-1fd5d26220bd/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (71)] Waiting until timeout for monitored process