./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/termination-bwb/display-bit.i --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 5e519f3a Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_097e3d7f-b4c3-45b9-98fe-f0306c1bb9c4/bin/uautomizer-Dbtcem3rbc/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_097e3d7f-b4c3-45b9-98fe-f0306c1bb9c4/bin/uautomizer-Dbtcem3rbc/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_097e3d7f-b4c3-45b9-98fe-f0306c1bb9c4/bin/uautomizer-Dbtcem3rbc/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_097e3d7f-b4c3-45b9-98fe-f0306c1bb9c4/bin/uautomizer-Dbtcem3rbc/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/termination-bwb/display-bit.i -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_097e3d7f-b4c3-45b9-98fe-f0306c1bb9c4/bin/uautomizer-Dbtcem3rbc/config/svcomp-Termination-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_097e3d7f-b4c3-45b9-98fe-f0306c1bb9c4/bin/uautomizer-Dbtcem3rbc --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 4355664fa2a6158e62d5701b8ccf1bad37ebc90f2ecb4b1919ebd02d94091d20 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-5e519f3 [2022-11-02 21:09:06,853 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-11-02 21:09:06,857 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-11-02 21:09:06,906 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-11-02 21:09:06,907 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-11-02 21:09:06,911 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-11-02 21:09:06,913 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-11-02 21:09:06,919 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-11-02 21:09:06,921 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-11-02 21:09:06,927 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-11-02 21:09:06,928 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-11-02 21:09:06,931 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-11-02 21:09:06,931 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-11-02 21:09:06,935 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-11-02 21:09:06,937 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-11-02 21:09:06,939 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-11-02 21:09:06,942 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-11-02 21:09:06,943 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-11-02 21:09:06,945 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-11-02 21:09:06,953 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-11-02 21:09:06,955 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-11-02 21:09:06,956 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-11-02 21:09:06,960 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-11-02 21:09:06,961 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-11-02 21:09:06,970 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-11-02 21:09:06,972 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-11-02 21:09:06,972 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-11-02 21:09:06,974 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-11-02 21:09:06,975 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-11-02 21:09:06,976 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-11-02 21:09:06,976 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-11-02 21:09:06,977 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-11-02 21:09:06,979 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-11-02 21:09:06,981 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-11-02 21:09:06,982 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-11-02 21:09:06,982 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-11-02 21:09:06,984 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-11-02 21:09:06,984 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-11-02 21:09:06,984 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-11-02 21:09:06,985 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-11-02 21:09:06,986 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-11-02 21:09:06,988 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_097e3d7f-b4c3-45b9-98fe-f0306c1bb9c4/bin/uautomizer-Dbtcem3rbc/config/svcomp-Termination-64bit-Automizer_Default.epf [2022-11-02 21:09:07,030 INFO L113 SettingsManager]: Loading preferences was successful [2022-11-02 21:09:07,031 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-11-02 21:09:07,031 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-11-02 21:09:07,032 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-11-02 21:09:07,033 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-11-02 21:09:07,034 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-11-02 21:09:07,034 INFO L138 SettingsManager]: * Use SBE=true [2022-11-02 21:09:07,034 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-11-02 21:09:07,034 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-11-02 21:09:07,034 INFO L138 SettingsManager]: * Use old map elimination=false [2022-11-02 21:09:07,036 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-11-02 21:09:07,037 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-11-02 21:09:07,037 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-11-02 21:09:07,037 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-11-02 21:09:07,037 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-11-02 21:09:07,037 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-11-02 21:09:07,038 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-11-02 21:09:07,038 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-11-02 21:09:07,038 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-11-02 21:09:07,038 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-11-02 21:09:07,039 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-11-02 21:09:07,039 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-11-02 21:09:07,039 INFO L138 SettingsManager]: * Use constant arrays=true [2022-11-02 21:09:07,041 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-11-02 21:09:07,041 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-11-02 21:09:07,041 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-11-02 21:09:07,041 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-11-02 21:09:07,042 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-11-02 21:09:07,043 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-11-02 21:09:07,043 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_097e3d7f-b4c3-45b9-98fe-f0306c1bb9c4/bin/uautomizer-Dbtcem3rbc/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_097e3d7f-b4c3-45b9-98fe-f0306c1bb9c4/bin/uautomizer-Dbtcem3rbc Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 4355664fa2a6158e62d5701b8ccf1bad37ebc90f2ecb4b1919ebd02d94091d20 [2022-11-02 21:09:07,349 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-11-02 21:09:07,378 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-11-02 21:09:07,381 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-11-02 21:09:07,382 INFO L271 PluginConnector]: Initializing CDTParser... [2022-11-02 21:09:07,383 INFO L275 PluginConnector]: CDTParser initialized [2022-11-02 21:09:07,385 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_097e3d7f-b4c3-45b9-98fe-f0306c1bb9c4/bin/uautomizer-Dbtcem3rbc/../../sv-benchmarks/c/termination-bwb/display-bit.i [2022-11-02 21:09:07,474 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_097e3d7f-b4c3-45b9-98fe-f0306c1bb9c4/bin/uautomizer-Dbtcem3rbc/data/fd33bb2e8/f6a1088918354aa5a8850a656dd0bdf0/FLAGf53474ca0 [2022-11-02 21:09:08,161 INFO L306 CDTParser]: Found 1 translation units. [2022-11-02 21:09:08,162 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_097e3d7f-b4c3-45b9-98fe-f0306c1bb9c4/sv-benchmarks/c/termination-bwb/display-bit.i [2022-11-02 21:09:08,176 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_097e3d7f-b4c3-45b9-98fe-f0306c1bb9c4/bin/uautomizer-Dbtcem3rbc/data/fd33bb2e8/f6a1088918354aa5a8850a656dd0bdf0/FLAGf53474ca0 [2022-11-02 21:09:08,189 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_097e3d7f-b4c3-45b9-98fe-f0306c1bb9c4/bin/uautomizer-Dbtcem3rbc/data/fd33bb2e8/f6a1088918354aa5a8850a656dd0bdf0 [2022-11-02 21:09:08,192 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-11-02 21:09:08,196 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-11-02 21:09:08,199 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-11-02 21:09:08,200 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-11-02 21:09:08,203 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-11-02 21:09:08,204 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.11 09:09:08" (1/1) ... [2022-11-02 21:09:08,205 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@60fe7e0e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 09:09:08, skipping insertion in model container [2022-11-02 21:09:08,205 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.11 09:09:08" (1/1) ... [2022-11-02 21:09:08,213 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-11-02 21:09:08,261 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-11-02 21:09:08,504 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-02 21:09:08,510 INFO L203 MainTranslator]: Completed pre-run [2022-11-02 21:09:08,543 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-02 21:09:08,562 INFO L208 MainTranslator]: Completed translation [2022-11-02 21:09:08,562 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 09:09:08 WrapperNode [2022-11-02 21:09:08,562 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-11-02 21:09:08,563 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-11-02 21:09:08,563 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-11-02 21:09:08,564 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-11-02 21:09:08,571 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 09:09:08" (1/1) ... [2022-11-02 21:09:08,586 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 09:09:08" (1/1) ... [2022-11-02 21:09:08,616 INFO L138 Inliner]: procedures = 90, calls = 9, calls flagged for inlining = 5, calls inlined = 5, statements flattened = 80 [2022-11-02 21:09:08,616 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-11-02 21:09:08,617 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-11-02 21:09:08,617 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-11-02 21:09:08,618 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-11-02 21:09:08,625 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 09:09:08" (1/1) ... [2022-11-02 21:09:08,625 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 09:09:08" (1/1) ... [2022-11-02 21:09:08,628 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 09:09:08" (1/1) ... [2022-11-02 21:09:08,628 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 09:09:08" (1/1) ... [2022-11-02 21:09:08,634 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 09:09:08" (1/1) ... [2022-11-02 21:09:08,638 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 09:09:08" (1/1) ... [2022-11-02 21:09:08,640 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 09:09:08" (1/1) ... [2022-11-02 21:09:08,641 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 09:09:08" (1/1) ... [2022-11-02 21:09:08,644 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-11-02 21:09:08,644 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-11-02 21:09:08,645 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-11-02 21:09:08,645 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-11-02 21:09:08,656 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 09:09:08" (1/1) ... [2022-11-02 21:09:08,665 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-02 21:09:08,678 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_097e3d7f-b4c3-45b9-98fe-f0306c1bb9c4/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:09:08,691 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_097e3d7f-b4c3-45b9-98fe-f0306c1bb9c4/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-02 21:09:08,716 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_097e3d7f-b4c3-45b9-98fe-f0306c1bb9c4/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-11-02 21:09:08,731 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-11-02 21:09:08,731 INFO L130 BoogieDeclarations]: Found specification of procedure putchar [2022-11-02 21:09:08,732 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-11-02 21:09:08,732 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-11-02 21:09:08,812 INFO L235 CfgBuilder]: Building ICFG [2022-11-02 21:09:08,814 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-11-02 21:09:09,047 INFO L276 CfgBuilder]: Performing block encoding [2022-11-02 21:09:09,055 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-11-02 21:09:09,055 INFO L300 CfgBuilder]: Removed 3 assume(true) statements. [2022-11-02 21:09:09,067 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.11 09:09:09 BoogieIcfgContainer [2022-11-02 21:09:09,067 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-11-02 21:09:09,068 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-11-02 21:09:09,068 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-11-02 21:09:09,073 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-11-02 21:09:09,074 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-02 21:09:09,074 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 02.11 09:09:08" (1/3) ... [2022-11-02 21:09:09,075 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@6b546ef7 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 02.11 09:09:09, skipping insertion in model container [2022-11-02 21:09:09,075 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-02 21:09:09,075 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 09:09:08" (2/3) ... [2022-11-02 21:09:09,075 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@6b546ef7 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 02.11 09:09:09, skipping insertion in model container [2022-11-02 21:09:09,076 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-02 21:09:09,076 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.11 09:09:09" (3/3) ... [2022-11-02 21:09:09,077 INFO L332 chiAutomizerObserver]: Analyzing ICFG display-bit.i [2022-11-02 21:09:09,191 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-11-02 21:09:09,191 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-11-02 21:09:09,192 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-11-02 21:09:09,192 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-11-02 21:09:09,192 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-11-02 21:09:09,192 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-11-02 21:09:09,192 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-11-02 21:09:09,193 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-11-02 21:09:09,198 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 26 states, 25 states have (on average 1.48) internal successors, (37), 25 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:09:09,237 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 15 [2022-11-02 21:09:09,241 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 21:09:09,241 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 21:09:09,247 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-11-02 21:09:09,247 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1] [2022-11-02 21:09:09,247 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-11-02 21:09:09,248 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 26 states, 25 states have (on average 1.48) internal successors, (37), 25 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:09:09,252 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 15 [2022-11-02 21:09:09,253 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 21:09:09,253 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 21:09:09,254 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-11-02 21:09:09,254 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1] [2022-11-02 21:09:09,266 INFO L748 eck$LassoCheckResult]: Stem: 14#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(8, 1);~number1~0 := 65535;~mask~0 := 1;~x~0 := 0;~c~0 := 1;~y~0 := 0; 6#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;assume { :begin_inline_displayBits } true;displayBits_#in~value#1 := ~mask~0;havoc displayBits_#t~nondet3#1, displayBits_#t~ite4#1, displayBits_#t~ret5#1, displayBits_#t~ret6#1, displayBits_#t~ret7#1, displayBits_~value#1, displayBits_~displayMask~0#1;displayBits_~value#1 := displayBits_#in~value#1;displayBits_~displayMask~0#1 := 2147483648;havoc displayBits_#t~nondet3#1; 12#L285-2true [2022-11-02 21:09:09,267 INFO L750 eck$LassoCheckResult]: Loop: 12#L285-2true assume !!(~c~0 <= 32); 13#L286true assume !(0 != (if 0 == displayBits_~value#1 || 0 == displayBits_~displayMask~0#1 then 0 else (if 1 == displayBits_~displayMask~0#1 then (if 1 == displayBits_~value#1 || 0 == displayBits_~value#1 then displayBits_~value#1 else (if displayBits_~value#1 >= 0 then displayBits_~value#1 % 2 else ~bitwiseAnd(displayBits_~value#1, displayBits_~displayMask~0#1))) else (if 1 == displayBits_~value#1 then (if 1 == displayBits_~displayMask~0#1 || 0 == displayBits_~displayMask~0#1 then displayBits_~displayMask~0#1 else (if displayBits_~displayMask~0#1 >= 0 then displayBits_~displayMask~0#1 % 2 else ~bitwiseAnd(displayBits_~value#1, displayBits_~displayMask~0#1))) else ~bitwiseAnd(displayBits_~value#1, displayBits_~displayMask~0#1)))) % 4294967296);displayBits_#t~ite4#1 := 48; 9#L286-2true call displayBits_#t~ret5#1 := putchar(displayBits_#t~ite4#1);havoc displayBits_#t~ite4#1;havoc displayBits_#t~ret5#1;displayBits_~value#1 := 2 * displayBits_~value#1; 22#L288true assume 0 == (if ~c~0 < 0 && 0 != ~c~0 % 8 then ~c~0 % 8 - 8 else ~c~0 % 8);call displayBits_#t~ret6#1 := putchar(32);havoc displayBits_#t~ret6#1; 11#L288-2true ~mask~0 := ~mask~0;~c~0 := ~c~0 + ~mask~0; 12#L285-2true [2022-11-02 21:09:09,278 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:09:09,279 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 1 times [2022-11-02 21:09:09,290 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:09:09,291 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1537121851] [2022-11-02 21:09:09,291 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:09:09,292 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:09:09,400 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:09:09,401 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:09:09,410 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:09:09,431 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:09:09,434 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:09:09,435 INFO L85 PathProgramCache]: Analyzing trace with hash 39282512, now seen corresponding path program 1 times [2022-11-02 21:09:09,435 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:09:09,437 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [580784853] [2022-11-02 21:09:09,438 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:09:09,438 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:09:09,509 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:09:09,510 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:09:09,556 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:09:09,563 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:09:09,572 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:09:09,579 INFO L85 PathProgramCache]: Analyzing trace with hash 1810721998, now seen corresponding path program 1 times [2022-11-02 21:09:09,580 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:09:09,580 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1921436279] [2022-11-02 21:09:09,580 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:09:09,581 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:09:09,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 21:09:09,830 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:09:09,830 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 21:09:09,830 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1921436279] [2022-11-02 21:09:09,831 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1921436279] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-02 21:09:09,831 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-02 21:09:09,831 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-02 21:09:09,832 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [654922816] [2022-11-02 21:09:09,833 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-02 21:09:14,871 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 21:09:14,917 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-02 21:09:14,919 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-02 21:09:14,921 INFO L87 Difference]: Start difference. First operand has 26 states, 25 states have (on average 1.48) internal successors, (37), 25 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 2.3333333333333335) internal successors, (7), 2 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:09:14,977 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 21:09:14,977 INFO L93 Difference]: Finished difference Result 31 states and 40 transitions. [2022-11-02 21:09:14,979 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 31 states and 40 transitions. [2022-11-02 21:09:14,984 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 15 [2022-11-02 21:09:14,991 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 31 states to 26 states and 35 transitions. [2022-11-02 21:09:14,993 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 26 [2022-11-02 21:09:14,993 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 26 [2022-11-02 21:09:14,994 INFO L73 IsDeterministic]: Start isDeterministic. Operand 26 states and 35 transitions. [2022-11-02 21:09:14,995 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-02 21:09:14,995 INFO L218 hiAutomatonCegarLoop]: Abstraction has 26 states and 35 transitions. [2022-11-02 21:09:15,013 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26 states and 35 transitions. [2022-11-02 21:09:15,023 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26 to 25. [2022-11-02 21:09:15,024 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25 states, 25 states have (on average 1.36) internal successors, (34), 24 states have internal predecessors, (34), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:09:15,027 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 34 transitions. [2022-11-02 21:09:15,028 INFO L240 hiAutomatonCegarLoop]: Abstraction has 25 states and 34 transitions. [2022-11-02 21:09:15,029 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-02 21:09:15,036 INFO L428 stractBuchiCegarLoop]: Abstraction has 25 states and 34 transitions. [2022-11-02 21:09:15,037 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-11-02 21:09:15,037 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 25 states and 34 transitions. [2022-11-02 21:09:15,041 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 15 [2022-11-02 21:09:15,041 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 21:09:15,043 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 21:09:15,045 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1] [2022-11-02 21:09:15,045 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1] [2022-11-02 21:09:15,046 INFO L748 eck$LassoCheckResult]: Stem: 68#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(8, 1);~number1~0 := 65535;~mask~0 := 1;~x~0 := 0;~c~0 := 1;~y~0 := 0; 69#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;assume { :begin_inline_displayBits } true;displayBits_#in~value#1 := ~mask~0;havoc displayBits_#t~nondet3#1, displayBits_#t~ite4#1, displayBits_#t~ret5#1, displayBits_#t~ret6#1, displayBits_#t~ret7#1, displayBits_~value#1, displayBits_~displayMask~0#1;displayBits_~value#1 := displayBits_#in~value#1;displayBits_~displayMask~0#1 := 2147483648;havoc displayBits_#t~nondet3#1; 82#L285-2 assume !!(~c~0 <= 32); 90#L286 assume 0 != (if 0 == displayBits_~value#1 || 0 == displayBits_~displayMask~0#1 then 0 else (if 1 == displayBits_~displayMask~0#1 then (if 1 == displayBits_~value#1 || 0 == displayBits_~value#1 then displayBits_~value#1 else (if displayBits_~value#1 >= 0 then displayBits_~value#1 % 2 else ~bitwiseAnd(displayBits_~value#1, displayBits_~displayMask~0#1))) else (if 1 == displayBits_~value#1 then (if 1 == displayBits_~displayMask~0#1 || 0 == displayBits_~displayMask~0#1 then displayBits_~displayMask~0#1 else (if displayBits_~displayMask~0#1 >= 0 then displayBits_~displayMask~0#1 % 2 else ~bitwiseAnd(displayBits_~value#1, displayBits_~displayMask~0#1))) else ~bitwiseAnd(displayBits_~value#1, displayBits_~displayMask~0#1)))) % 4294967296;displayBits_#t~ite4#1 := 49; 92#L286-2 call displayBits_#t~ret5#1 := putchar(displayBits_#t~ite4#1);havoc displayBits_#t~ite4#1;havoc displayBits_#t~ret5#1;displayBits_~value#1 := 2 * displayBits_~value#1; 86#L288 assume !(0 == (if ~c~0 < 0 && 0 != ~c~0 % 8 then ~c~0 % 8 - 8 else ~c~0 % 8)); 87#L288-2 [2022-11-02 21:09:15,046 INFO L750 eck$LassoCheckResult]: Loop: 87#L288-2 ~mask~0 := ~mask~0;~c~0 := ~c~0 + ~mask~0; 89#L285-2 assume !!(~c~0 <= 32); 91#L286 assume !(0 != (if 0 == displayBits_~value#1 || 0 == displayBits_~displayMask~0#1 then 0 else (if 1 == displayBits_~displayMask~0#1 then (if 1 == displayBits_~value#1 || 0 == displayBits_~value#1 then displayBits_~value#1 else (if displayBits_~value#1 >= 0 then displayBits_~value#1 % 2 else ~bitwiseAnd(displayBits_~value#1, displayBits_~displayMask~0#1))) else (if 1 == displayBits_~value#1 then (if 1 == displayBits_~displayMask~0#1 || 0 == displayBits_~displayMask~0#1 then displayBits_~displayMask~0#1 else (if displayBits_~displayMask~0#1 >= 0 then displayBits_~displayMask~0#1 % 2 else ~bitwiseAnd(displayBits_~value#1, displayBits_~displayMask~0#1))) else ~bitwiseAnd(displayBits_~value#1, displayBits_~displayMask~0#1)))) % 4294967296);displayBits_#t~ite4#1 := 48; 84#L286-2 call displayBits_#t~ret5#1 := putchar(displayBits_#t~ite4#1);havoc displayBits_#t~ite4#1;havoc displayBits_#t~ret5#1;displayBits_~value#1 := 2 * displayBits_~value#1; 85#L288 assume 0 == (if ~c~0 < 0 && 0 != ~c~0 % 8 then ~c~0 % 8 - 8 else ~c~0 % 8);call displayBits_#t~ret6#1 := putchar(32);havoc displayBits_#t~ret6#1; 87#L288-2 [2022-11-02 21:09:15,047 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:09:15,047 INFO L85 PathProgramCache]: Analyzing trace with hash 889692459, now seen corresponding path program 1 times [2022-11-02 21:09:15,047 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:09:15,047 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1348904356] [2022-11-02 21:09:15,048 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:09:15,048 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:09:15,096 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 21:09:15,360 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:09:15,361 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 21:09:15,362 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1348904356] [2022-11-02 21:09:15,363 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1348904356] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-02 21:09:15,366 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-02 21:09:15,367 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-02 21:09:15,367 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [197053380] [2022-11-02 21:09:15,367 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-02 21:09:15,368 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-02 21:09:15,370 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:09:15,370 INFO L85 PathProgramCache]: Analyzing trace with hash 52060832, now seen corresponding path program 2 times [2022-11-02 21:09:15,370 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:09:15,371 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [28041335] [2022-11-02 21:09:15,376 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:09:15,377 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:09:15,390 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:09:15,396 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:09:15,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:09:15,420 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:09:29,226 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 21:09:29,226 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-02 21:09:29,227 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-02 21:09:29,227 INFO L87 Difference]: Start difference. First operand 25 states and 34 transitions. cyclomatic complexity: 12 Second operand has 4 states, 4 states have (on average 1.5) internal successors, (6), 3 states have internal predecessors, (6), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:09:29,278 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 21:09:29,278 INFO L93 Difference]: Finished difference Result 25 states and 33 transitions. [2022-11-02 21:09:29,279 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 25 states and 33 transitions. [2022-11-02 21:09:29,279 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 15 [2022-11-02 21:09:29,293 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 25 states to 25 states and 33 transitions. [2022-11-02 21:09:29,293 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 25 [2022-11-02 21:09:29,293 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 25 [2022-11-02 21:09:29,293 INFO L73 IsDeterministic]: Start isDeterministic. Operand 25 states and 33 transitions. [2022-11-02 21:09:29,294 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-02 21:09:29,294 INFO L218 hiAutomatonCegarLoop]: Abstraction has 25 states and 33 transitions. [2022-11-02 21:09:29,294 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25 states and 33 transitions. [2022-11-02 21:09:29,295 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25 to 25. [2022-11-02 21:09:29,296 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25 states, 25 states have (on average 1.32) internal successors, (33), 24 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:09:29,296 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 33 transitions. [2022-11-02 21:09:29,297 INFO L240 hiAutomatonCegarLoop]: Abstraction has 25 states and 33 transitions. [2022-11-02 21:09:29,297 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-02 21:09:29,298 INFO L428 stractBuchiCegarLoop]: Abstraction has 25 states and 33 transitions. [2022-11-02 21:09:29,298 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-11-02 21:09:29,298 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 25 states and 33 transitions. [2022-11-02 21:09:29,299 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 15 [2022-11-02 21:09:29,299 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 21:09:29,299 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 21:09:29,300 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1] [2022-11-02 21:09:29,300 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1] [2022-11-02 21:09:29,300 INFO L748 eck$LassoCheckResult]: Stem: 127#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(8, 1);~number1~0 := 65535;~mask~0 := 1;~x~0 := 0;~c~0 := 1;~y~0 := 0; 128#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;assume { :begin_inline_displayBits } true;displayBits_#in~value#1 := ~mask~0;havoc displayBits_#t~nondet3#1, displayBits_#t~ite4#1, displayBits_#t~ret5#1, displayBits_#t~ret6#1, displayBits_#t~ret7#1, displayBits_~value#1, displayBits_~displayMask~0#1;displayBits_~value#1 := displayBits_#in~value#1;displayBits_~displayMask~0#1 := 2147483648;havoc displayBits_#t~nondet3#1; 141#L285-2 assume !!(~c~0 <= 32); 148#L286 assume !(0 != (if 0 == displayBits_~value#1 || 0 == displayBits_~displayMask~0#1 then 0 else (if 1 == displayBits_~displayMask~0#1 then (if 1 == displayBits_~value#1 || 0 == displayBits_~value#1 then displayBits_~value#1 else (if displayBits_~value#1 >= 0 then displayBits_~value#1 % 2 else ~bitwiseAnd(displayBits_~value#1, displayBits_~displayMask~0#1))) else (if 1 == displayBits_~value#1 then (if 1 == displayBits_~displayMask~0#1 || 0 == displayBits_~displayMask~0#1 then displayBits_~displayMask~0#1 else (if displayBits_~displayMask~0#1 >= 0 then displayBits_~displayMask~0#1 % 2 else ~bitwiseAnd(displayBits_~value#1, displayBits_~displayMask~0#1))) else ~bitwiseAnd(displayBits_~value#1, displayBits_~displayMask~0#1)))) % 4294967296);displayBits_#t~ite4#1 := 48; 143#L286-2 call displayBits_#t~ret5#1 := putchar(displayBits_#t~ite4#1);havoc displayBits_#t~ite4#1;havoc displayBits_#t~ret5#1;displayBits_~value#1 := 2 * displayBits_~value#1; 144#L288 assume !(0 == (if ~c~0 < 0 && 0 != ~c~0 % 8 then ~c~0 % 8 - 8 else ~c~0 % 8)); 145#L288-2 [2022-11-02 21:09:29,300 INFO L750 eck$LassoCheckResult]: Loop: 145#L288-2 ~mask~0 := ~mask~0;~c~0 := ~c~0 + ~mask~0; 147#L285-2 assume !!(~c~0 <= 32); 149#L286 assume !(0 != (if 0 == displayBits_~value#1 || 0 == displayBits_~displayMask~0#1 then 0 else (if 1 == displayBits_~displayMask~0#1 then (if 1 == displayBits_~value#1 || 0 == displayBits_~value#1 then displayBits_~value#1 else (if displayBits_~value#1 >= 0 then displayBits_~value#1 % 2 else ~bitwiseAnd(displayBits_~value#1, displayBits_~displayMask~0#1))) else (if 1 == displayBits_~value#1 then (if 1 == displayBits_~displayMask~0#1 || 0 == displayBits_~displayMask~0#1 then displayBits_~displayMask~0#1 else (if displayBits_~displayMask~0#1 >= 0 then displayBits_~displayMask~0#1 % 2 else ~bitwiseAnd(displayBits_~value#1, displayBits_~displayMask~0#1))) else ~bitwiseAnd(displayBits_~value#1, displayBits_~displayMask~0#1)))) % 4294967296);displayBits_#t~ite4#1 := 48; 151#L286-2 call displayBits_#t~ret5#1 := putchar(displayBits_#t~ite4#1);havoc displayBits_#t~ite4#1;havoc displayBits_#t~ret5#1;displayBits_~value#1 := 2 * displayBits_~value#1; 150#L288 assume 0 == (if ~c~0 < 0 && 0 != ~c~0 % 8 then ~c~0 % 8 - 8 else ~c~0 % 8);call displayBits_#t~ret6#1 := putchar(32);havoc displayBits_#t~ret6#1; 145#L288-2 [2022-11-02 21:09:29,301 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:09:29,301 INFO L85 PathProgramCache]: Analyzing trace with hash 889694381, now seen corresponding path program 1 times [2022-11-02 21:09:29,301 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:09:29,301 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1965373961] [2022-11-02 21:09:29,302 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:09:29,302 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:09:29,330 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:09:29,330 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:09:29,339 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:09:29,355 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:09:29,355 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:09:29,356 INFO L85 PathProgramCache]: Analyzing trace with hash 52060832, now seen corresponding path program 3 times [2022-11-02 21:09:29,356 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:09:29,356 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1608851811] [2022-11-02 21:09:29,356 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:09:29,357 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:09:29,366 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:09:29,376 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:09:29,384 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:09:29,386 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:09:29,386 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:09:29,387 INFO L85 PathProgramCache]: Analyzing trace with hash -1373813388, now seen corresponding path program 1 times [2022-11-02 21:09:29,387 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:09:29,387 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [849875702] [2022-11-02 21:09:29,387 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:09:29,387 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:09:29,409 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 21:09:29,541 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:09:29,543 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 21:09:29,543 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [849875702] [2022-11-02 21:09:29,543 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [849875702] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 21:09:29,544 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1412817232] [2022-11-02 21:09:29,544 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:09:29,544 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 21:09:29,544 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_097e3d7f-b4c3-45b9-98fe-f0306c1bb9c4/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:09:29,550 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_097e3d7f-b4c3-45b9-98fe-f0306c1bb9c4/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 21:09:29,557 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_097e3d7f-b4c3-45b9-98fe-f0306c1bb9c4/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2022-11-02 21:09:29,630 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 21:09:29,632 INFO L263 TraceCheckSpWp]: Trace formula consists of 50 conjuncts, 9 conjunts are in the unsatisfiable core [2022-11-02 21:09:29,634 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 21:09:29,681 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:09:29,682 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 21:09:29,770 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:09:29,770 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1412817232] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 21:09:29,770 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 21:09:29,770 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [2, 2, 2] total 5 [2022-11-02 21:09:29,771 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [131909757] [2022-11-02 21:09:29,771 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 21:09:55,697 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 21:09:55,698 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-11-02 21:09:55,698 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2022-11-02 21:09:55,698 INFO L87 Difference]: Start difference. First operand 25 states and 33 transitions. cyclomatic complexity: 11 Second operand has 7 states, 6 states have (on average 4.5) internal successors, (27), 6 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:09:55,814 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 21:09:55,814 INFO L93 Difference]: Finished difference Result 53 states and 67 transitions. [2022-11-02 21:09:55,814 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 53 states and 67 transitions. [2022-11-02 21:09:55,816 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 18 [2022-11-02 21:09:55,818 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 53 states to 53 states and 67 transitions. [2022-11-02 21:09:55,818 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 53 [2022-11-02 21:09:55,818 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 53 [2022-11-02 21:09:55,819 INFO L73 IsDeterministic]: Start isDeterministic. Operand 53 states and 67 transitions. [2022-11-02 21:09:55,819 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-02 21:09:55,819 INFO L218 hiAutomatonCegarLoop]: Abstraction has 53 states and 67 transitions. [2022-11-02 21:09:55,819 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53 states and 67 transitions. [2022-11-02 21:09:55,823 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53 to 47. [2022-11-02 21:09:55,823 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 47 states, 47 states have (on average 1.297872340425532) internal successors, (61), 46 states have internal predecessors, (61), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:09:55,824 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47 states to 47 states and 61 transitions. [2022-11-02 21:09:55,824 INFO L240 hiAutomatonCegarLoop]: Abstraction has 47 states and 61 transitions. [2022-11-02 21:09:55,825 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-11-02 21:09:55,825 INFO L428 stractBuchiCegarLoop]: Abstraction has 47 states and 61 transitions. [2022-11-02 21:09:55,825 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-11-02 21:09:55,825 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 47 states and 61 transitions. [2022-11-02 21:09:55,826 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 15 [2022-11-02 21:09:55,827 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 21:09:55,827 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 21:09:55,827 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [3, 3, 3, 2, 2, 1, 1, 1] [2022-11-02 21:09:55,827 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1] [2022-11-02 21:09:55,828 INFO L748 eck$LassoCheckResult]: Stem: 279#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(8, 1);~number1~0 := 65535;~mask~0 := 1;~x~0 := 0;~c~0 := 1;~y~0 := 0; 280#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;assume { :begin_inline_displayBits } true;displayBits_#in~value#1 := ~mask~0;havoc displayBits_#t~nondet3#1, displayBits_#t~ite4#1, displayBits_#t~ret5#1, displayBits_#t~ret6#1, displayBits_#t~ret7#1, displayBits_~value#1, displayBits_~displayMask~0#1;displayBits_~value#1 := displayBits_#in~value#1;displayBits_~displayMask~0#1 := 2147483648;havoc displayBits_#t~nondet3#1; 293#L285-2 assume !!(~c~0 <= 32); 309#L286 assume !(0 != (if 0 == displayBits_~value#1 || 0 == displayBits_~displayMask~0#1 then 0 else (if 1 == displayBits_~displayMask~0#1 then (if 1 == displayBits_~value#1 || 0 == displayBits_~value#1 then displayBits_~value#1 else (if displayBits_~value#1 >= 0 then displayBits_~value#1 % 2 else ~bitwiseAnd(displayBits_~value#1, displayBits_~displayMask~0#1))) else (if 1 == displayBits_~value#1 then (if 1 == displayBits_~displayMask~0#1 || 0 == displayBits_~displayMask~0#1 then displayBits_~displayMask~0#1 else (if displayBits_~displayMask~0#1 >= 0 then displayBits_~displayMask~0#1 % 2 else ~bitwiseAnd(displayBits_~value#1, displayBits_~displayMask~0#1))) else ~bitwiseAnd(displayBits_~value#1, displayBits_~displayMask~0#1)))) % 4294967296);displayBits_#t~ite4#1 := 48; 308#L286-2 call displayBits_#t~ret5#1 := putchar(displayBits_#t~ite4#1);havoc displayBits_#t~ite4#1;havoc displayBits_#t~ret5#1;displayBits_~value#1 := 2 * displayBits_~value#1; 307#L288 assume !(0 == (if ~c~0 < 0 && 0 != ~c~0 % 8 then ~c~0 % 8 - 8 else ~c~0 % 8)); 302#L288-2 ~mask~0 := ~mask~0;~c~0 := ~c~0 + ~mask~0; 303#L285-2 assume !!(~c~0 <= 32); 304#L286 assume 0 != (if 0 == displayBits_~value#1 || 0 == displayBits_~displayMask~0#1 then 0 else (if 1 == displayBits_~displayMask~0#1 then (if 1 == displayBits_~value#1 || 0 == displayBits_~value#1 then displayBits_~value#1 else (if displayBits_~value#1 >= 0 then displayBits_~value#1 % 2 else ~bitwiseAnd(displayBits_~value#1, displayBits_~displayMask~0#1))) else (if 1 == displayBits_~value#1 then (if 1 == displayBits_~displayMask~0#1 || 0 == displayBits_~displayMask~0#1 then displayBits_~displayMask~0#1 else (if displayBits_~displayMask~0#1 >= 0 then displayBits_~displayMask~0#1 % 2 else ~bitwiseAnd(displayBits_~value#1, displayBits_~displayMask~0#1))) else ~bitwiseAnd(displayBits_~value#1, displayBits_~displayMask~0#1)))) % 4294967296;displayBits_#t~ite4#1 := 49; 320#L286-2 call displayBits_#t~ret5#1 := putchar(displayBits_#t~ite4#1);havoc displayBits_#t~ite4#1;havoc displayBits_#t~ret5#1;displayBits_~value#1 := 2 * displayBits_~value#1; 319#L288 assume !(0 == (if ~c~0 < 0 && 0 != ~c~0 % 8 then ~c~0 % 8 - 8 else ~c~0 % 8)); 318#L288-2 ~mask~0 := ~mask~0;~c~0 := ~c~0 + ~mask~0; 316#L285-2 assume !!(~c~0 <= 32); 317#L286 assume 0 != (if 0 == displayBits_~value#1 || 0 == displayBits_~displayMask~0#1 then 0 else (if 1 == displayBits_~displayMask~0#1 then (if 1 == displayBits_~value#1 || 0 == displayBits_~value#1 then displayBits_~value#1 else (if displayBits_~value#1 >= 0 then displayBits_~value#1 % 2 else ~bitwiseAnd(displayBits_~value#1, displayBits_~displayMask~0#1))) else (if 1 == displayBits_~value#1 then (if 1 == displayBits_~displayMask~0#1 || 0 == displayBits_~displayMask~0#1 then displayBits_~displayMask~0#1 else (if displayBits_~displayMask~0#1 >= 0 then displayBits_~displayMask~0#1 % 2 else ~bitwiseAnd(displayBits_~value#1, displayBits_~displayMask~0#1))) else ~bitwiseAnd(displayBits_~value#1, displayBits_~displayMask~0#1)))) % 4294967296;displayBits_#t~ite4#1 := 49; 321#L286-2 call displayBits_#t~ret5#1 := putchar(displayBits_#t~ite4#1);havoc displayBits_#t~ite4#1;havoc displayBits_#t~ret5#1;displayBits_~value#1 := 2 * displayBits_~value#1; 299#L288 assume !(0 == (if ~c~0 < 0 && 0 != ~c~0 % 8 then ~c~0 % 8 - 8 else ~c~0 % 8)); 300#L288-2 [2022-11-02 21:09:55,828 INFO L750 eck$LassoCheckResult]: Loop: 300#L288-2 ~mask~0 := ~mask~0;~c~0 := ~c~0 + ~mask~0; 306#L285-2 assume !!(~c~0 <= 32); 305#L286 assume !(0 != (if 0 == displayBits_~value#1 || 0 == displayBits_~displayMask~0#1 then 0 else (if 1 == displayBits_~displayMask~0#1 then (if 1 == displayBits_~value#1 || 0 == displayBits_~value#1 then displayBits_~value#1 else (if displayBits_~value#1 >= 0 then displayBits_~value#1 % 2 else ~bitwiseAnd(displayBits_~value#1, displayBits_~displayMask~0#1))) else (if 1 == displayBits_~value#1 then (if 1 == displayBits_~displayMask~0#1 || 0 == displayBits_~displayMask~0#1 then displayBits_~displayMask~0#1 else (if displayBits_~displayMask~0#1 >= 0 then displayBits_~displayMask~0#1 % 2 else ~bitwiseAnd(displayBits_~value#1, displayBits_~displayMask~0#1))) else ~bitwiseAnd(displayBits_~value#1, displayBits_~displayMask~0#1)))) % 4294967296);displayBits_#t~ite4#1 := 48; 297#L286-2 call displayBits_#t~ret5#1 := putchar(displayBits_#t~ite4#1);havoc displayBits_#t~ite4#1;havoc displayBits_#t~ret5#1;displayBits_~value#1 := 2 * displayBits_~value#1; 298#L288 assume 0 == (if ~c~0 < 0 && 0 != ~c~0 % 8 then ~c~0 % 8 - 8 else ~c~0 % 8);call displayBits_#t~ret6#1 := putchar(32);havoc displayBits_#t~ret6#1; 300#L288-2 [2022-11-02 21:09:55,828 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:09:55,828 INFO L85 PathProgramCache]: Analyzing trace with hash 1432673549, now seen corresponding path program 1 times [2022-11-02 21:09:55,829 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:09:55,829 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1017448103] [2022-11-02 21:09:55,829 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:09:55,829 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:09:55,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:09:55,855 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:09:55,878 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:09:55,893 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:09:55,894 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:09:55,895 INFO L85 PathProgramCache]: Analyzing trace with hash 52060832, now seen corresponding path program 4 times [2022-11-02 21:09:55,895 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:09:55,895 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [611935187] [2022-11-02 21:09:55,898 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:09:55,899 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:09:55,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:09:55,913 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:09:55,919 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:09:55,931 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:09:55,931 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:09:55,931 INFO L85 PathProgramCache]: Analyzing trace with hash -1615737580, now seen corresponding path program 1 times [2022-11-02 21:09:55,932 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:09:55,932 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [67621613] [2022-11-02 21:09:55,932 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:09:55,932 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:09:55,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 21:09:56,280 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 27 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:09:56,280 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 21:09:56,281 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [67621613] [2022-11-02 21:09:56,285 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [67621613] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 21:09:56,285 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [162689498] [2022-11-02 21:09:56,285 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:09:56,286 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 21:09:56,286 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_097e3d7f-b4c3-45b9-98fe-f0306c1bb9c4/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 21:09:56,290 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_097e3d7f-b4c3-45b9-98fe-f0306c1bb9c4/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 21:09:56,292 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_097e3d7f-b4c3-45b9-98fe-f0306c1bb9c4/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2022-11-02 21:09:56,375 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 21:09:56,376 INFO L263 TraceCheckSpWp]: Trace formula consists of 72 conjuncts, 17 conjunts are in the unsatisfiable core [2022-11-02 21:09:56,378 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 21:09:56,490 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 27 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:09:56,491 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 21:09:56,632 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 27 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 21:09:56,632 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [162689498] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 21:09:56,632 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 21:09:56,633 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4] total 10 [2022-11-02 21:09:56,633 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1497629498] [2022-11-02 21:09:56,633 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 21:10:02,410 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 21:10:02,412 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2022-11-02 21:10:02,412 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=41, Invalid=91, Unknown=0, NotChecked=0, Total=132 [2022-11-02 21:10:02,414 INFO L87 Difference]: Start difference. First operand 47 states and 61 transitions. cyclomatic complexity: 17 Second operand has 12 states, 11 states have (on average 4.7272727272727275) internal successors, (52), 11 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:10:02,794 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 21:10:02,795 INFO L93 Difference]: Finished difference Result 101 states and 127 transitions. [2022-11-02 21:10:02,795 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 101 states and 127 transitions. [2022-11-02 21:10:02,796 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 18 [2022-11-02 21:10:02,800 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 101 states to 101 states and 127 transitions. [2022-11-02 21:10:02,800 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 101 [2022-11-02 21:10:02,801 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 101 [2022-11-02 21:10:02,801 INFO L73 IsDeterministic]: Start isDeterministic. Operand 101 states and 127 transitions. [2022-11-02 21:10:02,801 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-02 21:10:02,801 INFO L218 hiAutomatonCegarLoop]: Abstraction has 101 states and 127 transitions. [2022-11-02 21:10:02,802 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 101 states and 127 transitions. [2022-11-02 21:10:02,807 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 101 to 95. [2022-11-02 21:10:02,807 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 95 states, 95 states have (on average 1.2736842105263158) internal successors, (121), 94 states have internal predecessors, (121), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 21:10:02,809 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 95 states to 95 states and 121 transitions. [2022-11-02 21:10:02,809 INFO L240 hiAutomatonCegarLoop]: Abstraction has 95 states and 121 transitions. [2022-11-02 21:10:02,809 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2022-11-02 21:10:02,810 INFO L428 stractBuchiCegarLoop]: Abstraction has 95 states and 121 transitions. [2022-11-02 21:10:02,810 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-11-02 21:10:02,810 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 95 states and 121 transitions. [2022-11-02 21:10:02,811 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 15 [2022-11-02 21:10:02,812 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 21:10:02,812 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 21:10:02,813 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [7, 7, 7, 6, 6, 1, 1, 1] [2022-11-02 21:10:02,813 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1] [2022-11-02 21:10:02,813 INFO L748 eck$LassoCheckResult]: Stem: 570#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(8, 1);~number1~0 := 65535;~mask~0 := 1;~x~0 := 0;~c~0 := 1;~y~0 := 0; 571#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;assume { :begin_inline_displayBits } true;displayBits_#in~value#1 := ~mask~0;havoc displayBits_#t~nondet3#1, displayBits_#t~ite4#1, displayBits_#t~ret5#1, displayBits_#t~ret6#1, displayBits_#t~ret7#1, displayBits_~value#1, displayBits_~displayMask~0#1;displayBits_~value#1 := displayBits_#in~value#1;displayBits_~displayMask~0#1 := 2147483648;havoc displayBits_#t~nondet3#1; 584#L285-2 assume !!(~c~0 <= 32); 606#L286 assume !(0 != (if 0 == displayBits_~value#1 || 0 == displayBits_~displayMask~0#1 then 0 else (if 1 == displayBits_~displayMask~0#1 then (if 1 == displayBits_~value#1 || 0 == displayBits_~value#1 then displayBits_~value#1 else (if displayBits_~value#1 >= 0 then displayBits_~value#1 % 2 else ~bitwiseAnd(displayBits_~value#1, displayBits_~displayMask~0#1))) else (if 1 == displayBits_~value#1 then (if 1 == displayBits_~displayMask~0#1 || 0 == displayBits_~displayMask~0#1 then displayBits_~displayMask~0#1 else (if displayBits_~displayMask~0#1 >= 0 then displayBits_~displayMask~0#1 % 2 else ~bitwiseAnd(displayBits_~value#1, displayBits_~displayMask~0#1))) else ~bitwiseAnd(displayBits_~value#1, displayBits_~displayMask~0#1)))) % 4294967296);displayBits_#t~ite4#1 := 48; 607#L286-2 call displayBits_#t~ret5#1 := putchar(displayBits_#t~ite4#1);havoc displayBits_#t~ite4#1;havoc displayBits_#t~ret5#1;displayBits_~value#1 := 2 * displayBits_~value#1; 615#L288 assume !(0 == (if ~c~0 < 0 && 0 != ~c~0 % 8 then ~c~0 % 8 - 8 else ~c~0 % 8)); 614#L288-2 ~mask~0 := ~mask~0;~c~0 := ~c~0 + ~mask~0; 613#L285-2 assume !!(~c~0 <= 32); 608#L286 assume 0 != (if 0 == displayBits_~value#1 || 0 == displayBits_~displayMask~0#1 then 0 else (if 1 == displayBits_~displayMask~0#1 then (if 1 == displayBits_~value#1 || 0 == displayBits_~value#1 then displayBits_~value#1 else (if displayBits_~value#1 >= 0 then displayBits_~value#1 % 2 else ~bitwiseAnd(displayBits_~value#1, displayBits_~displayMask~0#1))) else (if 1 == displayBits_~value#1 then (if 1 == displayBits_~displayMask~0#1 || 0 == displayBits_~displayMask~0#1 then displayBits_~displayMask~0#1 else (if displayBits_~displayMask~0#1 >= 0 then displayBits_~displayMask~0#1 % 2 else ~bitwiseAnd(displayBits_~value#1, displayBits_~displayMask~0#1))) else ~bitwiseAnd(displayBits_~value#1, displayBits_~displayMask~0#1)))) % 4294967296;displayBits_#t~ite4#1 := 49; 605#L286-2 call displayBits_#t~ret5#1 := putchar(displayBits_#t~ite4#1);havoc displayBits_#t~ite4#1;havoc displayBits_#t~ret5#1;displayBits_~value#1 := 2 * displayBits_~value#1; 604#L288 assume !(0 == (if ~c~0 < 0 && 0 != ~c~0 % 8 then ~c~0 % 8 - 8 else ~c~0 % 8)); 595#L288-2 ~mask~0 := ~mask~0;~c~0 := ~c~0 + ~mask~0; 596#L285-2 assume !!(~c~0 <= 32); 609#L286 assume 0 != (if 0 == displayBits_~value#1 || 0 == displayBits_~displayMask~0#1 then 0 else (if 1 == displayBits_~displayMask~0#1 then (if 1 == displayBits_~value#1 || 0 == displayBits_~value#1 then displayBits_~value#1 else (if displayBits_~value#1 >= 0 then displayBits_~value#1 % 2 else ~bitwiseAnd(displayBits_~value#1, displayBits_~displayMask~0#1))) else (if 1 == displayBits_~value#1 then (if 1 == displayBits_~displayMask~0#1 || 0 == displayBits_~displayMask~0#1 then displayBits_~displayMask~0#1 else (if displayBits_~displayMask~0#1 >= 0 then displayBits_~displayMask~0#1 % 2 else ~bitwiseAnd(displayBits_~value#1, displayBits_~displayMask~0#1))) else ~bitwiseAnd(displayBits_~value#1, displayBits_~displayMask~0#1)))) % 4294967296;displayBits_#t~ite4#1 := 49; 612#L286-2 call displayBits_#t~ret5#1 := putchar(displayBits_#t~ite4#1);havoc displayBits_#t~ite4#1;havoc displayBits_#t~ret5#1;displayBits_~value#1 := 2 * displayBits_~value#1; 611#L288 assume !(0 == (if ~c~0 < 0 && 0 != ~c~0 % 8 then ~c~0 % 8 - 8 else ~c~0 % 8)); 610#L288-2 ~mask~0 := ~mask~0;~c~0 := ~c~0 + ~mask~0; 597#L285-2 assume !!(~c~0 <= 32); 598#L286 assume 0 != (if 0 == displayBits_~value#1 || 0 == displayBits_~displayMask~0#1 then 0 else (if 1 == displayBits_~displayMask~0#1 then (if 1 == displayBits_~value#1 || 0 == displayBits_~value#1 then displayBits_~value#1 else (if displayBits_~value#1 >= 0 then displayBits_~value#1 % 2 else ~bitwiseAnd(displayBits_~value#1, displayBits_~displayMask~0#1))) else (if 1 == displayBits_~value#1 then (if 1 == displayBits_~displayMask~0#1 || 0 == displayBits_~displayMask~0#1 then displayBits_~displayMask~0#1 else (if displayBits_~displayMask~0#1 >= 0 then displayBits_~displayMask~0#1 % 2 else ~bitwiseAnd(displayBits_~value#1, displayBits_~displayMask~0#1))) else ~bitwiseAnd(displayBits_~value#1, displayBits_~displayMask~0#1)))) % 4294967296;displayBits_#t~ite4#1 := 49; 661#L286-2 call displayBits_#t~ret5#1 := putchar(displayBits_#t~ite4#1);havoc displayBits_#t~ite4#1;havoc displayBits_#t~ret5#1;displayBits_~value#1 := 2 * displayBits_~value#1; 591#L288 assume !(0 == (if ~c~0 < 0 && 0 != ~c~0 % 8 then ~c~0 % 8 - 8 else ~c~0 % 8)); 592#L288-2 ~mask~0 := ~mask~0;~c~0 := ~c~0 + ~mask~0; 601#L285-2 assume !!(~c~0 <= 32); 603#L286 assume 0 != (if 0 == displayBits_~value#1 || 0 == displayBits_~displayMask~0#1 then 0 else (if 1 == displayBits_~displayMask~0#1 then (if 1 == displayBits_~value#1 || 0 == displayBits_~value#1 then displayBits_~value#1 else (if displayBits_~value#1 >= 0 then displayBits_~value#1 % 2 else ~bitwiseAnd(displayBits_~value#1, displayBits_~displayMask~0#1))) else (if 1 == displayBits_~value#1 then (if 1 == displayBits_~displayMask~0#1 || 0 == displayBits_~displayMask~0#1 then displayBits_~displayMask~0#1 else (if displayBits_~displayMask~0#1 >= 0 then displayBits_~displayMask~0#1 % 2 else ~bitwiseAnd(displayBits_~value#1, displayBits_~displayMask~0#1))) else ~bitwiseAnd(displayBits_~value#1, displayBits_~displayMask~0#1)))) % 4294967296;displayBits_#t~ite4#1 := 49; 640#L286-2 call displayBits_#t~ret5#1 := putchar(displayBits_#t~ite4#1);havoc displayBits_#t~ite4#1;havoc displayBits_#t~ret5#1;displayBits_~value#1 := 2 * displayBits_~value#1; 639#L288 assume !(0 == (if ~c~0 < 0 && 0 != ~c~0 % 8 then ~c~0 % 8 - 8 else ~c~0 % 8)); 638#L288-2 ~mask~0 := ~mask~0;~c~0 := ~c~0 + ~mask~0; 637#L285-2 assume !!(~c~0 <= 32); 636#L286 assume 0 != (if 0 == displayBits_~value#1 || 0 == displayBits_~displayMask~0#1 then 0 else (if 1 == displayBits_~displayMask~0#1 then (if 1 == displayBits_~value#1 || 0 == displayBits_~value#1 then displayBits_~value#1 else (if displayBits_~value#1 >= 0 then displayBits_~value#1 % 2 else ~bitwiseAnd(displayBits_~value#1, displayBits_~displayMask~0#1))) else (if 1 == displayBits_~value#1 then (if 1 == displayBits_~displayMask~0#1 || 0 == displayBits_~displayMask~0#1 then displayBits_~displayMask~0#1 else (if displayBits_~displayMask~0#1 >= 0 then displayBits_~displayMask~0#1 % 2 else ~bitwiseAnd(displayBits_~value#1, displayBits_~displayMask~0#1))) else ~bitwiseAnd(displayBits_~value#1, displayBits_~displayMask~0#1)))) % 4294967296;displayBits_#t~ite4#1 := 49; 635#L286-2 call displayBits_#t~ret5#1 := putchar(displayBits_#t~ite4#1);havoc displayBits_#t~ite4#1;havoc displayBits_#t~ret5#1;displayBits_~value#1 := 2 * displayBits_~value#1; 634#L288 assume !(0 == (if ~c~0 < 0 && 0 != ~c~0 % 8 then ~c~0 % 8 - 8 else ~c~0 % 8)); 633#L288-2 ~mask~0 := ~mask~0;~c~0 := ~c~0 + ~mask~0; 631#L285-2 assume !!(~c~0 <= 32); 630#L286 assume 0 != (if 0 == displayBits_~value#1 || 0 == displayBits_~displayMask~0#1 then 0 else (if 1 == displayBits_~displayMask~0#1 then (if 1 == displayBits_~value#1 || 0 == displayBits_~value#1 then displayBits_~value#1 else (if displayBits_~value#1 >= 0 then displayBits_~value#1 % 2 else ~bitwiseAnd(displayBits_~value#1, displayBits_~displayMask~0#1))) else (if 1 == displayBits_~value#1 then (if 1 == displayBits_~displayMask~0#1 || 0 == displayBits_~displayMask~0#1 then displayBits_~displayMask~0#1 else (if displayBits_~displayMask~0#1 >= 0 then displayBits_~displayMask~0#1 % 2 else ~bitwiseAnd(displayBits_~value#1, displayBits_~displayMask~0#1))) else ~bitwiseAnd(displayBits_~value#1, displayBits_~displayMask~0#1)))) % 4294967296;displayBits_#t~ite4#1 := 49; 629#L286-2 call displayBits_#t~ret5#1 := putchar(displayBits_#t~ite4#1);havoc displayBits_#t~ite4#1;havoc displayBits_#t~ret5#1;displayBits_~value#1 := 2 * displayBits_~value#1; 628#L288 assume !(0 == (if ~c~0 < 0 && 0 != ~c~0 % 8 then ~c~0 % 8 - 8 else ~c~0 % 8)); 626#L288-2 [2022-11-02 21:10:02,813 INFO L750 eck$LassoCheckResult]: Loop: 626#L288-2 ~mask~0 := ~mask~0;~c~0 := ~c~0 + ~mask~0; 625#L285-2 assume !!(~c~0 <= 32); 600#L286 assume !(0 != (if 0 == displayBits_~value#1 || 0 == displayBits_~displayMask~0#1 then 0 else (if 1 == displayBits_~displayMask~0#1 then (if 1 == displayBits_~value#1 || 0 == displayBits_~value#1 then displayBits_~value#1 else (if displayBits_~value#1 >= 0 then displayBits_~value#1 % 2 else ~bitwiseAnd(displayBits_~value#1, displayBits_~displayMask~0#1))) else (if 1 == displayBits_~value#1 then (if 1 == displayBits_~displayMask~0#1 || 0 == displayBits_~displayMask~0#1 then displayBits_~displayMask~0#1 else (if displayBits_~displayMask~0#1 >= 0 then displayBits_~displayMask~0#1 % 2 else ~bitwiseAnd(displayBits_~value#1, displayBits_~displayMask~0#1))) else ~bitwiseAnd(displayBits_~value#1, displayBits_~displayMask~0#1)))) % 4294967296);displayBits_#t~ite4#1 := 48; 588#L286-2 call displayBits_#t~ret5#1 := putchar(displayBits_#t~ite4#1);havoc displayBits_#t~ite4#1;havoc displayBits_#t~ret5#1;displayBits_~value#1 := 2 * displayBits_~value#1; 589#L288 assume 0 == (if ~c~0 < 0 && 0 != ~c~0 % 8 then ~c~0 % 8 - 8 else ~c~0 % 8);call displayBits_#t~ret6#1 := putchar(32);havoc displayBits_#t~ret6#1; 626#L288-2 [2022-11-02 21:10:02,814 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:10:02,814 INFO L85 PathProgramCache]: Analyzing trace with hash -894738995, now seen corresponding path program 2 times [2022-11-02 21:10:02,814 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:10:02,815 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2115624324] [2022-11-02 21:10:02,815 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:10:02,815 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:10:02,874 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:10:02,874 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:10:02,952 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:10:02,964 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:10:02,969 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:10:02,970 INFO L85 PathProgramCache]: Analyzing trace with hash 52060832, now seen corresponding path program 5 times [2022-11-02 21:10:02,970 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:10:02,970 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1724627853] [2022-11-02 21:10:02,970 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:10:02,970 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:10:02,978 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:10:02,979 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:10:02,988 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:10:02,991 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 21:10:02,991 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 21:10:02,992 INFO L85 PathProgramCache]: Analyzing trace with hash 975029332, now seen corresponding path program 2 times [2022-11-02 21:10:02,992 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 21:10:02,992 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [286579882] [2022-11-02 21:10:02,992 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 21:10:02,992 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 21:10:03,104 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:10:03,104 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 21:10:03,174 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 21:10:03,186 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace