./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/kundu.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 5e519f3a Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2ff84eed-a969-4a89-b9aa-9129b85958c5/bin/uautomizer-Dbtcem3rbc/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2ff84eed-a969-4a89-b9aa-9129b85958c5/bin/uautomizer-Dbtcem3rbc/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2ff84eed-a969-4a89-b9aa-9129b85958c5/bin/uautomizer-Dbtcem3rbc/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2ff84eed-a969-4a89-b9aa-9129b85958c5/bin/uautomizer-Dbtcem3rbc/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/kundu.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2ff84eed-a969-4a89-b9aa-9129b85958c5/bin/uautomizer-Dbtcem3rbc/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2ff84eed-a969-4a89-b9aa-9129b85958c5/bin/uautomizer-Dbtcem3rbc --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 941010afb19994aa6e2e07f5c4b80f87a4c5e60b4e0ef3217e91339d9dc3aacb --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-5e519f3 [2022-11-02 20:50:16,456 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-11-02 20:50:16,458 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-11-02 20:50:16,510 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-11-02 20:50:16,510 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-11-02 20:50:16,517 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-11-02 20:50:16,519 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-11-02 20:50:16,523 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-11-02 20:50:16,525 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-11-02 20:50:16,532 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-11-02 20:50:16,533 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-11-02 20:50:16,536 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-11-02 20:50:16,536 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-11-02 20:50:16,540 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-11-02 20:50:16,542 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-11-02 20:50:16,544 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-11-02 20:50:16,547 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-11-02 20:50:16,548 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-11-02 20:50:16,550 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-11-02 20:50:16,553 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-11-02 20:50:16,555 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-11-02 20:50:16,556 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-11-02 20:50:16,558 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-11-02 20:50:16,559 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-11-02 20:50:16,563 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-11-02 20:50:16,564 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-11-02 20:50:16,564 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-11-02 20:50:16,565 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-11-02 20:50:16,566 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-11-02 20:50:16,567 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-11-02 20:50:16,567 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-11-02 20:50:16,568 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-11-02 20:50:16,569 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-11-02 20:50:16,570 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-11-02 20:50:16,571 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-11-02 20:50:16,572 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-11-02 20:50:16,572 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-11-02 20:50:16,573 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-11-02 20:50:16,573 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-11-02 20:50:16,574 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-11-02 20:50:16,575 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-11-02 20:50:16,576 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2ff84eed-a969-4a89-b9aa-9129b85958c5/bin/uautomizer-Dbtcem3rbc/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-11-02 20:50:16,600 INFO L113 SettingsManager]: Loading preferences was successful [2022-11-02 20:50:16,601 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-11-02 20:50:16,601 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-11-02 20:50:16,602 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-11-02 20:50:16,603 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-11-02 20:50:16,603 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-11-02 20:50:16,603 INFO L138 SettingsManager]: * Use SBE=true [2022-11-02 20:50:16,604 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-11-02 20:50:16,604 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-11-02 20:50:16,604 INFO L138 SettingsManager]: * Use old map elimination=false [2022-11-02 20:50:16,604 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-11-02 20:50:16,605 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-11-02 20:50:16,605 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-11-02 20:50:16,605 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-11-02 20:50:16,606 INFO L138 SettingsManager]: * sizeof long=4 [2022-11-02 20:50:16,606 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-11-02 20:50:16,606 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-11-02 20:50:16,606 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-11-02 20:50:16,607 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-11-02 20:50:16,607 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-11-02 20:50:16,607 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-11-02 20:50:16,607 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-11-02 20:50:16,608 INFO L138 SettingsManager]: * sizeof long double=12 [2022-11-02 20:50:16,608 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-11-02 20:50:16,608 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-11-02 20:50:16,608 INFO L138 SettingsManager]: * Use constant arrays=true [2022-11-02 20:50:16,609 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-11-02 20:50:16,609 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-11-02 20:50:16,609 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-11-02 20:50:16,610 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-11-02 20:50:16,610 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-11-02 20:50:16,611 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-11-02 20:50:16,612 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2ff84eed-a969-4a89-b9aa-9129b85958c5/bin/uautomizer-Dbtcem3rbc/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2ff84eed-a969-4a89-b9aa-9129b85958c5/bin/uautomizer-Dbtcem3rbc Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 941010afb19994aa6e2e07f5c4b80f87a4c5e60b4e0ef3217e91339d9dc3aacb [2022-11-02 20:50:16,928 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-11-02 20:50:16,955 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-11-02 20:50:16,959 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-11-02 20:50:16,960 INFO L271 PluginConnector]: Initializing CDTParser... [2022-11-02 20:50:16,961 INFO L275 PluginConnector]: CDTParser initialized [2022-11-02 20:50:16,963 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2ff84eed-a969-4a89-b9aa-9129b85958c5/bin/uautomizer-Dbtcem3rbc/../../sv-benchmarks/c/systemc/kundu.cil.c [2022-11-02 20:50:17,047 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2ff84eed-a969-4a89-b9aa-9129b85958c5/bin/uautomizer-Dbtcem3rbc/data/6267c2543/014a3187107b4c999388a5c89bdd6fdc/FLAG3583c028d [2022-11-02 20:50:17,659 INFO L306 CDTParser]: Found 1 translation units. [2022-11-02 20:50:17,660 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2ff84eed-a969-4a89-b9aa-9129b85958c5/sv-benchmarks/c/systemc/kundu.cil.c [2022-11-02 20:50:17,680 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2ff84eed-a969-4a89-b9aa-9129b85958c5/bin/uautomizer-Dbtcem3rbc/data/6267c2543/014a3187107b4c999388a5c89bdd6fdc/FLAG3583c028d [2022-11-02 20:50:17,948 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2ff84eed-a969-4a89-b9aa-9129b85958c5/bin/uautomizer-Dbtcem3rbc/data/6267c2543/014a3187107b4c999388a5c89bdd6fdc [2022-11-02 20:50:17,951 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-11-02 20:50:17,953 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-11-02 20:50:17,961 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-11-02 20:50:17,961 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-11-02 20:50:17,966 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-11-02 20:50:17,967 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.11 08:50:17" (1/1) ... [2022-11-02 20:50:17,968 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@4d4282b9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 08:50:17, skipping insertion in model container [2022-11-02 20:50:17,971 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.11 08:50:17" (1/1) ... [2022-11-02 20:50:17,981 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-11-02 20:50:18,038 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-11-02 20:50:18,250 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2ff84eed-a969-4a89-b9aa-9129b85958c5/sv-benchmarks/c/systemc/kundu.cil.c[635,648] [2022-11-02 20:50:18,312 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-02 20:50:18,323 INFO L203 MainTranslator]: Completed pre-run [2022-11-02 20:50:18,337 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2ff84eed-a969-4a89-b9aa-9129b85958c5/sv-benchmarks/c/systemc/kundu.cil.c[635,648] [2022-11-02 20:50:18,373 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-02 20:50:18,392 INFO L208 MainTranslator]: Completed translation [2022-11-02 20:50:18,393 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 08:50:18 WrapperNode [2022-11-02 20:50:18,393 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-11-02 20:50:18,394 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-11-02 20:50:18,395 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-11-02 20:50:18,395 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-11-02 20:50:18,404 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 08:50:18" (1/1) ... [2022-11-02 20:50:18,414 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 08:50:18" (1/1) ... [2022-11-02 20:50:18,457 INFO L138 Inliner]: procedures = 34, calls = 40, calls flagged for inlining = 35, calls inlined = 45, statements flattened = 534 [2022-11-02 20:50:18,457 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-11-02 20:50:18,458 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-11-02 20:50:18,458 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-11-02 20:50:18,459 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-11-02 20:50:18,469 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 08:50:18" (1/1) ... [2022-11-02 20:50:18,469 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 08:50:18" (1/1) ... [2022-11-02 20:50:18,474 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 08:50:18" (1/1) ... [2022-11-02 20:50:18,475 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 08:50:18" (1/1) ... [2022-11-02 20:50:18,483 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 08:50:18" (1/1) ... [2022-11-02 20:50:18,492 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 08:50:18" (1/1) ... [2022-11-02 20:50:18,496 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 08:50:18" (1/1) ... [2022-11-02 20:50:18,498 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 08:50:18" (1/1) ... [2022-11-02 20:50:18,503 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-11-02 20:50:18,504 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-11-02 20:50:18,504 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-11-02 20:50:18,504 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-11-02 20:50:18,505 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 08:50:18" (1/1) ... [2022-11-02 20:50:18,513 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-02 20:50:18,528 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2ff84eed-a969-4a89-b9aa-9129b85958c5/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 20:50:18,542 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2ff84eed-a969-4a89-b9aa-9129b85958c5/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-02 20:50:18,583 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2ff84eed-a969-4a89-b9aa-9129b85958c5/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-11-02 20:50:18,611 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-11-02 20:50:18,611 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-11-02 20:50:18,612 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-11-02 20:50:18,612 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-11-02 20:50:18,713 INFO L235 CfgBuilder]: Building ICFG [2022-11-02 20:50:18,716 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-11-02 20:50:19,371 INFO L276 CfgBuilder]: Performing block encoding [2022-11-02 20:50:19,381 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-11-02 20:50:19,381 INFO L300 CfgBuilder]: Removed 5 assume(true) statements. [2022-11-02 20:50:19,384 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.11 08:50:19 BoogieIcfgContainer [2022-11-02 20:50:19,385 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-11-02 20:50:19,386 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-11-02 20:50:19,386 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-11-02 20:50:19,400 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-11-02 20:50:19,401 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-02 20:50:19,402 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 02.11 08:50:17" (1/3) ... [2022-11-02 20:50:19,404 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1a82dd86 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 02.11 08:50:19, skipping insertion in model container [2022-11-02 20:50:19,404 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-02 20:50:19,404 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 08:50:18" (2/3) ... [2022-11-02 20:50:19,405 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1a82dd86 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 02.11 08:50:19, skipping insertion in model container [2022-11-02 20:50:19,405 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-02 20:50:19,406 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.11 08:50:19" (3/3) ... [2022-11-02 20:50:19,407 INFO L332 chiAutomizerObserver]: Analyzing ICFG kundu.cil.c [2022-11-02 20:50:19,507 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-11-02 20:50:19,507 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-11-02 20:50:19,507 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-11-02 20:50:19,508 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-11-02 20:50:19,508 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-11-02 20:50:19,508 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-11-02 20:50:19,508 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-11-02 20:50:19,509 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-11-02 20:50:19,520 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 191 states, 190 states have (on average 1.5052631578947369) internal successors, (286), 190 states have internal predecessors, (286), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:50:19,579 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 154 [2022-11-02 20:50:19,579 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 20:50:19,579 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 20:50:19,603 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 20:50:19,605 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 20:50:19,606 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-11-02 20:50:19,607 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 191 states, 190 states have (on average 1.5052631578947369) internal successors, (286), 190 states have internal predecessors, (286), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:50:19,612 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 154 [2022-11-02 20:50:19,615 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 20:50:19,615 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 20:50:19,619 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 20:50:19,621 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 20:50:19,633 INFO L748 eck$LassoCheckResult]: Stem: 171#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 70#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 68#L613true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 55#L298true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 95#L305true assume !(1 == ~P_1_i~0);~P_1_st~0 := 2; 165#L305-2true assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 112#L310-1true assume !(1 == ~C_1_i~0);~C_1_st~0 := 2; 169#L315-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 157#L424true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 133#L118true assume !(1 == ~P_1_pc~0); 88#L118-2true is_P_1_triggered_~__retres1~0#1 := 0; 160#L129true is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 91#L130true activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 6#L491true assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 166#L491-2true assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 99#L186true assume 1 == ~P_2_pc~0; 175#L187true assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 107#L197true is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 105#L198true activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 73#L499true assume !(0 != activate_threads_~tmp___0~1#1); 81#L499-2true assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 37#L268true assume 1 == ~C_1_pc~0; 96#L269true assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 64#L289true is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 185#L290true activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 38#L507true assume !(0 != activate_threads_~tmp___1~1#1); 49#L507-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 125#L432true assume { :end_inline_reset_delta_events } true; 69#L561-2true [2022-11-02 20:50:19,635 INFO L750 eck$LassoCheckResult]: Loop: 69#L561-2true assume !false; 118#L562true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 178#L397true assume !true; 179#L413true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 76#L298-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 176#L424-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 161#L118-6true assume !(1 == ~P_1_pc~0); 8#L118-8true is_P_1_triggered_~__retres1~0#1 := 0; 24#L129-2true is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 89#L130-2true activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 141#L491-6true assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 47#L491-8true assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 98#L186-6true assume !(1 == ~P_2_pc~0); 48#L186-8true is_P_2_triggered_~__retres1~1#1 := 0; 153#L197-2true is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 111#L198-2true activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 56#L499-6true assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 53#L499-8true assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 20#L268-6true assume 1 == ~C_1_pc~0; 182#L269-2true assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 28#L289-2true is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 152#L290-2true activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 36#L507-6true assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 127#L507-8true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 106#L432-1true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 109#L328-1true assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 116#L345-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 42#L346-1true start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 3#L580true assume !(0 == start_simulation_~tmp~3#1); 22#L580-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 104#L328-2true assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 162#L345-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 25#L346-2true stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 123#L535true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12#L542true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 79#L543true start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 110#L593true assume !(0 != start_simulation_~tmp___0~2#1); 69#L561-2true [2022-11-02 20:50:19,651 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:50:19,652 INFO L85 PathProgramCache]: Analyzing trace with hash 1332213672, now seen corresponding path program 1 times [2022-11-02 20:50:19,666 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:50:19,667 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1570338232] [2022-11-02 20:50:19,667 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:50:19,668 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:50:19,793 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:50:19,903 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:50:19,904 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 20:50:19,904 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1570338232] [2022-11-02 20:50:19,905 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1570338232] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-02 20:50:19,906 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-02 20:50:19,906 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-02 20:50:19,908 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1899325367] [2022-11-02 20:50:19,909 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-02 20:50:19,914 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-02 20:50:19,915 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:50:19,916 INFO L85 PathProgramCache]: Analyzing trace with hash -1462313658, now seen corresponding path program 1 times [2022-11-02 20:50:19,916 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:50:19,916 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1588087673] [2022-11-02 20:50:19,917 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:50:19,917 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:50:19,931 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:50:19,950 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:50:19,951 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 20:50:19,951 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1588087673] [2022-11-02 20:50:19,951 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1588087673] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-02 20:50:19,952 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-02 20:50:19,952 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-02 20:50:19,952 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1780870095] [2022-11-02 20:50:19,953 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-02 20:50:19,954 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-02 20:50:19,955 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 20:50:19,995 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-02 20:50:19,997 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-02 20:50:20,003 INFO L87 Difference]: Start difference. First operand has 191 states, 190 states have (on average 1.5052631578947369) internal successors, (286), 190 states have internal predecessors, (286), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 9.333333333333334) internal successors, (28), 3 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:50:20,068 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 20:50:20,070 INFO L93 Difference]: Finished difference Result 187 states and 270 transitions. [2022-11-02 20:50:20,073 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 187 states and 270 transitions. [2022-11-02 20:50:20,087 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 146 [2022-11-02 20:50:20,097 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 187 states to 179 states and 262 transitions. [2022-11-02 20:50:20,100 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 179 [2022-11-02 20:50:20,101 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 179 [2022-11-02 20:50:20,102 INFO L73 IsDeterministic]: Start isDeterministic. Operand 179 states and 262 transitions. [2022-11-02 20:50:20,106 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-02 20:50:20,106 INFO L218 hiAutomatonCegarLoop]: Abstraction has 179 states and 262 transitions. [2022-11-02 20:50:20,128 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 179 states and 262 transitions. [2022-11-02 20:50:20,162 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 179 to 179. [2022-11-02 20:50:20,166 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 179 states, 179 states have (on average 1.4636871508379887) internal successors, (262), 178 states have internal predecessors, (262), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:50:20,169 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 179 states to 179 states and 262 transitions. [2022-11-02 20:50:20,170 INFO L240 hiAutomatonCegarLoop]: Abstraction has 179 states and 262 transitions. [2022-11-02 20:50:20,172 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-02 20:50:20,182 INFO L428 stractBuchiCegarLoop]: Abstraction has 179 states and 262 transitions. [2022-11-02 20:50:20,182 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-11-02 20:50:20,182 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 179 states and 262 transitions. [2022-11-02 20:50:20,185 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 146 [2022-11-02 20:50:20,186 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 20:50:20,186 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 20:50:20,190 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 20:50:20,190 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 20:50:20,192 INFO L748 eck$LassoCheckResult]: Stem: 564#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 506#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 502#L613 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 487#L298 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 488#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 533#L305-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 544#L310-1 assume !(1 == ~C_1_i~0);~C_1_st~0 := 2; 545#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 562#L424 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 551#L118 assume !(1 == ~P_1_pc~0); 525#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 526#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 529#L130 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 396#L491 assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 397#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 535#L186 assume 1 == ~P_2_pc~0; 536#L187 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 418#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 539#L198 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 509#L499 assume !(0 != activate_threads_~tmp___0~1#1); 510#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 459#L268 assume 1 == ~C_1_pc~0; 461#L269 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 498#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 499#L290 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 462#L507 assume !(0 != activate_threads_~tmp___1~1#1); 463#L507-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 479#L432 assume { :end_inline_reset_delta_events } true; 503#L561-2 [2022-11-02 20:50:20,200 INFO L750 eck$LassoCheckResult]: Loop: 503#L561-2 assume !false; 504#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 421#L397 assume !false; 438#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 439#L328 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 481#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 511#L346 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 512#L362 assume !(0 != eval_~tmp___2~0#1); 565#L413 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 513#L298-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 514#L424-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 563#L118-6 assume 1 == ~P_1_pc~0; 508#L119-2 assume 1 == ~P_1_ev~0;is_P_1_triggered_~__retres1~0#1 := 1; 399#L129-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 433#L130-2 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 524#L491-6 assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 473#L491-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 474#L186-6 assume 1 == ~P_2_pc~0; 534#L187-2 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 476#L197-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 543#L198-2 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 489#L499-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 486#L499-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 424#L268-6 assume 1 == ~C_1_pc~0; 425#L269-2 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 440#L289-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 441#L290-2 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 455#L507-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 456#L507-8 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 540#L432-1 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 541#L328-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 401#L345-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 466#L346-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 387#L580 assume !(0 == start_simulation_~tmp~3#1); 389#L580-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 430#L328-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 537#L345-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 434#L346-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 435#L535 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 407#L542 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 408#L543 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 517#L593 assume !(0 != start_simulation_~tmp___0~2#1); 503#L561-2 [2022-11-02 20:50:20,201 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:50:20,201 INFO L85 PathProgramCache]: Analyzing trace with hash 1466227178, now seen corresponding path program 1 times [2022-11-02 20:50:20,202 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:50:20,203 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [462260026] [2022-11-02 20:50:20,203 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:50:20,204 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:50:20,245 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:50:20,301 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:50:20,302 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 20:50:20,302 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [462260026] [2022-11-02 20:50:20,303 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [462260026] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-02 20:50:20,303 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-02 20:50:20,303 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-02 20:50:20,304 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1335419249] [2022-11-02 20:50:20,304 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-02 20:50:20,304 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-02 20:50:20,305 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:50:20,305 INFO L85 PathProgramCache]: Analyzing trace with hash 1194162143, now seen corresponding path program 1 times [2022-11-02 20:50:20,306 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:50:20,306 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [387539575] [2022-11-02 20:50:20,306 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:50:20,307 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:50:20,331 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:50:20,416 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:50:20,416 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 20:50:20,416 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [387539575] [2022-11-02 20:50:20,417 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [387539575] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-02 20:50:20,417 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-02 20:50:20,417 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-02 20:50:20,418 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [183727149] [2022-11-02 20:50:20,418 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-02 20:50:20,418 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-02 20:50:20,419 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 20:50:20,419 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-02 20:50:20,419 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-02 20:50:20,420 INFO L87 Difference]: Start difference. First operand 179 states and 262 transitions. cyclomatic complexity: 84 Second operand has 3 states, 3 states have (on average 9.333333333333334) internal successors, (28), 3 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:50:20,439 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 20:50:20,440 INFO L93 Difference]: Finished difference Result 179 states and 261 transitions. [2022-11-02 20:50:20,440 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 179 states and 261 transitions. [2022-11-02 20:50:20,442 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 146 [2022-11-02 20:50:20,443 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 179 states to 179 states and 261 transitions. [2022-11-02 20:50:20,444 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 179 [2022-11-02 20:50:20,444 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 179 [2022-11-02 20:50:20,445 INFO L73 IsDeterministic]: Start isDeterministic. Operand 179 states and 261 transitions. [2022-11-02 20:50:20,446 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-02 20:50:20,446 INFO L218 hiAutomatonCegarLoop]: Abstraction has 179 states and 261 transitions. [2022-11-02 20:50:20,446 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 179 states and 261 transitions. [2022-11-02 20:50:20,451 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 179 to 179. [2022-11-02 20:50:20,452 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 179 states, 179 states have (on average 1.458100558659218) internal successors, (261), 178 states have internal predecessors, (261), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:50:20,453 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 179 states to 179 states and 261 transitions. [2022-11-02 20:50:20,453 INFO L240 hiAutomatonCegarLoop]: Abstraction has 179 states and 261 transitions. [2022-11-02 20:50:20,454 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-02 20:50:20,455 INFO L428 stractBuchiCegarLoop]: Abstraction has 179 states and 261 transitions. [2022-11-02 20:50:20,455 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-11-02 20:50:20,455 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 179 states and 261 transitions. [2022-11-02 20:50:20,457 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 146 [2022-11-02 20:50:20,457 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 20:50:20,457 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 20:50:20,458 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 20:50:20,458 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 20:50:20,459 INFO L748 eck$LassoCheckResult]: Stem: 931#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 872#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 869#L613 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 854#L298 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 855#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 900#L305-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 911#L310-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 912#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 929#L424 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 918#L118 assume !(1 == ~P_1_pc~0); 891#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 892#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 896#L130 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 761#L491 assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 762#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 902#L186 assume 1 == ~P_2_pc~0; 903#L187 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 783#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 906#L198 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 875#L499 assume !(0 != activate_threads_~tmp___0~1#1); 876#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 824#L268 assume 1 == ~C_1_pc~0; 826#L269 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 865#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 866#L290 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 827#L507 assume !(0 != activate_threads_~tmp___1~1#1); 828#L507-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 844#L432 assume { :end_inline_reset_delta_events } true; 870#L561-2 [2022-11-02 20:50:20,459 INFO L750 eck$LassoCheckResult]: Loop: 870#L561-2 assume !false; 871#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 786#L397 assume !false; 803#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 804#L328 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 846#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 878#L346 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 879#L362 assume !(0 != eval_~tmp___2~0#1); 932#L413 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 880#L298-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 881#L424-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 930#L118-6 assume !(1 == ~P_1_pc~0); 765#L118-8 is_P_1_triggered_~__retres1~0#1 := 0; 766#L129-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 800#L130-2 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 893#L491-6 assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 840#L491-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 841#L186-6 assume 1 == ~P_2_pc~0; 901#L187-2 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 843#L197-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 910#L198-2 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 856#L499-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 853#L499-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 791#L268-6 assume 1 == ~C_1_pc~0; 792#L269-2 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 807#L289-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 808#L290-2 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 822#L507-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 823#L507-8 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 907#L432-1 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 908#L328-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 768#L345-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 833#L346-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 754#L580 assume !(0 == start_simulation_~tmp~3#1); 756#L580-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 797#L328-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 904#L345-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 801#L346-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 802#L535 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 774#L542 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 775#L543 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 884#L593 assume !(0 != start_simulation_~tmp___0~2#1); 870#L561-2 [2022-11-02 20:50:20,460 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:50:20,460 INFO L85 PathProgramCache]: Analyzing trace with hash 1247372460, now seen corresponding path program 1 times [2022-11-02 20:50:20,460 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:50:20,461 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [603415013] [2022-11-02 20:50:20,461 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:50:20,461 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:50:20,476 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:50:20,565 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:50:20,566 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 20:50:20,566 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [603415013] [2022-11-02 20:50:20,566 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [603415013] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-02 20:50:20,566 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-02 20:50:20,567 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-02 20:50:20,567 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [527990152] [2022-11-02 20:50:20,567 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-02 20:50:20,568 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-02 20:50:20,568 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:50:20,568 INFO L85 PathProgramCache]: Analyzing trace with hash -577308832, now seen corresponding path program 1 times [2022-11-02 20:50:20,569 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:50:20,569 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [297717056] [2022-11-02 20:50:20,569 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:50:20,570 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:50:20,594 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:50:20,714 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:50:20,715 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 20:50:20,716 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [297717056] [2022-11-02 20:50:20,717 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [297717056] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-02 20:50:20,718 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-02 20:50:20,718 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-02 20:50:20,718 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [822315683] [2022-11-02 20:50:20,719 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-02 20:50:20,720 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-02 20:50:20,721 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 20:50:20,722 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-02 20:50:20,722 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-02 20:50:20,722 INFO L87 Difference]: Start difference. First operand 179 states and 261 transitions. cyclomatic complexity: 83 Second operand has 5 states, 5 states have (on average 5.6) internal successors, (28), 5 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:50:20,914 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 20:50:20,914 INFO L93 Difference]: Finished difference Result 483 states and 703 transitions. [2022-11-02 20:50:20,915 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 483 states and 703 transitions. [2022-11-02 20:50:20,922 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 411 [2022-11-02 20:50:20,927 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 483 states to 483 states and 703 transitions. [2022-11-02 20:50:20,928 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 483 [2022-11-02 20:50:20,929 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 483 [2022-11-02 20:50:20,930 INFO L73 IsDeterministic]: Start isDeterministic. Operand 483 states and 703 transitions. [2022-11-02 20:50:20,936 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-02 20:50:20,936 INFO L218 hiAutomatonCegarLoop]: Abstraction has 483 states and 703 transitions. [2022-11-02 20:50:20,939 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 483 states and 703 transitions. [2022-11-02 20:50:20,950 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 483 to 191. [2022-11-02 20:50:20,954 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 191 states, 191 states have (on average 1.4293193717277486) internal successors, (273), 190 states have internal predecessors, (273), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:50:20,984 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 191 states to 191 states and 273 transitions. [2022-11-02 20:50:20,984 INFO L240 hiAutomatonCegarLoop]: Abstraction has 191 states and 273 transitions. [2022-11-02 20:50:20,985 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-11-02 20:50:20,985 INFO L428 stractBuchiCegarLoop]: Abstraction has 191 states and 273 transitions. [2022-11-02 20:50:20,986 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-11-02 20:50:20,986 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 191 states and 273 transitions. [2022-11-02 20:50:20,987 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 155 [2022-11-02 20:50:20,987 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 20:50:20,987 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 20:50:20,988 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 20:50:20,988 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 20:50:20,991 INFO L748 eck$LassoCheckResult]: Stem: 1617#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 1552#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 1548#L613 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1531#L298 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1532#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 1582#L305-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 1593#L310-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 1594#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1614#L424 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 1600#L118 assume !(1 == ~P_1_pc~0); 1573#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 1574#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 1616#L130 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1440#L491 assume !(0 != activate_threads_~tmp~1#1); 1441#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 1584#L186 assume 1 == ~P_2_pc~0; 1585#L187 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 1465#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 1588#L198 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1556#L499 assume !(0 != activate_threads_~tmp___0~1#1); 1557#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 1503#L268 assume 1 == ~C_1_pc~0; 1505#L269 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 1543#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 1544#L290 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1506#L507 assume !(0 != activate_threads_~tmp___1~1#1); 1507#L507-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1526#L432 assume { :end_inline_reset_delta_events } true; 1549#L561-2 [2022-11-02 20:50:20,991 INFO L750 eck$LassoCheckResult]: Loop: 1549#L561-2 assume !false; 1550#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 1461#L397 assume !false; 1480#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1481#L328 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1522#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1558#L346 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1559#L362 assume !(0 != eval_~tmp___2~0#1); 1619#L413 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1560#L298-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1561#L424-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 1615#L118-6 assume 1 == ~P_1_pc~0; 1554#L119-2 assume 1 == ~P_1_ev~0;is_P_1_triggered_~__retres1~0#1 := 1; 1555#L129-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 1571#L130-2 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1572#L491-6 assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 1517#L491-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 1518#L186-6 assume 1 == ~P_2_pc~0; 1583#L187-2 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 1520#L197-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 1592#L198-2 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1533#L499-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 1530#L499-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 1468#L268-6 assume 1 == ~C_1_pc~0; 1469#L269-2 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 1484#L289-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 1485#L290-2 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1499#L507-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 1500#L507-8 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1589#L432-1 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1590#L328-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1445#L345-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1510#L346-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 1431#L580 assume !(0 == start_simulation_~tmp~3#1); 1433#L580-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1474#L328-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1586#L345-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1478#L346-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 1479#L535 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1451#L542 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1452#L543 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 1564#L593 assume !(0 != start_simulation_~tmp___0~2#1); 1549#L561-2 [2022-11-02 20:50:20,992 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:50:20,994 INFO L85 PathProgramCache]: Analyzing trace with hash -32491218, now seen corresponding path program 1 times [2022-11-02 20:50:20,994 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:50:20,994 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [843128364] [2022-11-02 20:50:20,995 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:50:20,995 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:50:21,005 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:50:21,101 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:50:21,102 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 20:50:21,102 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [843128364] [2022-11-02 20:50:21,103 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [843128364] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-02 20:50:21,103 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-02 20:50:21,103 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-11-02 20:50:21,103 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1915873387] [2022-11-02 20:50:21,104 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-02 20:50:21,104 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-02 20:50:21,105 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:50:21,105 INFO L85 PathProgramCache]: Analyzing trace with hash 1194162143, now seen corresponding path program 2 times [2022-11-02 20:50:21,106 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:50:21,106 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1312113350] [2022-11-02 20:50:21,106 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:50:21,107 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:50:21,120 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:50:21,172 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:50:21,173 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 20:50:21,173 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1312113350] [2022-11-02 20:50:21,173 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1312113350] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-02 20:50:21,174 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-02 20:50:21,174 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-02 20:50:21,174 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1617597898] [2022-11-02 20:50:21,174 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-02 20:50:21,175 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-02 20:50:21,175 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 20:50:21,176 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-02 20:50:21,176 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-02 20:50:21,176 INFO L87 Difference]: Start difference. First operand 191 states and 273 transitions. cyclomatic complexity: 83 Second operand has 4 states, 4 states have (on average 7.0) internal successors, (28), 4 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:50:21,301 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 20:50:21,301 INFO L93 Difference]: Finished difference Result 478 states and 671 transitions. [2022-11-02 20:50:21,302 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 478 states and 671 transitions. [2022-11-02 20:50:21,308 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 415 [2022-11-02 20:50:21,312 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 478 states to 478 states and 671 transitions. [2022-11-02 20:50:21,312 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 478 [2022-11-02 20:50:21,313 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 478 [2022-11-02 20:50:21,313 INFO L73 IsDeterministic]: Start isDeterministic. Operand 478 states and 671 transitions. [2022-11-02 20:50:21,314 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-02 20:50:21,315 INFO L218 hiAutomatonCegarLoop]: Abstraction has 478 states and 671 transitions. [2022-11-02 20:50:21,315 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 478 states and 671 transitions. [2022-11-02 20:50:21,339 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 478 to 436. [2022-11-02 20:50:21,342 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 436 states, 436 states have (on average 1.4128440366972477) internal successors, (616), 435 states have internal predecessors, (616), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:50:21,344 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 436 states to 436 states and 616 transitions. [2022-11-02 20:50:21,344 INFO L240 hiAutomatonCegarLoop]: Abstraction has 436 states and 616 transitions. [2022-11-02 20:50:21,345 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-02 20:50:21,346 INFO L428 stractBuchiCegarLoop]: Abstraction has 436 states and 616 transitions. [2022-11-02 20:50:21,346 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-11-02 20:50:21,346 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 436 states and 616 transitions. [2022-11-02 20:50:21,349 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 399 [2022-11-02 20:50:21,349 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 20:50:21,349 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 20:50:21,354 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 20:50:21,354 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 20:50:21,354 INFO L748 eck$LassoCheckResult]: Stem: 2300#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 2236#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 2234#L613 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2216#L298 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2217#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 2265#L305-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 2277#L310-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 2278#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2298#L424 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 2286#L118 assume !(1 == ~P_1_pc~0); 2256#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 2257#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 2261#L130 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2120#L491 assume !(0 != activate_threads_~tmp~1#1); 2121#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 2267#L186 assume !(1 == ~P_2_pc~0); 2141#L186-2 is_P_2_triggered_~__retres1~1#1 := 0; 2142#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 2271#L198 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2238#L499 assume !(0 != activate_threads_~tmp___0~1#1); 2239#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 2183#L268 assume 1 == ~C_1_pc~0; 2185#L269 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 2228#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 2229#L290 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2186#L507 assume !(0 != activate_threads_~tmp___1~1#1); 2187#L507-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2203#L432 assume { :end_inline_reset_delta_events } true; 2232#L561-2 [2022-11-02 20:50:21,356 INFO L750 eck$LassoCheckResult]: Loop: 2232#L561-2 assume !false; 2233#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 2302#L397 assume !false; 2163#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2164#L328 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2205#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2243#L346 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2244#L362 assume !(0 != eval_~tmp___2~0#1); 2303#L413 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2245#L298-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2246#L424-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 2299#L118-6 assume !(1 == ~P_1_pc~0); 2124#L118-8 is_P_1_triggered_~__retres1~0#1 := 0; 2125#L129-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 2162#L130-2 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2258#L491-6 assume !(0 != activate_threads_~tmp~1#1); 2199#L491-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 2200#L186-6 assume !(1 == ~P_2_pc~0); 2266#L186-8 is_P_2_triggered_~__retres1~1#1 := 0; 2505#L197-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 2504#L198-2 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2433#L499-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 2432#L499-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 2150#L268-6 assume 1 == ~C_1_pc~0; 2151#L269-2 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 2167#L289-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 2168#L290-2 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2181#L507-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 2182#L507-8 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2272#L432-1 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2273#L328-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2130#L345-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2192#L346-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 2113#L580 assume !(0 == start_simulation_~tmp~3#1); 2115#L580-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2528#L328-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2526#L345-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2525#L346-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 2524#L535 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2523#L542 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2522#L543 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 2274#L593 assume !(0 != start_simulation_~tmp___0~2#1); 2232#L561-2 [2022-11-02 20:50:21,359 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:50:21,359 INFO L85 PathProgramCache]: Analyzing trace with hash -1311815953, now seen corresponding path program 1 times [2022-11-02 20:50:21,360 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:50:21,360 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1287225876] [2022-11-02 20:50:21,360 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:50:21,361 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:50:21,375 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:50:21,447 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:50:21,447 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 20:50:21,447 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1287225876] [2022-11-02 20:50:21,448 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1287225876] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-02 20:50:21,448 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-02 20:50:21,448 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-11-02 20:50:21,448 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1418150612] [2022-11-02 20:50:21,449 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-02 20:50:21,449 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-02 20:50:21,450 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:50:21,450 INFO L85 PathProgramCache]: Analyzing trace with hash -711684829, now seen corresponding path program 1 times [2022-11-02 20:50:21,450 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:50:21,450 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [659280917] [2022-11-02 20:50:21,451 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:50:21,451 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:50:21,461 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:50:21,504 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:50:21,505 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 20:50:21,505 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [659280917] [2022-11-02 20:50:21,505 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [659280917] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-02 20:50:21,506 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-02 20:50:21,506 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-02 20:50:21,506 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [197444334] [2022-11-02 20:50:21,507 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-02 20:50:21,507 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-02 20:50:21,507 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 20:50:21,508 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-02 20:50:21,508 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-02 20:50:21,508 INFO L87 Difference]: Start difference. First operand 436 states and 616 transitions. cyclomatic complexity: 182 Second operand has 4 states, 4 states have (on average 7.0) internal successors, (28), 4 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:50:21,651 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 20:50:21,652 INFO L93 Difference]: Finished difference Result 1188 states and 1642 transitions. [2022-11-02 20:50:21,652 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1188 states and 1642 transitions. [2022-11-02 20:50:21,661 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1108 [2022-11-02 20:50:21,673 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1188 states to 1188 states and 1642 transitions. [2022-11-02 20:50:21,673 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1188 [2022-11-02 20:50:21,675 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1188 [2022-11-02 20:50:21,675 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1188 states and 1642 transitions. [2022-11-02 20:50:21,677 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-02 20:50:21,677 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1188 states and 1642 transitions. [2022-11-02 20:50:21,679 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1188 states and 1642 transitions. [2022-11-02 20:50:21,695 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1188 to 1129. [2022-11-02 20:50:21,698 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1129 states, 1129 states have (on average 1.3906111603188662) internal successors, (1570), 1128 states have internal predecessors, (1570), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:50:21,702 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1129 states to 1129 states and 1570 transitions. [2022-11-02 20:50:21,702 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1129 states and 1570 transitions. [2022-11-02 20:50:21,703 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-02 20:50:21,703 INFO L428 stractBuchiCegarLoop]: Abstraction has 1129 states and 1570 transitions. [2022-11-02 20:50:21,704 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-11-02 20:50:21,704 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1129 states and 1570 transitions. [2022-11-02 20:50:21,732 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1087 [2022-11-02 20:50:21,732 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 20:50:21,732 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 20:50:21,734 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 20:50:21,734 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 20:50:21,734 INFO L748 eck$LassoCheckResult]: Stem: 3954#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 3874#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 3871#L613 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3853#L298 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3854#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 3907#L305-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 3921#L310-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 3922#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3951#L424 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 3933#L118 assume !(1 == ~P_1_pc~0); 3898#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 3899#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 3903#L130 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 3757#L491 assume !(0 != activate_threads_~tmp~1#1); 3758#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 3908#L186 assume !(1 == ~P_2_pc~0); 3778#L186-2 is_P_2_triggered_~__retres1~1#1 := 0; 3779#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 3915#L198 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 3877#L499 assume !(0 != activate_threads_~tmp___0~1#1); 3878#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 3821#L268 assume !(1 == ~C_1_pc~0); 3822#L268-2 assume 2 == ~C_1_pc~0; 3893#L279 assume 1 == ~C_1_ev~0;is_C_1_triggered_~__retres1~2#1 := 1; 3867#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 3868#L290 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3823#L507 assume !(0 != activate_threads_~tmp___1~1#1); 3824#L507-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3841#L432 assume { :end_inline_reset_delta_events } true; 3928#L561-2 [2022-11-02 20:50:21,736 INFO L750 eck$LassoCheckResult]: Loop: 3928#L561-2 assume !false; 4614#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 4608#L397 assume !false; 4604#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 4599#L328 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 4594#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 4590#L346 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 4587#L362 assume !(0 != eval_~tmp___2~0#1); 4588#L413 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4783#L298-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4781#L424-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 4779#L118-6 assume !(1 == ~P_1_pc~0); 4777#L118-8 is_P_1_triggered_~__retres1~0#1 := 0; 4775#L129-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 4773#L130-2 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 4771#L491-6 assume !(0 != activate_threads_~tmp~1#1); 4769#L491-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 4764#L186-6 assume !(1 == ~P_2_pc~0); 4761#L186-8 is_P_2_triggered_~__retres1~1#1 := 0; 4755#L197-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 4751#L198-2 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4747#L499-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 4744#L499-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 4690#L268-6 assume !(1 == ~C_1_pc~0); 4688#L268-8 assume 2 == ~C_1_pc~0; 4684#L279-2 assume 1 == ~C_1_ev~0;is_C_1_triggered_~__retres1~2#1 := 1; 4681#L289-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 4677#L290-2 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4674#L507-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 4671#L507-8 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4668#L432-1 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 4665#L328-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 4660#L345-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 4657#L346-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 4652#L580 assume !(0 == start_simulation_~tmp~3#1); 4648#L580-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 4645#L328-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 4642#L345-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 4640#L346-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 4638#L535 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4635#L542 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4632#L543 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 4627#L593 assume !(0 != start_simulation_~tmp___0~2#1); 3928#L561-2 [2022-11-02 20:50:21,737 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:50:21,738 INFO L85 PathProgramCache]: Analyzing trace with hash -122788309, now seen corresponding path program 1 times [2022-11-02 20:50:21,738 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:50:21,739 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [648384578] [2022-11-02 20:50:21,739 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:50:21,739 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:50:21,758 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:50:21,801 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:50:21,802 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 20:50:21,802 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [648384578] [2022-11-02 20:50:21,803 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [648384578] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-02 20:50:21,803 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-02 20:50:21,803 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-02 20:50:21,809 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [667790850] [2022-11-02 20:50:21,809 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-02 20:50:21,810 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-02 20:50:21,812 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:50:21,815 INFO L85 PathProgramCache]: Analyzing trace with hash 1040752634, now seen corresponding path program 1 times [2022-11-02 20:50:21,815 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:50:21,816 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1008907381] [2022-11-02 20:50:21,816 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:50:21,816 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:50:21,825 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:50:21,911 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:50:21,912 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 20:50:21,912 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1008907381] [2022-11-02 20:50:21,912 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1008907381] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-02 20:50:21,912 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-02 20:50:21,912 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-02 20:50:21,913 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [715698904] [2022-11-02 20:50:21,913 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-02 20:50:21,913 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-02 20:50:21,913 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 20:50:21,914 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-02 20:50:21,914 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-02 20:50:21,914 INFO L87 Difference]: Start difference. First operand 1129 states and 1570 transitions. cyclomatic complexity: 445 Second operand has 3 states, 3 states have (on average 9.666666666666666) internal successors, (29), 3 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:50:21,980 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 20:50:21,980 INFO L93 Difference]: Finished difference Result 1500 states and 2055 transitions. [2022-11-02 20:50:21,981 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1500 states and 2055 transitions. [2022-11-02 20:50:21,994 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1453 [2022-11-02 20:50:22,003 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1500 states to 1500 states and 2055 transitions. [2022-11-02 20:50:22,003 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1500 [2022-11-02 20:50:22,007 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1500 [2022-11-02 20:50:22,007 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1500 states and 2055 transitions. [2022-11-02 20:50:22,009 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-02 20:50:22,009 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1500 states and 2055 transitions. [2022-11-02 20:50:22,011 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1500 states and 2055 transitions. [2022-11-02 20:50:22,028 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1500 to 1476. [2022-11-02 20:50:22,031 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.3719512195121952) internal successors, (2025), 1475 states have internal predecessors, (2025), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:50:22,036 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2025 transitions. [2022-11-02 20:50:22,036 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1476 states and 2025 transitions. [2022-11-02 20:50:22,037 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-02 20:50:22,039 INFO L428 stractBuchiCegarLoop]: Abstraction has 1476 states and 2025 transitions. [2022-11-02 20:50:22,039 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-11-02 20:50:22,039 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2025 transitions. [2022-11-02 20:50:22,050 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1429 [2022-11-02 20:50:22,050 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 20:50:22,050 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 20:50:22,052 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 20:50:22,052 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 20:50:22,052 INFO L748 eck$LassoCheckResult]: Stem: 6589#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 6510#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 6508#L613 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6489#L298 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6490#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 6544#L305-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 6555#L310-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 6556#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6584#L424 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 6566#L118 assume !(1 == ~P_1_pc~0); 6535#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 6536#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 6540#L130 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 6395#L491 assume !(0 != activate_threads_~tmp~1#1); 6396#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 6545#L186 assume !(1 == ~P_2_pc~0); 6415#L186-2 is_P_2_triggered_~__retres1~1#1 := 0; 6416#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 6550#L198 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 6512#L499 assume !(0 != activate_threads_~tmp___0~1#1); 6513#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 6457#L268 assume !(1 == ~C_1_pc~0); 6458#L268-2 assume !(2 == ~C_1_pc~0); 6573#L278-1 is_C_1_triggered_~__retres1~2#1 := 0; 6502#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 6503#L290 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 6459#L507 assume !(0 != activate_threads_~tmp___1~1#1); 6460#L507-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6477#L432 assume { :end_inline_reset_delta_events } true; 6561#L561-2 [2022-11-02 20:50:22,052 INFO L750 eck$LassoCheckResult]: Loop: 6561#L561-2 assume !false; 7792#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 7788#L397 assume !false; 7785#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 7782#L328 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 7779#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 7777#L346 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 7773#L362 assume !(0 != eval_~tmp___2~0#1); 7774#L413 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7860#L298-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7859#L424-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 7857#L118-6 assume !(1 == ~P_1_pc~0); 7855#L118-8 is_P_1_triggered_~__retres1~0#1 := 0; 7853#L129-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 7851#L130-2 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 7849#L491-6 assume !(0 != activate_threads_~tmp~1#1); 7847#L491-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 7845#L186-6 assume !(1 == ~P_2_pc~0); 7843#L186-8 is_P_2_triggered_~__retres1~1#1 := 0; 7841#L197-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 7839#L198-2 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 7837#L499-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 7835#L499-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 7833#L268-6 assume !(1 == ~C_1_pc~0); 7831#L268-8 assume !(2 == ~C_1_pc~0); 7829#L278-5 is_C_1_triggered_~__retres1~2#1 := 0; 7827#L289-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 7825#L290-2 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 7823#L507-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 7821#L507-8 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7819#L432-1 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 7817#L328-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 7813#L345-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 7811#L346-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 7809#L580 assume !(0 == start_simulation_~tmp~3#1); 7807#L580-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 7805#L328-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 7803#L345-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 7801#L346-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 7800#L535 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7799#L542 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7798#L543 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 7797#L593 assume !(0 != start_simulation_~tmp___0~2#1); 6561#L561-2 [2022-11-02 20:50:22,053 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:50:22,053 INFO L85 PathProgramCache]: Analyzing trace with hash 1966545068, now seen corresponding path program 1 times [2022-11-02 20:50:22,054 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:50:22,054 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1510998106] [2022-11-02 20:50:22,054 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:50:22,055 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:50:22,068 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:50:22,068 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:50:22,079 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:50:22,124 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:50:22,124 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:50:22,125 INFO L85 PathProgramCache]: Analyzing trace with hash 2031917307, now seen corresponding path program 1 times [2022-11-02 20:50:22,126 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:50:22,126 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1314376560] [2022-11-02 20:50:22,126 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:50:22,126 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:50:22,148 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:50:22,231 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:50:22,232 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 20:50:22,232 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1314376560] [2022-11-02 20:50:22,232 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1314376560] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-02 20:50:22,232 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-02 20:50:22,232 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-02 20:50:22,232 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [369975736] [2022-11-02 20:50:22,232 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-02 20:50:22,232 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-02 20:50:22,232 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 20:50:22,233 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-02 20:50:22,233 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-02 20:50:22,233 INFO L87 Difference]: Start difference. First operand 1476 states and 2025 transitions. cyclomatic complexity: 553 Second operand has 5 states, 5 states have (on average 8.6) internal successors, (43), 5 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:50:22,368 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 20:50:22,368 INFO L93 Difference]: Finished difference Result 2613 states and 3559 transitions. [2022-11-02 20:50:22,368 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2613 states and 3559 transitions. [2022-11-02 20:50:22,413 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2548 [2022-11-02 20:50:22,437 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2613 states to 2613 states and 3559 transitions. [2022-11-02 20:50:22,441 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2613 [2022-11-02 20:50:22,444 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2613 [2022-11-02 20:50:22,459 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2613 states and 3559 transitions. [2022-11-02 20:50:22,463 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-02 20:50:22,463 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2613 states and 3559 transitions. [2022-11-02 20:50:22,466 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2613 states and 3559 transitions. [2022-11-02 20:50:22,539 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2613 to 1512. [2022-11-02 20:50:22,542 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1512 states, 1512 states have (on average 1.3630952380952381) internal successors, (2061), 1511 states have internal predecessors, (2061), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:50:22,547 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1512 states to 1512 states and 2061 transitions. [2022-11-02 20:50:22,548 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1512 states and 2061 transitions. [2022-11-02 20:50:22,548 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-11-02 20:50:22,549 INFO L428 stractBuchiCegarLoop]: Abstraction has 1512 states and 2061 transitions. [2022-11-02 20:50:22,549 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-11-02 20:50:22,549 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1512 states and 2061 transitions. [2022-11-02 20:50:22,559 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1465 [2022-11-02 20:50:22,559 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 20:50:22,559 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 20:50:22,560 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 20:50:22,560 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 20:50:22,561 INFO L748 eck$LassoCheckResult]: Stem: 10708#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 10616#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 10614#L613 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10593#L298 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10594#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 10649#L305-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 10662#L310-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 10663#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10703#L424 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 10677#L118 assume !(1 == ~P_1_pc~0); 10642#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 10643#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 10646#L130 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 10502#L491 assume !(0 != activate_threads_~tmp~1#1); 10503#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 10650#L186 assume !(1 == ~P_2_pc~0); 10525#L186-2 is_P_2_triggered_~__retres1~1#1 := 0; 10526#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 10655#L198 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 10621#L499 assume !(0 != activate_threads_~tmp___0~1#1); 10622#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 10565#L268 assume !(1 == ~C_1_pc~0); 10566#L268-2 assume !(2 == ~C_1_pc~0); 10683#L278-1 is_C_1_triggered_~__retres1~2#1 := 0; 10608#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 10609#L290 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 10567#L507 assume !(0 != activate_threads_~tmp___1~1#1); 10568#L507-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10587#L432 assume { :end_inline_reset_delta_events } true; 10673#L561-2 [2022-11-02 20:50:22,561 INFO L750 eck$LassoCheckResult]: Loop: 10673#L561-2 assume !false; 11966#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 11914#L397 assume !false; 11964#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 11957#L328 assume !(0 == ~P_1_st~0); 11958#L332 assume !(0 == ~P_2_st~0); 11956#L336 assume !(0 == ~C_1_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 11954#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 11953#L346 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 11752#L362 assume !(0 != eval_~tmp___2~0#1); 11753#L413 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10625#L298-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10626#L424-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 10705#L118-6 assume !(1 == ~P_1_pc~0); 10706#L118-8 is_P_1_triggered_~__retres1~0#1 := 0; 10536#L129-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 10537#L130-2 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 10641#L491-6 assume !(0 != activate_threads_~tmp~1#1); 11986#L491-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 11985#L186-6 assume !(1 == ~P_2_pc~0); 11984#L186-8 is_P_2_triggered_~__retres1~1#1 := 0; 10698#L197-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 10699#L198-2 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 10595#L499-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 10596#L499-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 11983#L268-6 assume !(1 == ~C_1_pc~0); 10666#L268-8 assume !(2 == ~C_1_pc~0); 10667#L278-5 is_C_1_triggered_~__retres1~2#1 := 0; 10544#L289-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 10545#L290-2 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 10559#L507-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 10560#L507-8 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10656#L432-1 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 10657#L328-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 11979#L345-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 11977#L346-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 11976#L580 assume !(0 == start_simulation_~tmp~3#1); 11974#L580-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 10652#L328-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 10653#L345-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 11971#L346-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 11970#L535 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11969#L542 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11968#L543 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 11967#L593 assume !(0 != start_simulation_~tmp___0~2#1); 10673#L561-2 [2022-11-02 20:50:22,561 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:50:22,562 INFO L85 PathProgramCache]: Analyzing trace with hash 1966545068, now seen corresponding path program 2 times [2022-11-02 20:50:22,562 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:50:22,562 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1475469344] [2022-11-02 20:50:22,562 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:50:22,563 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:50:22,571 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:50:22,571 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:50:22,576 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:50:22,587 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:50:22,588 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:50:22,588 INFO L85 PathProgramCache]: Analyzing trace with hash -1502717854, now seen corresponding path program 1 times [2022-11-02 20:50:22,588 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:50:22,588 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [274790933] [2022-11-02 20:50:22,589 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:50:22,589 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:50:22,596 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:50:22,618 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:50:22,618 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 20:50:22,619 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [274790933] [2022-11-02 20:50:22,619 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [274790933] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-02 20:50:22,619 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-02 20:50:22,619 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-02 20:50:22,619 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1539803188] [2022-11-02 20:50:22,620 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-02 20:50:22,620 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-02 20:50:22,620 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 20:50:22,621 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-02 20:50:22,621 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-02 20:50:22,621 INFO L87 Difference]: Start difference. First operand 1512 states and 2061 transitions. cyclomatic complexity: 553 Second operand has 3 states, 3 states have (on average 15.0) internal successors, (45), 3 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:50:22,667 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 20:50:22,668 INFO L93 Difference]: Finished difference Result 2343 states and 3154 transitions. [2022-11-02 20:50:22,668 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2343 states and 3154 transitions. [2022-11-02 20:50:22,686 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 2246 [2022-11-02 20:50:22,700 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2343 states to 2343 states and 3154 transitions. [2022-11-02 20:50:22,701 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2343 [2022-11-02 20:50:22,703 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2343 [2022-11-02 20:50:22,703 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2343 states and 3154 transitions. [2022-11-02 20:50:22,707 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-02 20:50:22,707 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2343 states and 3154 transitions. [2022-11-02 20:50:22,710 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2343 states and 3154 transitions. [2022-11-02 20:50:22,745 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2343 to 2343. [2022-11-02 20:50:22,749 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2343 states, 2343 states have (on average 1.3461374306444729) internal successors, (3154), 2342 states have internal predecessors, (3154), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:50:22,757 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2343 states to 2343 states and 3154 transitions. [2022-11-02 20:50:22,757 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2343 states and 3154 transitions. [2022-11-02 20:50:22,758 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-02 20:50:22,762 INFO L428 stractBuchiCegarLoop]: Abstraction has 2343 states and 3154 transitions. [2022-11-02 20:50:22,762 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-11-02 20:50:22,762 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2343 states and 3154 transitions. [2022-11-02 20:50:22,777 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 2246 [2022-11-02 20:50:22,777 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 20:50:22,777 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 20:50:22,780 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 20:50:22,780 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 20:50:22,781 INFO L748 eck$LassoCheckResult]: Stem: 14565#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 14477#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 14474#L613 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14454#L298 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14455#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 14511#L305-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 14524#L310-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 14525#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14562#L424 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 14543#L118 assume !(1 == ~P_1_pc~0); 14503#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 14504#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 14507#L130 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 14363#L491 assume !(0 != activate_threads_~tmp~1#1); 14364#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 14514#L186 assume !(1 == ~P_2_pc~0); 14386#L186-2 is_P_2_triggered_~__retres1~1#1 := 0; 14387#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 14517#L198 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 14482#L499 assume !(0 != activate_threads_~tmp___0~1#1); 14483#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 14427#L268 assume !(1 == ~C_1_pc~0); 14428#L268-2 assume !(2 == ~C_1_pc~0); 14549#L278-1 is_C_1_triggered_~__retres1~2#1 := 0; 14468#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 14469#L290 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 14429#L507 assume !(0 != activate_threads_~tmp___1~1#1); 14430#L507-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14448#L432 assume { :end_inline_reset_delta_events } true; 14538#L561-2 assume !false; 15716#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 15268#L397 [2022-11-02 20:50:22,781 INFO L750 eck$LassoCheckResult]: Loop: 15268#L397 assume !false; 15714#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 15712#L328 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 15709#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 15705#L346 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 15703#L362 assume 0 != eval_~tmp___2~0#1; 15701#L362-1 assume 0 == ~P_1_st~0;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 15699#L371 assume !(0 != eval_~tmp~0#1); 15697#L367 assume !(0 == ~P_2_st~0); 15692#L382 assume !(0 == ~C_1_st~0); 15268#L397 [2022-11-02 20:50:22,783 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:50:22,783 INFO L85 PathProgramCache]: Analyzing trace with hash 64203950, now seen corresponding path program 1 times [2022-11-02 20:50:22,783 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:50:22,783 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [743494098] [2022-11-02 20:50:22,783 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:50:22,784 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:50:22,795 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:50:22,795 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:50:22,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:50:22,823 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:50:22,824 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:50:22,824 INFO L85 PathProgramCache]: Analyzing trace with hash -658300295, now seen corresponding path program 1 times [2022-11-02 20:50:22,824 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:50:22,824 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [185370442] [2022-11-02 20:50:22,824 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:50:22,825 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:50:22,831 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:50:22,832 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:50:22,834 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:50:22,843 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:50:22,844 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:50:22,844 INFO L85 PathProgramCache]: Analyzing trace with hash -1216570650, now seen corresponding path program 1 times [2022-11-02 20:50:22,844 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:50:22,844 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1900900638] [2022-11-02 20:50:22,844 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:50:22,845 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:50:22,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:50:22,906 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:50:22,907 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 20:50:22,907 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1900900638] [2022-11-02 20:50:22,907 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1900900638] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-02 20:50:22,907 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-02 20:50:22,907 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-02 20:50:22,908 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [181672010] [2022-11-02 20:50:22,908 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-02 20:50:23,036 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 20:50:23,036 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-02 20:50:23,036 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-02 20:50:23,037 INFO L87 Difference]: Start difference. First operand 2343 states and 3154 transitions. cyclomatic complexity: 818 Second operand has 3 states, 3 states have (on average 13.666666666666666) internal successors, (41), 3 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:50:23,100 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 20:50:23,100 INFO L93 Difference]: Finished difference Result 3913 states and 5192 transitions. [2022-11-02 20:50:23,101 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3913 states and 5192 transitions. [2022-11-02 20:50:23,141 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 3761 [2022-11-02 20:50:23,169 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3913 states to 3913 states and 5192 transitions. [2022-11-02 20:50:23,169 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3913 [2022-11-02 20:50:23,176 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3913 [2022-11-02 20:50:23,176 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3913 states and 5192 transitions. [2022-11-02 20:50:23,182 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-02 20:50:23,183 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3913 states and 5192 transitions. [2022-11-02 20:50:23,187 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3913 states and 5192 transitions. [2022-11-02 20:50:23,262 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3913 to 3829. [2022-11-02 20:50:23,271 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3829 states, 3829 states have (on average 1.329328806476887) internal successors, (5090), 3828 states have internal predecessors, (5090), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:50:23,286 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3829 states to 3829 states and 5090 transitions. [2022-11-02 20:50:23,287 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3829 states and 5090 transitions. [2022-11-02 20:50:23,287 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-02 20:50:23,288 INFO L428 stractBuchiCegarLoop]: Abstraction has 3829 states and 5090 transitions. [2022-11-02 20:50:23,288 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-11-02 20:50:23,288 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3829 states and 5090 transitions. [2022-11-02 20:50:23,312 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 3677 [2022-11-02 20:50:23,312 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 20:50:23,312 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 20:50:23,313 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 20:50:23,313 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 20:50:23,313 INFO L748 eck$LassoCheckResult]: Stem: 20865#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 20743#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 20740#L613 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20722#L298 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 20723#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 20782#L305-2 assume !(1 == ~P_2_i~0);~P_2_st~0 := 2; 20800#L310-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 20801#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20848#L424 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 20849#L118 assume !(1 == ~P_1_pc~0); 20771#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 20772#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 20776#L130 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 20777#L491 assume !(0 != activate_threads_~tmp~1#1); 20857#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 20858#L186 assume !(1 == ~P_2_pc~0); 20645#L186-2 is_P_2_triggered_~__retres1~1#1 := 0; 20646#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 20790#L198 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 20791#L499 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 20748#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 20686#L268 assume !(1 == ~C_1_pc~0); 20687#L268-2 assume !(2 == ~C_1_pc~0); 20833#L278-1 is_C_1_triggered_~__retres1~2#1 := 0; 20834#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 20880#L290 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 20881#L507 assume !(0 != activate_threads_~tmp___1~1#1); 20709#L507-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20710#L432 assume { :end_inline_reset_delta_events } true; 22816#L561-2 assume !false; 22815#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 22809#L397 [2022-11-02 20:50:23,313 INFO L750 eck$LassoCheckResult]: Loop: 22809#L397 assume !false; 22810#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 22802#L328 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 22803#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 22795#L346 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 22796#L362 assume 0 != eval_~tmp___2~0#1; 22759#L362-1 assume 0 == ~P_1_st~0;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 22760#L371 assume !(0 != eval_~tmp~0#1); 23645#L367 assume 0 == ~P_2_st~0;eval_~tmp___0~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 23639#L386 assume !(0 != eval_~tmp___0~0#1); 23630#L382 assume !(0 == ~C_1_st~0); 22809#L397 [2022-11-02 20:50:23,314 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:50:23,314 INFO L85 PathProgramCache]: Analyzing trace with hash -131921874, now seen corresponding path program 1 times [2022-11-02 20:50:23,314 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:50:23,314 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [54368593] [2022-11-02 20:50:23,315 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:50:23,315 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:50:23,322 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:50:23,339 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:50:23,339 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 20:50:23,340 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [54368593] [2022-11-02 20:50:23,340 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [54368593] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-02 20:50:23,340 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-02 20:50:23,340 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-02 20:50:23,340 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [82477904] [2022-11-02 20:50:23,341 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-02 20:50:23,341 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-02 20:50:23,341 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:50:23,341 INFO L85 PathProgramCache]: Analyzing trace with hash 1067386761, now seen corresponding path program 1 times [2022-11-02 20:50:23,342 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:50:23,342 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1922304621] [2022-11-02 20:50:23,342 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:50:23,342 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:50:23,347 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:50:23,347 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:50:23,349 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:50:23,352 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:50:23,458 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 20:50:23,459 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-02 20:50:23,459 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-02 20:50:23,459 INFO L87 Difference]: Start difference. First operand 3829 states and 5090 transitions. cyclomatic complexity: 1268 Second operand has 3 states, 3 states have (on average 10.333333333333334) internal successors, (31), 3 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:50:23,483 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 20:50:23,483 INFO L93 Difference]: Finished difference Result 3804 states and 5062 transitions. [2022-11-02 20:50:23,483 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3804 states and 5062 transitions. [2022-11-02 20:50:23,511 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 3677 [2022-11-02 20:50:23,540 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3804 states to 3804 states and 5062 transitions. [2022-11-02 20:50:23,540 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3804 [2022-11-02 20:50:23,544 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3804 [2022-11-02 20:50:23,544 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3804 states and 5062 transitions. [2022-11-02 20:50:23,549 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-02 20:50:23,550 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3804 states and 5062 transitions. [2022-11-02 20:50:23,554 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3804 states and 5062 transitions. [2022-11-02 20:50:23,660 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3804 to 3804. [2022-11-02 20:50:23,667 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3804 states, 3804 states have (on average 1.3307045215562565) internal successors, (5062), 3803 states have internal predecessors, (5062), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:50:23,676 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3804 states to 3804 states and 5062 transitions. [2022-11-02 20:50:23,677 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3804 states and 5062 transitions. [2022-11-02 20:50:23,677 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-02 20:50:23,678 INFO L428 stractBuchiCegarLoop]: Abstraction has 3804 states and 5062 transitions. [2022-11-02 20:50:23,678 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-11-02 20:50:23,678 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3804 states and 5062 transitions. [2022-11-02 20:50:23,697 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 3677 [2022-11-02 20:50:23,697 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 20:50:23,697 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 20:50:23,698 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 20:50:23,698 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 20:50:23,698 INFO L748 eck$LassoCheckResult]: Stem: 28470#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 28378#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 28376#L613 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28355#L298 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28356#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 28410#L305-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 28425#L310-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 28426#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 28463#L424 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 28442#L118 assume !(1 == ~P_1_pc~0); 28403#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 28404#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 28407#L130 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 28266#L491 assume !(0 != activate_threads_~tmp~1#1); 28267#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 28414#L186 assume !(1 == ~P_2_pc~0); 28289#L186-2 is_P_2_triggered_~__retres1~1#1 := 0; 28290#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 28418#L198 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 28383#L499 assume !(0 != activate_threads_~tmp___0~1#1); 28384#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 28327#L268 assume !(1 == ~C_1_pc~0); 28328#L268-2 assume !(2 == ~C_1_pc~0); 28448#L278-1 is_C_1_triggered_~__retres1~2#1 := 0; 28369#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 28370#L290 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 28329#L507 assume !(0 != activate_threads_~tmp___1~1#1); 28330#L507-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28348#L432 assume { :end_inline_reset_delta_events } true; 28438#L561-2 assume !false; 31464#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 31368#L397 [2022-11-02 20:50:23,698 INFO L750 eck$LassoCheckResult]: Loop: 31368#L397 assume !false; 31459#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 31456#L328 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 31453#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 31450#L346 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 31447#L362 assume 0 != eval_~tmp___2~0#1; 31444#L362-1 assume 0 == ~P_1_st~0;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 31440#L371 assume !(0 != eval_~tmp~0#1); 30733#L367 assume 0 == ~P_2_st~0;eval_~tmp___0~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 30603#L386 assume !(0 != eval_~tmp___0~0#1); 30604#L382 assume !(0 == ~C_1_st~0); 31368#L397 [2022-11-02 20:50:23,699 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:50:23,699 INFO L85 PathProgramCache]: Analyzing trace with hash 64203950, now seen corresponding path program 2 times [2022-11-02 20:50:23,699 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:50:23,700 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [661398242] [2022-11-02 20:50:23,700 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:50:23,700 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:50:23,707 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:50:23,707 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:50:23,712 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:50:23,725 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:50:23,726 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:50:23,726 INFO L85 PathProgramCache]: Analyzing trace with hash 1067386761, now seen corresponding path program 2 times [2022-11-02 20:50:23,726 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:50:23,726 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1841092136] [2022-11-02 20:50:23,726 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:50:23,727 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:50:23,732 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:50:23,733 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:50:23,737 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:50:23,739 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:50:23,740 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:50:23,740 INFO L85 PathProgramCache]: Analyzing trace with hash 940874940, now seen corresponding path program 1 times [2022-11-02 20:50:23,740 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:50:23,740 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1295442380] [2022-11-02 20:50:23,740 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:50:23,741 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:50:23,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:50:23,788 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:50:23,789 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 20:50:23,789 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1295442380] [2022-11-02 20:50:23,789 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1295442380] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-02 20:50:23,789 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-02 20:50:23,789 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-02 20:50:23,792 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1377546484] [2022-11-02 20:50:23,792 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-02 20:50:23,908 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 20:50:23,909 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-02 20:50:23,909 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-02 20:50:23,909 INFO L87 Difference]: Start difference. First operand 3804 states and 5062 transitions. cyclomatic complexity: 1265 Second operand has 3 states, 2 states have (on average 21.0) internal successors, (42), 3 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:50:23,988 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 20:50:23,989 INFO L93 Difference]: Finished difference Result 6650 states and 8776 transitions. [2022-11-02 20:50:23,989 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6650 states and 8776 transitions. [2022-11-02 20:50:24,029 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 6427 [2022-11-02 20:50:24,072 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6650 states to 6650 states and 8776 transitions. [2022-11-02 20:50:24,072 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6650 [2022-11-02 20:50:24,078 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6650 [2022-11-02 20:50:24,079 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6650 states and 8776 transitions. [2022-11-02 20:50:24,088 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-02 20:50:24,088 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6650 states and 8776 transitions. [2022-11-02 20:50:24,097 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6650 states and 8776 transitions. [2022-11-02 20:50:24,200 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6650 to 6650. [2022-11-02 20:50:24,212 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6650 states, 6650 states have (on average 1.3196992481203007) internal successors, (8776), 6649 states have internal predecessors, (8776), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:50:24,307 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6650 states to 6650 states and 8776 transitions. [2022-11-02 20:50:24,307 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6650 states and 8776 transitions. [2022-11-02 20:50:24,308 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-02 20:50:24,308 INFO L428 stractBuchiCegarLoop]: Abstraction has 6650 states and 8776 transitions. [2022-11-02 20:50:24,308 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-11-02 20:50:24,308 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6650 states and 8776 transitions. [2022-11-02 20:50:24,387 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 6427 [2022-11-02 20:50:24,387 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 20:50:24,388 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 20:50:24,388 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 20:50:24,388 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-02 20:50:24,388 INFO L748 eck$LassoCheckResult]: Stem: 38948#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 38848#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 38846#L613 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 38822#L298 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 38823#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 38881#L305-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 38897#L310-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 38898#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 38941#L424 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 38919#L118 assume !(1 == ~P_1_pc~0); 38873#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 38874#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 38877#L130 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 38728#L491 assume !(0 != activate_threads_~tmp~1#1); 38729#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 38885#L186 assume !(1 == ~P_2_pc~0); 38751#L186-2 is_P_2_triggered_~__retres1~1#1 := 0; 38752#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 38890#L198 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 38853#L499 assume !(0 != activate_threads_~tmp___0~1#1); 38854#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 38794#L268 assume !(1 == ~C_1_pc~0); 38795#L268-2 assume !(2 == ~C_1_pc~0); 38927#L278-1 is_C_1_triggered_~__retres1~2#1 := 0; 38837#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 38838#L290 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 38796#L507 assume !(0 != activate_threads_~tmp___1~1#1); 38797#L507-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38815#L432 assume { :end_inline_reset_delta_events } true; 38913#L561-2 assume !false; 39770#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 39771#L397 [2022-11-02 20:50:24,389 INFO L750 eck$LassoCheckResult]: Loop: 39771#L397 assume !false; 40138#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 40137#L328 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 40136#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 40135#L346 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 40134#L362 assume 0 != eval_~tmp___2~0#1; 40133#L362-1 assume 0 == ~P_1_st~0;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 40131#L371 assume !(0 != eval_~tmp~0#1); 40130#L367 assume 0 == ~P_2_st~0;eval_~tmp___0~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 39766#L386 assume !(0 != eval_~tmp___0~0#1); 40129#L382 assume 0 == ~C_1_st~0;eval_~tmp___1~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 40139#L401 assume !(0 != eval_~tmp___1~0#1); 39771#L397 [2022-11-02 20:50:24,389 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:50:24,389 INFO L85 PathProgramCache]: Analyzing trace with hash 64203950, now seen corresponding path program 3 times [2022-11-02 20:50:24,389 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:50:24,390 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1316305093] [2022-11-02 20:50:24,390 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:50:24,390 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:50:24,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:50:24,398 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:50:24,415 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:50:24,419 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:50:24,420 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:50:24,420 INFO L85 PathProgramCache]: Analyzing trace with hash -1270750753, now seen corresponding path program 1 times [2022-11-02 20:50:24,420 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:50:24,420 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [6404467] [2022-11-02 20:50:24,421 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:50:24,421 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:50:24,424 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:50:24,424 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:50:24,426 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:50:24,429 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:50:24,432 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:50:24,432 INFO L85 PathProgramCache]: Analyzing trace with hash -897649908, now seen corresponding path program 1 times [2022-11-02 20:50:24,432 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:50:24,433 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1500820384] [2022-11-02 20:50:24,433 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:50:24,433 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:50:24,442 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:50:24,443 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:50:24,448 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:50:24,455 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:50:25,824 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:50:25,824 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:50:25,841 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:50:26,023 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 02.11 08:50:26 BoogieIcfgContainer [2022-11-02 20:50:26,028 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2022-11-02 20:50:26,031 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-11-02 20:50:26,035 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-11-02 20:50:26,035 INFO L275 PluginConnector]: Witness Printer initialized [2022-11-02 20:50:26,035 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.11 08:50:19" (3/4) ... [2022-11-02 20:50:26,039 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2022-11-02 20:50:26,160 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2ff84eed-a969-4a89-b9aa-9129b85958c5/bin/uautomizer-Dbtcem3rbc/witness.graphml [2022-11-02 20:50:26,161 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-11-02 20:50:26,162 INFO L158 Benchmark]: Toolchain (without parser) took 8208.58ms. Allocated memory was 109.1MB in the beginning and 341.8MB in the end (delta: 232.8MB). Free memory was 69.6MB in the beginning and 201.0MB in the end (delta: -131.5MB). Peak memory consumption was 102.2MB. Max. memory is 16.1GB. [2022-11-02 20:50:26,162 INFO L158 Benchmark]: CDTParser took 0.32ms. Allocated memory is still 109.1MB. Free memory is still 86.0MB. There was no memory consumed. Max. memory is 16.1GB. [2022-11-02 20:50:26,164 INFO L158 Benchmark]: CACSL2BoogieTranslator took 432.52ms. Allocated memory is still 109.1MB. Free memory was 69.4MB in the beginning and 82.4MB in the end (delta: -13.1MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. [2022-11-02 20:50:26,164 INFO L158 Benchmark]: Boogie Procedure Inliner took 63.12ms. Allocated memory is still 109.1MB. Free memory was 82.4MB in the beginning and 79.4MB in the end (delta: 3.0MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2022-11-02 20:50:26,165 INFO L158 Benchmark]: Boogie Preprocessor took 44.99ms. Allocated memory is still 109.1MB. Free memory was 79.4MB in the beginning and 76.9MB in the end (delta: 2.6MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-11-02 20:50:26,165 INFO L158 Benchmark]: RCFGBuilder took 881.17ms. Allocated memory is still 109.1MB. Free memory was 76.9MB in the beginning and 51.2MB in the end (delta: 25.6MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. [2022-11-02 20:50:26,168 INFO L158 Benchmark]: BuchiAutomizer took 6644.54ms. Allocated memory was 109.1MB in the beginning and 341.8MB in the end (delta: 232.8MB). Free memory was 51.2MB in the beginning and 206.3MB in the end (delta: -155.0MB). Peak memory consumption was 79.6MB. Max. memory is 16.1GB. [2022-11-02 20:50:26,168 INFO L158 Benchmark]: Witness Printer took 129.86ms. Allocated memory is still 341.8MB. Free memory was 206.3MB in the beginning and 201.0MB in the end (delta: 5.2MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. [2022-11-02 20:50:26,171 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.32ms. Allocated memory is still 109.1MB. Free memory is still 86.0MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 432.52ms. Allocated memory is still 109.1MB. Free memory was 69.4MB in the beginning and 82.4MB in the end (delta: -13.1MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 63.12ms. Allocated memory is still 109.1MB. Free memory was 82.4MB in the beginning and 79.4MB in the end (delta: 3.0MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 44.99ms. Allocated memory is still 109.1MB. Free memory was 79.4MB in the beginning and 76.9MB in the end (delta: 2.6MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 881.17ms. Allocated memory is still 109.1MB. Free memory was 76.9MB in the beginning and 51.2MB in the end (delta: 25.6MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. * BuchiAutomizer took 6644.54ms. Allocated memory was 109.1MB in the beginning and 341.8MB in the end (delta: 232.8MB). Free memory was 51.2MB in the beginning and 206.3MB in the end (delta: -155.0MB). Peak memory consumption was 79.6MB. Max. memory is 16.1GB. * Witness Printer took 129.86ms. Allocated memory is still 341.8MB. Free memory was 206.3MB in the beginning and 201.0MB in the end (delta: 5.2MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 11 terminating modules (11 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.11 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 6650 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 6.4s and 12 iterations. TraceHistogramMax:1. Analysis of lassos took 3.6s. Construction of modules took 0.4s. Büchi inclusion checks took 1.9s. Highest rank in rank-based complementation 0. Minimization of det autom 11. Minimization of nondet autom 0. Automata minimization 0.8s AutomataMinimizationTime, 11 MinimizatonAttempts, 1602 StatesRemovedByMinimization, 6 NontrivialMinimizations. Non-live state removal took 0.4s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 3995 SdHoareTripleChecker+Valid, 0.6s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 3995 mSDsluCounter, 6145 SdHoareTripleChecker+Invalid, 0.4s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 3372 mSDsCounter, 115 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 282 IncrementalHoareTripleChecker+Invalid, 397 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 115 mSolverCounterUnsat, 2773 mSDtfsCounter, 282 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI2 SFLT0 conc2 concLT0 SILN1 SILU0 SILI6 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 357]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L25] int max_loop ; [L26] int clk ; [L27] int num ; [L28] int i ; [L29] int e ; [L30] int timer ; [L31] char data_0 ; [L32] char data_1 ; [L75] int P_1_pc; [L76] int P_1_st ; [L77] int P_1_i ; [L78] int P_1_ev ; [L133] int P_2_pc ; [L134] int P_2_st ; [L135] int P_2_i ; [L136] int P_2_ev ; [L201] int C_1_pc ; [L202] int C_1_st ; [L203] int C_1_i ; [L204] int C_1_ev ; [L205] int C_1_pr ; VAL [C_1_ev=0, C_1_i=0, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=0, num=0, P_1_ev=0, P_1_i=0, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=0, P_2_pc=0, P_2_st=0, timer=0] [L617] int count ; [L618] int __retres2 ; [L622] num = 0 [L623] i = 0 [L624] clk = 0 [L625] max_loop = 8 [L627] timer = 0 [L628] P_1_pc = 0 [L629] P_2_pc = 0 [L630] C_1_pc = 0 [L632] count = 0 [L633] CALL init_model() [L609] P_1_i = 1 [L610] P_2_i = 1 [L611] C_1_i = 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L633] RET init_model() [L634] CALL start_simulation() [L547] int kernel_st ; [L548] int tmp ; [L549] int tmp___0 ; [L553] kernel_st = 0 [L554] FCALL update_channels() [L555] CALL init_threads() [L305] COND TRUE (int )P_1_i == 1 [L306] P_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L310] COND TRUE (int )P_2_i == 1 [L311] P_2_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L315] COND TRUE (int )C_1_i == 1 [L316] C_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L555] RET init_threads() [L556] FCALL fire_delta_events() [L557] CALL activate_threads() [L483] int tmp ; [L484] int tmp___0 ; [L485] int tmp___1 ; [L489] CALL, EXPR is_P_1_triggered() [L115] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L118] COND FALSE !((int )P_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L128] __retres1 = 0 VAL [__retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L130] return (__retres1); VAL [\result=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L489] RET, EXPR is_P_1_triggered() [L489] tmp = is_P_1_triggered() [L491] COND FALSE !(\read(tmp)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0, tmp=0] [L497] CALL, EXPR is_P_2_triggered() [L183] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L186] COND FALSE !((int )P_2_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L196] __retres1 = 0 VAL [__retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L198] return (__retres1); VAL [\result=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L497] RET, EXPR is_P_2_triggered() [L497] tmp___0 = is_P_2_triggered() [L499] COND FALSE !(\read(tmp___0)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0, tmp=0, tmp___0=0] [L505] CALL, EXPR is_C_1_triggered() [L265] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L268] COND FALSE !((int )C_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L278] COND FALSE !((int )C_1_pc == 2) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L288] __retres1 = 0 VAL [__retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L290] return (__retres1); VAL [\result=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L505] RET, EXPR is_C_1_triggered() [L505] tmp___1 = is_C_1_triggered() [L507] COND FALSE !(\read(tmp___1)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0, tmp=0, tmp___0=0, tmp___1=0] [L557] RET activate_threads() [L558] FCALL reset_delta_events() [L561] COND TRUE 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, kernel_st=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L564] kernel_st = 1 [L565] CALL eval() [L350] int tmp ; [L351] int tmp___0 ; [L352] int tmp___1 ; [L353] int tmp___2 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] Loop: [L357] COND TRUE 1 [L360] CALL, EXPR exists_runnable_thread() [L325] int __retres1 ; [L328] COND TRUE (int )P_1_st == 0 [L329] __retres1 = 1 [L346] return (__retres1); [L360] RET, EXPR exists_runnable_thread() [L360] tmp___2 = exists_runnable_thread() [L362] COND TRUE \read(tmp___2) [L367] COND TRUE (int )P_1_st == 0 [L369] tmp = __VERIFIER_nondet_int() [L371] COND FALSE !(\read(tmp)) [L382] COND TRUE (int )P_2_st == 0 [L384] tmp___0 = __VERIFIER_nondet_int() [L386] COND FALSE !(\read(tmp___0)) [L397] COND TRUE (int )C_1_st == 0 [L399] tmp___1 = __VERIFIER_nondet_int() [L401] COND FALSE !(\read(tmp___1)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 357]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int max_loop ; [L26] int clk ; [L27] int num ; [L28] int i ; [L29] int e ; [L30] int timer ; [L31] char data_0 ; [L32] char data_1 ; [L75] int P_1_pc; [L76] int P_1_st ; [L77] int P_1_i ; [L78] int P_1_ev ; [L133] int P_2_pc ; [L134] int P_2_st ; [L135] int P_2_i ; [L136] int P_2_ev ; [L201] int C_1_pc ; [L202] int C_1_st ; [L203] int C_1_i ; [L204] int C_1_ev ; [L205] int C_1_pr ; VAL [C_1_ev=0, C_1_i=0, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=0, num=0, P_1_ev=0, P_1_i=0, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=0, P_2_pc=0, P_2_st=0, timer=0] [L617] int count ; [L618] int __retres2 ; [L622] num = 0 [L623] i = 0 [L624] clk = 0 [L625] max_loop = 8 [L627] timer = 0 [L628] P_1_pc = 0 [L629] P_2_pc = 0 [L630] C_1_pc = 0 [L632] count = 0 [L633] CALL init_model() [L609] P_1_i = 1 [L610] P_2_i = 1 [L611] C_1_i = 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L633] RET init_model() [L634] CALL start_simulation() [L547] int kernel_st ; [L548] int tmp ; [L549] int tmp___0 ; [L553] kernel_st = 0 [L554] FCALL update_channels() [L555] CALL init_threads() [L305] COND TRUE (int )P_1_i == 1 [L306] P_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L310] COND TRUE (int )P_2_i == 1 [L311] P_2_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L315] COND TRUE (int )C_1_i == 1 [L316] C_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L555] RET init_threads() [L556] FCALL fire_delta_events() [L557] CALL activate_threads() [L483] int tmp ; [L484] int tmp___0 ; [L485] int tmp___1 ; [L489] CALL, EXPR is_P_1_triggered() [L115] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L118] COND FALSE !((int )P_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L128] __retres1 = 0 VAL [__retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L130] return (__retres1); VAL [\result=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L489] RET, EXPR is_P_1_triggered() [L489] tmp = is_P_1_triggered() [L491] COND FALSE !(\read(tmp)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0, tmp=0] [L497] CALL, EXPR is_P_2_triggered() [L183] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L186] COND FALSE !((int )P_2_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L196] __retres1 = 0 VAL [__retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L198] return (__retres1); VAL [\result=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L497] RET, EXPR is_P_2_triggered() [L497] tmp___0 = is_P_2_triggered() [L499] COND FALSE !(\read(tmp___0)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0, tmp=0, tmp___0=0] [L505] CALL, EXPR is_C_1_triggered() [L265] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L268] COND FALSE !((int )C_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L278] COND FALSE !((int )C_1_pc == 2) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L288] __retres1 = 0 VAL [__retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L290] return (__retres1); VAL [\result=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L505] RET, EXPR is_C_1_triggered() [L505] tmp___1 = is_C_1_triggered() [L507] COND FALSE !(\read(tmp___1)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0, tmp=0, tmp___0=0, tmp___1=0] [L557] RET activate_threads() [L558] FCALL reset_delta_events() [L561] COND TRUE 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, kernel_st=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L564] kernel_st = 1 [L565] CALL eval() [L350] int tmp ; [L351] int tmp___0 ; [L352] int tmp___1 ; [L353] int tmp___2 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] Loop: [L357] COND TRUE 1 [L360] CALL, EXPR exists_runnable_thread() [L325] int __retres1 ; [L328] COND TRUE (int )P_1_st == 0 [L329] __retres1 = 1 [L346] return (__retres1); [L360] RET, EXPR exists_runnable_thread() [L360] tmp___2 = exists_runnable_thread() [L362] COND TRUE \read(tmp___2) [L367] COND TRUE (int )P_1_st == 0 [L369] tmp = __VERIFIER_nondet_int() [L371] COND FALSE !(\read(tmp)) [L382] COND TRUE (int )P_2_st == 0 [L384] tmp___0 = __VERIFIER_nondet_int() [L386] COND FALSE !(\read(tmp___0)) [L397] COND TRUE (int )C_1_st == 0 [L399] tmp___1 = __VERIFIER_nondet_int() [L401] COND FALSE !(\read(tmp___1)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2022-11-02 20:50:26,311 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2ff84eed-a969-4a89-b9aa-9129b85958c5/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)