./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/array-examples/sanfoundry_24-1.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 5e519f3a Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/array-examples/sanfoundry_24-1.i -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash e0a16588b251f5de7b3febde43795c7086835cc989637b8bd82aa8d6af355c6b --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-5e519f3 [2022-11-02 20:24:26,680 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-11-02 20:24:26,682 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-11-02 20:24:26,726 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-11-02 20:24:26,727 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-11-02 20:24:26,730 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-11-02 20:24:26,733 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-11-02 20:24:26,738 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-11-02 20:24:26,740 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-11-02 20:24:26,746 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-11-02 20:24:26,747 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-11-02 20:24:26,749 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-11-02 20:24:26,750 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-11-02 20:24:26,752 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-11-02 20:24:26,754 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-11-02 20:24:26,756 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-11-02 20:24:26,758 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-11-02 20:24:26,759 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-11-02 20:24:26,760 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-11-02 20:24:26,764 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-11-02 20:24:26,765 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-11-02 20:24:26,766 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-11-02 20:24:26,769 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-11-02 20:24:26,770 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-11-02 20:24:26,777 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-11-02 20:24:26,781 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-11-02 20:24:26,782 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-11-02 20:24:26,783 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-11-02 20:24:26,784 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-11-02 20:24:26,785 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-11-02 20:24:26,787 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-11-02 20:24:26,788 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-11-02 20:24:26,790 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-11-02 20:24:26,791 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-11-02 20:24:26,793 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-11-02 20:24:26,793 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-11-02 20:24:26,794 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-11-02 20:24:26,794 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-11-02 20:24:26,795 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-11-02 20:24:26,795 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-11-02 20:24:26,796 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-11-02 20:24:26,797 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-11-02 20:24:26,833 INFO L113 SettingsManager]: Loading preferences was successful [2022-11-02 20:24:26,837 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-11-02 20:24:26,838 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-11-02 20:24:26,838 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-11-02 20:24:26,839 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-11-02 20:24:26,839 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-11-02 20:24:26,839 INFO L138 SettingsManager]: * Use SBE=true [2022-11-02 20:24:26,840 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-11-02 20:24:26,840 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-11-02 20:24:26,840 INFO L138 SettingsManager]: * Use old map elimination=false [2022-11-02 20:24:26,840 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-11-02 20:24:26,840 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-11-02 20:24:26,841 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-11-02 20:24:26,841 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-11-02 20:24:26,841 INFO L138 SettingsManager]: * sizeof long=4 [2022-11-02 20:24:26,841 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-11-02 20:24:26,841 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-11-02 20:24:26,841 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-11-02 20:24:26,842 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-11-02 20:24:26,842 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-11-02 20:24:26,842 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-11-02 20:24:26,842 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-11-02 20:24:26,842 INFO L138 SettingsManager]: * sizeof long double=12 [2022-11-02 20:24:26,842 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-11-02 20:24:26,843 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-11-02 20:24:26,843 INFO L138 SettingsManager]: * Use constant arrays=true [2022-11-02 20:24:26,843 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-11-02 20:24:26,845 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-11-02 20:24:26,845 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-11-02 20:24:26,845 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-11-02 20:24:26,845 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-11-02 20:24:26,847 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-11-02 20:24:26,847 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> e0a16588b251f5de7b3febde43795c7086835cc989637b8bd82aa8d6af355c6b [2022-11-02 20:24:27,129 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-11-02 20:24:27,155 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-11-02 20:24:27,158 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-11-02 20:24:27,159 INFO L271 PluginConnector]: Initializing CDTParser... [2022-11-02 20:24:27,160 INFO L275 PluginConnector]: CDTParser initialized [2022-11-02 20:24:27,161 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/../../sv-benchmarks/c/array-examples/sanfoundry_24-1.i [2022-11-02 20:24:27,233 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/data/a5dbabd51/b57726069fcf43e5bf98bb5984724ff8/FLAGdaf2fe96a [2022-11-02 20:24:27,672 INFO L306 CDTParser]: Found 1 translation units. [2022-11-02 20:24:27,673 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/sv-benchmarks/c/array-examples/sanfoundry_24-1.i [2022-11-02 20:24:27,678 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/data/a5dbabd51/b57726069fcf43e5bf98bb5984724ff8/FLAGdaf2fe96a [2022-11-02 20:24:28,058 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/data/a5dbabd51/b57726069fcf43e5bf98bb5984724ff8 [2022-11-02 20:24:28,061 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-11-02 20:24:28,062 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-11-02 20:24:28,069 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-11-02 20:24:28,069 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-11-02 20:24:28,072 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-11-02 20:24:28,073 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.11 08:24:28" (1/1) ... [2022-11-02 20:24:28,076 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@2a5dc94c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 08:24:28, skipping insertion in model container [2022-11-02 20:24:28,076 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.11 08:24:28" (1/1) ... [2022-11-02 20:24:28,091 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-11-02 20:24:28,108 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-11-02 20:24:28,287 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/sv-benchmarks/c/array-examples/sanfoundry_24-1.i[848,861] [2022-11-02 20:24:28,306 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-02 20:24:28,318 INFO L203 MainTranslator]: Completed pre-run [2022-11-02 20:24:28,340 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/sv-benchmarks/c/array-examples/sanfoundry_24-1.i[848,861] [2022-11-02 20:24:28,357 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-02 20:24:28,376 INFO L208 MainTranslator]: Completed translation [2022-11-02 20:24:28,377 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 08:24:28 WrapperNode [2022-11-02 20:24:28,377 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-11-02 20:24:28,379 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-11-02 20:24:28,379 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-11-02 20:24:28,379 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-11-02 20:24:28,387 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 08:24:28" (1/1) ... [2022-11-02 20:24:28,409 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 08:24:28" (1/1) ... [2022-11-02 20:24:28,441 INFO L138 Inliner]: procedures = 18, calls = 18, calls flagged for inlining = 6, calls inlined = 6, statements flattened = 73 [2022-11-02 20:24:28,441 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-11-02 20:24:28,442 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-11-02 20:24:28,443 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-11-02 20:24:28,443 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-11-02 20:24:28,453 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 08:24:28" (1/1) ... [2022-11-02 20:24:28,453 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 08:24:28" (1/1) ... [2022-11-02 20:24:28,459 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 08:24:28" (1/1) ... [2022-11-02 20:24:28,460 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 08:24:28" (1/1) ... [2022-11-02 20:24:28,476 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 08:24:28" (1/1) ... [2022-11-02 20:24:28,482 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 08:24:28" (1/1) ... [2022-11-02 20:24:28,488 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 08:24:28" (1/1) ... [2022-11-02 20:24:28,494 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 08:24:28" (1/1) ... [2022-11-02 20:24:28,496 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-11-02 20:24:28,499 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-11-02 20:24:28,500 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-11-02 20:24:28,501 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-11-02 20:24:28,502 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 08:24:28" (1/1) ... [2022-11-02 20:24:28,510 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-02 20:24:28,524 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 20:24:28,544 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-02 20:24:28,580 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-11-02 20:24:28,599 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-11-02 20:24:28,599 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-11-02 20:24:28,600 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2022-11-02 20:24:28,600 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2022-11-02 20:24:28,600 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-11-02 20:24:28,601 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-11-02 20:24:28,601 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2022-11-02 20:24:28,601 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2022-11-02 20:24:28,692 INFO L235 CfgBuilder]: Building ICFG [2022-11-02 20:24:28,694 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-11-02 20:24:28,954 INFO L276 CfgBuilder]: Performing block encoding [2022-11-02 20:24:28,960 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-11-02 20:24:28,960 INFO L300 CfgBuilder]: Removed 3 assume(true) statements. [2022-11-02 20:24:28,962 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.11 08:24:28 BoogieIcfgContainer [2022-11-02 20:24:28,962 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-11-02 20:24:28,963 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-11-02 20:24:28,964 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-11-02 20:24:28,987 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-11-02 20:24:28,988 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-02 20:24:28,988 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 02.11 08:24:28" (1/3) ... [2022-11-02 20:24:28,989 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@e07d9ce and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 02.11 08:24:28, skipping insertion in model container [2022-11-02 20:24:28,989 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-02 20:24:28,989 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 08:24:28" (2/3) ... [2022-11-02 20:24:28,990 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@e07d9ce and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 02.11 08:24:28, skipping insertion in model container [2022-11-02 20:24:28,990 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-02 20:24:28,990 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.11 08:24:28" (3/3) ... [2022-11-02 20:24:28,992 INFO L332 chiAutomizerObserver]: Analyzing ICFG sanfoundry_24-1.i [2022-11-02 20:24:29,070 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-11-02 20:24:29,070 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-11-02 20:24:29,071 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-11-02 20:24:29,071 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-11-02 20:24:29,071 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-11-02 20:24:29,071 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-11-02 20:24:29,071 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-11-02 20:24:29,072 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-11-02 20:24:29,084 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 24 states, 23 states have (on average 1.434782608695652) internal successors, (33), 23 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:24:29,113 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 16 [2022-11-02 20:24:29,114 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 20:24:29,114 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 20:24:29,119 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-11-02 20:24:29,119 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-02 20:24:29,120 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-11-02 20:24:29,120 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 24 states, 23 states have (on average 1.434782608695652) internal successors, (33), 23 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:24:29,122 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 16 [2022-11-02 20:24:29,126 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 20:24:29,126 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 20:24:29,127 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-11-02 20:24:29,127 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-02 20:24:29,135 INFO L748 eck$LassoCheckResult]: Stem: 4#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 7#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 19#L27-3true [2022-11-02 20:24:29,136 INFO L750 eck$LassoCheckResult]: Loop: 19#L27-3true assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 10#L27-2true main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19#L27-3true [2022-11-02 20:24:29,144 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:24:29,144 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 1 times [2022-11-02 20:24:29,156 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:24:29,157 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1707901960] [2022-11-02 20:24:29,158 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:24:29,160 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:24:29,289 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:24:29,289 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:24:29,309 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:24:29,330 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:24:29,333 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:24:29,333 INFO L85 PathProgramCache]: Analyzing trace with hash 1283, now seen corresponding path program 1 times [2022-11-02 20:24:29,333 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:24:29,334 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1887221720] [2022-11-02 20:24:29,335 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:24:29,335 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:24:29,354 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:24:29,355 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:24:29,367 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:24:29,374 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:24:29,380 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:24:29,381 INFO L85 PathProgramCache]: Analyzing trace with hash 925765, now seen corresponding path program 1 times [2022-11-02 20:24:29,381 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:24:29,381 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1344718754] [2022-11-02 20:24:29,382 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:24:29,382 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:24:29,416 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:24:29,417 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:24:29,447 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:24:29,450 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:24:29,865 INFO L210 LassoAnalysis]: Preferences: [2022-11-02 20:24:29,866 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2022-11-02 20:24:29,866 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2022-11-02 20:24:29,867 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2022-11-02 20:24:29,867 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2022-11-02 20:24:29,867 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-02 20:24:29,867 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2022-11-02 20:24:29,867 INFO L132 ssoRankerPreferences]: Path of dumped script: [2022-11-02 20:24:29,868 INFO L133 ssoRankerPreferences]: Filename of dumped script: sanfoundry_24-1.i_Iteration1_Lasso [2022-11-02 20:24:29,868 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2022-11-02 20:24:29,868 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2022-11-02 20:24:29,893 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-02 20:24:30,118 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-02 20:24:30,121 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-02 20:24:30,123 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-02 20:24:30,126 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-02 20:24:30,129 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-02 20:24:30,132 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-02 20:24:30,136 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-02 20:24:30,138 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-02 20:24:30,141 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-02 20:24:30,143 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-02 20:24:30,146 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-02 20:24:30,413 INFO L294 LassoAnalysis]: Preprocessing complete. [2022-11-02 20:24:30,417 INFO L490 LassoAnalysis]: Using template 'affine'. [2022-11-02 20:24:30,419 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-02 20:24:30,420 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 20:24:30,422 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-02 20:24:30,425 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2022-11-02 20:24:30,431 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-02 20:24:30,445 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-02 20:24:30,445 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-02 20:24:30,446 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-02 20:24:30,446 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-02 20:24:30,453 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-02 20:24:30,453 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-02 20:24:30,466 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-02 20:24:30,495 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Ended with exit code 0 [2022-11-02 20:24:30,496 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-02 20:24:30,496 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 20:24:30,497 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-02 20:24:30,500 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2022-11-02 20:24:30,501 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-02 20:24:30,521 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-02 20:24:30,521 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-02 20:24:30,521 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-02 20:24:30,521 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-02 20:24:30,526 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-02 20:24:30,526 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-02 20:24:30,536 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-02 20:24:30,573 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Forceful destruction successful, exit code 0 [2022-11-02 20:24:30,573 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-02 20:24:30,574 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 20:24:30,575 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-02 20:24:30,575 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2022-11-02 20:24:30,576 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-02 20:24:30,586 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-02 20:24:30,587 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-02 20:24:30,587 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-02 20:24:30,587 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-02 20:24:30,587 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-02 20:24:30,588 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-02 20:24:30,588 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-02 20:24:30,596 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-02 20:24:30,630 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Ended with exit code 0 [2022-11-02 20:24:30,631 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-02 20:24:30,631 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 20:24:30,632 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-02 20:24:30,633 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2022-11-02 20:24:30,638 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-02 20:24:30,649 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-02 20:24:30,649 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-02 20:24:30,649 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-02 20:24:30,650 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-02 20:24:30,658 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-02 20:24:30,658 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-02 20:24:30,680 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-02 20:24:30,707 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Ended with exit code 0 [2022-11-02 20:24:30,707 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-02 20:24:30,708 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 20:24:30,709 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-02 20:24:30,711 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2022-11-02 20:24:30,712 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-02 20:24:30,722 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-02 20:24:30,722 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-02 20:24:30,722 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-02 20:24:30,722 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-02 20:24:30,726 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-02 20:24:30,727 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-02 20:24:30,755 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-02 20:24:30,784 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Forceful destruction successful, exit code 0 [2022-11-02 20:24:30,785 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-02 20:24:30,785 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 20:24:30,786 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-02 20:24:30,793 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2022-11-02 20:24:30,794 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-02 20:24:30,803 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-02 20:24:30,804 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-02 20:24:30,804 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-02 20:24:30,804 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-02 20:24:30,807 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-02 20:24:30,808 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-02 20:24:30,830 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-02 20:24:30,852 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Forceful destruction successful, exit code 0 [2022-11-02 20:24:30,852 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-02 20:24:30,852 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 20:24:30,853 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-02 20:24:30,855 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2022-11-02 20:24:30,858 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-02 20:24:30,875 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-02 20:24:30,875 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-02 20:24:30,875 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-02 20:24:30,875 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-02 20:24:30,880 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-02 20:24:30,880 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-02 20:24:30,898 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-02 20:24:30,926 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Forceful destruction successful, exit code 0 [2022-11-02 20:24:30,926 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-02 20:24:30,927 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 20:24:30,929 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-02 20:24:30,934 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2022-11-02 20:24:30,935 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-02 20:24:30,944 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-02 20:24:30,945 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-02 20:24:30,945 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-02 20:24:30,945 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-02 20:24:30,948 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-02 20:24:30,948 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-02 20:24:30,966 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-02 20:24:30,987 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Ended with exit code 0 [2022-11-02 20:24:30,989 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-02 20:24:30,990 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 20:24:30,991 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-02 20:24:30,993 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2022-11-02 20:24:30,993 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-02 20:24:31,004 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-02 20:24:31,004 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-02 20:24:31,004 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-02 20:24:31,005 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-02 20:24:31,007 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-02 20:24:31,008 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-02 20:24:31,047 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-02 20:24:31,082 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Forceful destruction successful, exit code 0 [2022-11-02 20:24:31,083 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-02 20:24:31,083 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 20:24:31,084 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-02 20:24:31,101 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-02 20:24:31,114 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2022-11-02 20:24:31,115 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-02 20:24:31,116 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-02 20:24:31,116 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-02 20:24:31,116 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-02 20:24:31,131 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-02 20:24:31,131 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-02 20:24:31,150 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2022-11-02 20:24:31,198 INFO L443 ModelExtractionUtils]: Simplification made 10 calls to the SMT solver. [2022-11-02 20:24:31,198 INFO L444 ModelExtractionUtils]: 3 out of 16 variables were initially zero. Simplification set additionally 9 variables to zero. [2022-11-02 20:24:31,200 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-02 20:24:31,200 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 20:24:31,201 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-02 20:24:31,211 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2022-11-02 20:24:31,223 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2022-11-02 20:24:31,248 INFO L438 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2022-11-02 20:24:31,248 INFO L513 LassoAnalysis]: Proved termination. [2022-11-02 20:24:31,249 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(v_rep(select #length ULTIMATE.start_main_~#array~0#1.base)_1, ULTIMATE.start_main_~i~0#1, ULTIMATE.start_main_~#array~0#1.offset) = 1*v_rep(select #length ULTIMATE.start_main_~#array~0#1.base)_1 - 4*ULTIMATE.start_main_~i~0#1 - 1*ULTIMATE.start_main_~#array~0#1.offset Supporting invariants [] [2022-11-02 20:24:31,282 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Forceful destruction successful, exit code 0 [2022-11-02 20:24:31,313 INFO L156 tatePredicateManager]: 5 out of 5 supporting invariants were superfluous and have been removed [2022-11-02 20:24:31,371 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:24:31,390 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:24:31,392 INFO L263 TraceCheckSpWp]: Trace formula consists of 35 conjuncts, 2 conjunts are in the unsatisfiable core [2022-11-02 20:24:31,394 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 20:24:31,414 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:24:31,415 INFO L263 TraceCheckSpWp]: Trace formula consists of 13 conjuncts, 4 conjunts are in the unsatisfiable core [2022-11-02 20:24:31,416 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 20:24:31,462 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:24:31,521 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2022-11-02 20:24:31,524 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand has 24 states, 23 states have (on average 1.434782608695652) internal successors, (33), 23 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:24:31,605 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand has 24 states, 23 states have (on average 1.434782608695652) internal successors, (33), 23 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0). Second operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 47 states and 67 transitions. Complement of second has 8 states. [2022-11-02 20:24:31,608 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 5 states 1 stem states 2 non-accepting loop states 1 accepting loop states [2022-11-02 20:24:31,613 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:24:31,614 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 33 transitions. [2022-11-02 20:24:31,616 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 33 transitions. Stem has 2 letters. Loop has 2 letters. [2022-11-02 20:24:31,616 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-02 20:24:31,617 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 33 transitions. Stem has 4 letters. Loop has 2 letters. [2022-11-02 20:24:31,617 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-02 20:24:31,617 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 33 transitions. Stem has 2 letters. Loop has 4 letters. [2022-11-02 20:24:31,617 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-02 20:24:31,618 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 47 states and 67 transitions. [2022-11-02 20:24:31,622 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 14 [2022-11-02 20:24:31,626 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 47 states to 21 states and 29 transitions. [2022-11-02 20:24:31,627 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18 [2022-11-02 20:24:31,628 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19 [2022-11-02 20:24:31,629 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21 states and 29 transitions. [2022-11-02 20:24:31,629 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-02 20:24:31,629 INFO L218 hiAutomatonCegarLoop]: Abstraction has 21 states and 29 transitions. [2022-11-02 20:24:31,649 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21 states and 29 transitions. [2022-11-02 20:24:31,659 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21 to 21. [2022-11-02 20:24:31,659 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21 states, 21 states have (on average 1.380952380952381) internal successors, (29), 20 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:24:31,660 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 29 transitions. [2022-11-02 20:24:31,662 INFO L240 hiAutomatonCegarLoop]: Abstraction has 21 states and 29 transitions. [2022-11-02 20:24:31,662 INFO L428 stractBuchiCegarLoop]: Abstraction has 21 states and 29 transitions. [2022-11-02 20:24:31,662 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-11-02 20:24:31,662 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21 states and 29 transitions. [2022-11-02 20:24:31,663 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 14 [2022-11-02 20:24:31,663 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 20:24:31,664 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 20:24:31,664 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1] [2022-11-02 20:24:31,664 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-11-02 20:24:31,665 INFO L748 eck$LassoCheckResult]: Stem: 132#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 133#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 139#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 143#L27-4 main_~i~0#1 := 0; 144#L32-3 [2022-11-02 20:24:31,665 INFO L750 eck$LassoCheckResult]: Loop: 144#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 149#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 138#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 144#L32-3 [2022-11-02 20:24:31,666 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:24:31,666 INFO L85 PathProgramCache]: Analyzing trace with hash 925707, now seen corresponding path program 1 times [2022-11-02 20:24:31,666 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:24:31,666 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [689674799] [2022-11-02 20:24:31,667 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:24:31,667 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:24:31,679 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:24:31,680 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:24:31,687 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:24:31,690 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:24:31,690 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:24:31,691 INFO L85 PathProgramCache]: Analyzing trace with hash 54137, now seen corresponding path program 1 times [2022-11-02 20:24:31,691 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:24:31,691 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [707666975] [2022-11-02 20:24:31,691 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:24:31,692 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:24:31,702 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:24:31,702 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:24:31,709 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:24:31,712 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:24:31,712 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:24:31,713 INFO L85 PathProgramCache]: Analyzing trace with hash 1807957807, now seen corresponding path program 1 times [2022-11-02 20:24:31,713 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:24:31,713 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1908914589] [2022-11-02 20:24:31,713 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:24:31,714 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:24:31,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:24:31,833 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:24:31,834 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 20:24:31,834 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1908914589] [2022-11-02 20:24:31,835 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1908914589] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-02 20:24:31,835 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-02 20:24:31,836 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-02 20:24:31,836 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [606950037] [2022-11-02 20:24:31,837 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-02 20:24:31,917 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 20:24:31,920 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-02 20:24:31,922 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-11-02 20:24:31,923 INFO L87 Difference]: Start difference. First operand 21 states and 29 transitions. cyclomatic complexity: 11 Second operand has 5 states, 5 states have (on average 1.4) internal successors, (7), 5 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:24:32,022 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 20:24:32,023 INFO L93 Difference]: Finished difference Result 40 states and 47 transitions. [2022-11-02 20:24:32,023 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 40 states and 47 transitions. [2022-11-02 20:24:32,035 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-02 20:24:32,036 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 40 states to 32 states and 38 transitions. [2022-11-02 20:24:32,036 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 29 [2022-11-02 20:24:32,036 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 29 [2022-11-02 20:24:32,036 INFO L73 IsDeterministic]: Start isDeterministic. Operand 32 states and 38 transitions. [2022-11-02 20:24:32,037 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-02 20:24:32,037 INFO L218 hiAutomatonCegarLoop]: Abstraction has 32 states and 38 transitions. [2022-11-02 20:24:32,037 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32 states and 38 transitions. [2022-11-02 20:24:32,039 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32 to 20. [2022-11-02 20:24:32,039 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20 states, 20 states have (on average 1.2) internal successors, (24), 19 states have internal predecessors, (24), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:24:32,040 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 24 transitions. [2022-11-02 20:24:32,040 INFO L240 hiAutomatonCegarLoop]: Abstraction has 20 states and 24 transitions. [2022-11-02 20:24:32,042 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-02 20:24:32,043 INFO L428 stractBuchiCegarLoop]: Abstraction has 20 states and 24 transitions. [2022-11-02 20:24:32,044 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-11-02 20:24:32,044 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 20 states and 24 transitions. [2022-11-02 20:24:32,045 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-02 20:24:32,045 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 20:24:32,045 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 20:24:32,046 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1] [2022-11-02 20:24:32,046 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-11-02 20:24:32,046 INFO L748 eck$LassoCheckResult]: Stem: 203#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 204#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 209#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 212#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 213#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 214#L27-4 main_~i~0#1 := 0; 215#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 219#L34 [2022-11-02 20:24:32,047 INFO L750 eck$LassoCheckResult]: Loop: 219#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 208#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 216#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 219#L34 [2022-11-02 20:24:32,047 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:24:32,048 INFO L85 PathProgramCache]: Analyzing trace with hash 1809669547, now seen corresponding path program 1 times [2022-11-02 20:24:32,048 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:24:32,048 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1091040995] [2022-11-02 20:24:32,048 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:24:32,049 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:24:32,084 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:24:32,084 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:24:32,094 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:24:32,113 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:24:32,113 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:24:32,114 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 2 times [2022-11-02 20:24:32,114 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:24:32,114 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [175782998] [2022-11-02 20:24:32,114 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:24:32,114 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:24:32,128 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:24:32,129 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:24:32,139 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:24:32,141 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:24:32,142 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:24:32,142 INFO L85 PathProgramCache]: Analyzing trace with hash 1436015051, now seen corresponding path program 1 times [2022-11-02 20:24:32,142 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:24:32,142 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1578144304] [2022-11-02 20:24:32,143 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:24:32,143 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:24:32,154 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:24:32,305 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Forceful destruction successful, exit code 0 [2022-11-02 20:24:32,307 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:24:32,307 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 20:24:32,307 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1578144304] [2022-11-02 20:24:32,307 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1578144304] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 20:24:32,308 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2009707522] [2022-11-02 20:24:32,308 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:24:32,308 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 20:24:32,308 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 20:24:32,309 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 20:24:32,338 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2022-11-02 20:24:32,368 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:24:32,369 INFO L263 TraceCheckSpWp]: Trace formula consists of 66 conjuncts, 6 conjunts are in the unsatisfiable core [2022-11-02 20:24:32,370 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 20:24:32,468 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:24:32,468 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 20:24:32,541 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:24:32,541 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2009707522] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 20:24:32,542 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 20:24:32,542 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6] total 10 [2022-11-02 20:24:32,542 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1052673270] [2022-11-02 20:24:32,542 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 20:24:32,608 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 20:24:32,608 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2022-11-02 20:24:32,609 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=35, Invalid=75, Unknown=0, NotChecked=0, Total=110 [2022-11-02 20:24:32,609 INFO L87 Difference]: Start difference. First operand 20 states and 24 transitions. cyclomatic complexity: 7 Second operand has 11 states, 10 states have (on average 2.2) internal successors, (22), 11 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:24:32,800 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 20:24:32,800 INFO L93 Difference]: Finished difference Result 63 states and 74 transitions. [2022-11-02 20:24:32,800 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 63 states and 74 transitions. [2022-11-02 20:24:32,812 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-02 20:24:32,814 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 63 states to 46 states and 54 transitions. [2022-11-02 20:24:32,814 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 41 [2022-11-02 20:24:32,816 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 41 [2022-11-02 20:24:32,816 INFO L73 IsDeterministic]: Start isDeterministic. Operand 46 states and 54 transitions. [2022-11-02 20:24:32,816 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-02 20:24:32,816 INFO L218 hiAutomatonCegarLoop]: Abstraction has 46 states and 54 transitions. [2022-11-02 20:24:32,817 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 46 states and 54 transitions. [2022-11-02 20:24:32,821 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 46 to 28. [2022-11-02 20:24:32,822 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28 states, 28 states have (on average 1.1785714285714286) internal successors, (33), 27 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:24:32,823 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28 states to 28 states and 33 transitions. [2022-11-02 20:24:32,823 INFO L240 hiAutomatonCegarLoop]: Abstraction has 28 states and 33 transitions. [2022-11-02 20:24:32,823 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2022-11-02 20:24:32,825 INFO L428 stractBuchiCegarLoop]: Abstraction has 28 states and 33 transitions. [2022-11-02 20:24:32,825 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-11-02 20:24:32,826 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28 states and 33 transitions. [2022-11-02 20:24:32,830 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-02 20:24:32,830 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 20:24:32,831 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 20:24:32,831 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 2, 2, 1, 1, 1, 1, 1, 1] [2022-11-02 20:24:32,832 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-11-02 20:24:32,832 INFO L748 eck$LassoCheckResult]: Stem: 360#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 361#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 366#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 380#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 381#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 369#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 370#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 371#L27-4 main_~i~0#1 := 0; 372#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 377#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 365#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 374#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 379#L34 [2022-11-02 20:24:32,832 INFO L750 eck$LassoCheckResult]: Loop: 379#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 384#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 383#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 379#L34 [2022-11-02 20:24:32,833 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:24:32,833 INFO L85 PathProgramCache]: Analyzing trace with hash 780817485, now seen corresponding path program 2 times [2022-11-02 20:24:32,833 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:24:32,834 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1750635156] [2022-11-02 20:24:32,834 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:24:32,835 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:24:32,870 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:24:32,877 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:24:32,904 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:24:32,907 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:24:32,908 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:24:32,908 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 3 times [2022-11-02 20:24:32,908 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:24:32,909 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [599289027] [2022-11-02 20:24:32,909 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:24:32,909 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:24:32,914 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:24:32,914 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:24:32,919 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:24:32,921 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:24:32,921 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:24:32,921 INFO L85 PathProgramCache]: Analyzing trace with hash -209139735, now seen corresponding path program 3 times [2022-11-02 20:24:32,922 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:24:32,922 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [683251950] [2022-11-02 20:24:32,922 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:24:32,922 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:24:32,934 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:24:33,050 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 1 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:24:33,050 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 20:24:33,051 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [683251950] [2022-11-02 20:24:33,051 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [683251950] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 20:24:33,051 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [883682908] [2022-11-02 20:24:33,051 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-02 20:24:33,052 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 20:24:33,052 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 20:24:33,053 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 20:24:33,082 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Waiting until timeout for monitored process [2022-11-02 20:24:33,126 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2022-11-02 20:24:33,127 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-02 20:24:33,128 INFO L263 TraceCheckSpWp]: Trace formula consists of 87 conjuncts, 8 conjunts are in the unsatisfiable core [2022-11-02 20:24:33,130 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 20:24:33,256 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 5 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:24:33,256 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 20:24:33,333 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 5 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:24:33,333 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [883682908] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 20:24:33,333 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 20:24:33,334 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8] total 13 [2022-11-02 20:24:33,338 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [561781100] [2022-11-02 20:24:33,338 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 20:24:33,390 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 20:24:33,392 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2022-11-02 20:24:33,393 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=53, Invalid=129, Unknown=0, NotChecked=0, Total=182 [2022-11-02 20:24:33,393 INFO L87 Difference]: Start difference. First operand 28 states and 33 transitions. cyclomatic complexity: 8 Second operand has 14 states, 13 states have (on average 2.3076923076923075) internal successors, (30), 14 states have internal predecessors, (30), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:24:33,575 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 20:24:33,575 INFO L93 Difference]: Finished difference Result 89 states and 104 transitions. [2022-11-02 20:24:33,575 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 89 states and 104 transitions. [2022-11-02 20:24:33,577 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-02 20:24:33,580 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 89 states to 60 states and 70 transitions. [2022-11-02 20:24:33,580 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 53 [2022-11-02 20:24:33,580 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 53 [2022-11-02 20:24:33,580 INFO L73 IsDeterministic]: Start isDeterministic. Operand 60 states and 70 transitions. [2022-11-02 20:24:33,581 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-02 20:24:33,581 INFO L218 hiAutomatonCegarLoop]: Abstraction has 60 states and 70 transitions. [2022-11-02 20:24:33,581 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60 states and 70 transitions. [2022-11-02 20:24:33,585 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60 to 36. [2022-11-02 20:24:33,586 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 36 states, 36 states have (on average 1.1666666666666667) internal successors, (42), 35 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:24:33,588 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 42 transitions. [2022-11-02 20:24:33,588 INFO L240 hiAutomatonCegarLoop]: Abstraction has 36 states and 42 transitions. [2022-11-02 20:24:33,588 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2022-11-02 20:24:33,589 INFO L428 stractBuchiCegarLoop]: Abstraction has 36 states and 42 transitions. [2022-11-02 20:24:33,589 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-11-02 20:24:33,590 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 36 states and 42 transitions. [2022-11-02 20:24:33,592 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-02 20:24:33,592 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 20:24:33,593 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 20:24:33,594 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [3, 3, 3, 2, 2, 1, 1, 1, 1] [2022-11-02 20:24:33,594 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-11-02 20:24:33,595 INFO L748 eck$LassoCheckResult]: Stem: 586#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 587#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 592#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 603#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 604#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 595#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 596#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 607#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 606#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 597#L27-4 main_~i~0#1 := 0; 598#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 602#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 591#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 599#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 617#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 615#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 614#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 609#L34 [2022-11-02 20:24:33,595 INFO L750 eck$LassoCheckResult]: Loop: 609#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 610#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 608#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 609#L34 [2022-11-02 20:24:33,595 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:24:33,595 INFO L85 PathProgramCache]: Analyzing trace with hash -286749017, now seen corresponding path program 4 times [2022-11-02 20:24:33,595 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:24:33,595 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [868953490] [2022-11-02 20:24:33,596 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:24:33,596 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:24:33,644 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:24:33,646 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:24:33,656 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:24:33,667 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:24:33,667 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:24:33,668 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 4 times [2022-11-02 20:24:33,668 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:24:33,668 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [242363975] [2022-11-02 20:24:33,668 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:24:33,668 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:24:33,673 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:24:33,674 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:24:33,685 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:24:33,687 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:24:33,688 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:24:33,688 INFO L85 PathProgramCache]: Analyzing trace with hash 150026063, now seen corresponding path program 5 times [2022-11-02 20:24:33,689 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:24:33,689 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [125013803] [2022-11-02 20:24:33,689 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:24:33,689 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:24:33,716 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:24:33,941 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 5 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:24:33,942 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 20:24:33,942 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [125013803] [2022-11-02 20:24:33,942 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [125013803] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 20:24:33,942 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1239637044] [2022-11-02 20:24:33,942 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-02 20:24:33,943 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 20:24:33,943 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 20:24:33,972 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 20:24:33,990 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Waiting until timeout for monitored process [2022-11-02 20:24:34,070 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 4 check-sat command(s) [2022-11-02 20:24:34,071 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-02 20:24:34,072 INFO L263 TraceCheckSpWp]: Trace formula consists of 108 conjuncts, 10 conjunts are in the unsatisfiable core [2022-11-02 20:24:34,073 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 20:24:34,211 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 12 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:24:34,211 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 20:24:34,302 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 12 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:24:34,302 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1239637044] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 20:24:34,302 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 20:24:34,302 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10] total 16 [2022-11-02 20:24:34,304 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1992585136] [2022-11-02 20:24:34,305 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 20:24:34,352 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 20:24:34,352 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2022-11-02 20:24:34,353 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=75, Invalid=197, Unknown=0, NotChecked=0, Total=272 [2022-11-02 20:24:34,353 INFO L87 Difference]: Start difference. First operand 36 states and 42 transitions. cyclomatic complexity: 9 Second operand has 17 states, 16 states have (on average 2.375) internal successors, (38), 17 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:24:34,591 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 20:24:34,591 INFO L93 Difference]: Finished difference Result 115 states and 134 transitions. [2022-11-02 20:24:34,592 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 115 states and 134 transitions. [2022-11-02 20:24:34,593 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-02 20:24:34,593 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 115 states to 74 states and 86 transitions. [2022-11-02 20:24:34,593 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 65 [2022-11-02 20:24:34,594 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 65 [2022-11-02 20:24:34,594 INFO L73 IsDeterministic]: Start isDeterministic. Operand 74 states and 86 transitions. [2022-11-02 20:24:34,594 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-02 20:24:34,594 INFO L218 hiAutomatonCegarLoop]: Abstraction has 74 states and 86 transitions. [2022-11-02 20:24:34,595 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 74 states and 86 transitions. [2022-11-02 20:24:34,597 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 74 to 44. [2022-11-02 20:24:34,597 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 44 states, 44 states have (on average 1.1590909090909092) internal successors, (51), 43 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:24:34,597 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44 states to 44 states and 51 transitions. [2022-11-02 20:24:34,598 INFO L240 hiAutomatonCegarLoop]: Abstraction has 44 states and 51 transitions. [2022-11-02 20:24:34,598 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2022-11-02 20:24:34,599 INFO L428 stractBuchiCegarLoop]: Abstraction has 44 states and 51 transitions. [2022-11-02 20:24:34,599 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-11-02 20:24:34,600 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 44 states and 51 transitions. [2022-11-02 20:24:34,600 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-02 20:24:34,600 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 20:24:34,600 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 20:24:34,601 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 4, 4, 3, 3, 1, 1, 1, 1] [2022-11-02 20:24:34,601 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-11-02 20:24:34,602 INFO L748 eck$LassoCheckResult]: Stem: 881#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 882#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 887#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 901#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 902#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 890#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 891#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 910#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 909#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 905#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 904#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 892#L27-4 main_~i~0#1 := 0; 893#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 921#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 919#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 918#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 898#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 886#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 895#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 900#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 915#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 914#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 907#L34 [2022-11-02 20:24:34,602 INFO L750 eck$LassoCheckResult]: Loop: 907#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 908#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 906#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 907#L34 [2022-11-02 20:24:34,602 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:24:34,602 INFO L85 PathProgramCache]: Analyzing trace with hash 1958082385, now seen corresponding path program 6 times [2022-11-02 20:24:34,603 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:24:34,603 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2097357936] [2022-11-02 20:24:34,603 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:24:34,603 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:24:34,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:24:34,621 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:24:34,633 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:24:34,637 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:24:34,638 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:24:34,638 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 5 times [2022-11-02 20:24:34,638 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:24:34,639 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1482282755] [2022-11-02 20:24:34,639 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:24:34,639 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:24:34,643 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:24:34,643 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:24:34,647 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:24:34,649 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:24:34,650 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:24:34,650 INFO L85 PathProgramCache]: Analyzing trace with hash -1013442971, now seen corresponding path program 7 times [2022-11-02 20:24:34,650 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:24:34,651 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1706387526] [2022-11-02 20:24:34,651 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:24:34,651 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:24:34,669 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:24:34,879 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 12 proven. 26 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:24:34,879 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 20:24:34,879 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1706387526] [2022-11-02 20:24:34,880 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1706387526] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 20:24:34,880 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [145190789] [2022-11-02 20:24:34,880 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-11-02 20:24:34,880 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 20:24:34,881 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 20:24:34,883 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 20:24:34,914 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Waiting until timeout for monitored process [2022-11-02 20:24:34,970 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:24:34,972 INFO L263 TraceCheckSpWp]: Trace formula consists of 129 conjuncts, 12 conjunts are in the unsatisfiable core [2022-11-02 20:24:34,974 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 20:24:35,150 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 22 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:24:35,150 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 20:24:35,269 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 22 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:24:35,270 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [145190789] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 20:24:35,270 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 20:24:35,270 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12] total 19 [2022-11-02 20:24:35,270 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [772127109] [2022-11-02 20:24:35,271 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 20:24:35,324 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 20:24:35,324 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2022-11-02 20:24:35,325 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=101, Invalid=279, Unknown=0, NotChecked=0, Total=380 [2022-11-02 20:24:35,325 INFO L87 Difference]: Start difference. First operand 44 states and 51 transitions. cyclomatic complexity: 10 Second operand has 20 states, 19 states have (on average 2.4210526315789473) internal successors, (46), 20 states have internal predecessors, (46), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:24:35,597 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 20:24:35,597 INFO L93 Difference]: Finished difference Result 141 states and 164 transitions. [2022-11-02 20:24:35,597 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 141 states and 164 transitions. [2022-11-02 20:24:35,599 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-02 20:24:35,599 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 141 states to 88 states and 102 transitions. [2022-11-02 20:24:35,599 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 77 [2022-11-02 20:24:35,600 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 77 [2022-11-02 20:24:35,600 INFO L73 IsDeterministic]: Start isDeterministic. Operand 88 states and 102 transitions. [2022-11-02 20:24:35,600 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-02 20:24:35,600 INFO L218 hiAutomatonCegarLoop]: Abstraction has 88 states and 102 transitions. [2022-11-02 20:24:35,601 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 88 states and 102 transitions. [2022-11-02 20:24:35,603 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 88 to 52. [2022-11-02 20:24:35,603 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 52 states, 52 states have (on average 1.1538461538461537) internal successors, (60), 51 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:24:35,604 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52 states to 52 states and 60 transitions. [2022-11-02 20:24:35,604 INFO L240 hiAutomatonCegarLoop]: Abstraction has 52 states and 60 transitions. [2022-11-02 20:24:35,605 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2022-11-02 20:24:35,605 INFO L428 stractBuchiCegarLoop]: Abstraction has 52 states and 60 transitions. [2022-11-02 20:24:35,606 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-11-02 20:24:35,606 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 52 states and 60 transitions. [2022-11-02 20:24:35,606 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-02 20:24:35,606 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 20:24:35,606 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 20:24:35,607 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 5, 5, 4, 4, 1, 1, 1, 1] [2022-11-02 20:24:35,607 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-11-02 20:24:35,607 INFO L748 eck$LassoCheckResult]: Stem: 1245#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 1246#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 1251#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1265#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1266#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1254#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1255#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1276#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1275#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1274#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1273#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1269#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1268#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 1256#L27-4 main_~i~0#1 := 0; 1257#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1289#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 1286#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 1284#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1285#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 1293#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 1292#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1262#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 1250#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 1259#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1264#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 1281#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 1280#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1271#L34 [2022-11-02 20:24:35,608 INFO L750 eck$LassoCheckResult]: Loop: 1271#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 1272#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 1270#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1271#L34 [2022-11-02 20:24:35,608 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:24:35,608 INFO L85 PathProgramCache]: Analyzing trace with hash -1204484189, now seen corresponding path program 8 times [2022-11-02 20:24:35,608 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:24:35,609 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [426293627] [2022-11-02 20:24:35,609 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:24:35,609 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:24:35,645 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:24:35,645 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:24:35,666 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:24:35,670 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:24:35,671 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:24:35,671 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 6 times [2022-11-02 20:24:35,671 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:24:35,671 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1056787634] [2022-11-02 20:24:35,672 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:24:35,672 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:24:35,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:24:35,675 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:24:35,678 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:24:35,680 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:24:35,680 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:24:35,681 INFO L85 PathProgramCache]: Analyzing trace with hash 1663323347, now seen corresponding path program 9 times [2022-11-02 20:24:35,681 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:24:35,681 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1698082380] [2022-11-02 20:24:35,681 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:24:35,681 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:24:35,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:24:35,938 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 22 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:24:35,938 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 20:24:35,939 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1698082380] [2022-11-02 20:24:35,939 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1698082380] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 20:24:35,939 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [271964429] [2022-11-02 20:24:35,939 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-02 20:24:35,940 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 20:24:35,940 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 20:24:35,950 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 20:24:35,984 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Waiting until timeout for monitored process [2022-11-02 20:24:36,058 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2022-11-02 20:24:36,058 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-02 20:24:36,060 INFO L263 TraceCheckSpWp]: Trace formula consists of 150 conjuncts, 14 conjunts are in the unsatisfiable core [2022-11-02 20:24:36,061 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 20:24:36,266 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 35 proven. 25 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:24:36,266 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 20:24:36,459 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 35 proven. 25 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:24:36,459 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [271964429] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 20:24:36,459 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 20:24:36,460 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 14] total 22 [2022-11-02 20:24:36,461 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1424483339] [2022-11-02 20:24:36,461 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 20:24:36,524 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 20:24:36,525 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2022-11-02 20:24:36,525 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=131, Invalid=375, Unknown=0, NotChecked=0, Total=506 [2022-11-02 20:24:36,527 INFO L87 Difference]: Start difference. First operand 52 states and 60 transitions. cyclomatic complexity: 11 Second operand has 23 states, 22 states have (on average 2.4545454545454546) internal successors, (54), 23 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:24:36,880 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 20:24:36,880 INFO L93 Difference]: Finished difference Result 167 states and 194 transitions. [2022-11-02 20:24:36,881 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 167 states and 194 transitions. [2022-11-02 20:24:36,882 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-02 20:24:36,883 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 167 states to 102 states and 118 transitions. [2022-11-02 20:24:36,883 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 89 [2022-11-02 20:24:36,883 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 89 [2022-11-02 20:24:36,884 INFO L73 IsDeterministic]: Start isDeterministic. Operand 102 states and 118 transitions. [2022-11-02 20:24:36,884 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-02 20:24:36,884 INFO L218 hiAutomatonCegarLoop]: Abstraction has 102 states and 118 transitions. [2022-11-02 20:24:36,885 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 102 states and 118 transitions. [2022-11-02 20:24:36,891 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 102 to 60. [2022-11-02 20:24:36,891 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 60 states, 60 states have (on average 1.15) internal successors, (69), 59 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:24:36,895 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60 states to 60 states and 69 transitions. [2022-11-02 20:24:36,895 INFO L240 hiAutomatonCegarLoop]: Abstraction has 60 states and 69 transitions. [2022-11-02 20:24:36,896 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2022-11-02 20:24:36,897 INFO L428 stractBuchiCegarLoop]: Abstraction has 60 states and 69 transitions. [2022-11-02 20:24:36,897 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-11-02 20:24:36,897 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 60 states and 69 transitions. [2022-11-02 20:24:36,897 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-02 20:24:36,898 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 20:24:36,898 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 20:24:36,898 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [6, 6, 6, 5, 5, 1, 1, 1, 1] [2022-11-02 20:24:36,899 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-11-02 20:24:36,899 INFO L748 eck$LassoCheckResult]: Stem: 1678#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 1679#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 1684#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1698#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1699#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1687#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1688#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1711#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1710#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1709#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1708#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1707#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1706#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1702#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1701#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 1689#L27-4 main_~i~0#1 := 0; 1690#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1732#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 1721#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 1719#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1720#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 1724#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 1730#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1729#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 1728#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 1727#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1695#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 1683#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 1692#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1697#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 1716#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 1715#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1704#L34 [2022-11-02 20:24:36,899 INFO L750 eck$LassoCheckResult]: Loop: 1704#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 1705#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 1703#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1704#L34 [2022-11-02 20:24:36,899 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:24:36,900 INFO L85 PathProgramCache]: Analyzing trace with hash -1715309995, now seen corresponding path program 10 times [2022-11-02 20:24:36,900 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:24:36,900 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1997318506] [2022-11-02 20:24:36,900 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:24:36,900 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:24:36,969 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:24:36,969 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:24:37,020 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:24:37,025 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:24:37,025 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:24:37,026 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 7 times [2022-11-02 20:24:37,026 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:24:37,026 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1191244448] [2022-11-02 20:24:37,026 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:24:37,026 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:24:37,029 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:24:37,030 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:24:37,032 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:24:37,039 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:24:37,040 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:24:37,040 INFO L85 PathProgramCache]: Analyzing trace with hash 720866529, now seen corresponding path program 11 times [2022-11-02 20:24:37,040 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:24:37,040 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1207679932] [2022-11-02 20:24:37,040 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:24:37,040 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:24:37,061 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:24:37,450 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 35 proven. 52 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:24:37,450 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 20:24:37,451 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1207679932] [2022-11-02 20:24:37,451 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1207679932] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 20:24:37,451 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [688943317] [2022-11-02 20:24:37,451 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-02 20:24:37,451 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 20:24:37,452 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 20:24:37,458 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 20:24:37,482 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Waiting until timeout for monitored process [2022-11-02 20:24:37,606 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) [2022-11-02 20:24:37,607 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-02 20:24:37,609 INFO L263 TraceCheckSpWp]: Trace formula consists of 171 conjuncts, 16 conjunts are in the unsatisfiable core [2022-11-02 20:24:37,610 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 20:24:37,840 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 51 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:24:37,840 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 20:24:38,047 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 51 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:24:38,047 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [688943317] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 20:24:38,047 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 20:24:38,047 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16, 16] total 25 [2022-11-02 20:24:38,047 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2006517219] [2022-11-02 20:24:38,048 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 20:24:38,102 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 20:24:38,103 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2022-11-02 20:24:38,103 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=165, Invalid=485, Unknown=0, NotChecked=0, Total=650 [2022-11-02 20:24:38,103 INFO L87 Difference]: Start difference. First operand 60 states and 69 transitions. cyclomatic complexity: 12 Second operand has 26 states, 25 states have (on average 2.48) internal successors, (62), 26 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:24:38,468 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 20:24:38,468 INFO L93 Difference]: Finished difference Result 193 states and 224 transitions. [2022-11-02 20:24:38,468 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 193 states and 224 transitions. [2022-11-02 20:24:38,470 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-02 20:24:38,471 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 193 states to 116 states and 134 transitions. [2022-11-02 20:24:38,471 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 101 [2022-11-02 20:24:38,471 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 101 [2022-11-02 20:24:38,471 INFO L73 IsDeterministic]: Start isDeterministic. Operand 116 states and 134 transitions. [2022-11-02 20:24:38,472 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-02 20:24:38,472 INFO L218 hiAutomatonCegarLoop]: Abstraction has 116 states and 134 transitions. [2022-11-02 20:24:38,472 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 116 states and 134 transitions. [2022-11-02 20:24:38,479 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 116 to 68. [2022-11-02 20:24:38,480 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 68 states, 68 states have (on average 1.1470588235294117) internal successors, (78), 67 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:24:38,480 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 68 states to 68 states and 78 transitions. [2022-11-02 20:24:38,480 INFO L240 hiAutomatonCegarLoop]: Abstraction has 68 states and 78 transitions. [2022-11-02 20:24:38,483 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2022-11-02 20:24:38,483 INFO L428 stractBuchiCegarLoop]: Abstraction has 68 states and 78 transitions. [2022-11-02 20:24:38,483 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-11-02 20:24:38,483 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 68 states and 78 transitions. [2022-11-02 20:24:38,484 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-02 20:24:38,485 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 20:24:38,485 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 20:24:38,486 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [7, 7, 7, 6, 6, 1, 1, 1, 1] [2022-11-02 20:24:38,486 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-11-02 20:24:38,486 INFO L748 eck$LassoCheckResult]: Stem: 2180#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 2181#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 2186#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2201#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2202#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2189#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2190#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2216#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2215#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2214#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2213#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2212#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2211#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2210#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2209#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2205#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2204#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 2191#L27-4 main_~i~0#1 := 0; 2192#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2224#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2225#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2226#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2230#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2229#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2242#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2239#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2237#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2236#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2234#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2233#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2232#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2198#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2185#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2195#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2200#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2221#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2220#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2207#L34 [2022-11-02 20:24:38,486 INFO L750 eck$LassoCheckResult]: Loop: 2207#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2208#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2206#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2207#L34 [2022-11-02 20:24:38,487 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:24:38,487 INFO L85 PathProgramCache]: Analyzing trace with hash 1748928671, now seen corresponding path program 12 times [2022-11-02 20:24:38,488 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:24:38,488 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [78516258] [2022-11-02 20:24:38,488 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:24:38,488 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:24:38,549 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:24:38,549 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:24:38,596 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:24:38,603 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:24:38,605 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:24:38,605 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 8 times [2022-11-02 20:24:38,605 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:24:38,606 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1640243080] [2022-11-02 20:24:38,606 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:24:38,606 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:24:38,611 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:24:38,612 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:24:38,614 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:24:38,616 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:24:38,616 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:24:38,617 INFO L85 PathProgramCache]: Analyzing trace with hash 85809751, now seen corresponding path program 13 times [2022-11-02 20:24:38,617 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:24:38,619 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1211887633] [2022-11-02 20:24:38,619 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:24:38,620 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:24:38,639 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:24:39,046 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 51 proven. 68 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:24:39,046 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 20:24:39,046 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1211887633] [2022-11-02 20:24:39,046 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1211887633] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 20:24:39,046 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [60914170] [2022-11-02 20:24:39,047 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-11-02 20:24:39,047 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 20:24:39,047 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 20:24:39,053 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 20:24:39,059 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Waiting until timeout for monitored process [2022-11-02 20:24:39,132 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:24:39,134 INFO L263 TraceCheckSpWp]: Trace formula consists of 192 conjuncts, 18 conjunts are in the unsatisfiable core [2022-11-02 20:24:39,136 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 20:24:39,420 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 70 proven. 49 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:24:39,420 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 20:24:39,669 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 70 proven. 49 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:24:39,669 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [60914170] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 20:24:39,669 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 20:24:39,669 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18, 18] total 28 [2022-11-02 20:24:39,670 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [31386234] [2022-11-02 20:24:39,670 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 20:24:39,723 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 20:24:39,723 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2022-11-02 20:24:39,724 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=203, Invalid=609, Unknown=0, NotChecked=0, Total=812 [2022-11-02 20:24:39,724 INFO L87 Difference]: Start difference. First operand 68 states and 78 transitions. cyclomatic complexity: 13 Second operand has 29 states, 28 states have (on average 2.5) internal successors, (70), 29 states have internal predecessors, (70), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:24:40,174 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 20:24:40,174 INFO L93 Difference]: Finished difference Result 219 states and 254 transitions. [2022-11-02 20:24:40,174 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 219 states and 254 transitions. [2022-11-02 20:24:40,175 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-02 20:24:40,176 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 219 states to 130 states and 150 transitions. [2022-11-02 20:24:40,176 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 113 [2022-11-02 20:24:40,176 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 113 [2022-11-02 20:24:40,177 INFO L73 IsDeterministic]: Start isDeterministic. Operand 130 states and 150 transitions. [2022-11-02 20:24:40,178 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-02 20:24:40,179 INFO L218 hiAutomatonCegarLoop]: Abstraction has 130 states and 150 transitions. [2022-11-02 20:24:40,179 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 130 states and 150 transitions. [2022-11-02 20:24:40,183 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 130 to 76. [2022-11-02 20:24:40,184 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 76 states, 76 states have (on average 1.144736842105263) internal successors, (87), 75 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:24:40,184 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 76 states to 76 states and 87 transitions. [2022-11-02 20:24:40,184 INFO L240 hiAutomatonCegarLoop]: Abstraction has 76 states and 87 transitions. [2022-11-02 20:24:40,185 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2022-11-02 20:24:40,185 INFO L428 stractBuchiCegarLoop]: Abstraction has 76 states and 87 transitions. [2022-11-02 20:24:40,186 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-11-02 20:24:40,186 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 76 states and 87 transitions. [2022-11-02 20:24:40,186 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-02 20:24:40,186 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 20:24:40,187 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 20:24:40,187 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [8, 8, 8, 7, 7, 1, 1, 1, 1] [2022-11-02 20:24:40,188 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-11-02 20:24:40,188 INFO L748 eck$LassoCheckResult]: Stem: 2751#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 2752#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 2757#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2771#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2772#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2760#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2761#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2788#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2787#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2786#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2785#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2784#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2783#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2782#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2781#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2780#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2779#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2775#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2774#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 2762#L27-4 main_~i~0#1 := 0; 2763#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2822#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2798#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2796#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2797#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2801#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2821#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2818#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2816#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2815#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2812#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2810#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2809#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2807#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2805#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2804#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2768#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2756#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2765#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2770#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2793#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2792#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2777#L34 [2022-11-02 20:24:40,188 INFO L750 eck$LassoCheckResult]: Loop: 2777#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2778#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2776#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2777#L34 [2022-11-02 20:24:40,188 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:24:40,189 INFO L85 PathProgramCache]: Analyzing trace with hash -1204550311, now seen corresponding path program 14 times [2022-11-02 20:24:40,189 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:24:40,189 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1439413635] [2022-11-02 20:24:40,189 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:24:40,190 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:24:40,235 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:24:40,236 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:24:40,269 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:24:40,274 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:24:40,275 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:24:40,275 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 9 times [2022-11-02 20:24:40,275 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:24:40,276 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1120294893] [2022-11-02 20:24:40,276 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:24:40,276 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:24:40,279 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:24:40,280 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:24:40,282 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:24:40,284 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:24:40,284 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:24:40,285 INFO L85 PathProgramCache]: Analyzing trace with hash -306517155, now seen corresponding path program 15 times [2022-11-02 20:24:40,285 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:24:40,285 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [973308427] [2022-11-02 20:24:40,285 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:24:40,285 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:24:40,308 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:24:40,858 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 70 proven. 86 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:24:40,858 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 20:24:40,858 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [973308427] [2022-11-02 20:24:40,859 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [973308427] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 20:24:40,859 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1154641684] [2022-11-02 20:24:40,859 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-02 20:24:40,859 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 20:24:40,859 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 20:24:40,866 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 20:24:40,870 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Waiting until timeout for monitored process [2022-11-02 20:24:41,044 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) [2022-11-02 20:24:41,044 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-02 20:24:41,046 INFO L263 TraceCheckSpWp]: Trace formula consists of 213 conjuncts, 20 conjunts are in the unsatisfiable core [2022-11-02 20:24:41,048 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 20:24:41,382 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 92 proven. 64 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:24:41,382 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 20:24:41,640 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 92 proven. 64 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:24:41,641 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1154641684] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 20:24:41,641 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 20:24:41,641 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20, 20] total 31 [2022-11-02 20:24:41,641 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [79672623] [2022-11-02 20:24:41,641 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 20:24:41,692 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 20:24:41,692 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2022-11-02 20:24:41,693 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=245, Invalid=747, Unknown=0, NotChecked=0, Total=992 [2022-11-02 20:24:41,693 INFO L87 Difference]: Start difference. First operand 76 states and 87 transitions. cyclomatic complexity: 14 Second operand has 32 states, 31 states have (on average 2.5161290322580645) internal successors, (78), 32 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:24:42,188 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 20:24:42,188 INFO L93 Difference]: Finished difference Result 245 states and 284 transitions. [2022-11-02 20:24:42,188 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 245 states and 284 transitions. [2022-11-02 20:24:42,190 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-02 20:24:42,191 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 245 states to 144 states and 166 transitions. [2022-11-02 20:24:42,191 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 125 [2022-11-02 20:24:42,191 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 125 [2022-11-02 20:24:42,192 INFO L73 IsDeterministic]: Start isDeterministic. Operand 144 states and 166 transitions. [2022-11-02 20:24:42,192 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-02 20:24:42,192 INFO L218 hiAutomatonCegarLoop]: Abstraction has 144 states and 166 transitions. [2022-11-02 20:24:42,192 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 144 states and 166 transitions. [2022-11-02 20:24:42,195 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 144 to 84. [2022-11-02 20:24:42,195 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 84 states, 84 states have (on average 1.1428571428571428) internal successors, (96), 83 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:24:42,196 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 84 states to 84 states and 96 transitions. [2022-11-02 20:24:42,196 INFO L240 hiAutomatonCegarLoop]: Abstraction has 84 states and 96 transitions. [2022-11-02 20:24:42,196 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2022-11-02 20:24:42,197 INFO L428 stractBuchiCegarLoop]: Abstraction has 84 states and 96 transitions. [2022-11-02 20:24:42,197 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-11-02 20:24:42,197 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 84 states and 96 transitions. [2022-11-02 20:24:42,198 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-02 20:24:42,198 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 20:24:42,198 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 20:24:42,199 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [9, 9, 9, 8, 8, 1, 1, 1, 1] [2022-11-02 20:24:42,199 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-11-02 20:24:42,200 INFO L748 eck$LassoCheckResult]: Stem: 3391#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 3392#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 3397#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 3412#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3413#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 3400#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3401#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 3431#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3430#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 3429#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3428#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 3427#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3426#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 3425#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3424#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 3423#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3422#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 3421#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3420#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 3416#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3415#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 3402#L27-4 main_~i~0#1 := 0; 3403#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3439#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 3440#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 3441#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3445#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 3444#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 3469#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3466#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 3464#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 3463#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3460#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 3458#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 3457#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3454#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 3452#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 3451#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3449#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 3448#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 3447#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3409#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 3396#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 3406#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3411#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 3436#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 3435#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3418#L34 [2022-11-02 20:24:42,200 INFO L750 eck$LassoCheckResult]: Loop: 3418#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 3419#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 3417#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3418#L34 [2022-11-02 20:24:42,200 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:24:42,200 INFO L85 PathProgramCache]: Analyzing trace with hash -2004823653, now seen corresponding path program 16 times [2022-11-02 20:24:42,201 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:24:42,201 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1713480508] [2022-11-02 20:24:42,201 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:24:42,201 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:24:42,249 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:24:42,249 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:24:42,289 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:24:42,295 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:24:42,296 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:24:42,296 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 10 times [2022-11-02 20:24:42,296 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:24:42,296 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1697439918] [2022-11-02 20:24:42,296 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:24:42,297 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:24:42,300 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:24:42,300 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:24:42,303 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:24:42,305 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:24:42,305 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:24:42,305 INFO L85 PathProgramCache]: Analyzing trace with hash 113811419, now seen corresponding path program 17 times [2022-11-02 20:24:42,306 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:24:42,306 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [33387667] [2022-11-02 20:24:42,306 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:24:42,306 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:24:42,328 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:24:42,858 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 92 proven. 106 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:24:42,858 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 20:24:42,858 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [33387667] [2022-11-02 20:24:42,858 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [33387667] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 20:24:42,858 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1999922344] [2022-11-02 20:24:42,859 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-02 20:24:42,859 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 20:24:42,859 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 20:24:42,866 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 20:24:42,886 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Waiting until timeout for monitored process [2022-11-02 20:24:43,048 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) [2022-11-02 20:24:43,048 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-02 20:24:43,050 INFO L263 TraceCheckSpWp]: Trace formula consists of 234 conjuncts, 22 conjunts are in the unsatisfiable core [2022-11-02 20:24:43,052 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 20:24:43,435 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 117 proven. 81 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:24:43,435 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 20:24:43,758 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 117 proven. 81 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:24:43,758 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1999922344] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 20:24:43,759 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 20:24:43,759 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 22, 22] total 34 [2022-11-02 20:24:43,759 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2143271384] [2022-11-02 20:24:43,759 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 20:24:43,811 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 20:24:43,811 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2022-11-02 20:24:43,812 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=291, Invalid=899, Unknown=0, NotChecked=0, Total=1190 [2022-11-02 20:24:43,812 INFO L87 Difference]: Start difference. First operand 84 states and 96 transitions. cyclomatic complexity: 15 Second operand has 35 states, 34 states have (on average 2.5294117647058822) internal successors, (86), 35 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:24:44,384 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 20:24:44,385 INFO L93 Difference]: Finished difference Result 271 states and 314 transitions. [2022-11-02 20:24:44,385 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 271 states and 314 transitions. [2022-11-02 20:24:44,387 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-02 20:24:44,389 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 271 states to 158 states and 182 transitions. [2022-11-02 20:24:44,389 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 137 [2022-11-02 20:24:44,389 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 137 [2022-11-02 20:24:44,389 INFO L73 IsDeterministic]: Start isDeterministic. Operand 158 states and 182 transitions. [2022-11-02 20:24:44,390 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-02 20:24:44,390 INFO L218 hiAutomatonCegarLoop]: Abstraction has 158 states and 182 transitions. [2022-11-02 20:24:44,390 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 158 states and 182 transitions. [2022-11-02 20:24:44,394 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 158 to 92. [2022-11-02 20:24:44,394 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 92 states, 92 states have (on average 1.141304347826087) internal successors, (105), 91 states have internal predecessors, (105), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:24:44,395 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 92 states to 92 states and 105 transitions. [2022-11-02 20:24:44,395 INFO L240 hiAutomatonCegarLoop]: Abstraction has 92 states and 105 transitions. [2022-11-02 20:24:44,397 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2022-11-02 20:24:44,397 INFO L428 stractBuchiCegarLoop]: Abstraction has 92 states and 105 transitions. [2022-11-02 20:24:44,398 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-11-02 20:24:44,398 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 92 states and 105 transitions. [2022-11-02 20:24:44,399 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-02 20:24:44,399 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 20:24:44,399 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 20:24:44,400 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [10, 10, 10, 9, 9, 1, 1, 1, 1] [2022-11-02 20:24:44,400 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-11-02 20:24:44,400 INFO L748 eck$LassoCheckResult]: Stem: 4100#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 4101#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 4106#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4120#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4121#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4109#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4110#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4141#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4140#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4139#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4138#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4137#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4136#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4135#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4134#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4133#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4132#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4131#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4130#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4129#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4128#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4124#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4123#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 4111#L27-4 main_~i~0#1 := 0; 4112#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4186#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4151#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4149#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4150#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4154#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4184#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4181#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4179#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4178#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4175#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4173#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4172#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4169#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4167#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4166#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4163#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4161#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4160#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4159#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4158#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4157#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4117#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4105#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4114#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4119#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4146#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4145#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4126#L34 [2022-11-02 20:24:44,400 INFO L750 eck$LassoCheckResult]: Loop: 4126#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4127#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4125#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4126#L34 [2022-11-02 20:24:44,401 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:24:44,401 INFO L85 PathProgramCache]: Analyzing trace with hash 1133441117, now seen corresponding path program 18 times [2022-11-02 20:24:44,401 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:24:44,401 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [321082284] [2022-11-02 20:24:44,401 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:24:44,402 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:24:44,455 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:24:44,455 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:24:44,517 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:24:44,527 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:24:44,528 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:24:44,528 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 11 times [2022-11-02 20:24:44,528 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:24:44,529 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1588525748] [2022-11-02 20:24:44,529 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:24:44,529 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:24:44,557 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:24:44,557 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:24:44,559 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:24:44,561 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:24:44,561 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:24:44,561 INFO L85 PathProgramCache]: Analyzing trace with hash -688524839, now seen corresponding path program 19 times [2022-11-02 20:24:44,562 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:24:44,562 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1127402004] [2022-11-02 20:24:44,562 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:24:44,562 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:24:44,590 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:24:45,192 INFO L134 CoverageAnalysis]: Checked inductivity of 245 backedges. 117 proven. 128 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:24:45,192 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 20:24:45,193 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1127402004] [2022-11-02 20:24:45,193 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1127402004] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 20:24:45,193 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2087675091] [2022-11-02 20:24:45,193 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-11-02 20:24:45,193 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 20:24:45,193 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 20:24:45,198 INFO L229 MonitoredProcess]: Starting monitored process 22 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 20:24:45,222 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (22)] Waiting until timeout for monitored process [2022-11-02 20:24:45,328 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:24:45,330 INFO L263 TraceCheckSpWp]: Trace formula consists of 255 conjuncts, 24 conjunts are in the unsatisfiable core [2022-11-02 20:24:45,332 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 20:24:45,764 INFO L134 CoverageAnalysis]: Checked inductivity of 245 backedges. 145 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:24:45,764 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 20:24:46,135 INFO L134 CoverageAnalysis]: Checked inductivity of 245 backedges. 145 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:24:46,135 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2087675091] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 20:24:46,135 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 20:24:46,136 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24, 24] total 37 [2022-11-02 20:24:46,136 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1091561375] [2022-11-02 20:24:46,136 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 20:24:46,189 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 20:24:46,189 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2022-11-02 20:24:46,190 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=341, Invalid=1065, Unknown=0, NotChecked=0, Total=1406 [2022-11-02 20:24:46,190 INFO L87 Difference]: Start difference. First operand 92 states and 105 transitions. cyclomatic complexity: 16 Second operand has 38 states, 37 states have (on average 2.5405405405405403) internal successors, (94), 38 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:24:46,874 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 20:24:46,875 INFO L93 Difference]: Finished difference Result 297 states and 344 transitions. [2022-11-02 20:24:46,875 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 297 states and 344 transitions. [2022-11-02 20:24:46,877 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-02 20:24:46,878 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 297 states to 172 states and 198 transitions. [2022-11-02 20:24:46,879 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 149 [2022-11-02 20:24:46,879 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 149 [2022-11-02 20:24:46,879 INFO L73 IsDeterministic]: Start isDeterministic. Operand 172 states and 198 transitions. [2022-11-02 20:24:46,879 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-02 20:24:46,879 INFO L218 hiAutomatonCegarLoop]: Abstraction has 172 states and 198 transitions. [2022-11-02 20:24:46,880 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 172 states and 198 transitions. [2022-11-02 20:24:46,921 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 172 to 100. [2022-11-02 20:24:46,922 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 100 states, 100 states have (on average 1.14) internal successors, (114), 99 states have internal predecessors, (114), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:24:46,923 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 100 states to 100 states and 114 transitions. [2022-11-02 20:24:46,923 INFO L240 hiAutomatonCegarLoop]: Abstraction has 100 states and 114 transitions. [2022-11-02 20:24:46,926 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2022-11-02 20:24:46,927 INFO L428 stractBuchiCegarLoop]: Abstraction has 100 states and 114 transitions. [2022-11-02 20:24:46,927 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-11-02 20:24:46,927 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 100 states and 114 transitions. [2022-11-02 20:24:46,928 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-02 20:24:46,929 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 20:24:46,929 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 20:24:46,929 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [11, 11, 11, 10, 10, 1, 1, 1, 1] [2022-11-02 20:24:46,930 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-11-02 20:24:46,930 INFO L748 eck$LassoCheckResult]: Stem: 4878#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 4879#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 4884#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4899#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4900#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4887#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4888#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4922#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4921#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4920#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4919#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4918#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4917#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4916#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4915#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4914#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4913#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4912#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4911#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4910#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4909#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4908#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4907#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4903#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4902#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 4889#L27-4 main_~i~0#1 := 0; 4890#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4930#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4931#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4932#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4936#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4935#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4972#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4969#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4967#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4966#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4963#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4961#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4960#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4957#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4955#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4954#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4951#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4949#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4948#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4945#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4943#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4942#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4940#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4939#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4938#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4896#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4883#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4893#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4898#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4927#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4926#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4905#L34 [2022-11-02 20:24:46,930 INFO L750 eck$LassoCheckResult]: Loop: 4905#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4906#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4904#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4905#L34 [2022-11-02 20:24:46,931 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:24:46,931 INFO L85 PathProgramCache]: Analyzing trace with hash 125280919, now seen corresponding path program 20 times [2022-11-02 20:24:46,931 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:24:46,931 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [640047670] [2022-11-02 20:24:46,931 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:24:46,931 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:24:47,025 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:24:47,025 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:24:47,121 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:24:47,130 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:24:47,132 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:24:47,132 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 12 times [2022-11-02 20:24:47,132 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:24:47,132 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1992081321] [2022-11-02 20:24:47,133 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:24:47,133 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:24:47,139 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:24:47,139 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:24:47,141 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:24:47,144 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:24:47,146 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:24:47,146 INFO L85 PathProgramCache]: Analyzing trace with hash -82682529, now seen corresponding path program 21 times [2022-11-02 20:24:47,146 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:24:47,146 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [955479641] [2022-11-02 20:24:47,146 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:24:47,147 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:24:47,177 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:24:47,867 INFO L134 CoverageAnalysis]: Checked inductivity of 297 backedges. 145 proven. 152 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:24:47,867 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 20:24:47,867 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [955479641] [2022-11-02 20:24:47,867 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [955479641] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 20:24:47,867 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1563885329] [2022-11-02 20:24:47,867 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-02 20:24:47,868 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 20:24:47,868 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 20:24:47,871 INFO L229 MonitoredProcess]: Starting monitored process 23 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 20:24:47,894 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Waiting until timeout for monitored process [2022-11-02 20:24:48,371 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) [2022-11-02 20:24:48,371 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-02 20:24:48,375 INFO L263 TraceCheckSpWp]: Trace formula consists of 276 conjuncts, 26 conjunts are in the unsatisfiable core [2022-11-02 20:24:48,377 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 20:24:48,911 INFO L134 CoverageAnalysis]: Checked inductivity of 297 backedges. 176 proven. 121 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:24:48,911 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 20:24:49,335 INFO L134 CoverageAnalysis]: Checked inductivity of 297 backedges. 176 proven. 121 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:24:49,335 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1563885329] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 20:24:49,335 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 20:24:49,335 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 26, 26] total 40 [2022-11-02 20:24:49,335 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [791317377] [2022-11-02 20:24:49,336 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 20:24:49,391 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 20:24:49,392 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2022-11-02 20:24:49,392 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=395, Invalid=1245, Unknown=0, NotChecked=0, Total=1640 [2022-11-02 20:24:49,392 INFO L87 Difference]: Start difference. First operand 100 states and 114 transitions. cyclomatic complexity: 17 Second operand has 41 states, 40 states have (on average 2.55) internal successors, (102), 41 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:24:50,225 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 20:24:50,225 INFO L93 Difference]: Finished difference Result 323 states and 374 transitions. [2022-11-02 20:24:50,225 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 323 states and 374 transitions. [2022-11-02 20:24:50,228 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-02 20:24:50,229 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 323 states to 186 states and 214 transitions. [2022-11-02 20:24:50,229 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 161 [2022-11-02 20:24:50,229 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 161 [2022-11-02 20:24:50,229 INFO L73 IsDeterministic]: Start isDeterministic. Operand 186 states and 214 transitions. [2022-11-02 20:24:50,230 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-02 20:24:50,230 INFO L218 hiAutomatonCegarLoop]: Abstraction has 186 states and 214 transitions. [2022-11-02 20:24:50,230 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 186 states and 214 transitions. [2022-11-02 20:24:50,239 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 186 to 108. [2022-11-02 20:24:50,241 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 108 states, 108 states have (on average 1.1388888888888888) internal successors, (123), 107 states have internal predecessors, (123), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:24:50,242 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 108 states to 108 states and 123 transitions. [2022-11-02 20:24:50,242 INFO L240 hiAutomatonCegarLoop]: Abstraction has 108 states and 123 transitions. [2022-11-02 20:24:50,242 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2022-11-02 20:24:50,243 INFO L428 stractBuchiCegarLoop]: Abstraction has 108 states and 123 transitions. [2022-11-02 20:24:50,244 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-11-02 20:24:50,244 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 108 states and 123 transitions. [2022-11-02 20:24:50,245 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-02 20:24:50,245 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 20:24:50,245 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 20:24:50,247 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [12, 12, 12, 11, 11, 1, 1, 1, 1] [2022-11-02 20:24:50,248 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-11-02 20:24:50,248 INFO L748 eck$LassoCheckResult]: Stem: 5725#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 5726#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 5731#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5745#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5746#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5734#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5735#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5770#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5769#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5768#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5767#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5766#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5765#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5764#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5763#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5762#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5761#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5760#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5759#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5758#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5757#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5756#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5755#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5754#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5753#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5749#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5748#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 5736#L27-4 main_~i~0#1 := 0; 5737#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5828#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5780#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5778#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5779#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5783#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5827#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5824#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5822#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5821#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5818#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5816#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5815#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5812#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5810#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5809#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5806#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5804#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5803#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5800#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5798#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5797#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5794#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5792#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5791#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5789#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5787#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5786#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5742#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5730#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5739#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5744#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5775#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5774#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5751#L34 [2022-11-02 20:24:50,249 INFO L750 eck$LassoCheckResult]: Loop: 5751#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5752#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5750#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5751#L34 [2022-11-02 20:24:50,254 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:24:50,255 INFO L85 PathProgramCache]: Analyzing trace with hash -1940425887, now seen corresponding path program 22 times [2022-11-02 20:24:50,255 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:24:50,255 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1967115791] [2022-11-02 20:24:50,255 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:24:50,256 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:24:50,326 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:24:50,327 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:24:50,396 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:24:50,405 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:24:50,406 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:24:50,406 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 13 times [2022-11-02 20:24:50,406 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:24:50,406 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1715686630] [2022-11-02 20:24:50,406 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:24:50,407 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:24:50,410 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:24:50,410 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:24:50,413 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:24:50,415 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:24:50,416 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:24:50,416 INFO L85 PathProgramCache]: Analyzing trace with hash -1262722987, now seen corresponding path program 23 times [2022-11-02 20:24:50,416 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:24:50,416 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2058079347] [2022-11-02 20:24:50,416 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:24:50,417 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:24:50,447 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:24:51,218 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 176 proven. 178 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:24:51,219 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 20:24:51,219 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2058079347] [2022-11-02 20:24:51,219 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2058079347] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 20:24:51,219 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2099436679] [2022-11-02 20:24:51,219 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-02 20:24:51,219 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 20:24:51,219 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 20:24:51,222 INFO L229 MonitoredProcess]: Starting monitored process 24 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 20:24:51,229 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (24)] Waiting until timeout for monitored process [2022-11-02 20:24:51,814 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 13 check-sat command(s) [2022-11-02 20:24:51,815 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-02 20:24:51,819 INFO L263 TraceCheckSpWp]: Trace formula consists of 297 conjuncts, 28 conjunts are in the unsatisfiable core [2022-11-02 20:24:51,820 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 20:24:52,413 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 210 proven. 144 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:24:52,413 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 20:24:52,933 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 210 proven. 144 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:24:52,933 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2099436679] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 20:24:52,934 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 20:24:52,934 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 28, 28] total 43 [2022-11-02 20:24:52,934 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1582676467] [2022-11-02 20:24:52,934 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 20:24:52,995 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 20:24:52,996 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2022-11-02 20:24:52,997 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=453, Invalid=1439, Unknown=0, NotChecked=0, Total=1892 [2022-11-02 20:24:52,997 INFO L87 Difference]: Start difference. First operand 108 states and 123 transitions. cyclomatic complexity: 18 Second operand has 44 states, 43 states have (on average 2.558139534883721) internal successors, (110), 44 states have internal predecessors, (110), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:24:53,816 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 20:24:53,817 INFO L93 Difference]: Finished difference Result 349 states and 404 transitions. [2022-11-02 20:24:53,817 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 349 states and 404 transitions. [2022-11-02 20:24:53,820 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-02 20:24:53,821 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 349 states to 200 states and 230 transitions. [2022-11-02 20:24:53,821 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 173 [2022-11-02 20:24:53,821 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 173 [2022-11-02 20:24:53,822 INFO L73 IsDeterministic]: Start isDeterministic. Operand 200 states and 230 transitions. [2022-11-02 20:24:53,822 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-02 20:24:53,822 INFO L218 hiAutomatonCegarLoop]: Abstraction has 200 states and 230 transitions. [2022-11-02 20:24:53,822 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 200 states and 230 transitions. [2022-11-02 20:24:53,824 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 200 to 116. [2022-11-02 20:24:53,825 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 116 states, 116 states have (on average 1.1379310344827587) internal successors, (132), 115 states have internal predecessors, (132), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:24:53,825 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 116 states to 116 states and 132 transitions. [2022-11-02 20:24:53,825 INFO L240 hiAutomatonCegarLoop]: Abstraction has 116 states and 132 transitions. [2022-11-02 20:24:53,826 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2022-11-02 20:24:53,826 INFO L428 stractBuchiCegarLoop]: Abstraction has 116 states and 132 transitions. [2022-11-02 20:24:53,827 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-11-02 20:24:53,827 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 116 states and 132 transitions. [2022-11-02 20:24:53,828 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-02 20:24:53,828 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 20:24:53,828 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 20:24:53,829 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [13, 13, 13, 12, 12, 1, 1, 1, 1] [2022-11-02 20:24:53,829 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-11-02 20:24:53,829 INFO L748 eck$LassoCheckResult]: Stem: 6641#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 6642#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 6647#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6662#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6663#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6650#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6651#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6689#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6688#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6687#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6686#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6685#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6684#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6683#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6682#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6681#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6680#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6679#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6678#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6677#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6676#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6675#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6674#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6673#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6672#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6671#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6670#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6666#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6665#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 6652#L27-4 main_~i~0#1 := 0; 6653#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6697#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6698#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6699#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6703#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6702#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6751#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6748#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6746#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6745#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6742#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6740#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6739#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6736#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6734#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6733#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6730#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6728#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6727#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6724#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6722#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6721#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6718#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6716#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6715#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6712#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6710#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6709#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6707#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6706#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6705#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6659#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6646#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6656#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6661#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6694#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6693#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6668#L34 [2022-11-02 20:24:53,829 INFO L750 eck$LassoCheckResult]: Loop: 6668#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6669#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6667#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6668#L34 [2022-11-02 20:24:53,830 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:24:53,830 INFO L85 PathProgramCache]: Analyzing trace with hash -1264665709, now seen corresponding path program 24 times [2022-11-02 20:24:53,830 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:24:53,830 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1885830196] [2022-11-02 20:24:53,830 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:24:53,831 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:24:53,901 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:24:53,902 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:24:53,987 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:24:53,995 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:24:53,996 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:24:53,996 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 14 times [2022-11-02 20:24:53,996 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:24:53,996 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1597982598] [2022-11-02 20:24:53,997 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:24:53,997 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:24:54,000 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:24:54,000 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:24:54,003 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:24:54,005 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:24:54,005 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:24:54,006 INFO L85 PathProgramCache]: Analyzing trace with hash -202976541, now seen corresponding path program 25 times [2022-11-02 20:24:54,006 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:24:54,006 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2094325723] [2022-11-02 20:24:54,006 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:24:54,006 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:24:54,037 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:24:54,896 INFO L134 CoverageAnalysis]: Checked inductivity of 416 backedges. 210 proven. 206 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:24:54,896 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 20:24:54,896 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2094325723] [2022-11-02 20:24:54,896 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2094325723] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 20:24:54,897 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1699516826] [2022-11-02 20:24:54,897 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-11-02 20:24:54,897 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 20:24:54,897 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 20:24:54,902 INFO L229 MonitoredProcess]: Starting monitored process 25 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 20:24:54,907 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (25)] Waiting until timeout for monitored process [2022-11-02 20:24:55,040 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:24:55,042 INFO L263 TraceCheckSpWp]: Trace formula consists of 318 conjuncts, 30 conjunts are in the unsatisfiable core [2022-11-02 20:24:55,044 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 20:24:55,706 INFO L134 CoverageAnalysis]: Checked inductivity of 416 backedges. 247 proven. 169 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:24:55,707 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 20:24:56,223 INFO L134 CoverageAnalysis]: Checked inductivity of 416 backedges. 247 proven. 169 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:24:56,224 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1699516826] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 20:24:56,224 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 20:24:56,224 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 30, 30] total 46 [2022-11-02 20:24:56,224 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1439170415] [2022-11-02 20:24:56,225 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 20:24:56,284 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 20:24:56,284 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 47 interpolants. [2022-11-02 20:24:56,285 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=515, Invalid=1647, Unknown=0, NotChecked=0, Total=2162 [2022-11-02 20:24:56,286 INFO L87 Difference]: Start difference. First operand 116 states and 132 transitions. cyclomatic complexity: 19 Second operand has 47 states, 46 states have (on average 2.5652173913043477) internal successors, (118), 47 states have internal predecessors, (118), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:24:57,060 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 20:24:57,061 INFO L93 Difference]: Finished difference Result 375 states and 434 transitions. [2022-11-02 20:24:57,061 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 375 states and 434 transitions. [2022-11-02 20:24:57,064 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-02 20:24:57,065 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 375 states to 214 states and 246 transitions. [2022-11-02 20:24:57,065 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 185 [2022-11-02 20:24:57,066 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 185 [2022-11-02 20:24:57,066 INFO L73 IsDeterministic]: Start isDeterministic. Operand 214 states and 246 transitions. [2022-11-02 20:24:57,066 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-02 20:24:57,067 INFO L218 hiAutomatonCegarLoop]: Abstraction has 214 states and 246 transitions. [2022-11-02 20:24:57,067 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 214 states and 246 transitions. [2022-11-02 20:24:57,069 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 214 to 124. [2022-11-02 20:24:57,069 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 124 states, 124 states have (on average 1.1370967741935485) internal successors, (141), 123 states have internal predecessors, (141), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:24:57,070 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 124 states to 124 states and 141 transitions. [2022-11-02 20:24:57,070 INFO L240 hiAutomatonCegarLoop]: Abstraction has 124 states and 141 transitions. [2022-11-02 20:24:57,071 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2022-11-02 20:24:57,072 INFO L428 stractBuchiCegarLoop]: Abstraction has 124 states and 141 transitions. [2022-11-02 20:24:57,072 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-11-02 20:24:57,072 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 124 states and 141 transitions. [2022-11-02 20:24:57,073 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-02 20:24:57,073 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 20:24:57,074 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 20:24:57,074 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [14, 14, 14, 13, 13, 1, 1, 1, 1] [2022-11-02 20:24:57,074 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-11-02 20:24:57,075 INFO L748 eck$LassoCheckResult]: Stem: 7626#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 7627#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 7632#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 7646#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7647#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 7635#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7636#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 7675#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7674#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 7673#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7672#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 7671#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7670#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 7669#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7668#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 7667#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7666#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 7665#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7664#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 7663#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7662#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 7661#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7660#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 7659#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7658#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 7657#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7656#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 7655#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7654#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 7650#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7649#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 7637#L27-4 main_~i~0#1 := 0; 7638#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7744#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 7685#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 7683#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7684#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 7688#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 7742#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7739#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 7737#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 7736#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7733#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 7731#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 7730#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7727#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 7725#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 7724#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7721#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 7719#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 7718#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7715#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 7713#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 7712#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7709#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 7707#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 7706#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7703#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 7701#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 7700#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7697#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 7695#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 7694#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7693#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 7692#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 7691#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7643#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 7631#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 7640#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7645#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 7680#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 7679#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7652#L34 [2022-11-02 20:24:57,075 INFO L750 eck$LassoCheckResult]: Loop: 7652#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 7653#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 7651#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7652#L34 [2022-11-02 20:24:57,075 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:24:57,076 INFO L85 PathProgramCache]: Analyzing trace with hash 1142017637, now seen corresponding path program 26 times [2022-11-02 20:24:57,076 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:24:57,076 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1225081428] [2022-11-02 20:24:57,076 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:24:57,076 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:24:57,148 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:24:57,149 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:24:57,211 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:24:57,219 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:24:57,219 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:24:57,219 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 15 times [2022-11-02 20:24:57,219 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:24:57,220 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2088349870] [2022-11-02 20:24:57,220 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:24:57,220 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:24:57,223 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:24:57,223 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:24:57,225 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:24:57,227 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:24:57,227 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:24:57,228 INFO L85 PathProgramCache]: Analyzing trace with hash 1411512017, now seen corresponding path program 27 times [2022-11-02 20:24:57,228 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:24:57,228 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [318822697] [2022-11-02 20:24:57,228 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:24:57,228 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:24:57,255 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:24:58,108 INFO L134 CoverageAnalysis]: Checked inductivity of 483 backedges. 247 proven. 236 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:24:58,108 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 20:24:58,108 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [318822697] [2022-11-02 20:24:58,108 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [318822697] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 20:24:58,108 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1034250040] [2022-11-02 20:24:58,109 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-02 20:24:58,109 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 20:24:58,109 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 20:24:58,110 INFO L229 MonitoredProcess]: Starting monitored process 26 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 20:24:58,120 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (26)] Waiting until timeout for monitored process [2022-11-02 20:24:58,579 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 15 check-sat command(s) [2022-11-02 20:24:58,580 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-02 20:24:58,584 INFO L263 TraceCheckSpWp]: Trace formula consists of 339 conjuncts, 32 conjunts are in the unsatisfiable core [2022-11-02 20:24:58,585 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 20:24:59,346 INFO L134 CoverageAnalysis]: Checked inductivity of 483 backedges. 287 proven. 196 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:24:59,346 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 20:24:59,893 INFO L134 CoverageAnalysis]: Checked inductivity of 483 backedges. 287 proven. 196 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:24:59,894 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1034250040] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 20:24:59,894 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 20:24:59,894 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 32, 32] total 49 [2022-11-02 20:24:59,895 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1750322920] [2022-11-02 20:24:59,895 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 20:24:59,947 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 20:24:59,948 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2022-11-02 20:24:59,949 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=581, Invalid=1869, Unknown=0, NotChecked=0, Total=2450 [2022-11-02 20:24:59,950 INFO L87 Difference]: Start difference. First operand 124 states and 141 transitions. cyclomatic complexity: 20 Second operand has 50 states, 49 states have (on average 2.5714285714285716) internal successors, (126), 50 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:25:00,773 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 20:25:00,773 INFO L93 Difference]: Finished difference Result 401 states and 464 transitions. [2022-11-02 20:25:00,773 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 401 states and 464 transitions. [2022-11-02 20:25:00,777 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-02 20:25:00,778 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 401 states to 228 states and 262 transitions. [2022-11-02 20:25:00,778 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 197 [2022-11-02 20:25:00,779 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 197 [2022-11-02 20:25:00,779 INFO L73 IsDeterministic]: Start isDeterministic. Operand 228 states and 262 transitions. [2022-11-02 20:25:00,779 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-02 20:25:00,780 INFO L218 hiAutomatonCegarLoop]: Abstraction has 228 states and 262 transitions. [2022-11-02 20:25:00,780 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 228 states and 262 transitions. [2022-11-02 20:25:00,782 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 228 to 132. [2022-11-02 20:25:00,782 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 132 states, 132 states have (on average 1.1363636363636365) internal successors, (150), 131 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:25:00,783 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 132 states to 132 states and 150 transitions. [2022-11-02 20:25:00,783 INFO L240 hiAutomatonCegarLoop]: Abstraction has 132 states and 150 transitions. [2022-11-02 20:25:00,785 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2022-11-02 20:25:00,785 INFO L428 stractBuchiCegarLoop]: Abstraction has 132 states and 150 transitions. [2022-11-02 20:25:00,785 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-11-02 20:25:00,786 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 132 states and 150 transitions. [2022-11-02 20:25:00,787 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-02 20:25:00,787 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 20:25:00,787 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 20:25:00,788 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [15, 15, 15, 14, 14, 1, 1, 1, 1] [2022-11-02 20:25:00,788 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-11-02 20:25:00,788 INFO L748 eck$LassoCheckResult]: Stem: 8680#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 8681#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 8686#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8701#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8702#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8689#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8690#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8732#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8731#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8730#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8729#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8728#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8727#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8726#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8725#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8724#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8723#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8722#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8721#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8720#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8719#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8718#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8717#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8716#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8715#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8714#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8713#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8712#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8711#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8710#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8709#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8705#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8704#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 8691#L27-4 main_~i~0#1 := 0; 8692#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8740#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8741#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8742#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8746#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8745#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8806#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8803#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8801#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8800#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8797#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8795#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8794#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8791#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8789#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8788#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8785#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8783#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8782#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8779#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8777#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8776#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8773#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8771#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8770#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8767#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8765#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8764#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8761#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8759#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8758#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8755#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8753#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8752#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8750#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8749#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8748#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8698#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8685#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8695#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8700#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8737#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8736#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8707#L34 [2022-11-02 20:25:00,789 INFO L750 eck$LassoCheckResult]: Loop: 8707#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8708#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8706#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8707#L34 [2022-11-02 20:25:00,789 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:25:00,789 INFO L85 PathProgramCache]: Analyzing trace with hash -1133388657, now seen corresponding path program 28 times [2022-11-02 20:25:00,789 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:25:00,789 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1486585360] [2022-11-02 20:25:00,790 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:25:00,790 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:25:00,872 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:25:00,872 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:25:00,959 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:25:00,968 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:25:00,968 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:25:00,969 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 16 times [2022-11-02 20:25:00,969 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:25:00,969 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1365483762] [2022-11-02 20:25:00,969 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:25:00,969 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:25:00,972 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:25:00,973 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:25:00,975 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:25:00,977 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:25:00,977 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:25:00,977 INFO L85 PathProgramCache]: Analyzing trace with hash -2043527065, now seen corresponding path program 29 times [2022-11-02 20:25:00,978 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:25:00,978 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1739576440] [2022-11-02 20:25:00,978 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:25:00,978 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:25:01,011 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:25:01,922 INFO L134 CoverageAnalysis]: Checked inductivity of 555 backedges. 287 proven. 268 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:25:01,922 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 20:25:01,922 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1739576440] [2022-11-02 20:25:01,922 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1739576440] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 20:25:01,923 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [80883978] [2022-11-02 20:25:01,923 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-02 20:25:01,923 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 20:25:01,923 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 20:25:01,926 INFO L229 MonitoredProcess]: Starting monitored process 27 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 20:25:01,930 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (27)] Waiting until timeout for monitored process [2022-11-02 20:25:02,517 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 16 check-sat command(s) [2022-11-02 20:25:02,517 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-02 20:25:02,522 INFO L263 TraceCheckSpWp]: Trace formula consists of 360 conjuncts, 34 conjunts are in the unsatisfiable core [2022-11-02 20:25:02,524 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 20:25:03,290 INFO L134 CoverageAnalysis]: Checked inductivity of 555 backedges. 330 proven. 225 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:25:03,290 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 20:25:03,835 INFO L134 CoverageAnalysis]: Checked inductivity of 555 backedges. 330 proven. 225 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:25:03,835 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [80883978] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 20:25:03,835 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 20:25:03,836 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 34, 34] total 52 [2022-11-02 20:25:03,836 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [501646293] [2022-11-02 20:25:03,836 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 20:25:03,879 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 20:25:03,880 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 53 interpolants. [2022-11-02 20:25:03,881 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=651, Invalid=2105, Unknown=0, NotChecked=0, Total=2756 [2022-11-02 20:25:03,881 INFO L87 Difference]: Start difference. First operand 132 states and 150 transitions. cyclomatic complexity: 21 Second operand has 53 states, 52 states have (on average 2.576923076923077) internal successors, (134), 53 states have internal predecessors, (134), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:25:04,803 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 20:25:04,803 INFO L93 Difference]: Finished difference Result 427 states and 494 transitions. [2022-11-02 20:25:04,803 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 427 states and 494 transitions. [2022-11-02 20:25:04,806 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-02 20:25:04,808 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 427 states to 242 states and 278 transitions. [2022-11-02 20:25:04,808 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 209 [2022-11-02 20:25:04,808 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 209 [2022-11-02 20:25:04,809 INFO L73 IsDeterministic]: Start isDeterministic. Operand 242 states and 278 transitions. [2022-11-02 20:25:04,809 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-02 20:25:04,809 INFO L218 hiAutomatonCegarLoop]: Abstraction has 242 states and 278 transitions. [2022-11-02 20:25:04,809 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 242 states and 278 transitions. [2022-11-02 20:25:04,811 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 242 to 140. [2022-11-02 20:25:04,812 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 140 states, 140 states have (on average 1.1357142857142857) internal successors, (159), 139 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:25:04,812 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 140 states to 140 states and 159 transitions. [2022-11-02 20:25:04,813 INFO L240 hiAutomatonCegarLoop]: Abstraction has 140 states and 159 transitions. [2022-11-02 20:25:04,817 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2022-11-02 20:25:04,818 INFO L428 stractBuchiCegarLoop]: Abstraction has 140 states and 159 transitions. [2022-11-02 20:25:04,818 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2022-11-02 20:25:04,818 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 140 states and 159 transitions. [2022-11-02 20:25:04,819 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-02 20:25:04,820 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 20:25:04,820 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 20:25:04,820 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [16, 16, 16, 15, 15, 1, 1, 1, 1] [2022-11-02 20:25:04,821 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-11-02 20:25:04,821 INFO L748 eck$LassoCheckResult]: Stem: 9803#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 9804#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 9809#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9823#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9824#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9812#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9813#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9856#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9855#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9854#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9853#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9852#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9851#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9850#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9849#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9848#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9847#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9846#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9845#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9844#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9843#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9842#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9841#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9840#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9839#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9838#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9837#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9836#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9835#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9834#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9833#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9832#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9831#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9827#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9826#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 9814#L27-4 main_~i~0#1 := 0; 9815#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9938#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9866#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9864#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9865#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9869#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9937#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9934#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9932#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9931#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9928#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9926#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9925#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9922#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9920#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9919#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9916#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9914#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9913#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9910#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9908#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9907#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9904#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9902#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9901#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9898#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9896#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9895#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9892#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9890#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9889#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9886#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9884#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9883#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9880#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9878#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9877#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9875#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9873#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9872#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9820#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9808#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9817#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9822#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9861#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9860#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9829#L34 [2022-11-02 20:25:04,821 INFO L750 eck$LassoCheckResult]: Loop: 9829#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9830#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9828#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9829#L34 [2022-11-02 20:25:04,822 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:25:04,822 INFO L85 PathProgramCache]: Analyzing trace with hash 21119337, now seen corresponding path program 30 times [2022-11-02 20:25:04,822 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:25:04,822 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [502512196] [2022-11-02 20:25:04,823 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:25:04,823 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:25:04,926 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:25:04,926 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:25:05,017 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:25:05,025 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:25:05,026 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:25:05,026 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 17 times [2022-11-02 20:25:05,026 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:25:05,027 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1863122722] [2022-11-02 20:25:05,027 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:25:05,027 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:25:05,030 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:25:05,030 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:25:05,032 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:25:05,035 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:25:05,035 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:25:05,036 INFO L85 PathProgramCache]: Analyzing trace with hash 2100983117, now seen corresponding path program 31 times [2022-11-02 20:25:05,036 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:25:05,036 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [175432342] [2022-11-02 20:25:05,036 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:25:05,036 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:25:05,066 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:25:06,160 INFO L134 CoverageAnalysis]: Checked inductivity of 632 backedges. 330 proven. 302 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:25:06,160 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 20:25:06,160 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [175432342] [2022-11-02 20:25:06,161 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [175432342] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 20:25:06,161 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1064398329] [2022-11-02 20:25:06,161 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-11-02 20:25:06,161 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 20:25:06,161 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 20:25:06,164 INFO L229 MonitoredProcess]: Starting monitored process 28 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 20:25:06,167 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (28)] Waiting until timeout for monitored process [2022-11-02 20:25:06,307 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:25:06,310 INFO L263 TraceCheckSpWp]: Trace formula consists of 381 conjuncts, 36 conjunts are in the unsatisfiable core [2022-11-02 20:25:06,312 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 20:25:07,093 INFO L134 CoverageAnalysis]: Checked inductivity of 632 backedges. 376 proven. 256 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:25:07,093 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 20:25:07,698 INFO L134 CoverageAnalysis]: Checked inductivity of 632 backedges. 376 proven. 256 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:25:07,698 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1064398329] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 20:25:07,698 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 20:25:07,698 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 36, 36] total 55 [2022-11-02 20:25:07,699 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2088436089] [2022-11-02 20:25:07,699 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 20:25:07,760 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 20:25:07,761 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 56 interpolants. [2022-11-02 20:25:07,761 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=725, Invalid=2355, Unknown=0, NotChecked=0, Total=3080 [2022-11-02 20:25:07,762 INFO L87 Difference]: Start difference. First operand 140 states and 159 transitions. cyclomatic complexity: 22 Second operand has 56 states, 55 states have (on average 2.581818181818182) internal successors, (142), 56 states have internal predecessors, (142), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:25:08,728 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 20:25:08,729 INFO L93 Difference]: Finished difference Result 453 states and 524 transitions. [2022-11-02 20:25:08,729 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 453 states and 524 transitions. [2022-11-02 20:25:08,732 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-02 20:25:08,734 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 453 states to 256 states and 294 transitions. [2022-11-02 20:25:08,734 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 221 [2022-11-02 20:25:08,734 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 221 [2022-11-02 20:25:08,734 INFO L73 IsDeterministic]: Start isDeterministic. Operand 256 states and 294 transitions. [2022-11-02 20:25:08,735 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-02 20:25:08,735 INFO L218 hiAutomatonCegarLoop]: Abstraction has 256 states and 294 transitions. [2022-11-02 20:25:08,735 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 256 states and 294 transitions. [2022-11-02 20:25:08,738 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 256 to 148. [2022-11-02 20:25:08,738 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 148 states, 148 states have (on average 1.135135135135135) internal successors, (168), 147 states have internal predecessors, (168), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:25:08,739 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 148 states to 148 states and 168 transitions. [2022-11-02 20:25:08,739 INFO L240 hiAutomatonCegarLoop]: Abstraction has 148 states and 168 transitions. [2022-11-02 20:25:08,742 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2022-11-02 20:25:08,743 INFO L428 stractBuchiCegarLoop]: Abstraction has 148 states and 168 transitions. [2022-11-02 20:25:08,743 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2022-11-02 20:25:08,743 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 148 states and 168 transitions. [2022-11-02 20:25:08,744 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-02 20:25:08,744 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 20:25:08,744 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 20:25:08,745 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [17, 17, 17, 16, 16, 1, 1, 1, 1] [2022-11-02 20:25:08,745 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-11-02 20:25:08,745 INFO L748 eck$LassoCheckResult]: Stem: 10995#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 10996#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 11001#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11016#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11017#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11004#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11005#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11051#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11050#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11049#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11048#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11047#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11046#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11045#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11044#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11043#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11042#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11041#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11040#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11039#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11038#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11037#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11036#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11035#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11034#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11033#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11032#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11031#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11030#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11029#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11028#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11027#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11026#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11025#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11024#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11020#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11019#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 11006#L27-4 main_~i~0#1 := 0; 11007#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11059#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11060#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11061#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11065#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11064#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11137#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11134#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11132#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11131#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11128#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11126#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11125#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11122#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11120#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11119#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11116#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11114#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11113#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11110#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11108#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11107#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11104#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11102#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11101#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11098#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11096#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11095#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11092#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11090#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11089#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11086#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11084#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11083#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11080#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11078#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11077#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11074#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11072#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11071#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11069#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11068#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11067#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11013#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11000#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11010#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11015#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11056#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11055#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11022#L34 [2022-11-02 20:25:08,746 INFO L750 eck$LassoCheckResult]: Loop: 11022#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11023#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11021#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11022#L34 [2022-11-02 20:25:08,746 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:25:08,746 INFO L85 PathProgramCache]: Analyzing trace with hash 611108235, now seen corresponding path program 32 times [2022-11-02 20:25:08,746 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:25:08,747 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1469661261] [2022-11-02 20:25:08,747 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:25:08,747 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:25:08,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:25:08,851 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:25:08,931 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:25:08,940 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:25:08,940 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:25:08,941 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 18 times [2022-11-02 20:25:08,941 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:25:08,941 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [462617330] [2022-11-02 20:25:08,941 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:25:08,941 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:25:08,944 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:25:08,945 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:25:08,947 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:25:08,948 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:25:08,949 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:25:08,949 INFO L85 PathProgramCache]: Analyzing trace with hash -840899093, now seen corresponding path program 33 times [2022-11-02 20:25:08,949 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:25:08,949 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [866513003] [2022-11-02 20:25:08,950 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:25:08,950 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:25:08,980 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:25:10,110 INFO L134 CoverageAnalysis]: Checked inductivity of 714 backedges. 376 proven. 338 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:25:10,110 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 20:25:10,111 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [866513003] [2022-11-02 20:25:10,111 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [866513003] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 20:25:10,111 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [228908703] [2022-11-02 20:25:10,111 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-02 20:25:10,111 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 20:25:10,111 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 20:25:10,114 INFO L229 MonitoredProcess]: Starting monitored process 29 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 20:25:10,129 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (29)] Waiting until timeout for monitored process [2022-11-02 20:25:11,247 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 18 check-sat command(s) [2022-11-02 20:25:11,248 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-02 20:25:11,253 INFO L263 TraceCheckSpWp]: Trace formula consists of 402 conjuncts, 38 conjunts are in the unsatisfiable core [2022-11-02 20:25:11,255 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 20:25:12,186 INFO L134 CoverageAnalysis]: Checked inductivity of 714 backedges. 425 proven. 289 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:25:12,186 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 20:25:12,845 INFO L134 CoverageAnalysis]: Checked inductivity of 714 backedges. 425 proven. 289 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:25:12,845 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [228908703] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 20:25:12,845 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 20:25:12,846 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 38, 38] total 58 [2022-11-02 20:25:12,846 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [55565933] [2022-11-02 20:25:12,846 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 20:25:12,898 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 20:25:12,899 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 59 interpolants. [2022-11-02 20:25:12,900 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=803, Invalid=2619, Unknown=0, NotChecked=0, Total=3422 [2022-11-02 20:25:12,900 INFO L87 Difference]: Start difference. First operand 148 states and 168 transitions. cyclomatic complexity: 23 Second operand has 59 states, 58 states have (on average 2.586206896551724) internal successors, (150), 59 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:25:13,923 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 20:25:13,924 INFO L93 Difference]: Finished difference Result 479 states and 554 transitions. [2022-11-02 20:25:13,924 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 479 states and 554 transitions. [2022-11-02 20:25:13,928 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-02 20:25:13,929 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 479 states to 270 states and 310 transitions. [2022-11-02 20:25:13,929 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 233 [2022-11-02 20:25:13,930 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 233 [2022-11-02 20:25:13,930 INFO L73 IsDeterministic]: Start isDeterministic. Operand 270 states and 310 transitions. [2022-11-02 20:25:13,930 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-02 20:25:13,931 INFO L218 hiAutomatonCegarLoop]: Abstraction has 270 states and 310 transitions. [2022-11-02 20:25:13,931 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 270 states and 310 transitions. [2022-11-02 20:25:13,933 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 270 to 156. [2022-11-02 20:25:13,933 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 156 states, 156 states have (on average 1.1346153846153846) internal successors, (177), 155 states have internal predecessors, (177), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:25:13,934 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 156 states to 156 states and 177 transitions. [2022-11-02 20:25:13,934 INFO L240 hiAutomatonCegarLoop]: Abstraction has 156 states and 177 transitions. [2022-11-02 20:25:13,935 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2022-11-02 20:25:13,935 INFO L428 stractBuchiCegarLoop]: Abstraction has 156 states and 177 transitions. [2022-11-02 20:25:13,935 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2022-11-02 20:25:13,936 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 156 states and 177 transitions. [2022-11-02 20:25:13,937 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-02 20:25:13,937 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 20:25:13,937 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 20:25:13,938 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [18, 18, 18, 17, 17, 1, 1, 1, 1] [2022-11-02 20:25:13,938 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-11-02 20:25:13,938 INFO L748 eck$LassoCheckResult]: Stem: 12256#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 12257#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 12262#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 12276#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 12277#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 12265#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 12266#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 12313#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 12312#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 12311#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 12310#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 12309#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 12308#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 12307#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 12306#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 12305#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 12304#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 12303#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 12302#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 12301#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 12300#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 12299#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 12298#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 12297#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 12296#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 12295#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 12294#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 12293#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 12292#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 12291#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 12290#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 12289#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 12288#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 12287#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 12286#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 12285#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 12284#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 12280#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 12279#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 12267#L27-4 main_~i~0#1 := 0; 12268#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12406#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 12323#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 12321#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12322#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 12326#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 12404#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12401#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 12399#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 12398#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12395#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 12393#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 12392#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12389#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 12387#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 12386#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12383#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 12381#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 12380#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12377#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 12375#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 12374#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12371#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 12369#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 12368#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12365#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 12363#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 12362#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12359#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 12357#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 12356#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12353#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 12351#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 12350#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12347#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 12345#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 12344#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12341#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 12339#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 12338#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12335#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 12333#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 12332#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12331#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 12330#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 12329#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12273#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 12261#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 12270#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12275#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 12318#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 12317#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12282#L34 [2022-11-02 20:25:13,938 INFO L750 eck$LassoCheckResult]: Loop: 12282#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 12283#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 12281#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12282#L34 [2022-11-02 20:25:13,939 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:25:13,939 INFO L85 PathProgramCache]: Analyzing trace with hash -1016263571, now seen corresponding path program 34 times [2022-11-02 20:25:13,939 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:25:13,939 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1274673985] [2022-11-02 20:25:13,939 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:25:13,940 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:25:14,045 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:25:14,045 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:25:14,153 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:25:14,163 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:25:14,164 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:25:14,164 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 19 times [2022-11-02 20:25:14,164 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:25:14,165 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [210816170] [2022-11-02 20:25:14,165 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:25:14,165 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:25:14,168 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:25:14,168 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:25:14,170 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:25:14,172 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:25:14,173 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:25:14,173 INFO L85 PathProgramCache]: Analyzing trace with hash -283534391, now seen corresponding path program 35 times [2022-11-02 20:25:14,173 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:25:14,173 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [772117917] [2022-11-02 20:25:14,173 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:25:14,174 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:25:14,243 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:25:15,559 INFO L134 CoverageAnalysis]: Checked inductivity of 801 backedges. 425 proven. 376 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:25:15,559 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 20:25:15,560 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [772117917] [2022-11-02 20:25:15,560 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [772117917] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 20:25:15,560 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1041439520] [2022-11-02 20:25:15,560 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-02 20:25:15,560 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 20:25:15,560 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 20:25:15,562 INFO L229 MonitoredProcess]: Starting monitored process 30 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 20:25:15,564 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (30)] Waiting until timeout for monitored process [2022-11-02 20:25:16,416 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 19 check-sat command(s) [2022-11-02 20:25:16,416 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-02 20:25:16,422 INFO L263 TraceCheckSpWp]: Trace formula consists of 423 conjuncts, 40 conjunts are in the unsatisfiable core [2022-11-02 20:25:16,425 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 20:25:17,388 INFO L134 CoverageAnalysis]: Checked inductivity of 801 backedges. 477 proven. 324 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:25:17,388 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 20:25:18,107 INFO L134 CoverageAnalysis]: Checked inductivity of 801 backedges. 477 proven. 324 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:25:18,107 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1041439520] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 20:25:18,108 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 20:25:18,108 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [40, 40, 40] total 61 [2022-11-02 20:25:18,108 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [608946689] [2022-11-02 20:25:18,108 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 20:25:18,162 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 20:25:18,163 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 62 interpolants. [2022-11-02 20:25:18,164 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=885, Invalid=2897, Unknown=0, NotChecked=0, Total=3782 [2022-11-02 20:25:18,164 INFO L87 Difference]: Start difference. First operand 156 states and 177 transitions. cyclomatic complexity: 24 Second operand has 62 states, 61 states have (on average 2.5901639344262297) internal successors, (158), 62 states have internal predecessors, (158), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:25:19,351 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 20:25:19,352 INFO L93 Difference]: Finished difference Result 505 states and 584 transitions. [2022-11-02 20:25:19,352 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 505 states and 584 transitions. [2022-11-02 20:25:19,355 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-02 20:25:19,357 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 505 states to 284 states and 326 transitions. [2022-11-02 20:25:19,357 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 245 [2022-11-02 20:25:19,358 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 245 [2022-11-02 20:25:19,358 INFO L73 IsDeterministic]: Start isDeterministic. Operand 284 states and 326 transitions. [2022-11-02 20:25:19,358 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-02 20:25:19,358 INFO L218 hiAutomatonCegarLoop]: Abstraction has 284 states and 326 transitions. [2022-11-02 20:25:19,359 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 284 states and 326 transitions. [2022-11-02 20:25:19,361 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 284 to 164. [2022-11-02 20:25:19,362 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 164 states, 164 states have (on average 1.1341463414634145) internal successors, (186), 163 states have internal predecessors, (186), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:25:19,362 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 164 states to 164 states and 186 transitions. [2022-11-02 20:25:19,362 INFO L240 hiAutomatonCegarLoop]: Abstraction has 164 states and 186 transitions. [2022-11-02 20:25:19,363 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2022-11-02 20:25:19,363 INFO L428 stractBuchiCegarLoop]: Abstraction has 164 states and 186 transitions. [2022-11-02 20:25:19,364 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2022-11-02 20:25:19,364 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 164 states and 186 transitions. [2022-11-02 20:25:19,365 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-02 20:25:19,365 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 20:25:19,365 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 20:25:19,366 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [19, 19, 19, 18, 18, 1, 1, 1, 1] [2022-11-02 20:25:19,366 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-11-02 20:25:19,366 INFO L748 eck$LassoCheckResult]: Stem: 13586#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 13587#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 13592#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 13607#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 13608#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 13595#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 13596#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 13646#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 13645#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 13644#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 13643#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 13642#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 13641#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 13640#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 13639#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 13638#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 13637#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 13636#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 13635#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 13634#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 13633#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 13632#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 13631#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 13630#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 13629#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 13628#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 13627#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 13626#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 13625#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 13624#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 13623#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 13622#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 13621#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 13620#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 13619#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 13618#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 13617#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 13616#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 13615#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 13611#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 13610#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 13597#L27-4 main_~i~0#1 := 0; 13598#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13654#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 13655#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 13656#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13660#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 13659#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 13744#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13741#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 13739#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 13738#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13735#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 13733#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 13732#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13729#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 13727#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 13726#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13723#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 13721#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 13720#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13717#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 13715#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 13714#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13711#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 13709#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 13708#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13705#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 13703#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 13702#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13699#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 13697#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 13696#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13693#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 13691#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 13690#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13687#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 13685#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 13684#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13681#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 13679#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 13678#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13675#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 13673#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 13672#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13669#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 13667#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 13666#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13664#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 13663#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 13662#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13604#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 13591#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 13601#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13606#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 13651#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 13650#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13613#L34 [2022-11-02 20:25:19,367 INFO L750 eck$LassoCheckResult]: Loop: 13613#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 13614#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 13612#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13613#L34 [2022-11-02 20:25:19,367 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:25:19,367 INFO L85 PathProgramCache]: Analyzing trace with hash 1191917191, now seen corresponding path program 36 times [2022-11-02 20:25:19,368 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:25:19,368 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [539266841] [2022-11-02 20:25:19,368 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:25:19,368 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:25:19,485 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:25:19,485 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:25:19,643 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:25:19,661 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:25:19,661 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:25:19,662 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 20 times [2022-11-02 20:25:19,662 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:25:19,662 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [540168994] [2022-11-02 20:25:19,662 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:25:19,662 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:25:19,666 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:25:19,666 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:25:19,668 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:25:19,670 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:25:19,671 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:25:19,671 INFO L85 PathProgramCache]: Analyzing trace with hash 1910440815, now seen corresponding path program 37 times [2022-11-02 20:25:19,671 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:25:19,671 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [276557590] [2022-11-02 20:25:19,671 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:25:19,672 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:25:19,703 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:25:21,063 INFO L134 CoverageAnalysis]: Checked inductivity of 893 backedges. 477 proven. 416 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:25:21,063 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 20:25:21,063 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [276557590] [2022-11-02 20:25:21,063 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [276557590] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 20:25:21,064 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1106510067] [2022-11-02 20:25:21,064 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-11-02 20:25:21,064 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 20:25:21,064 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 20:25:21,066 INFO L229 MonitoredProcess]: Starting monitored process 31 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 20:25:21,074 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (31)] Waiting until timeout for monitored process [2022-11-02 20:25:21,262 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:25:21,265 INFO L263 TraceCheckSpWp]: Trace formula consists of 444 conjuncts, 42 conjunts are in the unsatisfiable core [2022-11-02 20:25:21,268 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 20:25:22,295 INFO L134 CoverageAnalysis]: Checked inductivity of 893 backedges. 532 proven. 361 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:25:22,295 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 20:25:23,024 INFO L134 CoverageAnalysis]: Checked inductivity of 893 backedges. 532 proven. 361 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:25:23,024 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1106510067] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 20:25:23,025 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 20:25:23,025 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [42, 42, 42] total 64 [2022-11-02 20:25:23,025 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [755608112] [2022-11-02 20:25:23,025 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 20:25:23,070 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 20:25:23,071 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 65 interpolants. [2022-11-02 20:25:23,073 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=971, Invalid=3189, Unknown=0, NotChecked=0, Total=4160 [2022-11-02 20:25:23,073 INFO L87 Difference]: Start difference. First operand 164 states and 186 transitions. cyclomatic complexity: 25 Second operand has 65 states, 64 states have (on average 2.59375) internal successors, (166), 65 states have internal predecessors, (166), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:25:24,379 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 20:25:24,380 INFO L93 Difference]: Finished difference Result 531 states and 614 transitions. [2022-11-02 20:25:24,380 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 531 states and 614 transitions. [2022-11-02 20:25:24,385 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-02 20:25:24,387 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 531 states to 298 states and 342 transitions. [2022-11-02 20:25:24,387 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 257 [2022-11-02 20:25:24,387 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 257 [2022-11-02 20:25:24,387 INFO L73 IsDeterministic]: Start isDeterministic. Operand 298 states and 342 transitions. [2022-11-02 20:25:24,388 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-02 20:25:24,388 INFO L218 hiAutomatonCegarLoop]: Abstraction has 298 states and 342 transitions. [2022-11-02 20:25:24,389 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 298 states and 342 transitions. [2022-11-02 20:25:24,392 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 298 to 172. [2022-11-02 20:25:24,392 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 172 states, 172 states have (on average 1.1337209302325582) internal successors, (195), 171 states have internal predecessors, (195), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:25:24,393 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 172 states to 172 states and 195 transitions. [2022-11-02 20:25:24,393 INFO L240 hiAutomatonCegarLoop]: Abstraction has 172 states and 195 transitions. [2022-11-02 20:25:24,394 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2022-11-02 20:25:24,394 INFO L428 stractBuchiCegarLoop]: Abstraction has 172 states and 195 transitions. [2022-11-02 20:25:24,394 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2022-11-02 20:25:24,395 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 172 states and 195 transitions. [2022-11-02 20:25:24,396 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-02 20:25:24,396 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 20:25:24,396 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 20:25:24,397 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [20, 20, 20, 19, 19, 1, 1, 1, 1] [2022-11-02 20:25:24,397 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-11-02 20:25:24,398 INFO L748 eck$LassoCheckResult]: Stem: 14985#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 14986#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 14991#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 15005#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15006#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 14994#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14995#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 15046#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15045#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 15044#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15043#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 15042#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15041#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 15040#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15039#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 15038#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15037#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 15036#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15035#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 15034#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15033#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 15032#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15031#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 15030#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15029#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 15028#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15027#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 15026#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15025#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 15024#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15023#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 15022#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15021#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 15020#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15019#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 15018#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15017#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 15016#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15015#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 15014#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15013#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 15009#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15008#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 14996#L27-4 main_~i~0#1 := 0; 14997#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15152#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 15056#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 15054#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15055#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 15059#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 15151#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15148#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 15146#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 15145#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15142#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 15140#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 15139#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15136#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 15134#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 15133#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15130#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 15128#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 15127#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15124#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 15122#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 15121#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15118#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 15116#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 15115#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15112#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 15110#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 15109#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15106#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 15104#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 15103#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15100#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 15098#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 15097#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15094#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 15092#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 15091#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15088#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 15086#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 15085#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15082#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 15080#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 15079#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15076#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 15074#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 15073#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15070#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 15068#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 15067#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15065#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 15063#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 15062#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15002#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 14990#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 14999#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15004#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 15051#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 15050#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15011#L34 [2022-11-02 20:25:24,398 INFO L750 eck$LassoCheckResult]: Loop: 15011#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 15012#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 15010#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15011#L34 [2022-11-02 20:25:24,399 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:25:24,399 INFO L85 PathProgramCache]: Analyzing trace with hash 1997959025, now seen corresponding path program 38 times [2022-11-02 20:25:24,399 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:25:24,399 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1808330201] [2022-11-02 20:25:24,400 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:25:24,400 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:25:24,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:25:24,546 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:25:24,687 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:25:24,698 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:25:24,698 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:25:24,698 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 21 times [2022-11-02 20:25:24,699 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:25:24,699 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1082610249] [2022-11-02 20:25:24,699 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:25:24,699 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:25:24,702 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:25:24,702 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:25:24,704 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:25:24,706 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:25:24,707 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:25:24,707 INFO L85 PathProgramCache]: Analyzing trace with hash 1540565573, now seen corresponding path program 39 times [2022-11-02 20:25:24,708 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:25:24,708 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1400872691] [2022-11-02 20:25:24,708 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:25:24,708 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:25:24,739 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:25:26,164 INFO L134 CoverageAnalysis]: Checked inductivity of 990 backedges. 532 proven. 458 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:25:26,164 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 20:25:26,164 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1400872691] [2022-11-02 20:25:26,164 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1400872691] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 20:25:26,164 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1550689682] [2022-11-02 20:25:26,164 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-02 20:25:26,165 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 20:25:26,165 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 20:25:26,167 INFO L229 MonitoredProcess]: Starting monitored process 32 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 20:25:26,168 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (32)] Waiting until timeout for monitored process [2022-11-02 20:25:27,711 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 21 check-sat command(s) [2022-11-02 20:25:27,711 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-02 20:25:27,717 INFO L263 TraceCheckSpWp]: Trace formula consists of 465 conjuncts, 44 conjunts are in the unsatisfiable core [2022-11-02 20:25:27,719 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 20:25:28,738 INFO L134 CoverageAnalysis]: Checked inductivity of 990 backedges. 590 proven. 400 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:25:28,738 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 20:25:29,542 INFO L134 CoverageAnalysis]: Checked inductivity of 990 backedges. 590 proven. 400 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:25:29,542 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1550689682] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 20:25:29,542 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 20:25:29,542 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [44, 44, 44] total 67 [2022-11-02 20:25:29,543 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1099187342] [2022-11-02 20:25:29,543 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 20:25:29,587 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 20:25:29,588 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 68 interpolants. [2022-11-02 20:25:29,590 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1061, Invalid=3495, Unknown=0, NotChecked=0, Total=4556 [2022-11-02 20:25:29,590 INFO L87 Difference]: Start difference. First operand 172 states and 195 transitions. cyclomatic complexity: 26 Second operand has 68 states, 67 states have (on average 2.5970149253731343) internal successors, (174), 68 states have internal predecessors, (174), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:25:30,817 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 20:25:30,817 INFO L93 Difference]: Finished difference Result 557 states and 644 transitions. [2022-11-02 20:25:30,817 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 557 states and 644 transitions. [2022-11-02 20:25:30,819 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-02 20:25:30,821 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 557 states to 312 states and 358 transitions. [2022-11-02 20:25:30,821 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 269 [2022-11-02 20:25:30,822 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 269 [2022-11-02 20:25:30,822 INFO L73 IsDeterministic]: Start isDeterministic. Operand 312 states and 358 transitions. [2022-11-02 20:25:30,822 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-02 20:25:30,822 INFO L218 hiAutomatonCegarLoop]: Abstraction has 312 states and 358 transitions. [2022-11-02 20:25:30,823 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 312 states and 358 transitions. [2022-11-02 20:25:30,825 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 312 to 180. [2022-11-02 20:25:30,826 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 180 states, 180 states have (on average 1.1333333333333333) internal successors, (204), 179 states have internal predecessors, (204), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:25:30,826 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 180 states to 180 states and 204 transitions. [2022-11-02 20:25:30,826 INFO L240 hiAutomatonCegarLoop]: Abstraction has 180 states and 204 transitions. [2022-11-02 20:25:30,834 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2022-11-02 20:25:30,835 INFO L428 stractBuchiCegarLoop]: Abstraction has 180 states and 204 transitions. [2022-11-02 20:25:30,835 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2022-11-02 20:25:30,835 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 180 states and 204 transitions. [2022-11-02 20:25:30,836 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-02 20:25:30,836 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 20:25:30,836 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 20:25:30,837 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [21, 21, 21, 20, 20, 1, 1, 1, 1] [2022-11-02 20:25:30,838 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-11-02 20:25:30,838 INFO L748 eck$LassoCheckResult]: Stem: 16453#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 16454#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 16459#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 16474#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 16475#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 16462#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 16463#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 16517#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 16516#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 16515#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 16514#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 16513#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 16512#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 16511#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 16510#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 16509#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 16508#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 16507#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 16506#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 16505#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 16504#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 16503#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 16502#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 16501#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 16500#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 16499#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 16498#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 16497#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 16496#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 16495#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 16494#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 16493#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 16492#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 16491#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 16490#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 16489#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 16488#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 16487#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 16486#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 16485#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 16484#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 16483#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 16482#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 16478#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 16477#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 16464#L27-4 main_~i~0#1 := 0; 16465#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16525#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 16526#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 16527#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16531#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 16530#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 16627#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16624#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 16622#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 16621#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16618#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 16616#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 16615#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16612#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 16610#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 16609#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16606#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 16604#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 16603#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16600#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 16598#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 16597#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16594#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 16592#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 16591#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16588#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 16586#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 16585#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16582#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 16580#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 16579#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16576#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 16574#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 16573#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16570#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 16568#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 16567#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16564#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 16562#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 16561#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16558#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 16556#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 16555#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16552#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 16550#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 16549#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16546#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 16544#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 16543#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16540#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 16538#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 16537#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16535#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 16534#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 16533#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16471#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 16458#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 16468#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16473#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 16522#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 16521#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16480#L34 [2022-11-02 20:25:30,838 INFO L750 eck$LassoCheckResult]: Loop: 16480#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 16481#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 16479#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16480#L34 [2022-11-02 20:25:30,839 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:25:30,839 INFO L85 PathProgramCache]: Analyzing trace with hash 1338568579, now seen corresponding path program 40 times [2022-11-02 20:25:30,839 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:25:30,839 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1534172951] [2022-11-02 20:25:30,839 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:25:30,840 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:25:30,979 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:25:30,980 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:25:31,095 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:25:31,107 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:25:31,108 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:25:31,108 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 22 times [2022-11-02 20:25:31,108 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:25:31,109 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [990331403] [2022-11-02 20:25:31,109 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:25:31,109 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:25:31,112 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:25:31,112 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:25:31,114 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:25:31,116 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:25:31,117 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:25:31,117 INFO L85 PathProgramCache]: Analyzing trace with hash -1474766605, now seen corresponding path program 41 times [2022-11-02 20:25:31,117 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:25:31,117 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1725797855] [2022-11-02 20:25:31,118 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:25:31,118 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:25:31,154 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:25:32,638 INFO L134 CoverageAnalysis]: Checked inductivity of 1092 backedges. 590 proven. 502 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:25:32,638 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 20:25:32,638 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1725797855] [2022-11-02 20:25:32,638 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1725797855] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 20:25:32,638 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [866463380] [2022-11-02 20:25:32,638 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-02 20:25:32,638 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 20:25:32,638 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 20:25:32,640 INFO L229 MonitoredProcess]: Starting monitored process 33 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 20:25:32,641 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (33)] Waiting until timeout for monitored process [2022-11-02 20:25:34,094 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 22 check-sat command(s) [2022-11-02 20:25:34,094 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-02 20:25:34,102 INFO L263 TraceCheckSpWp]: Trace formula consists of 486 conjuncts, 46 conjunts are in the unsatisfiable core [2022-11-02 20:25:34,104 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 20:25:35,238 INFO L134 CoverageAnalysis]: Checked inductivity of 1092 backedges. 651 proven. 441 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:25:35,238 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 20:25:36,227 INFO L134 CoverageAnalysis]: Checked inductivity of 1092 backedges. 651 proven. 441 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:25:36,227 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [866463380] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 20:25:36,228 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 20:25:36,228 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [46, 46, 46] total 70 [2022-11-02 20:25:36,228 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1860441853] [2022-11-02 20:25:36,228 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 20:25:36,284 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 20:25:36,285 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 71 interpolants. [2022-11-02 20:25:36,286 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1155, Invalid=3815, Unknown=0, NotChecked=0, Total=4970 [2022-11-02 20:25:36,287 INFO L87 Difference]: Start difference. First operand 180 states and 204 transitions. cyclomatic complexity: 27 Second operand has 71 states, 70 states have (on average 2.6) internal successors, (182), 71 states have internal predecessors, (182), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:25:37,745 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 20:25:37,745 INFO L93 Difference]: Finished difference Result 583 states and 674 transitions. [2022-11-02 20:25:37,746 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 583 states and 674 transitions. [2022-11-02 20:25:37,750 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-02 20:25:37,752 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 583 states to 326 states and 374 transitions. [2022-11-02 20:25:37,752 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 281 [2022-11-02 20:25:37,753 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 281 [2022-11-02 20:25:37,753 INFO L73 IsDeterministic]: Start isDeterministic. Operand 326 states and 374 transitions. [2022-11-02 20:25:37,753 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-02 20:25:37,754 INFO L218 hiAutomatonCegarLoop]: Abstraction has 326 states and 374 transitions. [2022-11-02 20:25:37,754 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 326 states and 374 transitions. [2022-11-02 20:25:37,757 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 326 to 188. [2022-11-02 20:25:37,757 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 188 states, 188 states have (on average 1.1329787234042554) internal successors, (213), 187 states have internal predecessors, (213), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:25:37,758 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 188 states to 188 states and 213 transitions. [2022-11-02 20:25:37,758 INFO L240 hiAutomatonCegarLoop]: Abstraction has 188 states and 213 transitions. [2022-11-02 20:25:37,760 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2022-11-02 20:25:37,761 INFO L428 stractBuchiCegarLoop]: Abstraction has 188 states and 213 transitions. [2022-11-02 20:25:37,761 INFO L335 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2022-11-02 20:25:37,761 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 188 states and 213 transitions. [2022-11-02 20:25:37,762 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-02 20:25:37,762 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 20:25:37,762 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 20:25:37,764 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [22, 22, 22, 21, 21, 1, 1, 1, 1] [2022-11-02 20:25:37,764 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-11-02 20:25:37,764 INFO L748 eck$LassoCheckResult]: Stem: 17990#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 17991#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 17996#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 18010#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 18011#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 17999#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 18000#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 18055#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 18054#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 18053#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 18052#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 18051#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 18050#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 18049#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 18048#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 18047#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 18046#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 18045#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 18044#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 18043#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 18042#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 18041#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 18040#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 18039#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 18038#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 18037#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 18036#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 18035#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 18034#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 18033#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 18032#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 18031#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 18030#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 18029#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 18028#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 18027#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 18026#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 18025#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 18024#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 18023#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 18022#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 18021#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 18020#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 18019#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 18018#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 18014#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 18013#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 18001#L27-4 main_~i~0#1 := 0; 18002#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18172#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 18065#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 18063#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18064#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 18068#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 18170#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18167#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 18165#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 18164#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18161#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 18159#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 18158#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18155#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 18153#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 18152#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18149#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 18147#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 18146#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18143#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 18141#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 18140#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18137#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 18135#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 18134#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18131#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 18129#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 18128#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18125#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 18123#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 18122#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18119#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 18117#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 18116#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18113#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 18111#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 18110#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18107#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 18105#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 18104#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18101#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 18099#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 18098#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18095#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 18093#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 18092#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18089#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 18087#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 18086#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18083#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 18081#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 18080#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18077#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 18075#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 18074#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18073#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 18072#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 18071#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18007#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 17995#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 18004#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18009#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 18060#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 18059#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18016#L34 [2022-11-02 20:25:37,764 INFO L750 eck$LassoCheckResult]: Loop: 18016#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 18017#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 18015#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18016#L34 [2022-11-02 20:25:37,765 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:25:37,765 INFO L85 PathProgramCache]: Analyzing trace with hash 2042800757, now seen corresponding path program 42 times [2022-11-02 20:25:37,765 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:25:37,765 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1652700267] [2022-11-02 20:25:37,765 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:25:37,766 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:25:37,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:25:37,928 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:25:38,028 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:25:38,040 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:25:38,040 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:25:38,041 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 23 times [2022-11-02 20:25:38,041 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:25:38,041 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1062953707] [2022-11-02 20:25:38,041 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:25:38,041 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:25:38,044 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:25:38,045 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:25:38,047 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:25:38,049 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:25:38,049 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:25:38,049 INFO L85 PathProgramCache]: Analyzing trace with hash 1685774529, now seen corresponding path program 43 times [2022-11-02 20:25:38,050 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:25:38,050 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1857041340] [2022-11-02 20:25:38,050 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:25:38,050 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:25:38,084 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:25:39,665 INFO L134 CoverageAnalysis]: Checked inductivity of 1199 backedges. 651 proven. 548 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:25:39,665 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 20:25:39,665 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1857041340] [2022-11-02 20:25:39,665 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1857041340] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 20:25:39,666 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [996949180] [2022-11-02 20:25:39,666 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-11-02 20:25:39,666 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 20:25:39,666 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 20:25:39,668 INFO L229 MonitoredProcess]: Starting monitored process 34 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 20:25:39,669 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (34)] Waiting until timeout for monitored process [2022-11-02 20:25:39,858 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:25:39,861 INFO L263 TraceCheckSpWp]: Trace formula consists of 507 conjuncts, 48 conjunts are in the unsatisfiable core [2022-11-02 20:25:39,864 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 20:25:41,093 INFO L134 CoverageAnalysis]: Checked inductivity of 1199 backedges. 715 proven. 484 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:25:41,094 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 20:25:42,034 INFO L134 CoverageAnalysis]: Checked inductivity of 1199 backedges. 715 proven. 484 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:25:42,035 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [996949180] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 20:25:42,035 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 20:25:42,035 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 48, 48] total 73 [2022-11-02 20:25:42,035 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [690519863] [2022-11-02 20:25:42,035 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 20:25:42,077 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 20:25:42,078 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 74 interpolants. [2022-11-02 20:25:42,078 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1253, Invalid=4149, Unknown=0, NotChecked=0, Total=5402 [2022-11-02 20:25:42,079 INFO L87 Difference]: Start difference. First operand 188 states and 213 transitions. cyclomatic complexity: 28 Second operand has 74 states, 73 states have (on average 2.6027397260273974) internal successors, (190), 74 states have internal predecessors, (190), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:25:43,382 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 20:25:43,382 INFO L93 Difference]: Finished difference Result 609 states and 704 transitions. [2022-11-02 20:25:43,382 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 609 states and 704 transitions. [2022-11-02 20:25:43,385 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-02 20:25:43,387 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 609 states to 340 states and 390 transitions. [2022-11-02 20:25:43,387 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 293 [2022-11-02 20:25:43,388 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 293 [2022-11-02 20:25:43,388 INFO L73 IsDeterministic]: Start isDeterministic. Operand 340 states and 390 transitions. [2022-11-02 20:25:43,389 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-02 20:25:43,389 INFO L218 hiAutomatonCegarLoop]: Abstraction has 340 states and 390 transitions. [2022-11-02 20:25:43,389 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 340 states and 390 transitions. [2022-11-02 20:25:43,392 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 340 to 196. [2022-11-02 20:25:43,392 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 196 states, 196 states have (on average 1.1326530612244898) internal successors, (222), 195 states have internal predecessors, (222), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:25:43,393 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 196 states to 196 states and 222 transitions. [2022-11-02 20:25:43,393 INFO L240 hiAutomatonCegarLoop]: Abstraction has 196 states and 222 transitions. [2022-11-02 20:25:43,402 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2022-11-02 20:25:43,402 INFO L428 stractBuchiCegarLoop]: Abstraction has 196 states and 222 transitions. [2022-11-02 20:25:43,403 INFO L335 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2022-11-02 20:25:43,403 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 196 states and 222 transitions. [2022-11-02 20:25:43,404 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-02 20:25:43,404 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 20:25:43,404 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 20:25:43,405 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [23, 23, 23, 22, 22, 1, 1, 1, 1] [2022-11-02 20:25:43,405 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-11-02 20:25:43,406 INFO L748 eck$LassoCheckResult]: Stem: 19596#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 19597#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 19602#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 19617#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19618#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 19605#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19606#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 19664#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19663#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 19662#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19661#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 19660#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19659#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 19658#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19657#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 19656#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19655#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 19654#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19653#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 19652#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19651#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 19650#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19649#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 19648#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19647#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 19646#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19645#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 19644#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19643#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 19642#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19641#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 19640#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19639#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 19638#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19637#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 19636#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19635#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 19634#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19633#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 19632#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19631#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 19630#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19629#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 19628#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19627#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 19626#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19625#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 19621#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19620#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 19607#L27-4 main_~i~0#1 := 0; 19608#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19672#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 19673#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 19674#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19678#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 19677#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 19786#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19783#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 19781#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 19780#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19777#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 19775#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 19774#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19771#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 19769#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 19768#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19765#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 19763#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 19762#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19759#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 19757#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 19756#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19753#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 19751#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 19750#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19747#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 19745#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 19744#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19741#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 19739#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 19738#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19735#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 19733#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 19732#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19729#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 19727#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 19726#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19723#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 19721#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 19720#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19717#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 19715#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 19714#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19711#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 19709#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 19708#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19705#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 19703#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 19702#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19699#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 19697#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 19696#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19693#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 19691#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 19690#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19687#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 19685#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 19684#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19682#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 19681#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 19680#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19614#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 19601#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 19611#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19616#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 19669#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 19668#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19623#L34 [2022-11-02 20:25:43,406 INFO L750 eck$LassoCheckResult]: Loop: 19623#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 19624#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 19622#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19623#L34 [2022-11-02 20:25:43,406 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:25:43,407 INFO L85 PathProgramCache]: Analyzing trace with hash -1222528897, now seen corresponding path program 44 times [2022-11-02 20:25:43,407 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:25:43,407 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [761486446] [2022-11-02 20:25:43,407 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:25:43,407 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:25:43,584 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:25:43,584 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:25:43,714 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:25:43,726 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:25:43,727 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:25:43,727 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 24 times [2022-11-02 20:25:43,727 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:25:43,727 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1087876656] [2022-11-02 20:25:43,727 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:25:43,727 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:25:43,730 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:25:43,731 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:25:43,732 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:25:43,735 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:25:43,735 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:25:43,735 INFO L85 PathProgramCache]: Analyzing trace with hash 964339319, now seen corresponding path program 45 times [2022-11-02 20:25:43,735 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:25:43,735 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2104947255] [2022-11-02 20:25:43,736 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:25:43,736 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:25:43,771 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:25:45,468 INFO L134 CoverageAnalysis]: Checked inductivity of 1311 backedges. 715 proven. 596 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:25:45,468 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 20:25:45,468 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2104947255] [2022-11-02 20:25:45,469 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2104947255] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 20:25:45,469 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1649219245] [2022-11-02 20:25:45,469 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-02 20:25:45,469 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 20:25:45,469 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 20:25:45,474 INFO L229 MonitoredProcess]: Starting monitored process 35 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 20:25:45,479 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (35)] Waiting until timeout for monitored process [2022-11-02 20:25:47,674 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 24 check-sat command(s) [2022-11-02 20:25:47,674 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-02 20:25:47,685 INFO L263 TraceCheckSpWp]: Trace formula consists of 528 conjuncts, 50 conjunts are in the unsatisfiable core [2022-11-02 20:25:47,688 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 20:25:49,067 INFO L134 CoverageAnalysis]: Checked inductivity of 1311 backedges. 782 proven. 529 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:25:49,068 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 20:25:50,158 INFO L134 CoverageAnalysis]: Checked inductivity of 1311 backedges. 782 proven. 529 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:25:50,159 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1649219245] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 20:25:50,159 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 20:25:50,159 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 50, 50] total 76 [2022-11-02 20:25:50,159 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1442993702] [2022-11-02 20:25:50,159 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 20:25:50,222 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 20:25:50,223 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 77 interpolants. [2022-11-02 20:25:50,224 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1355, Invalid=4497, Unknown=0, NotChecked=0, Total=5852 [2022-11-02 20:25:50,225 INFO L87 Difference]: Start difference. First operand 196 states and 222 transitions. cyclomatic complexity: 29 Second operand has 77 states, 76 states have (on average 2.6052631578947367) internal successors, (198), 77 states have internal predecessors, (198), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:25:51,831 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 20:25:51,831 INFO L93 Difference]: Finished difference Result 635 states and 734 transitions. [2022-11-02 20:25:51,831 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 635 states and 734 transitions. [2022-11-02 20:25:51,835 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-02 20:25:51,836 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 635 states to 354 states and 406 transitions. [2022-11-02 20:25:51,837 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 305 [2022-11-02 20:25:51,837 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 305 [2022-11-02 20:25:51,837 INFO L73 IsDeterministic]: Start isDeterministic. Operand 354 states and 406 transitions. [2022-11-02 20:25:51,838 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-02 20:25:51,838 INFO L218 hiAutomatonCegarLoop]: Abstraction has 354 states and 406 transitions. [2022-11-02 20:25:51,839 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 354 states and 406 transitions. [2022-11-02 20:25:51,841 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 354 to 204. [2022-11-02 20:25:51,842 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 204 states, 204 states have (on average 1.1323529411764706) internal successors, (231), 203 states have internal predecessors, (231), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:25:51,842 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 204 states to 204 states and 231 transitions. [2022-11-02 20:25:51,842 INFO L240 hiAutomatonCegarLoop]: Abstraction has 204 states and 231 transitions. [2022-11-02 20:25:51,843 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 52 states. [2022-11-02 20:25:51,843 INFO L428 stractBuchiCegarLoop]: Abstraction has 204 states and 231 transitions. [2022-11-02 20:25:51,843 INFO L335 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2022-11-02 20:25:51,843 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 204 states and 231 transitions. [2022-11-02 20:25:51,844 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-02 20:25:51,844 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 20:25:51,845 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 20:25:51,846 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [24, 24, 24, 23, 23, 1, 1, 1, 1] [2022-11-02 20:25:51,846 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-11-02 20:25:51,846 INFO L748 eck$LassoCheckResult]: Stem: 21271#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 21272#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 21277#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21291#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21292#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21280#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21281#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21340#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21339#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21338#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21337#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21336#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21335#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21334#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21333#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21332#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21331#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21330#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21329#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21328#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21327#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21326#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21325#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21324#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21323#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21322#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21321#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21320#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21319#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21318#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21317#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21316#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21315#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21314#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21313#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21312#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21311#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21310#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21309#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21308#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21307#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21306#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21305#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21304#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21303#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21302#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21301#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21300#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21299#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21295#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21294#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 21282#L27-4 main_~i~0#1 := 0; 21283#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21470#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21350#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21348#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21349#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21353#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21469#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21466#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21464#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21463#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21460#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21458#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21457#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21454#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21452#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21451#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21448#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21446#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21445#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21442#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21440#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21439#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21436#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21434#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21433#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21430#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21428#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21427#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21424#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21422#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21421#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21418#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21416#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21415#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21412#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21410#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21409#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21406#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21404#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21403#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21400#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21398#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21397#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21394#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21392#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21391#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21388#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21386#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21385#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21382#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21380#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21379#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21376#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21374#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21373#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21370#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21368#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21367#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21364#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21362#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21361#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21359#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21357#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21356#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21288#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21276#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21285#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21290#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21345#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21344#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21297#L34 [2022-11-02 20:25:51,846 INFO L750 eck$LassoCheckResult]: Loop: 21297#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21298#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21296#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21297#L34 [2022-11-02 20:25:51,847 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:25:51,847 INFO L85 PathProgramCache]: Analyzing trace with hash 502660473, now seen corresponding path program 46 times [2022-11-02 20:25:51,847 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:25:51,847 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [386195686] [2022-11-02 20:25:51,847 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:25:51,847 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:25:52,003 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:25:52,004 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:25:52,129 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:25:52,144 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:25:52,144 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:25:52,144 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 25 times [2022-11-02 20:25:52,145 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:25:52,145 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1468997089] [2022-11-02 20:25:52,145 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:25:52,145 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:25:52,148 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:25:52,149 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:25:52,150 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:25:52,153 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:25:52,153 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:25:52,153 INFO L85 PathProgramCache]: Analyzing trace with hash -1792770243, now seen corresponding path program 47 times [2022-11-02 20:25:52,153 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:25:52,154 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [942305869] [2022-11-02 20:25:52,154 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:25:52,154 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:25:52,191 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:25:54,089 INFO L134 CoverageAnalysis]: Checked inductivity of 1428 backedges. 782 proven. 646 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:25:54,090 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 20:25:54,090 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [942305869] [2022-11-02 20:25:54,090 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [942305869] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 20:25:54,090 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [306529264] [2022-11-02 20:25:54,090 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-02 20:25:54,090 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 20:25:54,090 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 20:25:54,093 INFO L229 MonitoredProcess]: Starting monitored process 36 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 20:25:54,094 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (36)] Waiting until timeout for monitored process [2022-11-02 20:25:55,576 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 25 check-sat command(s) [2022-11-02 20:25:55,576 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-02 20:25:55,584 INFO L263 TraceCheckSpWp]: Trace formula consists of 549 conjuncts, 52 conjunts are in the unsatisfiable core [2022-11-02 20:25:55,586 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 20:25:56,982 INFO L134 CoverageAnalysis]: Checked inductivity of 1428 backedges. 852 proven. 576 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:25:56,982 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 20:25:58,083 INFO L134 CoverageAnalysis]: Checked inductivity of 1428 backedges. 852 proven. 576 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:25:58,083 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [306529264] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 20:25:58,083 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 20:25:58,083 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [52, 52, 52] total 79 [2022-11-02 20:25:58,083 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1736442827] [2022-11-02 20:25:58,083 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 20:25:58,126 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 20:25:58,127 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 80 interpolants. [2022-11-02 20:25:58,130 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1461, Invalid=4859, Unknown=0, NotChecked=0, Total=6320 [2022-11-02 20:25:58,130 INFO L87 Difference]: Start difference. First operand 204 states and 231 transitions. cyclomatic complexity: 30 Second operand has 80 states, 79 states have (on average 2.607594936708861) internal successors, (206), 80 states have internal predecessors, (206), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:25:59,553 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 20:25:59,553 INFO L93 Difference]: Finished difference Result 661 states and 764 transitions. [2022-11-02 20:25:59,553 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 661 states and 764 transitions. [2022-11-02 20:25:59,556 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-02 20:25:59,557 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 661 states to 368 states and 422 transitions. [2022-11-02 20:25:59,557 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 317 [2022-11-02 20:25:59,558 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 317 [2022-11-02 20:25:59,558 INFO L73 IsDeterministic]: Start isDeterministic. Operand 368 states and 422 transitions. [2022-11-02 20:25:59,558 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-02 20:25:59,558 INFO L218 hiAutomatonCegarLoop]: Abstraction has 368 states and 422 transitions. [2022-11-02 20:25:59,559 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 368 states and 422 transitions. [2022-11-02 20:25:59,561 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 368 to 212. [2022-11-02 20:25:59,562 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 212 states, 212 states have (on average 1.1320754716981132) internal successors, (240), 211 states have internal predecessors, (240), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:25:59,562 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 212 states to 212 states and 240 transitions. [2022-11-02 20:25:59,562 INFO L240 hiAutomatonCegarLoop]: Abstraction has 212 states and 240 transitions. [2022-11-02 20:25:59,563 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 54 states. [2022-11-02 20:25:59,563 INFO L428 stractBuchiCegarLoop]: Abstraction has 212 states and 240 transitions. [2022-11-02 20:25:59,564 INFO L335 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2022-11-02 20:25:59,564 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 212 states and 240 transitions. [2022-11-02 20:25:59,565 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-02 20:25:59,565 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 20:25:59,565 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 20:25:59,566 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [25, 25, 25, 24, 24, 1, 1, 1, 1] [2022-11-02 20:25:59,566 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-11-02 20:25:59,567 INFO L748 eck$LassoCheckResult]: Stem: 23015#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 23016#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 23021#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23036#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23037#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23024#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23025#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23087#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23086#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23085#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23084#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23083#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23082#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23081#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23080#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23079#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23078#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23077#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23076#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23075#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23074#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23073#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23072#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23071#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23070#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23069#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23068#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23067#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23066#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23065#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23064#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23063#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23062#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23061#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23060#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23059#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23058#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23057#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23056#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23055#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23054#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23053#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23052#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23051#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23050#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23049#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23048#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23047#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23046#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23045#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23044#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23040#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23039#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 23026#L27-4 main_~i~0#1 := 0; 23027#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23095#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23096#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23097#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23101#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23100#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23221#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23218#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23216#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23215#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23212#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23210#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23209#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23206#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23204#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23203#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23200#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23198#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23197#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23194#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23192#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23191#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23188#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23186#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23185#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23182#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23180#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23179#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23176#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23174#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23173#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23170#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23168#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23167#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23164#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23162#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23161#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23158#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23156#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23155#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23152#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23150#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23149#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23146#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23144#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23143#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23140#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23138#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23137#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23134#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23132#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23131#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23128#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23126#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23125#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23122#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23120#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23119#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23116#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23114#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23113#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23110#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23108#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23107#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23105#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23104#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23103#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23033#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23020#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23030#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23035#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23092#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23091#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23042#L34 [2022-11-02 20:25:59,567 INFO L750 eck$LassoCheckResult]: Loop: 23042#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23043#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23041#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23042#L34 [2022-11-02 20:25:59,567 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:25:59,567 INFO L85 PathProgramCache]: Analyzing trace with hash -1097778821, now seen corresponding path program 48 times [2022-11-02 20:25:59,568 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:25:59,568 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1948913210] [2022-11-02 20:25:59,568 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:25:59,568 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:25:59,749 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:25:59,750 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:25:59,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:25:59,945 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:25:59,946 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:25:59,946 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 26 times [2022-11-02 20:25:59,946 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:25:59,946 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [483731266] [2022-11-02 20:25:59,946 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:25:59,947 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:25:59,950 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:25:59,950 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:25:59,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:25:59,954 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:25:59,954 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:25:59,955 INFO L85 PathProgramCache]: Analyzing trace with hash -2047824901, now seen corresponding path program 49 times [2022-11-02 20:25:59,955 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:25:59,955 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [262724558] [2022-11-02 20:25:59,955 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:25:59,955 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:25:59,997 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:26:01,827 INFO L134 CoverageAnalysis]: Checked inductivity of 1550 backedges. 852 proven. 698 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:26:01,827 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 20:26:01,827 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [262724558] [2022-11-02 20:26:01,827 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [262724558] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 20:26:01,828 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2129889391] [2022-11-02 20:26:01,828 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-11-02 20:26:01,828 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 20:26:01,828 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 20:26:01,833 INFO L229 MonitoredProcess]: Starting monitored process 37 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 20:26:01,835 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (37)] Waiting until timeout for monitored process [2022-11-02 20:26:02,051 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:26:02,055 INFO L263 TraceCheckSpWp]: Trace formula consists of 570 conjuncts, 54 conjunts are in the unsatisfiable core [2022-11-02 20:26:02,056 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 20:26:03,568 INFO L134 CoverageAnalysis]: Checked inductivity of 1550 backedges. 925 proven. 625 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:26:03,568 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 20:26:04,698 INFO L134 CoverageAnalysis]: Checked inductivity of 1550 backedges. 925 proven. 625 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:26:04,698 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2129889391] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 20:26:04,698 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 20:26:04,698 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [54, 54, 54] total 82 [2022-11-02 20:26:04,698 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [199483796] [2022-11-02 20:26:04,699 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 20:26:04,742 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 20:26:04,743 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 83 interpolants. [2022-11-02 20:26:04,745 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1571, Invalid=5235, Unknown=0, NotChecked=0, Total=6806 [2022-11-02 20:26:04,745 INFO L87 Difference]: Start difference. First operand 212 states and 240 transitions. cyclomatic complexity: 31 Second operand has 83 states, 82 states have (on average 2.6097560975609757) internal successors, (214), 83 states have internal predecessors, (214), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:26:06,378 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 20:26:06,378 INFO L93 Difference]: Finished difference Result 687 states and 794 transitions. [2022-11-02 20:26:06,379 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 687 states and 794 transitions. [2022-11-02 20:26:06,383 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-02 20:26:06,385 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 687 states to 382 states and 438 transitions. [2022-11-02 20:26:06,385 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 329 [2022-11-02 20:26:06,386 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 329 [2022-11-02 20:26:06,386 INFO L73 IsDeterministic]: Start isDeterministic. Operand 382 states and 438 transitions. [2022-11-02 20:26:06,387 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-02 20:26:06,387 INFO L218 hiAutomatonCegarLoop]: Abstraction has 382 states and 438 transitions. [2022-11-02 20:26:06,387 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 382 states and 438 transitions. [2022-11-02 20:26:06,390 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 382 to 220. [2022-11-02 20:26:06,391 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 220 states, 220 states have (on average 1.1318181818181818) internal successors, (249), 219 states have internal predecessors, (249), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:26:06,392 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 220 states to 220 states and 249 transitions. [2022-11-02 20:26:06,392 INFO L240 hiAutomatonCegarLoop]: Abstraction has 220 states and 249 transitions. [2022-11-02 20:26:06,392 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 56 states. [2022-11-02 20:26:06,393 INFO L428 stractBuchiCegarLoop]: Abstraction has 220 states and 249 transitions. [2022-11-02 20:26:06,393 INFO L335 stractBuchiCegarLoop]: ======== Iteration 28 ============ [2022-11-02 20:26:06,393 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 220 states and 249 transitions. [2022-11-02 20:26:06,394 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-02 20:26:06,394 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 20:26:06,395 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 20:26:06,396 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [26, 26, 26, 25, 25, 1, 1, 1, 1] [2022-11-02 20:26:06,396 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-11-02 20:26:06,396 INFO L748 eck$LassoCheckResult]: Stem: 24828#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 24829#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 24834#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24848#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24849#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24837#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24838#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24901#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24900#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24899#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24898#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24897#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24896#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24895#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24894#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24893#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24892#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24891#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24890#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24889#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24888#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24887#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24886#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24885#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24884#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24883#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24882#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24881#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24880#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24879#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24878#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24877#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24876#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24875#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24874#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24873#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24872#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24871#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24870#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24869#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24868#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24867#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24866#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24865#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24864#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24863#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24862#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24861#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24860#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24859#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24858#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24857#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24856#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24852#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24851#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 24839#L27-4 main_~i~0#1 := 0; 24840#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 25042#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 24911#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 24909#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 24910#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 24914#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 25040#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 25037#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 25035#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 25034#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 25031#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 25029#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 25028#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 25025#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 25023#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 25022#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 25019#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 25017#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 25016#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 25013#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 25011#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 25010#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 25007#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 25005#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 25004#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 25001#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 24999#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 24998#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 24995#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 24993#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 24992#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 24989#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 24987#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 24986#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 24983#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 24981#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 24980#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 24977#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 24975#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 24974#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 24971#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 24969#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 24968#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 24965#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 24963#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 24962#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 24959#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 24957#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 24956#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 24953#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 24951#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 24950#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 24947#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 24945#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 24944#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 24941#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 24939#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 24938#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 24935#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 24933#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 24932#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 24929#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 24927#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 24926#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 24923#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 24921#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 24920#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 24919#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 24918#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 24917#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 24845#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 24833#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 24842#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 24847#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 24906#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 24905#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 24854#L34 [2022-11-02 20:26:06,397 INFO L750 eck$LassoCheckResult]: Loop: 24854#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 24855#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 24853#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 24854#L34 [2022-11-02 20:26:06,397 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:26:06,397 INFO L85 PathProgramCache]: Analyzing trace with hash 791980157, now seen corresponding path program 50 times [2022-11-02 20:26:06,397 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:26:06,398 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1040733192] [2022-11-02 20:26:06,398 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:26:06,398 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:26:06,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:26:06,625 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:26:06,784 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:26:06,879 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:26:06,879 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:26:06,880 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 27 times [2022-11-02 20:26:06,880 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:26:06,880 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [948299130] [2022-11-02 20:26:06,880 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:26:06,880 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:26:06,885 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:26:06,886 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:26:06,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:26:06,891 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:26:06,892 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:26:06,892 INFO L85 PathProgramCache]: Analyzing trace with hash 1625540025, now seen corresponding path program 51 times [2022-11-02 20:26:06,892 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:26:06,892 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [369593987] [2022-11-02 20:26:06,893 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:26:06,893 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:26:06,965 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:26:09,108 INFO L134 CoverageAnalysis]: Checked inductivity of 1677 backedges. 925 proven. 752 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:26:09,108 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 20:26:09,108 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [369593987] [2022-11-02 20:26:09,108 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [369593987] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 20:26:09,108 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [476970440] [2022-11-02 20:26:09,108 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-02 20:26:09,110 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 20:26:09,110 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 20:26:09,112 INFO L229 MonitoredProcess]: Starting monitored process 38 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 20:26:09,123 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (38)] Waiting until timeout for monitored process [2022-11-02 20:26:15,281 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 27 check-sat command(s) [2022-11-02 20:26:15,281 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-02 20:26:15,296 INFO L263 TraceCheckSpWp]: Trace formula consists of 591 conjuncts, 56 conjunts are in the unsatisfiable core [2022-11-02 20:26:15,298 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 20:26:16,959 INFO L134 CoverageAnalysis]: Checked inductivity of 1677 backedges. 1001 proven. 676 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:26:16,959 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 20:26:18,130 INFO L134 CoverageAnalysis]: Checked inductivity of 1677 backedges. 1001 proven. 676 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:26:18,130 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [476970440] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 20:26:18,131 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 20:26:18,131 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [56, 56, 56] total 85 [2022-11-02 20:26:18,131 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1629476619] [2022-11-02 20:26:18,131 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 20:26:18,174 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 20:26:18,174 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 86 interpolants. [2022-11-02 20:26:18,175 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1685, Invalid=5625, Unknown=0, NotChecked=0, Total=7310 [2022-11-02 20:26:18,176 INFO L87 Difference]: Start difference. First operand 220 states and 249 transitions. cyclomatic complexity: 32 Second operand has 86 states, 85 states have (on average 2.611764705882353) internal successors, (222), 86 states have internal predecessors, (222), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:26:19,866 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 20:26:19,867 INFO L93 Difference]: Finished difference Result 713 states and 824 transitions. [2022-11-02 20:26:19,867 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 713 states and 824 transitions. [2022-11-02 20:26:19,870 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-02 20:26:19,872 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 713 states to 396 states and 454 transitions. [2022-11-02 20:26:19,872 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 341 [2022-11-02 20:26:19,873 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 341 [2022-11-02 20:26:19,873 INFO L73 IsDeterministic]: Start isDeterministic. Operand 396 states and 454 transitions. [2022-11-02 20:26:19,873 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-02 20:26:19,873 INFO L218 hiAutomatonCegarLoop]: Abstraction has 396 states and 454 transitions. [2022-11-02 20:26:19,874 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 396 states and 454 transitions. [2022-11-02 20:26:19,877 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 396 to 228. [2022-11-02 20:26:19,877 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 228 states, 228 states have (on average 1.131578947368421) internal successors, (258), 227 states have internal predecessors, (258), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:26:19,878 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 228 states to 228 states and 258 transitions. [2022-11-02 20:26:19,878 INFO L240 hiAutomatonCegarLoop]: Abstraction has 228 states and 258 transitions. [2022-11-02 20:26:19,879 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 58 states. [2022-11-02 20:26:19,879 INFO L428 stractBuchiCegarLoop]: Abstraction has 228 states and 258 transitions. [2022-11-02 20:26:19,879 INFO L335 stractBuchiCegarLoop]: ======== Iteration 29 ============ [2022-11-02 20:26:19,880 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 228 states and 258 transitions. [2022-11-02 20:26:19,881 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-02 20:26:19,881 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 20:26:19,881 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 20:26:19,882 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [27, 27, 27, 26, 26, 1, 1, 1, 1] [2022-11-02 20:26:19,882 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-11-02 20:26:19,883 INFO L748 eck$LassoCheckResult]: Stem: 26710#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 26711#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 26716#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26731#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26732#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26719#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26720#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26786#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26785#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26784#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26783#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26782#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26781#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26780#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26779#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26778#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26777#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26776#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26775#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26774#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26773#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26772#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26771#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26770#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26769#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26768#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26767#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26766#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26765#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26764#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26763#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26762#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26761#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26760#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26759#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26758#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26757#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26756#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26755#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26754#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26753#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26752#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26751#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26750#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26749#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26748#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26747#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26746#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26745#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26744#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26743#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26742#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26741#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26740#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26739#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26735#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26734#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 26721#L27-4 main_~i~0#1 := 0; 26722#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26794#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26795#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26796#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26800#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26799#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26932#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26929#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26927#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26926#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26923#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26921#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26920#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26917#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26915#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26914#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26911#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26909#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26908#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26905#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26903#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26902#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26899#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26897#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26896#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26893#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26891#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26890#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26887#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26885#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26884#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26881#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26879#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26878#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26875#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26873#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26872#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26869#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26867#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26866#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26863#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26861#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26860#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26857#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26855#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26854#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26851#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26849#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26848#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26845#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26843#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26842#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26839#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26837#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26836#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26833#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26831#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26830#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26827#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26825#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26824#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26821#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26819#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26818#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26815#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26813#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26812#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26809#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26807#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26806#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26804#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26803#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26802#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26728#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26715#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26725#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26730#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26791#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26790#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26737#L34 [2022-11-02 20:26:19,883 INFO L750 eck$LassoCheckResult]: Loop: 26737#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26738#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26736#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26737#L34 [2022-11-02 20:26:19,883 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:26:19,883 INFO L85 PathProgramCache]: Analyzing trace with hash -325891465, now seen corresponding path program 52 times [2022-11-02 20:26:19,884 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:26:19,884 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [914306661] [2022-11-02 20:26:19,884 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:26:19,884 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:26:20,058 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:26:20,059 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:26:20,237 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:26:20,253 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:26:20,253 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:26:20,254 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 28 times [2022-11-02 20:26:20,254 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:26:20,254 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1119958141] [2022-11-02 20:26:20,254 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:26:20,254 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:26:20,258 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:26:20,258 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:26:20,260 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:26:20,262 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:26:20,263 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:26:20,263 INFO L85 PathProgramCache]: Analyzing trace with hash -2006505089, now seen corresponding path program 53 times [2022-11-02 20:26:20,263 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:26:20,263 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1012972553] [2022-11-02 20:26:20,263 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:26:20,263 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:26:20,307 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:26:22,295 INFO L134 CoverageAnalysis]: Checked inductivity of 1809 backedges. 1001 proven. 808 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:26:22,295 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 20:26:22,295 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1012972553] [2022-11-02 20:26:22,295 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1012972553] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 20:26:22,295 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1211589482] [2022-11-02 20:26:22,296 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-02 20:26:22,296 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 20:26:22,296 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 20:26:22,302 INFO L229 MonitoredProcess]: Starting monitored process 39 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 20:26:22,310 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (39)] Waiting until timeout for monitored process [2022-11-02 20:26:24,927 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 28 check-sat command(s) [2022-11-02 20:26:24,927 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-02 20:26:24,936 INFO L263 TraceCheckSpWp]: Trace formula consists of 612 conjuncts, 58 conjunts are in the unsatisfiable core [2022-11-02 20:26:24,939 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 20:26:26,657 INFO L134 CoverageAnalysis]: Checked inductivity of 1809 backedges. 1080 proven. 729 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:26:26,657 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 20:26:27,917 INFO L134 CoverageAnalysis]: Checked inductivity of 1809 backedges. 1080 proven. 729 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:26:27,918 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1211589482] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 20:26:27,918 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 20:26:27,918 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [58, 58, 58] total 88 [2022-11-02 20:26:27,918 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [660695240] [2022-11-02 20:26:27,918 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 20:26:27,961 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 20:26:27,962 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 89 interpolants. [2022-11-02 20:26:27,962 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1803, Invalid=6029, Unknown=0, NotChecked=0, Total=7832 [2022-11-02 20:26:27,963 INFO L87 Difference]: Start difference. First operand 228 states and 258 transitions. cyclomatic complexity: 33 Second operand has 89 states, 88 states have (on average 2.6136363636363638) internal successors, (230), 89 states have internal predecessors, (230), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:26:29,626 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 20:26:29,627 INFO L93 Difference]: Finished difference Result 739 states and 854 transitions. [2022-11-02 20:26:29,627 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 739 states and 854 transitions. [2022-11-02 20:26:29,629 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-02 20:26:29,631 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 739 states to 410 states and 470 transitions. [2022-11-02 20:26:29,631 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 353 [2022-11-02 20:26:29,632 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 353 [2022-11-02 20:26:29,632 INFO L73 IsDeterministic]: Start isDeterministic. Operand 410 states and 470 transitions. [2022-11-02 20:26:29,633 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-02 20:26:29,633 INFO L218 hiAutomatonCegarLoop]: Abstraction has 410 states and 470 transitions. [2022-11-02 20:26:29,633 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 410 states and 470 transitions. [2022-11-02 20:26:29,636 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 410 to 236. [2022-11-02 20:26:29,636 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 236 states, 236 states have (on average 1.13135593220339) internal successors, (267), 235 states have internal predecessors, (267), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:26:29,637 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 236 states to 236 states and 267 transitions. [2022-11-02 20:26:29,637 INFO L240 hiAutomatonCegarLoop]: Abstraction has 236 states and 267 transitions. [2022-11-02 20:26:29,638 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 60 states. [2022-11-02 20:26:29,639 INFO L428 stractBuchiCegarLoop]: Abstraction has 236 states and 267 transitions. [2022-11-02 20:26:29,639 INFO L335 stractBuchiCegarLoop]: ======== Iteration 30 ============ [2022-11-02 20:26:29,639 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 236 states and 267 transitions. [2022-11-02 20:26:29,640 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-02 20:26:29,640 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 20:26:29,641 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 20:26:29,645 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [28, 28, 28, 27, 27, 1, 1, 1, 1] [2022-11-02 20:26:29,645 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-11-02 20:26:29,646 INFO L748 eck$LassoCheckResult]: Stem: 28661#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 28662#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 28667#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28681#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28682#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28670#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28671#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28738#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28737#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28736#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28735#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28734#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28733#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28732#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28731#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28730#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28729#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28728#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28727#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28726#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28725#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28724#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28723#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28722#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28721#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28720#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28719#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28718#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28717#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28716#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28715#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28714#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28713#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28712#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28711#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28710#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28709#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28708#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28707#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28706#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28705#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28704#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28703#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28702#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28701#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28700#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28699#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28698#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28697#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28696#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28695#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28694#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28693#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28692#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28691#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28690#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28689#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28685#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28684#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 28672#L27-4 main_~i~0#1 := 0; 28673#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28892#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28748#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28746#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28747#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28751#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28891#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28888#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28886#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28885#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28882#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28880#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28879#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28876#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28874#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28873#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28870#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28868#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28867#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28864#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28862#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28861#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28858#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28856#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28855#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28852#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28850#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28849#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28846#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28844#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28843#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28840#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28838#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28837#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28834#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28832#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28831#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28828#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28826#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28825#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28822#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28820#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28819#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28816#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28814#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28813#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28810#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28808#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28807#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28804#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28802#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28801#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28798#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28796#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28795#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28792#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28790#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28789#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28786#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28784#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28783#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28780#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28778#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28777#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28774#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28772#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28771#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28768#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28766#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28765#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28762#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28760#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28759#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28757#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28755#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28754#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28678#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28666#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28675#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28680#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28743#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28742#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28687#L34 [2022-11-02 20:26:29,646 INFO L750 eck$LassoCheckResult]: Loop: 28687#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28688#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28686#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28687#L34 [2022-11-02 20:26:29,646 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:26:29,646 INFO L85 PathProgramCache]: Analyzing trace with hash 1979902849, now seen corresponding path program 54 times [2022-11-02 20:26:29,647 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:26:29,647 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [497857021] [2022-11-02 20:26:29,647 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:26:29,647 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:26:29,841 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:26:29,842 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:26:30,033 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:26:30,056 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:26:30,056 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:26:30,057 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 29 times [2022-11-02 20:26:30,057 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:26:30,057 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1047552814] [2022-11-02 20:26:30,057 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:26:30,057 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:26:30,061 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:26:30,061 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:26:30,062 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:26:30,065 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:26:30,065 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:26:30,065 INFO L85 PathProgramCache]: Analyzing trace with hash 499938357, now seen corresponding path program 55 times [2022-11-02 20:26:30,065 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:26:30,066 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [471236022] [2022-11-02 20:26:30,066 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:26:30,066 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:26:30,162 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:26:32,205 INFO L134 CoverageAnalysis]: Checked inductivity of 1946 backedges. 1080 proven. 866 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:26:32,206 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 20:26:32,206 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [471236022] [2022-11-02 20:26:32,206 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [471236022] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 20:26:32,206 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1957010528] [2022-11-02 20:26:32,206 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-11-02 20:26:32,206 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 20:26:32,206 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 20:26:32,208 INFO L229 MonitoredProcess]: Starting monitored process 40 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 20:26:32,210 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (40)] Waiting until timeout for monitored process [2022-11-02 20:26:32,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:26:32,473 INFO L263 TraceCheckSpWp]: Trace formula consists of 633 conjuncts, 60 conjunts are in the unsatisfiable core [2022-11-02 20:26:32,477 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 20:26:34,236 INFO L134 CoverageAnalysis]: Checked inductivity of 1946 backedges. 1162 proven. 784 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:26:34,237 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 20:26:35,568 INFO L134 CoverageAnalysis]: Checked inductivity of 1946 backedges. 1162 proven. 784 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:26:35,569 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1957010528] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 20:26:35,569 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 20:26:35,569 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [60, 60, 60] total 91 [2022-11-02 20:26:35,569 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [795432844] [2022-11-02 20:26:35,570 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 20:26:35,610 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 20:26:35,611 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 92 interpolants. [2022-11-02 20:26:35,612 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1925, Invalid=6447, Unknown=0, NotChecked=0, Total=8372 [2022-11-02 20:26:35,612 INFO L87 Difference]: Start difference. First operand 236 states and 267 transitions. cyclomatic complexity: 34 Second operand has 92 states, 91 states have (on average 2.6153846153846154) internal successors, (238), 92 states have internal predecessors, (238), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:26:37,491 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 20:26:37,492 INFO L93 Difference]: Finished difference Result 765 states and 884 transitions. [2022-11-02 20:26:37,492 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 765 states and 884 transitions. [2022-11-02 20:26:37,495 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-02 20:26:37,497 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 765 states to 424 states and 486 transitions. [2022-11-02 20:26:37,498 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 365 [2022-11-02 20:26:37,498 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 365 [2022-11-02 20:26:37,498 INFO L73 IsDeterministic]: Start isDeterministic. Operand 424 states and 486 transitions. [2022-11-02 20:26:37,499 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-02 20:26:37,499 INFO L218 hiAutomatonCegarLoop]: Abstraction has 424 states and 486 transitions. [2022-11-02 20:26:37,500 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 424 states and 486 transitions. [2022-11-02 20:26:37,503 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 424 to 244. [2022-11-02 20:26:37,504 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 244 states, 244 states have (on average 1.1311475409836065) internal successors, (276), 243 states have internal predecessors, (276), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:26:37,504 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 244 states to 244 states and 276 transitions. [2022-11-02 20:26:37,504 INFO L240 hiAutomatonCegarLoop]: Abstraction has 244 states and 276 transitions. [2022-11-02 20:26:37,505 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 62 states. [2022-11-02 20:26:37,505 INFO L428 stractBuchiCegarLoop]: Abstraction has 244 states and 276 transitions. [2022-11-02 20:26:37,506 INFO L335 stractBuchiCegarLoop]: ======== Iteration 31 ============ [2022-11-02 20:26:37,506 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 244 states and 276 transitions. [2022-11-02 20:26:37,507 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-02 20:26:37,507 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 20:26:37,507 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 20:26:37,508 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [29, 29, 29, 28, 28, 1, 1, 1, 1] [2022-11-02 20:26:37,509 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-11-02 20:26:37,509 INFO L748 eck$LassoCheckResult]: Stem: 30681#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 30682#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 30687#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30702#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30703#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30690#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30691#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30761#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30760#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30759#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30758#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30757#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30756#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30755#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30754#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30753#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30752#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30751#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30750#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30749#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30748#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30747#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30746#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30745#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30744#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30743#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30742#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30741#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30740#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30739#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30738#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30737#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30736#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30735#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30734#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30733#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30732#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30731#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30730#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30729#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30728#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30727#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30726#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30725#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30724#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30723#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30722#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30721#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30720#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30719#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30718#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30717#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30716#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30715#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30714#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30713#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30712#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30711#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30710#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30706#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30705#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 30692#L27-4 main_~i~0#1 := 0; 30693#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30769#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30770#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30771#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30775#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30774#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30919#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30916#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30914#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30913#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30910#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30908#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30907#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30904#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30902#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30901#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30898#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30896#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30895#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30892#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30890#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30889#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30886#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30884#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30883#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30880#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30878#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30877#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30874#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30872#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30871#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30868#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30866#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30865#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30862#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30860#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30859#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30856#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30854#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30853#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30850#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30848#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30847#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30844#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30842#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30841#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30838#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30836#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30835#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30832#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30830#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30829#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30826#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30824#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30823#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30820#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30818#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30817#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30814#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30812#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30811#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30808#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30806#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30805#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30802#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30800#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30799#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30796#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30794#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30793#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30790#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30788#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30787#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30784#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30782#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30781#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30779#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30778#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30777#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30699#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30686#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30696#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30701#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30766#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30765#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30708#L34 [2022-11-02 20:26:37,509 INFO L750 eck$LassoCheckResult]: Loop: 30708#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30709#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30707#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30708#L34 [2022-11-02 20:26:37,510 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:26:37,510 INFO L85 PathProgramCache]: Analyzing trace with hash -2002541709, now seen corresponding path program 56 times [2022-11-02 20:26:37,510 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:26:37,510 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1175761710] [2022-11-02 20:26:37,510 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:26:37,510 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:26:37,778 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:26:37,778 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:26:37,969 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:26:37,987 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:26:37,988 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:26:37,988 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 30 times [2022-11-02 20:26:37,988 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:26:37,988 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [904304357] [2022-11-02 20:26:37,989 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:26:37,989 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:26:37,992 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:26:37,993 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:26:37,994 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:26:37,997 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:26:37,998 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:26:37,998 INFO L85 PathProgramCache]: Analyzing trace with hash -624271613, now seen corresponding path program 57 times [2022-11-02 20:26:37,998 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:26:37,998 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [466548575] [2022-11-02 20:26:37,998 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:26:37,999 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:26:38,047 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:26:40,271 INFO L134 CoverageAnalysis]: Checked inductivity of 2088 backedges. 1162 proven. 926 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:26:40,271 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 20:26:40,271 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [466548575] [2022-11-02 20:26:40,271 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [466548575] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 20:26:40,271 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [363203513] [2022-11-02 20:26:40,271 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-02 20:26:40,271 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 20:26:40,272 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 20:26:40,274 INFO L229 MonitoredProcess]: Starting monitored process 41 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 20:26:40,274 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (41)] Waiting until timeout for monitored process [2022-11-02 20:26:55,711 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 30 check-sat command(s) [2022-11-02 20:26:55,711 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-02 20:26:55,738 INFO L263 TraceCheckSpWp]: Trace formula consists of 654 conjuncts, 62 conjunts are in the unsatisfiable core [2022-11-02 20:26:55,741 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 20:26:57,768 INFO L134 CoverageAnalysis]: Checked inductivity of 2088 backedges. 1247 proven. 841 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:26:57,768 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 20:26:59,274 INFO L134 CoverageAnalysis]: Checked inductivity of 2088 backedges. 1247 proven. 841 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:26:59,274 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [363203513] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 20:26:59,274 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 20:26:59,274 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [62, 62, 62] total 94 [2022-11-02 20:26:59,274 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1833161477] [2022-11-02 20:26:59,274 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 20:26:59,316 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 20:26:59,317 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 95 interpolants. [2022-11-02 20:26:59,318 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=2051, Invalid=6879, Unknown=0, NotChecked=0, Total=8930 [2022-11-02 20:26:59,319 INFO L87 Difference]: Start difference. First operand 244 states and 276 transitions. cyclomatic complexity: 35 Second operand has 95 states, 94 states have (on average 2.617021276595745) internal successors, (246), 95 states have internal predecessors, (246), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:27:01,287 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 20:27:01,287 INFO L93 Difference]: Finished difference Result 791 states and 914 transitions. [2022-11-02 20:27:01,287 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 791 states and 914 transitions. [2022-11-02 20:27:01,289 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-02 20:27:01,291 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 791 states to 438 states and 502 transitions. [2022-11-02 20:27:01,291 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 377 [2022-11-02 20:27:01,292 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 377 [2022-11-02 20:27:01,292 INFO L73 IsDeterministic]: Start isDeterministic. Operand 438 states and 502 transitions. [2022-11-02 20:27:01,293 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-02 20:27:01,293 INFO L218 hiAutomatonCegarLoop]: Abstraction has 438 states and 502 transitions. [2022-11-02 20:27:01,293 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 438 states and 502 transitions. [2022-11-02 20:27:01,307 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 438 to 252. [2022-11-02 20:27:01,308 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 252 states, 252 states have (on average 1.130952380952381) internal successors, (285), 251 states have internal predecessors, (285), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:27:01,309 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 252 states to 252 states and 285 transitions. [2022-11-02 20:27:01,309 INFO L240 hiAutomatonCegarLoop]: Abstraction has 252 states and 285 transitions. [2022-11-02 20:27:01,309 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 64 states. [2022-11-02 20:27:01,309 INFO L428 stractBuchiCegarLoop]: Abstraction has 252 states and 285 transitions. [2022-11-02 20:27:01,310 INFO L335 stractBuchiCegarLoop]: ======== Iteration 32 ============ [2022-11-02 20:27:01,310 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 252 states and 285 transitions. [2022-11-02 20:27:01,311 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-02 20:27:01,311 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 20:27:01,311 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 20:27:01,312 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [30, 30, 30, 29, 29, 1, 1, 1, 1] [2022-11-02 20:27:01,312 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-11-02 20:27:01,313 INFO L748 eck$LassoCheckResult]: Stem: 32770#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 32771#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 32776#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32790#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32791#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32779#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32780#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32851#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32850#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32849#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32848#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32847#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32846#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32845#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32844#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32843#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32842#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32841#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32840#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32839#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32838#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32837#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32836#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32835#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32834#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32833#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32832#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32831#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32830#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32829#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32828#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32827#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32826#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32825#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32824#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32823#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32822#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32821#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32820#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32819#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32818#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32817#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32816#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32815#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32814#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32813#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32812#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32811#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32810#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32809#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32808#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32807#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32806#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32805#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32804#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32803#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32802#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32801#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32800#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32799#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32798#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32794#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32793#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 32781#L27-4 main_~i~0#1 := 0; 32782#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 33016#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32861#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32859#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32860#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32864#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 33014#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 33011#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 33009#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 33008#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 33005#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 33003#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 33002#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32999#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32997#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32996#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32993#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32991#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32990#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32987#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32985#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32984#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32981#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32979#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32978#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32975#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32973#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32972#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32969#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32967#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32966#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32963#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32961#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32960#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32957#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32955#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32954#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32951#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32949#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32948#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32945#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32943#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32942#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32939#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32937#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32936#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32933#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32931#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32930#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32927#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32925#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32924#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32921#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32919#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32918#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32915#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32913#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32912#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32909#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32907#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32906#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32903#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32901#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32900#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32897#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32895#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32894#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32891#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32889#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32888#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32885#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32883#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32882#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32879#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32877#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32876#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32873#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32871#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32870#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32869#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32868#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32867#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32787#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32775#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32784#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32789#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32856#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32855#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32796#L34 [2022-11-02 20:27:01,313 INFO L750 eck$LassoCheckResult]: Loop: 32796#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32797#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32795#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32796#L34 [2022-11-02 20:27:01,313 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:27:01,314 INFO L85 PathProgramCache]: Analyzing trace with hash 1004865157, now seen corresponding path program 58 times [2022-11-02 20:27:01,314 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:27:01,314 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [18698338] [2022-11-02 20:27:01,314 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:27:01,314 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:27:01,541 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:27:01,542 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:27:01,791 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:27:01,807 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:27:01,807 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:27:01,807 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 31 times [2022-11-02 20:27:01,807 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:27:01,808 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1221626651] [2022-11-02 20:27:01,808 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:27:01,808 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:27:01,812 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:27:01,812 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:27:01,813 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:27:01,816 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:27:01,817 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:27:01,817 INFO L85 PathProgramCache]: Analyzing trace with hash 15878833, now seen corresponding path program 59 times [2022-11-02 20:27:01,817 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:27:01,817 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [456412021] [2022-11-02 20:27:01,817 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:27:01,818 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:27:01,866 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:27:04,334 INFO L134 CoverageAnalysis]: Checked inductivity of 2235 backedges. 1247 proven. 988 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:27:04,335 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 20:27:04,335 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [456412021] [2022-11-02 20:27:04,335 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [456412021] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 20:27:04,335 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2142612278] [2022-11-02 20:27:04,335 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-02 20:27:04,335 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 20:27:04,335 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 20:27:04,337 INFO L229 MonitoredProcess]: Starting monitored process 42 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 20:27:04,338 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (42)] Waiting until timeout for monitored process [2022-11-02 20:27:07,582 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 31 check-sat command(s) [2022-11-02 20:27:07,582 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-02 20:27:07,593 INFO L263 TraceCheckSpWp]: Trace formula consists of 675 conjuncts, 64 conjunts are in the unsatisfiable core [2022-11-02 20:27:07,595 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 20:27:09,660 INFO L134 CoverageAnalysis]: Checked inductivity of 2235 backedges. 1335 proven. 900 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:27:09,660 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 20:27:11,203 INFO L134 CoverageAnalysis]: Checked inductivity of 2235 backedges. 1335 proven. 900 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:27:11,203 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2142612278] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 20:27:11,203 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 20:27:11,203 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [64, 64, 64] total 97 [2022-11-02 20:27:11,204 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [484778206] [2022-11-02 20:27:11,204 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 20:27:11,256 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 20:27:11,257 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 98 interpolants. [2022-11-02 20:27:11,258 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=2181, Invalid=7325, Unknown=0, NotChecked=0, Total=9506 [2022-11-02 20:27:11,258 INFO L87 Difference]: Start difference. First operand 252 states and 285 transitions. cyclomatic complexity: 36 Second operand has 98 states, 97 states have (on average 2.618556701030928) internal successors, (254), 98 states have internal predecessors, (254), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:27:13,521 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 20:27:13,522 INFO L93 Difference]: Finished difference Result 817 states and 944 transitions. [2022-11-02 20:27:13,522 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 817 states and 944 transitions. [2022-11-02 20:27:13,524 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-02 20:27:13,527 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 817 states to 452 states and 518 transitions. [2022-11-02 20:27:13,527 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 389 [2022-11-02 20:27:13,527 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 389 [2022-11-02 20:27:13,528 INFO L73 IsDeterministic]: Start isDeterministic. Operand 452 states and 518 transitions. [2022-11-02 20:27:13,529 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-02 20:27:13,529 INFO L218 hiAutomatonCegarLoop]: Abstraction has 452 states and 518 transitions. [2022-11-02 20:27:13,529 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 452 states and 518 transitions. [2022-11-02 20:27:13,534 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 452 to 260. [2022-11-02 20:27:13,534 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 260 states, 260 states have (on average 1.1307692307692307) internal successors, (294), 259 states have internal predecessors, (294), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:27:13,535 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 260 states to 260 states and 294 transitions. [2022-11-02 20:27:13,536 INFO L240 hiAutomatonCegarLoop]: Abstraction has 260 states and 294 transitions. [2022-11-02 20:27:13,536 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 66 states. [2022-11-02 20:27:13,537 INFO L428 stractBuchiCegarLoop]: Abstraction has 260 states and 294 transitions. [2022-11-02 20:27:13,537 INFO L335 stractBuchiCegarLoop]: ======== Iteration 33 ============ [2022-11-02 20:27:13,537 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 260 states and 294 transitions. [2022-11-02 20:27:13,539 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-02 20:27:13,539 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 20:27:13,539 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 20:27:13,540 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [31, 31, 31, 30, 30, 1, 1, 1, 1] [2022-11-02 20:27:13,540 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-11-02 20:27:13,541 INFO L748 eck$LassoCheckResult]: Stem: 34928#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 34929#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 34934#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 34949#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 34950#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 34937#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 34938#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 35012#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 35011#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 35010#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 35009#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 35008#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 35007#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 35006#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 35005#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 35004#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 35003#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 35002#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 35001#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 35000#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 34999#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 34998#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 34997#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 34996#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 34995#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 34994#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 34993#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 34992#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 34991#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 34990#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 34989#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 34988#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 34987#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 34986#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 34985#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 34984#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 34983#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 34982#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 34981#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 34980#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 34979#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 34978#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 34977#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 34976#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 34975#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 34974#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 34973#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 34972#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 34971#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 34970#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 34969#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 34968#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 34967#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 34966#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 34965#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 34964#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 34963#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 34962#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 34961#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 34960#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 34959#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 34958#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 34957#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 34953#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 34952#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 34939#L27-4 main_~i~0#1 := 0; 34940#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35020#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35021#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35022#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35026#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35025#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35182#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35179#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35177#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35176#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35173#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35171#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35170#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35167#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35165#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35164#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35161#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35159#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35158#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35155#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35153#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35152#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35149#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35147#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35146#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35143#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35141#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35140#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35137#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35135#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35134#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35131#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35129#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35128#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35125#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35123#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35122#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35119#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35117#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35116#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35113#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35111#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35110#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35107#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35105#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35104#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35101#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35099#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35098#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35095#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35093#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35092#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35089#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35087#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35086#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35083#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35081#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35080#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35077#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35075#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35074#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35071#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35069#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35068#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35065#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35063#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35062#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35059#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35057#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35056#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35053#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35051#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35050#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35047#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35045#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35044#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35041#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35039#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35038#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35035#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35033#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35032#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35030#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35029#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35028#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 34946#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 34933#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 34943#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 34948#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35017#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35016#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 34955#L34 [2022-11-02 20:27:13,541 INFO L750 eck$LassoCheckResult]: Loop: 34955#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 34956#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 34954#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 34955#L34 [2022-11-02 20:27:13,542 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:27:13,542 INFO L85 PathProgramCache]: Analyzing trace with hash 389940335, now seen corresponding path program 60 times [2022-11-02 20:27:13,542 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:27:13,542 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1607827598] [2022-11-02 20:27:13,543 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:27:13,543 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:27:13,861 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:27:13,862 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:27:14,190 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:27:14,213 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:27:14,213 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:27:14,213 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 32 times [2022-11-02 20:27:14,214 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:27:14,214 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [117359948] [2022-11-02 20:27:14,216 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:27:14,220 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:27:14,225 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:27:14,226 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:27:14,228 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:27:14,232 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:27:14,232 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:27:14,233 INFO L85 PathProgramCache]: Analyzing trace with hash -1173975929, now seen corresponding path program 61 times [2022-11-02 20:27:14,233 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:27:14,233 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1261527447] [2022-11-02 20:27:14,233 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:27:14,234 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:27:14,297 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:27:17,017 INFO L134 CoverageAnalysis]: Checked inductivity of 2387 backedges. 1335 proven. 1052 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:27:17,017 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 20:27:17,017 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1261527447] [2022-11-02 20:27:17,017 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1261527447] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 20:27:17,018 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [55004514] [2022-11-02 20:27:17,018 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-11-02 20:27:17,018 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 20:27:17,018 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 20:27:17,019 INFO L229 MonitoredProcess]: Starting monitored process 43 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 20:27:17,020 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (43)] Waiting until timeout for monitored process [2022-11-02 20:27:17,317 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:27:17,322 INFO L263 TraceCheckSpWp]: Trace formula consists of 696 conjuncts, 66 conjunts are in the unsatisfiable core [2022-11-02 20:27:17,324 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 20:27:19,540 INFO L134 CoverageAnalysis]: Checked inductivity of 2387 backedges. 1426 proven. 961 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:27:19,540 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 20:27:21,349 INFO L134 CoverageAnalysis]: Checked inductivity of 2387 backedges. 1426 proven. 961 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:27:21,350 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [55004514] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 20:27:21,350 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 20:27:21,350 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [66, 66, 66] total 100 [2022-11-02 20:27:21,350 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [102014611] [2022-11-02 20:27:21,350 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 20:27:21,404 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 20:27:21,406 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 101 interpolants. [2022-11-02 20:27:21,407 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=2315, Invalid=7785, Unknown=0, NotChecked=0, Total=10100 [2022-11-02 20:27:21,408 INFO L87 Difference]: Start difference. First operand 260 states and 294 transitions. cyclomatic complexity: 37 Second operand has 101 states, 100 states have (on average 2.62) internal successors, (262), 101 states have internal predecessors, (262), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:27:23,891 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 20:27:23,892 INFO L93 Difference]: Finished difference Result 843 states and 974 transitions. [2022-11-02 20:27:23,892 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 843 states and 974 transitions. [2022-11-02 20:27:23,895 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-02 20:27:23,896 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 843 states to 466 states and 534 transitions. [2022-11-02 20:27:23,896 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 401 [2022-11-02 20:27:23,897 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 401 [2022-11-02 20:27:23,897 INFO L73 IsDeterministic]: Start isDeterministic. Operand 466 states and 534 transitions. [2022-11-02 20:27:23,898 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-02 20:27:23,898 INFO L218 hiAutomatonCegarLoop]: Abstraction has 466 states and 534 transitions. [2022-11-02 20:27:23,899 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 466 states and 534 transitions. [2022-11-02 20:27:23,904 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 466 to 268. [2022-11-02 20:27:23,904 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 268 states, 268 states have (on average 1.1305970149253732) internal successors, (303), 267 states have internal predecessors, (303), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:27:23,905 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 268 states to 268 states and 303 transitions. [2022-11-02 20:27:23,905 INFO L240 hiAutomatonCegarLoop]: Abstraction has 268 states and 303 transitions. [2022-11-02 20:27:23,908 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 68 states. [2022-11-02 20:27:23,909 INFO L428 stractBuchiCegarLoop]: Abstraction has 268 states and 303 transitions. [2022-11-02 20:27:23,909 INFO L335 stractBuchiCegarLoop]: ======== Iteration 34 ============ [2022-11-02 20:27:23,909 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 268 states and 303 transitions. [2022-11-02 20:27:23,911 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-02 20:27:23,911 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 20:27:23,911 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 20:27:23,912 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [32, 32, 32, 31, 31, 1, 1, 1, 1] [2022-11-02 20:27:23,912 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-11-02 20:27:23,913 INFO L748 eck$LassoCheckResult]: Stem: 37155#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 37156#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 37161#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37175#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37176#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37164#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37165#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37240#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37239#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37238#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37237#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37236#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37235#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37234#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37233#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37232#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37231#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37230#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37229#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37228#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37227#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37226#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37225#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37224#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37223#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37222#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37221#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37220#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37219#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37218#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37217#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37216#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37215#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37214#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37213#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37212#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37211#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37210#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37209#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37208#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37207#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37206#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37205#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37204#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37203#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37202#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37201#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37200#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37199#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37198#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37197#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37196#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37195#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37194#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37193#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37192#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37191#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37190#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37189#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37188#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37187#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37186#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37185#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37184#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37183#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37179#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37178#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 37166#L27-4 main_~i~0#1 := 0; 37167#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37418#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37250#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37248#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37249#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37253#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37417#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37414#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37412#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37411#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37408#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37406#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37405#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37402#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37400#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37399#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37396#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37394#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37393#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37390#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37388#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37387#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37384#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37382#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37381#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37378#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37376#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37375#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37372#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37370#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37369#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37366#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37364#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37363#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37360#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37358#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37357#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37354#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37352#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37351#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37348#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37346#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37345#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37342#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37340#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37339#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37336#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37334#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37333#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37330#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37328#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37327#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37324#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37322#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37321#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37318#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37316#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37315#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37312#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37310#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37309#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37306#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37304#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37303#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37300#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37298#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37297#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37294#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37292#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37291#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37288#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37286#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37285#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37282#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37280#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37279#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37276#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37274#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37273#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37270#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37268#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37267#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37264#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37262#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37261#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37259#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37257#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37256#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37172#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37160#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37169#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37174#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37245#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37244#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37181#L34 [2022-11-02 20:27:23,913 INFO L750 eck$LassoCheckResult]: Loop: 37181#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37182#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37180#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37181#L34 [2022-11-02 20:27:23,914 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:27:23,914 INFO L85 PathProgramCache]: Analyzing trace with hash -815842935, now seen corresponding path program 62 times [2022-11-02 20:27:23,914 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:27:23,915 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [806829957] [2022-11-02 20:27:23,915 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:27:23,915 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:27:24,323 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:27:24,324 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:27:24,599 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:27:24,621 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:27:24,621 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:27:24,621 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 33 times [2022-11-02 20:27:24,622 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:27:24,622 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2082847832] [2022-11-02 20:27:24,622 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:27:24,622 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:27:24,627 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:27:24,628 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:27:24,629 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:27:24,633 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:27:24,633 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:27:24,633 INFO L85 PathProgramCache]: Analyzing trace with hash 443091245, now seen corresponding path program 63 times [2022-11-02 20:27:24,634 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:27:24,634 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1491126873] [2022-11-02 20:27:24,634 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:27:24,634 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:27:24,765 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-02 20:27:27,901 INFO L134 CoverageAnalysis]: Checked inductivity of 2544 backedges. 1426 proven. 1118 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:27:27,902 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-02 20:27:27,902 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1491126873] [2022-11-02 20:27:27,902 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1491126873] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-02 20:27:27,902 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [298801934] [2022-11-02 20:27:27,902 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-02 20:27:27,903 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-02 20:27:27,903 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 [2022-11-02 20:27:27,910 INFO L229 MonitoredProcess]: Starting monitored process 44 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-02 20:27:27,942 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_04505547-1e86-4a57-b18f-ed1c3af9fa76/bin/uautomizer-Dbtcem3rbc/z3 -smt2 -in SMTLIB2_COMPLIANT=true (44)] Waiting until timeout for monitored process [2022-11-02 20:27:41,613 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 33 check-sat command(s) [2022-11-02 20:27:41,613 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-02 20:27:41,633 INFO L263 TraceCheckSpWp]: Trace formula consists of 717 conjuncts, 68 conjunts are in the unsatisfiable core [2022-11-02 20:27:41,635 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-02 20:27:43,763 INFO L134 CoverageAnalysis]: Checked inductivity of 2544 backedges. 1520 proven. 1024 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:27:43,763 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-02 20:27:45,496 INFO L134 CoverageAnalysis]: Checked inductivity of 2544 backedges. 1520 proven. 1024 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-02 20:27:45,496 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [298801934] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-02 20:27:45,496 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-02 20:27:45,496 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [68, 68, 68] total 103 [2022-11-02 20:27:45,496 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [435217848] [2022-11-02 20:27:45,497 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-02 20:27:45,548 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-02 20:27:45,549 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 104 interpolants. [2022-11-02 20:27:45,550 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=2453, Invalid=8259, Unknown=0, NotChecked=0, Total=10712 [2022-11-02 20:27:45,550 INFO L87 Difference]: Start difference. First operand 268 states and 303 transitions. cyclomatic complexity: 38 Second operand has 104 states, 103 states have (on average 2.621359223300971) internal successors, (270), 104 states have internal predecessors, (270), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:27:47,734 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-02 20:27:47,735 INFO L93 Difference]: Finished difference Result 869 states and 1004 transitions. [2022-11-02 20:27:47,735 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 869 states and 1004 transitions. [2022-11-02 20:27:47,739 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-02 20:27:47,740 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 869 states to 480 states and 550 transitions. [2022-11-02 20:27:47,741 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 413 [2022-11-02 20:27:47,741 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 413 [2022-11-02 20:27:47,741 INFO L73 IsDeterministic]: Start isDeterministic. Operand 480 states and 550 transitions. [2022-11-02 20:27:47,742 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-02 20:27:47,742 INFO L218 hiAutomatonCegarLoop]: Abstraction has 480 states and 550 transitions. [2022-11-02 20:27:47,743 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 480 states and 550 transitions. [2022-11-02 20:27:47,747 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 480 to 276. [2022-11-02 20:27:47,747 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 276 states, 276 states have (on average 1.1304347826086956) internal successors, (312), 275 states have internal predecessors, (312), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-02 20:27:47,748 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 276 states to 276 states and 312 transitions. [2022-11-02 20:27:47,748 INFO L240 hiAutomatonCegarLoop]: Abstraction has 276 states and 312 transitions. [2022-11-02 20:27:47,754 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 70 states. [2022-11-02 20:27:47,755 INFO L428 stractBuchiCegarLoop]: Abstraction has 276 states and 312 transitions. [2022-11-02 20:27:47,755 INFO L335 stractBuchiCegarLoop]: ======== Iteration 35 ============ [2022-11-02 20:27:47,755 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 276 states and 312 transitions. [2022-11-02 20:27:47,757 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-02 20:27:47,758 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-02 20:27:47,758 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-02 20:27:47,759 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [33, 33, 33, 32, 32, 1, 1, 1, 1] [2022-11-02 20:27:47,759 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-11-02 20:27:47,759 INFO L748 eck$LassoCheckResult]: Stem: 39451#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 39452#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 39457#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39472#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39473#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39460#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39461#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39539#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39538#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39537#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39536#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39535#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39534#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39533#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39532#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39531#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39530#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39529#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39528#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39527#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39526#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39525#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39524#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39523#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39522#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39521#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39520#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39519#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39518#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39517#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39516#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39515#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39514#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39513#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39512#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39511#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39510#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39509#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39508#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39507#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39506#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39505#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39504#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39503#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39502#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39501#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39500#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39499#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39498#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39497#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39496#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39495#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39494#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39493#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39492#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39491#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39490#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39489#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39488#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39487#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39486#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39485#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39484#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39483#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39482#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39481#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39480#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39476#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39475#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 39462#L27-4 main_~i~0#1 := 0; 39463#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39547#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39548#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39549#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39553#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39552#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39721#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39718#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39716#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39715#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39712#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39710#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39709#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39706#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39704#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39703#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39700#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39698#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39697#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39694#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39692#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39691#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39688#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39686#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39685#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39682#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39680#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39679#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39676#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39674#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39673#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39670#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39668#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39667#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39664#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39662#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39661#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39658#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39656#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39655#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39652#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39650#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39649#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39646#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39644#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39643#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39640#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39638#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39637#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39634#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39632#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39631#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39628#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39626#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39625#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39622#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39620#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39619#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39616#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39614#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39613#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39610#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39608#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39607#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39604#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39602#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39601#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39598#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39596#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39595#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39592#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39590#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39589#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39586#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39584#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39583#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39580#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39578#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39577#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39574#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39572#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39571#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39568#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39566#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39565#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39562#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39560#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39559#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39557#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39556#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39555#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39469#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39456#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39466#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39471#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39544#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39543#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39478#L34 [2022-11-02 20:27:47,760 INFO L750 eck$LassoCheckResult]: Loop: 39478#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39479#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39477#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39478#L34 [2022-11-02 20:27:47,760 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:27:47,760 INFO L85 PathProgramCache]: Analyzing trace with hash -706859669, now seen corresponding path program 64 times [2022-11-02 20:27:47,760 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:27:47,761 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [498311448] [2022-11-02 20:27:47,761 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:27:47,761 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:27:47,978 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:27:47,978 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:27:48,229 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:27:48,246 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:27:48,247 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:27:48,247 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 34 times [2022-11-02 20:27:48,247 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:27:48,247 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [521662397] [2022-11-02 20:27:48,248 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:27:48,248 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:27:48,252 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:27:48,252 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-02 20:27:48,254 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-02 20:27:48,257 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-02 20:27:48,257 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-02 20:27:48,257 INFO L85 PathProgramCache]: Analyzing trace with hash 168292875, now seen corresponding path program 65 times [2022-11-02 20:27:48,257 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-02 20:27:48,258 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1451786863] [2022-11-02 20:27:48,258 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-02 20:27:48,258 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-02 20:27:48,315 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat