./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/termination-crafted-lit/Urban-WST2013-Fig2-modified1000.c --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version e04fb08f Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21e01fdd-cc36-4b11-ab5f-0d9093cc2036/bin/uautomizer-tPACEb0tL8/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21e01fdd-cc36-4b11-ab5f-0d9093cc2036/bin/uautomizer-tPACEb0tL8/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21e01fdd-cc36-4b11-ab5f-0d9093cc2036/bin/uautomizer-tPACEb0tL8/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21e01fdd-cc36-4b11-ab5f-0d9093cc2036/bin/uautomizer-tPACEb0tL8/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/termination-crafted-lit/Urban-WST2013-Fig2-modified1000.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21e01fdd-cc36-4b11-ab5f-0d9093cc2036/bin/uautomizer-tPACEb0tL8/config/svcomp-Termination-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21e01fdd-cc36-4b11-ab5f-0d9093cc2036/bin/uautomizer-tPACEb0tL8 --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 0b3c6d5b6497aa5ff0eb68154ec5345da59cc3565c3dc280e241d196cfa0cbf4 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-e04fb08 [2022-11-16 11:33:41,742 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-11-16 11:33:41,745 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-11-16 11:33:41,767 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-11-16 11:33:41,768 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-11-16 11:33:41,769 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-11-16 11:33:41,771 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-11-16 11:33:41,773 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-11-16 11:33:41,775 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-11-16 11:33:41,776 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-11-16 11:33:41,777 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-11-16 11:33:41,779 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-11-16 11:33:41,779 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-11-16 11:33:41,781 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-11-16 11:33:41,782 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-11-16 11:33:41,784 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-11-16 11:33:41,785 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-11-16 11:33:41,786 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-11-16 11:33:41,788 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-11-16 11:33:41,791 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-11-16 11:33:41,793 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-11-16 11:33:41,802 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-11-16 11:33:41,803 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-11-16 11:33:41,807 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-11-16 11:33:41,811 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-11-16 11:33:41,817 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-11-16 11:33:41,817 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-11-16 11:33:41,818 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-11-16 11:33:41,819 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-11-16 11:33:41,821 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-11-16 11:33:41,822 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-11-16 11:33:41,823 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-11-16 11:33:41,825 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-11-16 11:33:41,827 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-11-16 11:33:41,828 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-11-16 11:33:41,829 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-11-16 11:33:41,831 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-11-16 11:33:41,831 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-11-16 11:33:41,831 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-11-16 11:33:41,832 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-11-16 11:33:41,833 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-11-16 11:33:41,834 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21e01fdd-cc36-4b11-ab5f-0d9093cc2036/bin/uautomizer-tPACEb0tL8/config/svcomp-Termination-64bit-Automizer_Default.epf [2022-11-16 11:33:41,882 INFO L113 SettingsManager]: Loading preferences was successful [2022-11-16 11:33:41,883 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-11-16 11:33:41,884 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-11-16 11:33:41,884 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-11-16 11:33:41,886 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-11-16 11:33:41,886 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-11-16 11:33:41,886 INFO L138 SettingsManager]: * Use SBE=true [2022-11-16 11:33:41,887 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-11-16 11:33:41,887 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-11-16 11:33:41,887 INFO L138 SettingsManager]: * Use old map elimination=false [2022-11-16 11:33:41,889 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-11-16 11:33:41,889 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-11-16 11:33:41,889 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-11-16 11:33:41,890 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-11-16 11:33:41,890 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-11-16 11:33:41,890 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-11-16 11:33:41,891 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-11-16 11:33:41,891 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-11-16 11:33:41,891 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-11-16 11:33:41,891 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-11-16 11:33:41,892 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-11-16 11:33:41,892 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-11-16 11:33:41,892 INFO L138 SettingsManager]: * Use constant arrays=true [2022-11-16 11:33:41,895 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-11-16 11:33:41,895 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-11-16 11:33:41,895 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-11-16 11:33:41,896 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-11-16 11:33:41,896 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-11-16 11:33:41,897 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-11-16 11:33:41,898 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21e01fdd-cc36-4b11-ab5f-0d9093cc2036/bin/uautomizer-tPACEb0tL8/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21e01fdd-cc36-4b11-ab5f-0d9093cc2036/bin/uautomizer-tPACEb0tL8 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 0b3c6d5b6497aa5ff0eb68154ec5345da59cc3565c3dc280e241d196cfa0cbf4 [2022-11-16 11:33:42,196 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-11-16 11:33:42,222 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-11-16 11:33:42,225 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-11-16 11:33:42,226 INFO L271 PluginConnector]: Initializing CDTParser... [2022-11-16 11:33:42,227 INFO L275 PluginConnector]: CDTParser initialized [2022-11-16 11:33:42,229 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21e01fdd-cc36-4b11-ab5f-0d9093cc2036/bin/uautomizer-tPACEb0tL8/../../sv-benchmarks/c/termination-crafted-lit/Urban-WST2013-Fig2-modified1000.c [2022-11-16 11:33:42,302 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21e01fdd-cc36-4b11-ab5f-0d9093cc2036/bin/uautomizer-tPACEb0tL8/data/b859dbf70/4d36aa0a6b1c4c508e01d08e6b3eb7e7/FLAG6fa537ab5 [2022-11-16 11:33:42,795 INFO L306 CDTParser]: Found 1 translation units. [2022-11-16 11:33:42,795 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21e01fdd-cc36-4b11-ab5f-0d9093cc2036/sv-benchmarks/c/termination-crafted-lit/Urban-WST2013-Fig2-modified1000.c [2022-11-16 11:33:42,803 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21e01fdd-cc36-4b11-ab5f-0d9093cc2036/bin/uautomizer-tPACEb0tL8/data/b859dbf70/4d36aa0a6b1c4c508e01d08e6b3eb7e7/FLAG6fa537ab5 [2022-11-16 11:33:43,157 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21e01fdd-cc36-4b11-ab5f-0d9093cc2036/bin/uautomizer-tPACEb0tL8/data/b859dbf70/4d36aa0a6b1c4c508e01d08e6b3eb7e7 [2022-11-16 11:33:43,161 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-11-16 11:33:43,164 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-11-16 11:33:43,170 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-11-16 11:33:43,170 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-11-16 11:33:43,174 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-11-16 11:33:43,175 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.11 11:33:43" (1/1) ... [2022-11-16 11:33:43,178 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@fb2b53b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:33:43, skipping insertion in model container [2022-11-16 11:33:43,178 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.11 11:33:43" (1/1) ... [2022-11-16 11:33:43,186 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-11-16 11:33:43,200 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-11-16 11:33:43,406 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-16 11:33:43,426 INFO L203 MainTranslator]: Completed pre-run [2022-11-16 11:33:43,454 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-16 11:33:43,469 INFO L208 MainTranslator]: Completed translation [2022-11-16 11:33:43,470 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:33:43 WrapperNode [2022-11-16 11:33:43,471 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-11-16 11:33:43,472 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-11-16 11:33:43,473 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-11-16 11:33:43,473 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-11-16 11:33:43,482 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:33:43" (1/1) ... [2022-11-16 11:33:43,490 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:33:43" (1/1) ... [2022-11-16 11:33:43,509 INFO L138 Inliner]: procedures = 4, calls = 2, calls flagged for inlining = 2, calls inlined = 2, statements flattened = 21 [2022-11-16 11:33:43,510 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-11-16 11:33:43,512 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-11-16 11:33:43,512 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-11-16 11:33:43,512 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-11-16 11:33:43,522 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:33:43" (1/1) ... [2022-11-16 11:33:43,523 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:33:43" (1/1) ... [2022-11-16 11:33:43,524 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:33:43" (1/1) ... [2022-11-16 11:33:43,525 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:33:43" (1/1) ... [2022-11-16 11:33:43,528 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:33:43" (1/1) ... [2022-11-16 11:33:43,533 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:33:43" (1/1) ... [2022-11-16 11:33:43,534 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:33:43" (1/1) ... [2022-11-16 11:33:43,535 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:33:43" (1/1) ... [2022-11-16 11:33:43,536 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-11-16 11:33:43,538 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-11-16 11:33:43,538 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-11-16 11:33:43,539 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-11-16 11:33:43,540 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:33:43" (1/1) ... [2022-11-16 11:33:43,548 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-16 11:33:43,561 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21e01fdd-cc36-4b11-ab5f-0d9093cc2036/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:33:43,579 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21e01fdd-cc36-4b11-ab5f-0d9093cc2036/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-16 11:33:43,601 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21e01fdd-cc36-4b11-ab5f-0d9093cc2036/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-11-16 11:33:43,639 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-11-16 11:33:43,640 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-11-16 11:33:43,736 INFO L235 CfgBuilder]: Building ICFG [2022-11-16 11:33:43,739 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-11-16 11:33:43,811 INFO L276 CfgBuilder]: Performing block encoding [2022-11-16 11:33:43,818 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-11-16 11:33:43,818 INFO L300 CfgBuilder]: Removed 2 assume(true) statements. [2022-11-16 11:33:43,820 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.11 11:33:43 BoogieIcfgContainer [2022-11-16 11:33:43,821 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-11-16 11:33:43,822 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-11-16 11:33:43,822 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-11-16 11:33:43,829 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-11-16 11:33:43,829 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-16 11:33:43,830 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 16.11 11:33:43" (1/3) ... [2022-11-16 11:33:43,830 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@71fd09e3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 16.11 11:33:43, skipping insertion in model container [2022-11-16 11:33:43,831 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-16 11:33:43,831 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:33:43" (2/3) ... [2022-11-16 11:33:43,831 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@71fd09e3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 16.11 11:33:43, skipping insertion in model container [2022-11-16 11:33:43,832 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-16 11:33:43,832 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.11 11:33:43" (3/3) ... [2022-11-16 11:33:43,833 INFO L332 chiAutomizerObserver]: Analyzing ICFG Urban-WST2013-Fig2-modified1000.c [2022-11-16 11:33:43,896 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-11-16 11:33:43,896 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-11-16 11:33:43,897 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-11-16 11:33:43,897 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-11-16 11:33:43,897 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-11-16 11:33:43,897 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-11-16 11:33:43,897 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-11-16 11:33:43,897 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-11-16 11:33:43,902 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 9 states, 8 states have (on average 1.5) internal successors, (12), 8 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:33:43,922 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2022-11-16 11:33:43,922 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:33:43,923 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:33:43,928 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-11-16 11:33:43,929 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-11-16 11:33:43,929 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-11-16 11:33:43,929 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 9 states, 8 states have (on average 1.5) internal successors, (12), 8 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:33:43,930 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2022-11-16 11:33:43,930 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:33:43,931 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:33:43,931 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-11-16 11:33:43,931 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-11-16 11:33:43,939 INFO L748 eck$LassoCheckResult]: Stem: 5#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true; 8#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_#t~nondet1#1, main_~x1~0#1, main_~x2~0#1;havoc main_~x1~0#1;havoc main_~x2~0#1;main_~x1~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~x2~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1; 2#L19-2true [2022-11-16 11:33:43,940 INFO L750 eck$LassoCheckResult]: Loop: 2#L19-2true assume !!(main_~x1~0#1 <= 10);main_~x2~0#1 := 1000; 6#L21-2true assume !(main_~x2~0#1 > 1); 4#L21-3true main_~x1~0#1 := 1 + main_~x1~0#1; 2#L19-2true [2022-11-16 11:33:43,946 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:33:43,947 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 1 times [2022-11-16 11:33:43,957 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:33:43,959 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [378951762] [2022-11-16 11:33:43,959 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:33:43,961 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:33:44,042 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:33:44,043 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:33:44,046 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:33:44,064 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:33:44,067 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:33:44,068 INFO L85 PathProgramCache]: Analyzing trace with hash 40944, now seen corresponding path program 1 times [2022-11-16 11:33:44,068 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:33:44,068 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1647219275] [2022-11-16 11:33:44,068 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:33:44,069 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:33:44,078 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:33:44,196 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:33:44,196 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:33:44,196 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1647219275] [2022-11-16 11:33:44,197 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1647219275] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:33:44,197 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:33:44,198 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-16 11:33:44,198 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [665342032] [2022-11-16 11:33:44,199 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:33:44,204 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:33:44,205 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:33:44,258 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 11:33:44,259 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 11:33:44,261 INFO L87 Difference]: Start difference. First operand has 9 states, 8 states have (on average 1.5) internal successors, (12), 8 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 1.0) internal successors, (3), 2 states have internal predecessors, (3), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:33:44,284 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:33:44,285 INFO L93 Difference]: Finished difference Result 10 states and 11 transitions. [2022-11-16 11:33:44,286 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10 states and 11 transitions. [2022-11-16 11:33:44,288 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2022-11-16 11:33:44,292 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10 states to 6 states and 7 transitions. [2022-11-16 11:33:44,293 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2022-11-16 11:33:44,294 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2022-11-16 11:33:44,295 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6 states and 7 transitions. [2022-11-16 11:33:44,296 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:33:44,296 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6 states and 7 transitions. [2022-11-16 11:33:44,316 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6 states and 7 transitions. [2022-11-16 11:33:44,325 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6 to 6. [2022-11-16 11:33:44,325 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6 states, 6 states have (on average 1.1666666666666667) internal successors, (7), 5 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:33:44,326 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6 states to 6 states and 7 transitions. [2022-11-16 11:33:44,327 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6 states and 7 transitions. [2022-11-16 11:33:44,328 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 11:33:44,333 INFO L428 stractBuchiCegarLoop]: Abstraction has 6 states and 7 transitions. [2022-11-16 11:33:44,333 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-11-16 11:33:44,333 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6 states and 7 transitions. [2022-11-16 11:33:44,334 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2022-11-16 11:33:44,334 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:33:44,334 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:33:44,335 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-11-16 11:33:44,335 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2022-11-16 11:33:44,335 INFO L748 eck$LassoCheckResult]: Stem: 31#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true; 32#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_#t~nondet1#1, main_~x1~0#1, main_~x2~0#1;havoc main_~x1~0#1;havoc main_~x2~0#1;main_~x1~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~x2~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1; 28#L19-2 [2022-11-16 11:33:44,336 INFO L750 eck$LassoCheckResult]: Loop: 28#L19-2 assume !!(main_~x1~0#1 <= 10);main_~x2~0#1 := 1000; 29#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 33#L21-2 assume !(main_~x2~0#1 > 1); 30#L21-3 main_~x1~0#1 := 1 + main_~x1~0#1; 28#L19-2 [2022-11-16 11:33:44,337 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:33:44,337 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 2 times [2022-11-16 11:33:44,337 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:33:44,338 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1327909734] [2022-11-16 11:33:44,338 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:33:44,338 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:33:44,343 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:33:44,343 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:33:44,345 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:33:44,346 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:33:44,347 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:33:44,347 INFO L85 PathProgramCache]: Analyzing trace with hash 1271024, now seen corresponding path program 1 times [2022-11-16 11:33:44,348 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:33:44,348 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1430787765] [2022-11-16 11:33:44,348 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:33:44,349 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:33:44,356 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:33:44,396 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:33:44,396 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:33:44,396 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1430787765] [2022-11-16 11:33:44,397 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1430787765] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:33:44,397 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [29490161] [2022-11-16 11:33:44,397 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:33:44,398 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:33:44,398 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21e01fdd-cc36-4b11-ab5f-0d9093cc2036/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:33:44,402 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21e01fdd-cc36-4b11-ab5f-0d9093cc2036/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:33:44,431 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21e01fdd-cc36-4b11-ab5f-0d9093cc2036/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2022-11-16 11:33:44,512 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:33:44,515 INFO L263 TraceCheckSpWp]: Trace formula consists of 11 conjuncts, 3 conjunts are in the unsatisfiable core [2022-11-16 11:33:44,525 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:33:44,594 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:33:44,594 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:33:44,628 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:33:44,629 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [29490161] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:33:44,629 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-16 11:33:44,629 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 5 [2022-11-16 11:33:44,629 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1074046350] [2022-11-16 11:33:44,630 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-16 11:33:44,630 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:33:44,630 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:33:44,631 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2022-11-16 11:33:44,631 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2022-11-16 11:33:44,632 INFO L87 Difference]: Start difference. First operand 6 states and 7 transitions. cyclomatic complexity: 2 Second operand has 6 states, 6 states have (on average 1.1666666666666667) internal successors, (7), 5 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:33:44,661 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:33:44,661 INFO L93 Difference]: Finished difference Result 9 states and 10 transitions. [2022-11-16 11:33:44,661 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9 states and 10 transitions. [2022-11-16 11:33:44,662 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 7 [2022-11-16 11:33:44,663 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9 states to 9 states and 10 transitions. [2022-11-16 11:33:44,663 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9 [2022-11-16 11:33:44,663 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2022-11-16 11:33:44,664 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9 states and 10 transitions. [2022-11-16 11:33:44,664 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:33:44,664 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9 states and 10 transitions. [2022-11-16 11:33:44,664 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9 states and 10 transitions. [2022-11-16 11:33:44,665 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9 to 9. [2022-11-16 11:33:44,666 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9 states, 9 states have (on average 1.1111111111111112) internal successors, (10), 8 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:33:44,666 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9 states to 9 states and 10 transitions. [2022-11-16 11:33:44,667 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9 states and 10 transitions. [2022-11-16 11:33:44,667 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-11-16 11:33:44,668 INFO L428 stractBuchiCegarLoop]: Abstraction has 9 states and 10 transitions. [2022-11-16 11:33:44,669 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-11-16 11:33:44,669 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9 states and 10 transitions. [2022-11-16 11:33:44,670 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 7 [2022-11-16 11:33:44,670 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:33:44,670 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:33:44,671 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-11-16 11:33:44,671 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [4, 1, 1, 1] [2022-11-16 11:33:44,671 INFO L748 eck$LassoCheckResult]: Stem: 73#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true; 74#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_#t~nondet1#1, main_~x1~0#1, main_~x2~0#1;havoc main_~x1~0#1;havoc main_~x2~0#1;main_~x1~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~x2~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1; 70#L19-2 [2022-11-16 11:33:44,671 INFO L750 eck$LassoCheckResult]: Loop: 70#L19-2 assume !!(main_~x1~0#1 <= 10);main_~x2~0#1 := 1000; 71#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 75#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 78#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 77#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 76#L21-2 assume !(main_~x2~0#1 > 1); 72#L21-3 main_~x1~0#1 := 1 + main_~x1~0#1; 70#L19-2 [2022-11-16 11:33:44,672 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:33:44,672 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 3 times [2022-11-16 11:33:44,673 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:33:44,673 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [716376864] [2022-11-16 11:33:44,673 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:33:44,674 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:33:44,678 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:33:44,678 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:33:44,681 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:33:44,682 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:33:44,683 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:33:44,683 INFO L85 PathProgramCache]: Analyzing trace with hash -787882000, now seen corresponding path program 2 times [2022-11-16 11:33:44,684 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:33:44,685 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [882698391] [2022-11-16 11:33:44,685 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:33:44,686 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:33:44,710 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:33:44,837 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:33:44,837 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:33:44,838 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [882698391] [2022-11-16 11:33:44,838 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [882698391] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:33:44,838 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1477021274] [2022-11-16 11:33:44,839 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-16 11:33:44,839 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:33:44,839 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21e01fdd-cc36-4b11-ab5f-0d9093cc2036/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:33:44,843 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21e01fdd-cc36-4b11-ab5f-0d9093cc2036/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:33:44,860 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21e01fdd-cc36-4b11-ab5f-0d9093cc2036/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2022-11-16 11:33:44,891 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-16 11:33:44,891 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-16 11:33:44,892 INFO L263 TraceCheckSpWp]: Trace formula consists of 20 conjuncts, 6 conjunts are in the unsatisfiable core [2022-11-16 11:33:44,894 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:33:44,918 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:33:44,919 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:33:45,008 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:33:45,008 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1477021274] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:33:45,008 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-16 11:33:45,008 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6] total 11 [2022-11-16 11:33:45,009 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1425562592] [2022-11-16 11:33:45,009 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-16 11:33:45,009 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:33:45,010 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:33:45,010 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2022-11-16 11:33:45,011 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=66, Unknown=0, NotChecked=0, Total=132 [2022-11-16 11:33:45,011 INFO L87 Difference]: Start difference. First operand 9 states and 10 transitions. cyclomatic complexity: 2 Second operand has 12 states, 12 states have (on average 1.0833333333333333) internal successors, (13), 11 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:33:45,041 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:33:45,041 INFO L93 Difference]: Finished difference Result 15 states and 16 transitions. [2022-11-16 11:33:45,041 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 15 states and 16 transitions. [2022-11-16 11:33:45,042 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 13 [2022-11-16 11:33:45,043 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 15 states to 15 states and 16 transitions. [2022-11-16 11:33:45,043 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15 [2022-11-16 11:33:45,043 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15 [2022-11-16 11:33:45,043 INFO L73 IsDeterministic]: Start isDeterministic. Operand 15 states and 16 transitions. [2022-11-16 11:33:45,044 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:33:45,044 INFO L218 hiAutomatonCegarLoop]: Abstraction has 15 states and 16 transitions. [2022-11-16 11:33:45,044 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15 states and 16 transitions. [2022-11-16 11:33:45,046 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15 to 15. [2022-11-16 11:33:45,046 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15 states, 15 states have (on average 1.0666666666666667) internal successors, (16), 14 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:33:45,047 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15 states to 15 states and 16 transitions. [2022-11-16 11:33:45,047 INFO L240 hiAutomatonCegarLoop]: Abstraction has 15 states and 16 transitions. [2022-11-16 11:33:45,047 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2022-11-16 11:33:45,048 INFO L428 stractBuchiCegarLoop]: Abstraction has 15 states and 16 transitions. [2022-11-16 11:33:45,049 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-11-16 11:33:45,049 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 15 states and 16 transitions. [2022-11-16 11:33:45,050 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 13 [2022-11-16 11:33:45,050 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:33:45,050 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:33:45,051 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-11-16 11:33:45,051 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [10, 1, 1, 1] [2022-11-16 11:33:45,051 INFO L748 eck$LassoCheckResult]: Stem: 148#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true; 149#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_#t~nondet1#1, main_~x1~0#1, main_~x2~0#1;havoc main_~x1~0#1;havoc main_~x2~0#1;main_~x1~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~x2~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1; 145#L19-2 [2022-11-16 11:33:45,051 INFO L750 eck$LassoCheckResult]: Loop: 145#L19-2 assume !!(main_~x1~0#1 <= 10);main_~x2~0#1 := 1000; 146#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 150#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 159#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 158#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 157#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 156#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 155#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 154#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 153#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 152#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 151#L21-2 assume !(main_~x2~0#1 > 1); 147#L21-3 main_~x1~0#1 := 1 + main_~x1~0#1; 145#L19-2 [2022-11-16 11:33:45,052 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:33:45,052 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 4 times [2022-11-16 11:33:45,053 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:33:45,053 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [720430438] [2022-11-16 11:33:45,053 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:33:45,053 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:33:45,057 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:33:45,058 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:33:45,060 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:33:45,061 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:33:45,062 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:33:45,062 INFO L85 PathProgramCache]: Analyzing trace with hash 1798029296, now seen corresponding path program 3 times [2022-11-16 11:33:45,063 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:33:45,063 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [148118986] [2022-11-16 11:33:45,063 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:33:45,064 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:33:45,083 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:33:45,467 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:33:45,468 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:33:45,468 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [148118986] [2022-11-16 11:33:45,468 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [148118986] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:33:45,469 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1160011481] [2022-11-16 11:33:45,469 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-16 11:33:45,469 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:33:45,469 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21e01fdd-cc36-4b11-ab5f-0d9093cc2036/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:33:45,491 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21e01fdd-cc36-4b11-ab5f-0d9093cc2036/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:33:45,532 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21e01fdd-cc36-4b11-ab5f-0d9093cc2036/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2022-11-16 11:33:45,573 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2022-11-16 11:33:45,573 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-16 11:33:45,574 INFO L263 TraceCheckSpWp]: Trace formula consists of 38 conjuncts, 12 conjunts are in the unsatisfiable core [2022-11-16 11:33:45,576 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:33:45,670 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:33:45,670 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:33:46,064 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:33:46,065 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1160011481] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:33:46,066 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-16 11:33:46,066 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12] total 23 [2022-11-16 11:33:46,066 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [609082586] [2022-11-16 11:33:46,066 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-16 11:33:46,068 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:33:46,068 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:33:46,071 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2022-11-16 11:33:46,073 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=276, Invalid=276, Unknown=0, NotChecked=0, Total=552 [2022-11-16 11:33:46,074 INFO L87 Difference]: Start difference. First operand 15 states and 16 transitions. cyclomatic complexity: 2 Second operand has 24 states, 24 states have (on average 1.0416666666666667) internal successors, (25), 23 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:33:46,171 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:33:46,171 INFO L93 Difference]: Finished difference Result 27 states and 28 transitions. [2022-11-16 11:33:46,171 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27 states and 28 transitions. [2022-11-16 11:33:46,173 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 25 [2022-11-16 11:33:46,173 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27 states to 27 states and 28 transitions. [2022-11-16 11:33:46,174 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27 [2022-11-16 11:33:46,174 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27 [2022-11-16 11:33:46,174 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27 states and 28 transitions. [2022-11-16 11:33:46,174 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:33:46,174 INFO L218 hiAutomatonCegarLoop]: Abstraction has 27 states and 28 transitions. [2022-11-16 11:33:46,175 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27 states and 28 transitions. [2022-11-16 11:33:46,176 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27 to 27. [2022-11-16 11:33:46,177 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27 states, 27 states have (on average 1.037037037037037) internal successors, (28), 26 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:33:46,177 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 28 transitions. [2022-11-16 11:33:46,178 INFO L240 hiAutomatonCegarLoop]: Abstraction has 27 states and 28 transitions. [2022-11-16 11:33:46,181 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2022-11-16 11:33:46,182 INFO L428 stractBuchiCegarLoop]: Abstraction has 27 states and 28 transitions. [2022-11-16 11:33:46,183 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-11-16 11:33:46,183 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27 states and 28 transitions. [2022-11-16 11:33:46,186 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 25 [2022-11-16 11:33:46,186 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:33:46,186 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:33:46,187 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-11-16 11:33:46,187 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [22, 1, 1, 1] [2022-11-16 11:33:46,188 INFO L748 eck$LassoCheckResult]: Stem: 289#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true; 290#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_#t~nondet1#1, main_~x1~0#1, main_~x2~0#1;havoc main_~x1~0#1;havoc main_~x2~0#1;main_~x1~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~x2~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1; 286#L19-2 [2022-11-16 11:33:46,188 INFO L750 eck$LassoCheckResult]: Loop: 286#L19-2 assume !!(main_~x1~0#1 <= 10);main_~x2~0#1 := 1000; 287#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 291#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 312#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 311#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 310#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 309#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 308#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 307#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 306#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 305#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 304#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 303#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 302#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 301#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 300#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 299#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 298#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 297#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 296#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 295#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 294#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 293#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 292#L21-2 assume !(main_~x2~0#1 > 1); 288#L21-3 main_~x1~0#1 := 1 + main_~x1~0#1; 286#L19-2 [2022-11-16 11:33:46,188 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:33:46,188 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 5 times [2022-11-16 11:33:46,189 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:33:46,189 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1049327866] [2022-11-16 11:33:46,189 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:33:46,189 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:33:46,193 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:33:46,193 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:33:46,195 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:33:46,196 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:33:46,197 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:33:46,197 INFO L85 PathProgramCache]: Analyzing trace with hash -1296597008, now seen corresponding path program 4 times [2022-11-16 11:33:46,197 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:33:46,197 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1900379379] [2022-11-16 11:33:46,197 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:33:46,198 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:33:46,222 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:33:46,982 INFO L134 CoverageAnalysis]: Checked inductivity of 253 backedges. 0 proven. 253 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:33:46,982 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:33:46,982 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1900379379] [2022-11-16 11:33:46,982 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1900379379] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:33:46,983 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1506431784] [2022-11-16 11:33:46,983 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-16 11:33:46,983 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:33:46,983 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21e01fdd-cc36-4b11-ab5f-0d9093cc2036/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:33:46,990 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21e01fdd-cc36-4b11-ab5f-0d9093cc2036/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:33:47,010 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21e01fdd-cc36-4b11-ab5f-0d9093cc2036/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2022-11-16 11:33:47,069 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-16 11:33:47,069 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-16 11:33:47,070 INFO L263 TraceCheckSpWp]: Trace formula consists of 74 conjuncts, 24 conjunts are in the unsatisfiable core [2022-11-16 11:33:47,073 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:33:47,197 INFO L134 CoverageAnalysis]: Checked inductivity of 253 backedges. 0 proven. 253 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:33:47,197 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:33:48,205 INFO L134 CoverageAnalysis]: Checked inductivity of 253 backedges. 0 proven. 253 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:33:48,205 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1506431784] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:33:48,205 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-16 11:33:48,206 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24, 24] total 47 [2022-11-16 11:33:48,206 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [453485519] [2022-11-16 11:33:48,206 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-16 11:33:48,207 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:33:48,207 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:33:48,208 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 48 interpolants. [2022-11-16 11:33:48,209 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1128, Invalid=1128, Unknown=0, NotChecked=0, Total=2256 [2022-11-16 11:33:48,209 INFO L87 Difference]: Start difference. First operand 27 states and 28 transitions. cyclomatic complexity: 2 Second operand has 48 states, 48 states have (on average 1.0208333333333333) internal successors, (49), 47 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:33:48,322 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:33:48,322 INFO L93 Difference]: Finished difference Result 51 states and 52 transitions. [2022-11-16 11:33:48,322 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 51 states and 52 transitions. [2022-11-16 11:33:48,328 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 49 [2022-11-16 11:33:48,337 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 51 states to 51 states and 52 transitions. [2022-11-16 11:33:48,338 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 51 [2022-11-16 11:33:48,338 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 51 [2022-11-16 11:33:48,340 INFO L73 IsDeterministic]: Start isDeterministic. Operand 51 states and 52 transitions. [2022-11-16 11:33:48,341 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:33:48,341 INFO L218 hiAutomatonCegarLoop]: Abstraction has 51 states and 52 transitions. [2022-11-16 11:33:48,341 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51 states and 52 transitions. [2022-11-16 11:33:48,345 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51 to 51. [2022-11-16 11:33:48,347 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 51 states, 51 states have (on average 1.0196078431372548) internal successors, (52), 50 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:33:48,350 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51 states to 51 states and 52 transitions. [2022-11-16 11:33:48,350 INFO L240 hiAutomatonCegarLoop]: Abstraction has 51 states and 52 transitions. [2022-11-16 11:33:48,351 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2022-11-16 11:33:48,354 INFO L428 stractBuchiCegarLoop]: Abstraction has 51 states and 52 transitions. [2022-11-16 11:33:48,355 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-11-16 11:33:48,355 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 51 states and 52 transitions. [2022-11-16 11:33:48,356 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 49 [2022-11-16 11:33:48,357 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:33:48,357 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:33:48,358 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-11-16 11:33:48,359 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [46, 1, 1, 1] [2022-11-16 11:33:48,360 INFO L748 eck$LassoCheckResult]: Stem: 562#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true; 563#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_#t~nondet1#1, main_~x1~0#1, main_~x2~0#1;havoc main_~x1~0#1;havoc main_~x2~0#1;main_~x1~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~x2~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1; 559#L19-2 [2022-11-16 11:33:48,365 INFO L750 eck$LassoCheckResult]: Loop: 559#L19-2 assume !!(main_~x1~0#1 <= 10);main_~x2~0#1 := 1000; 560#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 564#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 609#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 608#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 607#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 606#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 605#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 604#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 603#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 602#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 601#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 600#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 599#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 598#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 597#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 596#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 595#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 594#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 593#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 592#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 591#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 590#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 589#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 588#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 587#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 586#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 585#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 584#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 583#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 582#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 581#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 580#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 579#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 578#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 577#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 576#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 575#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 574#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 573#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 572#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 571#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 570#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 569#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 568#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 567#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 566#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 565#L21-2 assume !(main_~x2~0#1 > 1); 561#L21-3 main_~x1~0#1 := 1 + main_~x1~0#1; 559#L19-2 [2022-11-16 11:33:48,366 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:33:48,367 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 6 times [2022-11-16 11:33:48,368 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:33:48,368 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [596984061] [2022-11-16 11:33:48,369 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:33:48,370 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:33:48,372 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:33:48,375 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:33:48,378 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:33:48,385 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:33:48,386 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:33:48,386 INFO L85 PathProgramCache]: Analyzing trace with hash -1762721808, now seen corresponding path program 5 times [2022-11-16 11:33:48,386 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:33:48,387 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [599700489] [2022-11-16 11:33:48,387 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:33:48,387 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:33:48,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:33:50,224 INFO L134 CoverageAnalysis]: Checked inductivity of 1081 backedges. 0 proven. 1081 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:33:50,224 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:33:50,224 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [599700489] [2022-11-16 11:33:50,225 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [599700489] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:33:50,225 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [980747960] [2022-11-16 11:33:50,225 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-16 11:33:50,225 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:33:50,225 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21e01fdd-cc36-4b11-ab5f-0d9093cc2036/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:33:50,238 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21e01fdd-cc36-4b11-ab5f-0d9093cc2036/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:33:50,263 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21e01fdd-cc36-4b11-ab5f-0d9093cc2036/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2022-11-16 11:33:50,330 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 24 check-sat command(s) [2022-11-16 11:33:50,330 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-16 11:33:50,333 INFO L263 TraceCheckSpWp]: Trace formula consists of 146 conjuncts, 48 conjunts are in the unsatisfiable core [2022-11-16 11:33:50,337 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:33:50,538 INFO L134 CoverageAnalysis]: Checked inductivity of 1081 backedges. 0 proven. 1081 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:33:50,538 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:33:54,123 INFO L134 CoverageAnalysis]: Checked inductivity of 1081 backedges. 0 proven. 1081 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:33:54,123 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [980747960] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:33:54,123 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-16 11:33:54,124 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 48, 48] total 95 [2022-11-16 11:33:54,124 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1900293864] [2022-11-16 11:33:54,124 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-16 11:33:54,125 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:33:54,125 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:33:54,127 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 96 interpolants. [2022-11-16 11:33:54,131 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=4560, Invalid=4560, Unknown=0, NotChecked=0, Total=9120 [2022-11-16 11:33:54,132 INFO L87 Difference]: Start difference. First operand 51 states and 52 transitions. cyclomatic complexity: 2 Second operand has 96 states, 96 states have (on average 1.0104166666666667) internal successors, (97), 95 states have internal predecessors, (97), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:33:54,438 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:33:54,438 INFO L93 Difference]: Finished difference Result 99 states and 100 transitions. [2022-11-16 11:33:54,438 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 99 states and 100 transitions. [2022-11-16 11:33:54,440 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 97 [2022-11-16 11:33:54,441 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 99 states to 99 states and 100 transitions. [2022-11-16 11:33:54,441 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 99 [2022-11-16 11:33:54,442 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 99 [2022-11-16 11:33:54,442 INFO L73 IsDeterministic]: Start isDeterministic. Operand 99 states and 100 transitions. [2022-11-16 11:33:54,443 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:33:54,443 INFO L218 hiAutomatonCegarLoop]: Abstraction has 99 states and 100 transitions. [2022-11-16 11:33:54,443 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 99 states and 100 transitions. [2022-11-16 11:33:54,449 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 99 to 99. [2022-11-16 11:33:54,452 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 99 states, 99 states have (on average 1.0101010101010102) internal successors, (100), 98 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:33:54,454 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99 states to 99 states and 100 transitions. [2022-11-16 11:33:54,455 INFO L240 hiAutomatonCegarLoop]: Abstraction has 99 states and 100 transitions. [2022-11-16 11:33:54,456 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 96 states. [2022-11-16 11:33:54,457 INFO L428 stractBuchiCegarLoop]: Abstraction has 99 states and 100 transitions. [2022-11-16 11:33:54,458 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-11-16 11:33:54,459 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 99 states and 100 transitions. [2022-11-16 11:33:54,460 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 97 [2022-11-16 11:33:54,463 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:33:54,464 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:33:54,465 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-11-16 11:33:54,467 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [94, 1, 1, 1] [2022-11-16 11:33:54,468 INFO L748 eck$LassoCheckResult]: Stem: 1099#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true; 1100#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_#t~nondet1#1, main_~x1~0#1, main_~x2~0#1;havoc main_~x1~0#1;havoc main_~x2~0#1;main_~x1~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~x2~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1; 1096#L19-2 [2022-11-16 11:33:54,468 INFO L750 eck$LassoCheckResult]: Loop: 1096#L19-2 assume !!(main_~x1~0#1 <= 10);main_~x2~0#1 := 1000; 1097#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1101#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1194#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1193#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1192#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1191#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1190#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1189#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1188#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1187#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1186#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1185#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1184#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1183#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1182#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1181#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1180#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1179#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1178#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1177#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1176#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1175#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1174#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1173#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1172#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1171#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1170#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1169#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1168#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1167#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1166#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1165#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1164#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1163#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1162#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1161#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1160#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1159#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1158#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1157#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1156#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1155#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1154#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1153#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1152#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1151#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1150#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1149#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1148#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1147#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1146#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1145#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1144#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1143#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1142#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1141#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1140#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1139#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1138#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1137#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1136#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1135#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1134#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1133#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1132#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1131#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1130#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1129#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1128#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1127#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1126#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1125#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1124#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1123#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1122#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1121#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1120#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1119#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1118#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1117#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1116#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1115#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1114#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1113#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1112#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1111#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1110#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1109#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1108#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1107#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1106#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1105#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1104#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1103#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 1102#L21-2 assume !(main_~x2~0#1 > 1); 1098#L21-3 main_~x1~0#1 := 1 + main_~x1~0#1; 1096#L19-2 [2022-11-16 11:33:54,470 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:33:54,470 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 7 times [2022-11-16 11:33:54,471 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:33:54,471 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [165540089] [2022-11-16 11:33:54,471 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:33:54,472 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:33:54,474 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:33:54,474 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:33:54,475 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:33:54,477 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:33:54,478 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:33:54,478 INFO L85 PathProgramCache]: Analyzing trace with hash -203554832, now seen corresponding path program 6 times [2022-11-16 11:33:54,478 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:33:54,478 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1445268176] [2022-11-16 11:33:54,478 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:33:54,479 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:33:54,606 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:34:00,266 INFO L134 CoverageAnalysis]: Checked inductivity of 4465 backedges. 0 proven. 4465 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:34:00,267 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:34:00,267 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1445268176] [2022-11-16 11:34:00,267 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1445268176] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:34:00,268 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1162978944] [2022-11-16 11:34:00,268 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-11-16 11:34:00,268 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:34:00,268 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21e01fdd-cc36-4b11-ab5f-0d9093cc2036/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:34:00,270 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21e01fdd-cc36-4b11-ab5f-0d9093cc2036/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:34:00,272 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21e01fdd-cc36-4b11-ab5f-0d9093cc2036/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2022-11-16 11:34:00,380 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 48 check-sat command(s) [2022-11-16 11:34:00,380 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-16 11:34:00,383 INFO L263 TraceCheckSpWp]: Trace formula consists of 290 conjuncts, 96 conjunts are in the unsatisfiable core [2022-11-16 11:34:00,388 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:34:00,680 INFO L134 CoverageAnalysis]: Checked inductivity of 4465 backedges. 0 proven. 4465 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:34:00,680 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:34:12,667 INFO L134 CoverageAnalysis]: Checked inductivity of 4465 backedges. 0 proven. 4465 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:34:12,667 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1162978944] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:34:12,667 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-16 11:34:12,667 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [96, 96, 96] total 191 [2022-11-16 11:34:12,668 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [550522419] [2022-11-16 11:34:12,668 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-16 11:34:12,669 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:34:12,669 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:34:12,675 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 192 interpolants. [2022-11-16 11:34:12,686 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=18336, Invalid=18336, Unknown=0, NotChecked=0, Total=36672 [2022-11-16 11:34:12,687 INFO L87 Difference]: Start difference. First operand 99 states and 100 transitions. cyclomatic complexity: 2 Second operand has 192 states, 192 states have (on average 1.0052083333333333) internal successors, (193), 191 states have internal predecessors, (193), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:34:13,485 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:34:13,485 INFO L93 Difference]: Finished difference Result 195 states and 196 transitions. [2022-11-16 11:34:13,485 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 195 states and 196 transitions. [2022-11-16 11:34:13,492 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 193 [2022-11-16 11:34:13,497 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 195 states to 195 states and 196 transitions. [2022-11-16 11:34:13,497 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 195 [2022-11-16 11:34:13,498 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 195 [2022-11-16 11:34:13,499 INFO L73 IsDeterministic]: Start isDeterministic. Operand 195 states and 196 transitions. [2022-11-16 11:34:13,505 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:34:13,507 INFO L218 hiAutomatonCegarLoop]: Abstraction has 195 states and 196 transitions. [2022-11-16 11:34:13,508 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 195 states and 196 transitions. [2022-11-16 11:34:13,516 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 195 to 195. [2022-11-16 11:34:13,522 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 195 states, 195 states have (on average 1.005128205128205) internal successors, (196), 194 states have internal predecessors, (196), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:34:13,524 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 195 states to 195 states and 196 transitions. [2022-11-16 11:34:13,526 INFO L240 hiAutomatonCegarLoop]: Abstraction has 195 states and 196 transitions. [2022-11-16 11:34:13,526 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 192 states. [2022-11-16 11:34:13,527 INFO L428 stractBuchiCegarLoop]: Abstraction has 195 states and 196 transitions. [2022-11-16 11:34:13,528 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-11-16 11:34:13,529 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 195 states and 196 transitions. [2022-11-16 11:34:13,531 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 193 [2022-11-16 11:34:13,532 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:34:13,532 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:34:13,535 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-11-16 11:34:13,540 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [190, 1, 1, 1] [2022-11-16 11:34:13,541 INFO L748 eck$LassoCheckResult]: Stem: 2164#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true; 2165#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_#t~nondet1#1, main_~x1~0#1, main_~x2~0#1;havoc main_~x1~0#1;havoc main_~x2~0#1;main_~x1~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~x2~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1; 2161#L19-2 [2022-11-16 11:34:13,541 INFO L750 eck$LassoCheckResult]: Loop: 2161#L19-2 assume !!(main_~x1~0#1 <= 10);main_~x2~0#1 := 1000; 2162#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2166#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2355#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2354#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2353#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2352#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2351#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2350#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2349#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2348#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2347#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2346#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2345#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2344#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2343#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2342#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2341#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2340#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2339#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2338#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2337#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2336#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2335#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2334#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2333#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2332#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2331#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2330#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2329#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2328#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2327#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2326#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2325#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2324#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2323#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2322#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2321#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2320#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2319#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2318#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2317#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2316#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2315#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2314#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2313#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2312#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2311#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2310#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2309#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2308#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2307#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2306#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2305#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2304#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2303#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2302#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2301#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2300#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2299#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2298#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2297#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2296#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2295#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2294#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2293#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2292#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2291#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2290#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2289#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2288#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2287#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2286#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2285#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2284#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2283#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2282#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2281#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2280#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2279#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2278#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2277#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2276#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2275#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2274#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2273#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2272#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2271#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2270#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2269#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2268#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2267#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2266#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2265#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2264#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2263#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2262#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2261#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2260#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2259#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2258#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2257#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2256#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2255#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2254#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2253#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2252#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2251#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2250#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2249#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2248#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2247#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2246#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2245#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2244#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2243#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2242#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2241#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2240#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2239#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2238#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2237#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2236#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2235#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2234#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2233#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2232#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2231#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2230#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2229#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2228#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2227#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2226#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2225#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2224#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2223#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2222#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2221#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2220#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2219#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2218#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2217#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2216#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2215#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2214#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2213#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2212#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2211#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2210#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2209#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2208#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2207#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2206#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2205#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2204#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2203#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2202#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2201#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2200#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2199#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2198#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2197#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2196#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2195#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2194#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2193#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2192#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2191#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2190#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2189#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2188#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2187#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2186#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2185#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2184#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2183#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2182#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2181#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2180#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2179#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2178#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2177#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2176#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2175#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2174#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2173#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2172#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2171#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2170#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2169#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2168#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 2167#L21-2 assume !(main_~x2~0#1 > 1); 2163#L21-3 main_~x1~0#1 := 1 + main_~x1~0#1; 2161#L19-2 [2022-11-16 11:34:13,542 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:34:13,548 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 8 times [2022-11-16 11:34:13,548 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:34:13,549 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [448456058] [2022-11-16 11:34:13,549 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:34:13,549 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:34:13,552 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:34:13,552 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:34:13,553 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:34:13,554 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:34:13,556 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:34:13,557 INFO L85 PathProgramCache]: Analyzing trace with hash -4456464, now seen corresponding path program 7 times [2022-11-16 11:34:13,557 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:34:13,557 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [26399941] [2022-11-16 11:34:13,557 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:34:13,558 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:34:13,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:34:34,881 INFO L134 CoverageAnalysis]: Checked inductivity of 18145 backedges. 0 proven. 18145 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:34:34,882 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:34:34,882 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [26399941] [2022-11-16 11:34:34,882 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [26399941] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:34:34,882 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [133918671] [2022-11-16 11:34:34,882 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-11-16 11:34:34,883 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:34:34,883 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21e01fdd-cc36-4b11-ab5f-0d9093cc2036/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:34:34,888 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21e01fdd-cc36-4b11-ab5f-0d9093cc2036/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:34:34,891 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21e01fdd-cc36-4b11-ab5f-0d9093cc2036/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Waiting until timeout for monitored process [2022-11-16 11:34:35,039 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:34:35,045 INFO L263 TraceCheckSpWp]: Trace formula consists of 578 conjuncts, 192 conjunts are in the unsatisfiable core [2022-11-16 11:34:35,054 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:34:35,528 INFO L134 CoverageAnalysis]: Checked inductivity of 18145 backedges. 0 proven. 18145 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:34:35,528 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:35:22,175 INFO L134 CoverageAnalysis]: Checked inductivity of 18145 backedges. 0 proven. 18145 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:35:22,176 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [133918671] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:35:22,176 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-16 11:35:22,176 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [192, 192, 192] total 383 [2022-11-16 11:35:22,176 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1078884248] [2022-11-16 11:35:22,177 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-16 11:35:22,178 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:35:22,178 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:35:22,200 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 384 interpolants. [2022-11-16 11:35:22,215 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=73536, Invalid=73536, Unknown=0, NotChecked=0, Total=147072 [2022-11-16 11:35:22,216 INFO L87 Difference]: Start difference. First operand 195 states and 196 transitions. cyclomatic complexity: 2 Second operand has 384 states, 384 states have (on average 1.0026041666666667) internal successors, (385), 383 states have internal predecessors, (385), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:35:24,539 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:35:24,539 INFO L93 Difference]: Finished difference Result 387 states and 388 transitions. [2022-11-16 11:35:24,539 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 387 states and 388 transitions. [2022-11-16 11:35:24,542 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 385 [2022-11-16 11:35:24,545 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 387 states to 387 states and 388 transitions. [2022-11-16 11:35:24,545 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 387 [2022-11-16 11:35:24,545 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 387 [2022-11-16 11:35:24,546 INFO L73 IsDeterministic]: Start isDeterministic. Operand 387 states and 388 transitions. [2022-11-16 11:35:24,546 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:35:24,546 INFO L218 hiAutomatonCegarLoop]: Abstraction has 387 states and 388 transitions. [2022-11-16 11:35:24,547 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 387 states and 388 transitions. [2022-11-16 11:35:24,559 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 387 to 387. [2022-11-16 11:35:24,560 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 387 states, 387 states have (on average 1.0025839793281655) internal successors, (388), 386 states have internal predecessors, (388), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:35:24,563 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 387 states to 387 states and 388 transitions. [2022-11-16 11:35:24,563 INFO L240 hiAutomatonCegarLoop]: Abstraction has 387 states and 388 transitions. [2022-11-16 11:35:24,563 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 384 states. [2022-11-16 11:35:24,564 INFO L428 stractBuchiCegarLoop]: Abstraction has 387 states and 388 transitions. [2022-11-16 11:35:24,564 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-11-16 11:35:24,564 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 387 states and 388 transitions. [2022-11-16 11:35:24,567 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 385 [2022-11-16 11:35:24,567 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:35:24,567 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:35:24,570 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-11-16 11:35:24,570 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [382, 1, 1, 1] [2022-11-16 11:35:24,570 INFO L748 eck$LassoCheckResult]: Stem: 4285#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true; 4286#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_#t~nondet1#1, main_~x1~0#1, main_~x2~0#1;havoc main_~x1~0#1;havoc main_~x2~0#1;main_~x1~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~x2~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1; 4282#L19-2 [2022-11-16 11:35:24,571 INFO L750 eck$LassoCheckResult]: Loop: 4282#L19-2 assume !!(main_~x1~0#1 <= 10);main_~x2~0#1 := 1000; 4283#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4287#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4668#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4667#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4666#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4665#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4664#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4663#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4662#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4661#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4660#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4659#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4658#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4657#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4656#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4655#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4654#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4653#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4652#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4651#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4650#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4649#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4648#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4647#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4646#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4645#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4644#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4643#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4642#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4641#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4640#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4639#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4638#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4637#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4636#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4635#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4634#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4633#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4632#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4631#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4630#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4629#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4628#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4627#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4626#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4625#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4624#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4623#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4622#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4621#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4620#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4619#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4618#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4617#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4616#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4615#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4614#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4613#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4612#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4611#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4610#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4609#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4608#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4607#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4606#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4605#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4604#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4603#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4602#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4601#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4600#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4599#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4598#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4597#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4596#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4595#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4594#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4593#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4592#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4591#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4590#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4589#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4588#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4587#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4586#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4585#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4584#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4583#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4582#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4581#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4580#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4579#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4578#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4577#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4576#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4575#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4574#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4573#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4572#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4571#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4570#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4569#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4568#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4567#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4566#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4565#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4564#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4563#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4562#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4561#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4560#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4559#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4558#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4557#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4556#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4555#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4554#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4553#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4552#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4551#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4550#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4549#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4548#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4547#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4546#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4545#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4544#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4543#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4542#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4541#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4540#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4539#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4538#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4537#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4536#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4535#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4534#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4533#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4532#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4531#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4530#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4529#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4528#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4527#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4526#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4525#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4524#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4523#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4522#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4521#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4520#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4519#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4518#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4517#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4516#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4515#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4514#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4513#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4512#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4511#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4510#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4509#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4508#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4507#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4506#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4505#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4504#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4503#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4502#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4501#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4500#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4499#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4498#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4497#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4496#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4495#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4494#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4493#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4492#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4491#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4490#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4489#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4488#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4487#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4486#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4485#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4484#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4483#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4482#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4481#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4480#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4479#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4478#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4477#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4476#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4475#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4474#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4473#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4472#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4471#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4470#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4469#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4468#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4467#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4466#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4465#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4464#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4463#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4462#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4461#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4460#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4459#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4458#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4457#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4456#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4455#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4454#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4453#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4452#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4451#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4450#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4449#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4448#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4447#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4446#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4445#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4444#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4443#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4442#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4441#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4440#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4439#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4438#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4437#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4436#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4435#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4434#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4433#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4432#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4431#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4430#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4429#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4428#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4427#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4426#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4425#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4424#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4423#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4422#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4421#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4420#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4419#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4418#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4417#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4416#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4415#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4414#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4413#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4412#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4411#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4410#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4409#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4408#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4407#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4406#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4405#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4404#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4403#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4402#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4401#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4400#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4399#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4398#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4397#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4396#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4395#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4394#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4393#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4392#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4391#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4390#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4389#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4388#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4387#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4386#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4385#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4384#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4383#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4382#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4381#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4380#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4379#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4378#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4377#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4376#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4375#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4374#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4373#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4372#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4371#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4370#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4369#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4368#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4367#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4366#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4365#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4364#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4363#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4362#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4361#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4360#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4359#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4358#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4357#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4356#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4355#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4354#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4353#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4352#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4351#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4350#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4349#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4348#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4347#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4346#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4345#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4344#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4343#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4342#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4341#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4340#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4339#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4338#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4337#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4336#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4335#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4334#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4333#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4332#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4331#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4330#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4329#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4328#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4327#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4326#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4325#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4324#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4323#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4322#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4321#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4320#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4319#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4318#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4317#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4316#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4315#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4314#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4313#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4312#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4311#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4310#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4309#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4308#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4307#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4306#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4305#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4304#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4303#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4302#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4301#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4300#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4299#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4298#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4297#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4296#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4295#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4294#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4293#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4292#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4291#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4290#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4289#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 4288#L21-2 assume !(main_~x2~0#1 > 1); 4284#L21-3 main_~x1~0#1 := 1 + main_~x1~0#1; 4282#L19-2 [2022-11-16 11:35:24,571 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:35:24,571 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 9 times [2022-11-16 11:35:24,571 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:35:24,572 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1228870793] [2022-11-16 11:35:24,572 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:35:24,572 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:35:24,574 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:35:24,574 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:35:24,575 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:35:24,576 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:35:24,576 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:35:24,577 INFO L85 PathProgramCache]: Analyzing trace with hash 1601699824, now seen corresponding path program 8 times [2022-11-16 11:35:24,577 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:35:24,577 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1816335864] [2022-11-16 11:35:24,577 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:35:24,577 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:35:25,479 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:36:45,407 INFO L134 CoverageAnalysis]: Checked inductivity of 73153 backedges. 0 proven. 73153 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:36:45,407 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:36:45,407 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1816335864] [2022-11-16 11:36:45,408 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1816335864] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:36:45,408 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [505073317] [2022-11-16 11:36:45,408 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-16 11:36:45,408 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:36:45,408 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21e01fdd-cc36-4b11-ab5f-0d9093cc2036/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:36:45,418 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21e01fdd-cc36-4b11-ab5f-0d9093cc2036/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:36:45,441 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21e01fdd-cc36-4b11-ab5f-0d9093cc2036/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2022-11-16 11:36:45,671 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-16 11:36:45,671 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-16 11:36:45,682 INFO L263 TraceCheckSpWp]: Trace formula consists of 1154 conjuncts, 384 conjunts are in the unsatisfiable core [2022-11-16 11:36:45,694 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:36:46,425 INFO L134 CoverageAnalysis]: Checked inductivity of 73153 backedges. 0 proven. 73153 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:36:46,425 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:39:41,460 INFO L134 CoverageAnalysis]: Checked inductivity of 73153 backedges. 0 proven. 73153 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:39:41,460 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [505073317] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:39:41,460 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-16 11:39:41,461 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [384, 384, 384] total 767 [2022-11-16 11:39:41,461 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1007739133] [2022-11-16 11:39:41,461 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-16 11:39:41,463 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:39:41,463 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:39:41,500 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 768 interpolants. [2022-11-16 11:39:41,538 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=294528, Invalid=294528, Unknown=0, NotChecked=0, Total=589056 [2022-11-16 11:39:41,540 INFO L87 Difference]: Start difference. First operand 387 states and 388 transitions. cyclomatic complexity: 2 Second operand has 768 states, 768 states have (on average 1.0013020833333333) internal successors, (769), 767 states have internal predecessors, (769), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:39:56,705 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:39:56,705 INFO L93 Difference]: Finished difference Result 771 states and 772 transitions. [2022-11-16 11:39:56,705 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 771 states and 772 transitions. [2022-11-16 11:39:56,716 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 769 [2022-11-16 11:39:56,721 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 771 states to 771 states and 772 transitions. [2022-11-16 11:39:56,722 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 771 [2022-11-16 11:39:56,723 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 771 [2022-11-16 11:39:56,723 INFO L73 IsDeterministic]: Start isDeterministic. Operand 771 states and 772 transitions. [2022-11-16 11:39:56,724 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:39:56,724 INFO L218 hiAutomatonCegarLoop]: Abstraction has 771 states and 772 transitions. [2022-11-16 11:39:56,725 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 771 states and 772 transitions. [2022-11-16 11:39:56,744 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 771 to 771. [2022-11-16 11:39:56,747 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 771 states, 771 states have (on average 1.0012970168612192) internal successors, (772), 770 states have internal predecessors, (772), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:39:56,751 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 771 states to 771 states and 772 transitions. [2022-11-16 11:39:56,751 INFO L240 hiAutomatonCegarLoop]: Abstraction has 771 states and 772 transitions. [2022-11-16 11:39:56,752 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 768 states. [2022-11-16 11:39:56,752 INFO L428 stractBuchiCegarLoop]: Abstraction has 771 states and 772 transitions. [2022-11-16 11:39:56,752 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-11-16 11:39:56,752 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 771 states and 772 transitions. [2022-11-16 11:39:56,756 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 769 [2022-11-16 11:39:56,756 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:39:56,756 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:39:56,762 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-11-16 11:39:56,762 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [766, 1, 1, 1] [2022-11-16 11:39:56,762 INFO L748 eck$LassoCheckResult]: Stem: 8518#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true; 8519#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_#t~nondet1#1, main_~x1~0#1, main_~x2~0#1;havoc main_~x1~0#1;havoc main_~x2~0#1;main_~x1~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~x2~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1; 8515#L19-2 [2022-11-16 11:39:56,763 INFO L750 eck$LassoCheckResult]: Loop: 8515#L19-2 assume !!(main_~x1~0#1 <= 10);main_~x2~0#1 := 1000; 8516#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8520#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9285#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9284#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9283#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9282#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9281#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9280#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9279#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9278#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9277#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9276#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9275#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9274#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9273#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9272#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9271#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9270#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9269#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9268#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9267#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9266#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9265#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9264#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9263#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9262#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9261#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9260#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9259#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9258#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9257#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9256#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9255#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9254#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9253#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9252#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9251#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9250#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9249#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9248#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9247#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9246#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9245#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9244#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9243#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9242#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9241#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9240#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9239#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9238#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9237#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9236#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9235#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9234#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9233#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9232#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9231#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9230#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9229#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9228#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9227#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9226#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9225#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9224#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9223#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9222#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9221#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9220#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9219#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9218#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9217#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9216#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9215#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9214#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9213#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9212#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9211#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9210#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9209#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9208#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9207#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9206#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9205#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9204#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9203#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9202#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9201#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9200#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9199#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9198#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9197#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9196#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9195#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9194#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9193#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9192#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9191#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9190#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9189#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9188#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9187#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9186#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9185#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9184#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9183#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9182#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9181#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9180#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9179#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9178#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9177#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9176#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9175#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9174#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9173#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9172#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9171#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9170#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9169#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9168#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9167#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9166#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9165#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9164#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9163#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9162#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9161#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9160#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9159#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9158#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9157#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9156#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9155#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9154#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9153#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9152#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9151#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9150#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9149#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9148#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9147#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9146#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9145#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9144#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9143#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9142#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9141#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9140#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9139#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9138#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9137#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9136#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9135#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9134#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9133#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9132#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9131#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9130#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9129#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9128#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9127#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9126#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9125#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9124#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9123#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9122#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9121#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9120#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9119#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9118#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9117#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9116#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9115#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9114#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9113#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9112#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9111#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9110#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9109#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9108#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9107#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9106#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9105#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9104#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9103#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9102#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9101#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9100#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9099#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9098#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9097#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9096#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9095#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9094#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9093#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9092#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9091#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9090#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9089#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9088#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9087#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9086#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9085#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9084#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9083#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9082#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9081#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9080#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9079#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9078#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9077#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9076#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9075#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9074#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9073#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9072#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9071#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9070#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9069#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9068#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9067#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9066#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9065#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9064#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9063#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9062#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9061#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9060#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9059#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9058#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9057#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9056#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9055#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9054#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9053#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9052#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9051#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9050#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9049#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9048#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9047#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9046#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9045#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9044#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9043#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9042#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9041#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9040#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9039#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9038#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9037#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9036#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9035#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9034#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9033#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9032#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9031#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9030#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9029#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9028#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9027#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9026#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9025#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9024#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9023#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9022#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9021#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9020#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9019#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9018#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9017#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9016#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9015#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9014#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9013#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9012#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9011#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9010#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9009#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9008#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9007#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9006#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9005#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9004#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9003#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9002#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9001#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 9000#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8999#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8998#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8997#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8996#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8995#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8994#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8993#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8992#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8991#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8990#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8989#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8988#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8987#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8986#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8985#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8984#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8983#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8982#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8981#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8980#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8979#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8978#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8977#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8976#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8975#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8974#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8973#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8972#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8971#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8970#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8969#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8968#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8967#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8966#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8965#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8964#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8963#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8962#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8961#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8960#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8959#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8958#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8957#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8956#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8955#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8954#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8953#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8952#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8951#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8950#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8949#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8948#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8947#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8946#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8945#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8944#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8943#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8942#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8941#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8940#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8939#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8938#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8937#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8936#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8935#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8934#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8933#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8932#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8931#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8930#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8929#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8928#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8927#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8926#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8925#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8924#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8923#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8922#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8921#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8920#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8919#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8918#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8917#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8916#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8915#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8914#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8913#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8912#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8911#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8910#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8909#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8908#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8907#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8906#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8905#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8904#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8903#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8902#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8901#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8900#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8899#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8898#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8897#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8896#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8895#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8894#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8893#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8892#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8891#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8890#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8889#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8888#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8887#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8886#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8885#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8884#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8883#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8882#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8881#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8880#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8879#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8878#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8877#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8876#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8875#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8874#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8873#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8872#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8871#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8870#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8869#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8868#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8867#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8866#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8865#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8864#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8863#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8862#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8861#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8860#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8859#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8858#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8857#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8856#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8855#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8854#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8853#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8852#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8851#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8850#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8849#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8848#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8847#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8846#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8845#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8844#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8843#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8842#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8841#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8840#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8839#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8838#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8837#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8836#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8835#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8834#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8833#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8832#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8831#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8830#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8829#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8828#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8827#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8826#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8825#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8824#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8823#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8822#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8821#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8820#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8819#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8818#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8817#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8816#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8815#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8814#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8813#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8812#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8811#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8810#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8809#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8808#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8807#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8806#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8805#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8804#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8803#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8802#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8801#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8800#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8799#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8798#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8797#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8796#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8795#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8794#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8793#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8792#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8791#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8790#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8789#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8788#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8787#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8786#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8785#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8784#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8783#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8782#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8781#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8780#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8779#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8778#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8777#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8776#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8775#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8774#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8773#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8772#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8771#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8770#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8769#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8768#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8767#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8766#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8765#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8764#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8763#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8762#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8761#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8760#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8759#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8758#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8757#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8756#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8755#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8754#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8753#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8752#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8751#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8750#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8749#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8748#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8747#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8746#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8745#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8744#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8743#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8742#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8741#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8740#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8739#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8738#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8737#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8736#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8735#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8734#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8733#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8732#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8731#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8730#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8729#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8728#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8727#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8726#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8725#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8724#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8723#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8722#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8721#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8720#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8719#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8718#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8717#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8716#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8715#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8714#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8713#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8712#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8711#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8710#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8709#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8708#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8707#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8706#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8705#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8704#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8703#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8702#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8701#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8700#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8699#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8698#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8697#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8696#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8695#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8694#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8693#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8692#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8691#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8690#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8689#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8688#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8687#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8686#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8685#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8684#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8683#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8682#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8681#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8680#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8679#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8678#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8677#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8676#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8675#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8674#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8673#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8672#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8671#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8670#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8669#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8668#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8667#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8666#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8665#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8664#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8663#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8662#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8661#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8660#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8659#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8658#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8657#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8656#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8655#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8654#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8653#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8652#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8651#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8650#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8649#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8648#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8647#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8646#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8645#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8644#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8643#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8642#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8641#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8640#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8639#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8638#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8637#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8636#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8635#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8634#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8633#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8632#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8631#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8630#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8629#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8628#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8627#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8626#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8625#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8624#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8623#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8622#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8621#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8620#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8619#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8618#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8617#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8616#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8615#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8614#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8613#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8612#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8611#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8610#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8609#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8608#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8607#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8606#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8605#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8604#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8603#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8602#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8601#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8600#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8599#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8598#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8597#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8596#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8595#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8594#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8593#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8592#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8591#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8590#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8589#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8588#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8587#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8586#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8585#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8584#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8583#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8582#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8581#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8580#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8579#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8578#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8577#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8576#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8575#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8574#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8573#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8572#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8571#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8570#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8569#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8568#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8567#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8566#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8565#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8564#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8563#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8562#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8561#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8560#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8559#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8558#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8557#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8556#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8555#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8554#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8553#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8552#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8551#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8550#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8549#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8548#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8547#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8546#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8545#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8544#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8543#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8542#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8541#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8540#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8539#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8538#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8537#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8536#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8535#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8534#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8533#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8532#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8531#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8530#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8529#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8528#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8527#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8526#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8525#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8524#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8523#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8522#L21-2 assume !!(main_~x2~0#1 > 1);main_~x2~0#1 := main_~x2~0#1 - 1; 8521#L21-2 assume !(main_~x2~0#1 > 1); 8517#L21-3 main_~x1~0#1 := 1 + main_~x1~0#1; 8515#L19-2 [2022-11-16 11:39:56,764 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:39:56,764 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 10 times [2022-11-16 11:39:56,764 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:39:56,765 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1893396237] [2022-11-16 11:39:56,765 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:39:56,765 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:39:56,767 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:39:56,767 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:39:56,768 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:39:56,768 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:39:56,769 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:39:56,769 INFO L85 PathProgramCache]: Analyzing trace with hash 1055916016, now seen corresponding path program 9 times [2022-11-16 11:39:56,769 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:39:56,769 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [809192467] [2022-11-16 11:39:56,770 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:39:56,770 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:40:00,236 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:45:54,822 INFO L134 CoverageAnalysis]: Checked inductivity of 293761 backedges. 0 proven. 293761 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:45:54,823 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:45:54,823 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [809192467] [2022-11-16 11:45:54,823 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [809192467] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:45:54,823 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1356754828] [2022-11-16 11:45:54,823 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-16 11:45:54,824 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:45:54,824 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21e01fdd-cc36-4b11-ab5f-0d9093cc2036/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:45:54,827 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21e01fdd-cc36-4b11-ab5f-0d9093cc2036/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:45:54,829 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_21e01fdd-cc36-4b11-ab5f-0d9093cc2036/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2022-11-16 11:45:58,161 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 384 check-sat command(s) [2022-11-16 11:45:58,161 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-16 11:45:58,202 INFO L263 TraceCheckSpWp]: Trace formula consists of 2306 conjuncts, 768 conjunts are in the unsatisfiable core [2022-11-16 11:45:58,217 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:45:59,628 INFO L134 CoverageAnalysis]: Checked inductivity of 293761 backedges. 0 proven. 293761 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:45:59,628 INFO L328 TraceCheckSpWp]: Computing backward predicates...