./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/termination-15/array16_alloca_fixed.i --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version e04fb08f Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/termination-15/array16_alloca_fixed.i -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/config/svcomp-Termination-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8 --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 2a580f3a42bca030605af1bbd4c6a77550e46d88a6197c1e34cf45bb050eadef --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-e04fb08 [2022-11-16 11:25:43,752 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-11-16 11:25:43,754 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-11-16 11:25:43,780 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-11-16 11:25:43,781 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-11-16 11:25:43,782 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-11-16 11:25:43,783 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-11-16 11:25:43,785 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-11-16 11:25:43,787 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-11-16 11:25:43,788 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-11-16 11:25:43,789 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-11-16 11:25:43,792 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-11-16 11:25:43,792 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-11-16 11:25:43,794 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-11-16 11:25:43,795 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-11-16 11:25:43,796 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-11-16 11:25:43,797 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-11-16 11:25:43,798 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-11-16 11:25:43,799 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-11-16 11:25:43,801 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-11-16 11:25:43,803 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-11-16 11:25:43,811 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-11-16 11:25:43,816 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-11-16 11:25:43,817 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-11-16 11:25:43,823 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-11-16 11:25:43,823 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-11-16 11:25:43,824 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-11-16 11:25:43,824 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-11-16 11:25:43,825 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-11-16 11:25:43,826 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-11-16 11:25:43,826 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-11-16 11:25:43,827 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-11-16 11:25:43,828 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-11-16 11:25:43,829 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-11-16 11:25:43,830 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-11-16 11:25:43,830 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-11-16 11:25:43,831 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-11-16 11:25:43,831 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-11-16 11:25:43,831 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-11-16 11:25:43,832 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-11-16 11:25:43,833 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-11-16 11:25:43,834 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/config/svcomp-Termination-64bit-Automizer_Default.epf [2022-11-16 11:25:43,856 INFO L113 SettingsManager]: Loading preferences was successful [2022-11-16 11:25:43,856 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-11-16 11:25:43,856 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-11-16 11:25:43,857 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-11-16 11:25:43,858 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-11-16 11:25:43,858 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-11-16 11:25:43,858 INFO L138 SettingsManager]: * Use SBE=true [2022-11-16 11:25:43,859 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-11-16 11:25:43,859 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-11-16 11:25:43,859 INFO L138 SettingsManager]: * Use old map elimination=false [2022-11-16 11:25:43,860 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-11-16 11:25:43,860 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-11-16 11:25:43,860 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-11-16 11:25:43,860 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-11-16 11:25:43,860 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-11-16 11:25:43,861 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-11-16 11:25:43,861 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-11-16 11:25:43,861 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-11-16 11:25:43,861 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-11-16 11:25:43,862 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-11-16 11:25:43,862 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-11-16 11:25:43,862 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-11-16 11:25:43,862 INFO L138 SettingsManager]: * Use constant arrays=true [2022-11-16 11:25:43,863 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-11-16 11:25:43,863 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-11-16 11:25:43,863 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-11-16 11:25:43,863 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-11-16 11:25:43,864 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-11-16 11:25:43,865 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-11-16 11:25:43,865 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 2a580f3a42bca030605af1bbd4c6a77550e46d88a6197c1e34cf45bb050eadef [2022-11-16 11:25:44,181 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-11-16 11:25:44,204 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-11-16 11:25:44,206 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-11-16 11:25:44,207 INFO L271 PluginConnector]: Initializing CDTParser... [2022-11-16 11:25:44,208 INFO L275 PluginConnector]: CDTParser initialized [2022-11-16 11:25:44,211 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/../../sv-benchmarks/c/termination-15/array16_alloca_fixed.i [2022-11-16 11:25:44,293 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/data/9ec66a3db/b6acd84160c54fd380064497110d3076/FLAGe916e4cfc [2022-11-16 11:25:44,894 INFO L306 CDTParser]: Found 1 translation units. [2022-11-16 11:25:44,895 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/sv-benchmarks/c/termination-15/array16_alloca_fixed.i [2022-11-16 11:25:44,904 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/data/9ec66a3db/b6acd84160c54fd380064497110d3076/FLAGe916e4cfc [2022-11-16 11:25:45,215 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/data/9ec66a3db/b6acd84160c54fd380064497110d3076 [2022-11-16 11:25:45,219 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-11-16 11:25:45,225 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-11-16 11:25:45,228 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-11-16 11:25:45,229 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-11-16 11:25:45,232 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-11-16 11:25:45,233 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.11 11:25:45" (1/1) ... [2022-11-16 11:25:45,234 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@25c0d614 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:25:45, skipping insertion in model container [2022-11-16 11:25:45,234 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.11 11:25:45" (1/1) ... [2022-11-16 11:25:45,243 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-11-16 11:25:45,294 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-11-16 11:25:45,706 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-16 11:25:45,718 INFO L203 MainTranslator]: Completed pre-run [2022-11-16 11:25:45,777 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-16 11:25:45,804 INFO L208 MainTranslator]: Completed translation [2022-11-16 11:25:45,804 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:25:45 WrapperNode [2022-11-16 11:25:45,804 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-11-16 11:25:45,805 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-11-16 11:25:45,805 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-11-16 11:25:45,805 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-11-16 11:25:45,812 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:25:45" (1/1) ... [2022-11-16 11:25:45,825 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:25:45" (1/1) ... [2022-11-16 11:25:45,845 INFO L138 Inliner]: procedures = 151, calls = 10, calls flagged for inlining = 2, calls inlined = 2, statements flattened = 54 [2022-11-16 11:25:45,845 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-11-16 11:25:45,846 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-11-16 11:25:45,846 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-11-16 11:25:45,846 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-11-16 11:25:45,855 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:25:45" (1/1) ... [2022-11-16 11:25:45,856 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:25:45" (1/1) ... [2022-11-16 11:25:45,857 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:25:45" (1/1) ... [2022-11-16 11:25:45,858 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:25:45" (1/1) ... [2022-11-16 11:25:45,877 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:25:45" (1/1) ... [2022-11-16 11:25:45,880 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:25:45" (1/1) ... [2022-11-16 11:25:45,881 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:25:45" (1/1) ... [2022-11-16 11:25:45,882 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:25:45" (1/1) ... [2022-11-16 11:25:45,884 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-11-16 11:25:45,885 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-11-16 11:25:45,885 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-11-16 11:25:45,885 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-11-16 11:25:45,886 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:25:45" (1/1) ... [2022-11-16 11:25:45,892 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-16 11:25:45,904 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:25:45,924 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-16 11:25:45,949 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-11-16 11:25:45,976 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2022-11-16 11:25:45,977 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2022-11-16 11:25:45,977 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2022-11-16 11:25:45,978 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2022-11-16 11:25:45,978 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-11-16 11:25:45,978 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-11-16 11:25:46,054 INFO L235 CfgBuilder]: Building ICFG [2022-11-16 11:25:46,055 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-11-16 11:25:46,267 INFO L276 CfgBuilder]: Performing block encoding [2022-11-16 11:25:46,272 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-11-16 11:25:46,275 INFO L300 CfgBuilder]: Removed 2 assume(true) statements. [2022-11-16 11:25:46,277 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.11 11:25:46 BoogieIcfgContainer [2022-11-16 11:25:46,278 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-11-16 11:25:46,279 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-11-16 11:25:46,280 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-11-16 11:25:46,285 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-11-16 11:25:46,285 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-16 11:25:46,286 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 16.11 11:25:45" (1/3) ... [2022-11-16 11:25:46,287 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@d546eb9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 16.11 11:25:46, skipping insertion in model container [2022-11-16 11:25:46,287 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-16 11:25:46,288 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:25:45" (2/3) ... [2022-11-16 11:25:46,289 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@d546eb9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 16.11 11:25:46, skipping insertion in model container [2022-11-16 11:25:46,289 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-16 11:25:46,289 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.11 11:25:46" (3/3) ... [2022-11-16 11:25:46,290 INFO L332 chiAutomizerObserver]: Analyzing ICFG array16_alloca_fixed.i [2022-11-16 11:25:46,393 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-11-16 11:25:46,394 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-11-16 11:25:46,394 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-11-16 11:25:46,394 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-11-16 11:25:46,394 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-11-16 11:25:46,394 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-11-16 11:25:46,395 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-11-16 11:25:46,395 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-11-16 11:25:46,399 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 15 states, 14 states have (on average 1.5714285714285714) internal successors, (22), 14 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:25:46,439 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5 [2022-11-16 11:25:46,440 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:25:46,440 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:25:46,445 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1] [2022-11-16 11:25:46,446 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-11-16 11:25:46,446 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-11-16 11:25:46,446 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 15 states, 14 states have (on average 1.5714285714285714) internal successors, (22), 14 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:25:46,448 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5 [2022-11-16 11:25:46,448 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:25:46,448 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:25:46,449 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1] [2022-11-16 11:25:46,449 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-11-16 11:25:46,456 INFO L748 eck$LassoCheckResult]: Stem: 3#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 6#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 10#L367true assume !(main_~length~0#1 < 1); 7#L367-2true call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 4#L369true assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 5#L370-3true [2022-11-16 11:25:46,466 INFO L750 eck$LassoCheckResult]: Loop: 5#L370-3true assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12#L372true assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15#L370-2true main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5#L370-3true [2022-11-16 11:25:46,472 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:25:46,482 INFO L85 PathProgramCache]: Analyzing trace with hash 28695753, now seen corresponding path program 1 times [2022-11-16 11:25:46,496 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:25:46,497 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2001372680] [2022-11-16 11:25:46,497 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:25:46,497 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:25:46,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:25:46,590 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:25:46,603 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:25:46,642 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:25:46,645 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:25:46,645 INFO L85 PathProgramCache]: Analyzing trace with hash 51737, now seen corresponding path program 1 times [2022-11-16 11:25:46,646 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:25:46,647 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1522669140] [2022-11-16 11:25:46,648 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:25:46,649 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:25:46,680 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:25:46,685 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:25:46,708 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:25:46,718 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:25:46,724 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:25:46,729 INFO L85 PathProgramCache]: Analyzing trace with hash 176707665, now seen corresponding path program 1 times [2022-11-16 11:25:46,730 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:25:46,730 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [340465031] [2022-11-16 11:25:46,730 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:25:46,731 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:25:46,778 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:25:46,782 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:25:46,815 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:25:46,828 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:25:47,179 INFO L210 LassoAnalysis]: Preferences: [2022-11-16 11:25:47,180 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2022-11-16 11:25:47,180 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2022-11-16 11:25:47,180 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2022-11-16 11:25:47,180 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2022-11-16 11:25:47,181 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-16 11:25:47,181 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2022-11-16 11:25:47,181 INFO L132 ssoRankerPreferences]: Path of dumped script: [2022-11-16 11:25:47,181 INFO L133 ssoRankerPreferences]: Filename of dumped script: array16_alloca_fixed.i_Iteration1_Lasso [2022-11-16 11:25:47,181 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2022-11-16 11:25:47,182 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2022-11-16 11:25:47,203 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-16 11:25:47,214 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-16 11:25:47,226 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-16 11:25:47,233 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-16 11:25:47,239 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-16 11:25:47,242 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-16 11:25:47,385 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-16 11:25:47,388 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-16 11:25:47,391 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-16 11:25:47,394 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-16 11:25:47,396 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-16 11:25:47,400 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-16 11:25:47,761 INFO L294 LassoAnalysis]: Preprocessing complete. [2022-11-16 11:25:47,768 INFO L490 LassoAnalysis]: Using template 'affine'. [2022-11-16 11:25:47,770 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-16 11:25:47,770 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:25:47,775 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-16 11:25:47,781 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2022-11-16 11:25:47,781 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-16 11:25:47,795 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-16 11:25:47,795 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-16 11:25:47,795 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-16 11:25:47,796 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-16 11:25:47,796 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-16 11:25:47,798 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-16 11:25:47,798 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-16 11:25:47,808 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-16 11:25:47,817 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Forceful destruction successful, exit code 0 [2022-11-16 11:25:47,818 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-16 11:25:47,818 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:25:47,823 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-16 11:25:47,828 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-16 11:25:47,840 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-16 11:25:47,841 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-16 11:25:47,841 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-16 11:25:47,841 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-16 11:25:47,844 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-16 11:25:47,845 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-16 11:25:47,846 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2022-11-16 11:25:47,857 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-16 11:25:47,861 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Forceful destruction successful, exit code 0 [2022-11-16 11:25:47,862 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-16 11:25:47,862 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:25:47,864 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-16 11:25:47,868 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2022-11-16 11:25:47,868 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-16 11:25:47,881 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-16 11:25:47,881 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-16 11:25:47,881 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-16 11:25:47,882 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-16 11:25:47,882 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-16 11:25:47,885 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-16 11:25:47,886 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-16 11:25:47,898 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-16 11:25:47,902 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Ended with exit code 0 [2022-11-16 11:25:47,903 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-16 11:25:47,903 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:25:47,907 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-16 11:25:47,917 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-16 11:25:47,930 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2022-11-16 11:25:47,931 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-16 11:25:47,931 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-16 11:25:47,931 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-16 11:25:47,931 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-16 11:25:47,932 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-16 11:25:47,933 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-16 11:25:47,933 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-16 11:25:47,954 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-16 11:25:47,958 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Forceful destruction successful, exit code 0 [2022-11-16 11:25:47,959 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-16 11:25:47,959 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:25:47,960 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-16 11:25:47,967 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2022-11-16 11:25:47,967 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-16 11:25:47,979 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-16 11:25:47,980 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-16 11:25:47,980 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-16 11:25:47,980 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-16 11:25:47,980 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-16 11:25:47,981 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-16 11:25:47,981 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-16 11:25:47,994 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-16 11:25:48,003 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Forceful destruction successful, exit code 0 [2022-11-16 11:25:48,004 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-16 11:25:48,004 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:25:48,008 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-16 11:25:48,015 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2022-11-16 11:25:48,016 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-16 11:25:48,028 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-16 11:25:48,029 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-16 11:25:48,029 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-16 11:25:48,029 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-16 11:25:48,029 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-16 11:25:48,030 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-16 11:25:48,030 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-16 11:25:48,039 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-16 11:25:48,043 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Forceful destruction successful, exit code 0 [2022-11-16 11:25:48,044 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-16 11:25:48,044 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:25:48,045 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-16 11:25:48,056 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-16 11:25:48,068 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-16 11:25:48,069 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-16 11:25:48,069 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-16 11:25:48,069 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-16 11:25:48,070 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2022-11-16 11:25:48,074 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-16 11:25:48,075 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-16 11:25:48,098 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-16 11:25:48,102 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Forceful destruction successful, exit code 0 [2022-11-16 11:25:48,103 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-16 11:25:48,103 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:25:48,104 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-16 11:25:48,111 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-16 11:25:48,124 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-16 11:25:48,124 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-16 11:25:48,124 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-16 11:25:48,124 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-16 11:25:48,124 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2022-11-16 11:25:48,128 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-16 11:25:48,129 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-16 11:25:48,140 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-16 11:25:48,149 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Forceful destruction successful, exit code 0 [2022-11-16 11:25:48,149 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-16 11:25:48,149 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:25:48,151 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-16 11:25:48,162 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2022-11-16 11:25:48,163 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-16 11:25:48,176 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-16 11:25:48,177 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-16 11:25:48,177 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-16 11:25:48,177 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-16 11:25:48,197 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-16 11:25:48,197 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-16 11:25:48,218 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2022-11-16 11:25:48,288 INFO L443 ModelExtractionUtils]: Simplification made 15 calls to the SMT solver. [2022-11-16 11:25:48,289 INFO L444 ModelExtractionUtils]: 7 out of 22 variables were initially zero. Simplification set additionally 11 variables to zero. [2022-11-16 11:25:48,290 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-16 11:25:48,291 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:25:48,331 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-16 11:25:48,332 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2022-11-16 11:25:48,333 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2022-11-16 11:25:48,345 INFO L438 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2022-11-16 11:25:48,345 INFO L513 LassoAnalysis]: Proved termination. [2022-11-16 11:25:48,345 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~i~0#1, ULTIMATE.start_main_~arr~0#1.offset, v_rep(select #length ULTIMATE.start_main_~arr~0#1.base)_1) = -4*ULTIMATE.start_main_~i~0#1 - 1*ULTIMATE.start_main_~arr~0#1.offset + 1*v_rep(select #length ULTIMATE.start_main_~arr~0#1.base)_1 Supporting invariants [] [2022-11-16 11:25:48,351 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Forceful destruction successful, exit code 0 [2022-11-16 11:25:48,371 INFO L156 tatePredicateManager]: 3 out of 3 supporting invariants were superfluous and have been removed [2022-11-16 11:25:48,409 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:25:48,424 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:25:48,426 INFO L263 TraceCheckSpWp]: Trace formula consists of 30 conjuncts, 2 conjunts are in the unsatisfiable core [2022-11-16 11:25:48,427 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:25:48,453 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:25:48,454 INFO L263 TraceCheckSpWp]: Trace formula consists of 24 conjuncts, 4 conjunts are in the unsatisfiable core [2022-11-16 11:25:48,455 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:25:48,487 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:25:48,528 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2022-11-16 11:25:48,530 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand has 15 states, 14 states have (on average 1.5714285714285714) internal successors, (22), 14 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 2.6666666666666665) internal successors, (8), 3 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:25:48,591 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand has 15 states, 14 states have (on average 1.5714285714285714) internal successors, (22), 14 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0). Second operand has 3 states, 3 states have (on average 2.6666666666666665) internal successors, (8), 3 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 35 states and 50 transitions. Complement of second has 7 states. [2022-11-16 11:25:48,593 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 5 states 1 stem states 2 non-accepting loop states 1 accepting loop states [2022-11-16 11:25:48,598 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 2.6666666666666665) internal successors, (8), 3 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:25:48,598 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 33 transitions. [2022-11-16 11:25:48,600 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 33 transitions. Stem has 5 letters. Loop has 3 letters. [2022-11-16 11:25:48,601 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-16 11:25:48,601 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 33 transitions. Stem has 8 letters. Loop has 3 letters. [2022-11-16 11:25:48,601 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-16 11:25:48,601 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 33 transitions. Stem has 5 letters. Loop has 6 letters. [2022-11-16 11:25:48,602 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-16 11:25:48,602 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 35 states and 50 transitions. [2022-11-16 11:25:48,605 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:25:48,608 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 35 states to 12 states and 17 transitions. [2022-11-16 11:25:48,610 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2022-11-16 11:25:48,610 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2022-11-16 11:25:48,610 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12 states and 17 transitions. [2022-11-16 11:25:48,611 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:25:48,611 INFO L218 hiAutomatonCegarLoop]: Abstraction has 12 states and 17 transitions. [2022-11-16 11:25:48,631 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12 states and 17 transitions. [2022-11-16 11:25:48,639 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12 to 12. [2022-11-16 11:25:48,639 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12 states, 12 states have (on average 1.4166666666666667) internal successors, (17), 11 states have internal predecessors, (17), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:25:48,641 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 17 transitions. [2022-11-16 11:25:48,642 INFO L240 hiAutomatonCegarLoop]: Abstraction has 12 states and 17 transitions. [2022-11-16 11:25:48,642 INFO L428 stractBuchiCegarLoop]: Abstraction has 12 states and 17 transitions. [2022-11-16 11:25:48,642 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-11-16 11:25:48,643 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12 states and 17 transitions. [2022-11-16 11:25:48,646 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:25:48,646 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:25:48,646 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:25:48,647 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:25:48,647 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-16 11:25:48,647 INFO L748 eck$LassoCheckResult]: Stem: 112#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 113#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 120#L367 assume !(main_~length~0#1 < 1); 114#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 115#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 116#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 117#L370-4 main_~j~0#1 := 0; 118#L378-2 [2022-11-16 11:25:48,647 INFO L750 eck$LassoCheckResult]: Loop: 118#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 119#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 118#L378-2 [2022-11-16 11:25:48,653 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:25:48,653 INFO L85 PathProgramCache]: Analyzing trace with hash 1806815510, now seen corresponding path program 1 times [2022-11-16 11:25:48,653 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:25:48,654 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1071897680] [2022-11-16 11:25:48,655 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:25:48,655 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:25:48,679 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Forceful destruction successful, exit code 0 [2022-11-16 11:25:48,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:25:48,771 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:25:48,771 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:25:48,771 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1071897680] [2022-11-16 11:25:48,772 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1071897680] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:25:48,772 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:25:48,772 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-11-16 11:25:48,773 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1047631607] [2022-11-16 11:25:48,773 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:25:48,775 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:25:48,775 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:25:48,776 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 1 times [2022-11-16 11:25:48,776 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:25:48,776 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1867176976] [2022-11-16 11:25:48,776 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:25:48,776 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:25:48,784 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:25:48,785 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:25:48,791 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:25:48,793 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:25:48,853 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:25:48,855 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 11:25:48,856 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2022-11-16 11:25:48,857 INFO L87 Difference]: Start difference. First operand 12 states and 17 transitions. cyclomatic complexity: 7 Second operand has 4 states, 4 states have (on average 1.75) internal successors, (7), 4 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:25:48,886 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:25:48,886 INFO L93 Difference]: Finished difference Result 14 states and 19 transitions. [2022-11-16 11:25:48,886 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14 states and 19 transitions. [2022-11-16 11:25:48,887 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:25:48,887 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14 states to 14 states and 19 transitions. [2022-11-16 11:25:48,888 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9 [2022-11-16 11:25:48,888 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2022-11-16 11:25:48,888 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14 states and 19 transitions. [2022-11-16 11:25:48,888 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:25:48,888 INFO L218 hiAutomatonCegarLoop]: Abstraction has 14 states and 19 transitions. [2022-11-16 11:25:48,889 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14 states and 19 transitions. [2022-11-16 11:25:48,889 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14 to 12. [2022-11-16 11:25:48,890 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12 states, 12 states have (on average 1.3333333333333333) internal successors, (16), 11 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:25:48,890 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 16 transitions. [2022-11-16 11:25:48,890 INFO L240 hiAutomatonCegarLoop]: Abstraction has 12 states and 16 transitions. [2022-11-16 11:25:48,895 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-16 11:25:48,896 INFO L428 stractBuchiCegarLoop]: Abstraction has 12 states and 16 transitions. [2022-11-16 11:25:48,896 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-11-16 11:25:48,896 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12 states and 16 transitions. [2022-11-16 11:25:48,896 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:25:48,897 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:25:48,897 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:25:48,897 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:25:48,897 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-16 11:25:48,898 INFO L748 eck$LassoCheckResult]: Stem: 145#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 146#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 153#L367 assume !(main_~length~0#1 < 1); 147#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 148#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 149#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 154#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 156#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 155#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 150#L370-4 main_~j~0#1 := 0; 151#L378-2 [2022-11-16 11:25:48,898 INFO L750 eck$LassoCheckResult]: Loop: 151#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 152#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 151#L378-2 [2022-11-16 11:25:48,898 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:25:48,898 INFO L85 PathProgramCache]: Analyzing trace with hash -1982565540, now seen corresponding path program 1 times [2022-11-16 11:25:48,898 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:25:48,899 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1668976608] [2022-11-16 11:25:48,899 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:25:48,899 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:25:48,939 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:25:48,940 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:25:48,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:25:48,969 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:25:48,970 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:25:48,970 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 2 times [2022-11-16 11:25:48,971 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:25:48,971 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1232601696] [2022-11-16 11:25:48,971 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:25:48,971 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:25:48,993 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:25:48,993 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:25:48,999 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:25:49,001 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:25:49,001 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:25:49,002 INFO L85 PathProgramCache]: Analyzing trace with hash 1719996831, now seen corresponding path program 1 times [2022-11-16 11:25:49,002 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:25:49,002 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [168229901] [2022-11-16 11:25:49,002 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:25:49,003 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:25:49,028 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:25:49,032 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:25:49,060 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:25:49,070 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:25:49,468 INFO L210 LassoAnalysis]: Preferences: [2022-11-16 11:25:49,468 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2022-11-16 11:25:49,469 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2022-11-16 11:25:49,469 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2022-11-16 11:25:49,469 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2022-11-16 11:25:49,469 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-16 11:25:49,469 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2022-11-16 11:25:49,469 INFO L132 ssoRankerPreferences]: Path of dumped script: [2022-11-16 11:25:49,469 INFO L133 ssoRankerPreferences]: Filename of dumped script: array16_alloca_fixed.i_Iteration3_Lasso [2022-11-16 11:25:49,469 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2022-11-16 11:25:49,469 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2022-11-16 11:25:49,472 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-16 11:25:49,475 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-16 11:25:49,478 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-16 11:25:49,482 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-16 11:25:49,485 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-16 11:25:49,678 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-16 11:25:49,681 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-16 11:25:49,683 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-16 11:25:49,686 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-16 11:25:49,688 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-16 11:25:49,692 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-16 11:25:50,075 INFO L294 LassoAnalysis]: Preprocessing complete. [2022-11-16 11:25:50,076 INFO L490 LassoAnalysis]: Using template 'affine'. [2022-11-16 11:25:50,076 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-16 11:25:50,076 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:25:50,078 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-16 11:25:50,088 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-16 11:25:50,101 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-16 11:25:50,101 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-16 11:25:50,101 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-16 11:25:50,101 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-16 11:25:50,101 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-16 11:25:50,102 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-16 11:25:50,102 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-16 11:25:50,103 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2022-11-16 11:25:50,111 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-16 11:25:50,120 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Forceful destruction successful, exit code 0 [2022-11-16 11:25:50,120 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-16 11:25:50,120 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:25:50,122 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-16 11:25:50,131 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-16 11:25:50,144 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-16 11:25:50,144 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-16 11:25:50,144 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-16 11:25:50,144 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-16 11:25:50,144 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-16 11:25:50,145 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-16 11:25:50,145 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-16 11:25:50,146 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Waiting until timeout for monitored process [2022-11-16 11:25:50,159 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-16 11:25:50,167 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Forceful destruction successful, exit code 0 [2022-11-16 11:25:50,168 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-16 11:25:50,168 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:25:50,169 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-16 11:25:50,179 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-16 11:25:50,192 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-16 11:25:50,192 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-16 11:25:50,192 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-16 11:25:50,192 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-16 11:25:50,192 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Waiting until timeout for monitored process [2022-11-16 11:25:50,194 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-16 11:25:50,195 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-16 11:25:50,222 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-16 11:25:50,230 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Forceful destruction successful, exit code 0 [2022-11-16 11:25:50,231 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-16 11:25:50,231 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:25:50,232 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-16 11:25:50,241 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-16 11:25:50,253 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-16 11:25:50,253 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-16 11:25:50,253 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-16 11:25:50,253 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-16 11:25:50,253 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-16 11:25:50,254 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-16 11:25:50,254 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-16 11:25:50,256 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Waiting until timeout for monitored process [2022-11-16 11:25:50,270 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-16 11:25:50,278 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Forceful destruction successful, exit code 0 [2022-11-16 11:25:50,279 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-16 11:25:50,279 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:25:50,280 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-16 11:25:50,284 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-16 11:25:50,296 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-16 11:25:50,296 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-16 11:25:50,297 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-16 11:25:50,297 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-16 11:25:50,300 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Waiting until timeout for monitored process [2022-11-16 11:25:50,308 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-16 11:25:50,308 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-16 11:25:50,326 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2022-11-16 11:25:50,354 INFO L443 ModelExtractionUtils]: Simplification made 10 calls to the SMT solver. [2022-11-16 11:25:50,354 INFO L444 ModelExtractionUtils]: 17 out of 25 variables were initially zero. Simplification set additionally 5 variables to zero. [2022-11-16 11:25:50,354 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-16 11:25:50,354 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:25:50,355 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-16 11:25:50,364 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2022-11-16 11:25:50,376 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Waiting until timeout for monitored process [2022-11-16 11:25:50,392 INFO L438 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2022-11-16 11:25:50,392 INFO L513 LassoAnalysis]: Proved termination. [2022-11-16 11:25:50,392 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~length~0#1, ULTIMATE.start_main_~j~0#1) = 1*ULTIMATE.start_main_~length~0#1 - 1*ULTIMATE.start_main_~j~0#1 Supporting invariants [] [2022-11-16 11:25:50,396 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Forceful destruction successful, exit code 0 [2022-11-16 11:25:50,410 INFO L156 tatePredicateManager]: 3 out of 3 supporting invariants were superfluous and have been removed [2022-11-16 11:25:50,426 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:25:50,450 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:25:50,451 INFO L263 TraceCheckSpWp]: Trace formula consists of 48 conjuncts, 2 conjunts are in the unsatisfiable core [2022-11-16 11:25:50,451 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:25:50,480 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:25:50,481 INFO L263 TraceCheckSpWp]: Trace formula consists of 14 conjuncts, 4 conjunts are in the unsatisfiable core [2022-11-16 11:25:50,482 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:25:50,495 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:25:50,496 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2022-11-16 11:25:50,496 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 12 states and 16 transitions. cyclomatic complexity: 6 Second operand has 3 states, 3 states have (on average 4.0) internal successors, (12), 3 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:25:50,513 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 12 states and 16 transitions. cyclomatic complexity: 6. Second operand has 3 states, 3 states have (on average 4.0) internal successors, (12), 3 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 16 states and 22 transitions. Complement of second has 5 states. [2022-11-16 11:25:50,515 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2022-11-16 11:25:50,516 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 4.0) internal successors, (12), 3 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:25:50,516 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 14 transitions. [2022-11-16 11:25:50,516 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 14 transitions. Stem has 10 letters. Loop has 2 letters. [2022-11-16 11:25:50,516 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-16 11:25:50,517 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 14 transitions. Stem has 12 letters. Loop has 2 letters. [2022-11-16 11:25:50,517 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-16 11:25:50,517 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 14 transitions. Stem has 10 letters. Loop has 4 letters. [2022-11-16 11:25:50,517 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-16 11:25:50,517 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 16 states and 22 transitions. [2022-11-16 11:25:50,518 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:25:50,519 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 16 states to 16 states and 22 transitions. [2022-11-16 11:25:50,519 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2022-11-16 11:25:50,519 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11 [2022-11-16 11:25:50,519 INFO L73 IsDeterministic]: Start isDeterministic. Operand 16 states and 22 transitions. [2022-11-16 11:25:50,520 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-16 11:25:50,520 INFO L218 hiAutomatonCegarLoop]: Abstraction has 16 states and 22 transitions. [2022-11-16 11:25:50,520 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16 states and 22 transitions. [2022-11-16 11:25:50,521 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16 to 16. [2022-11-16 11:25:50,521 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16 states, 16 states have (on average 1.375) internal successors, (22), 15 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:25:50,522 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16 states to 16 states and 22 transitions. [2022-11-16 11:25:50,522 INFO L240 hiAutomatonCegarLoop]: Abstraction has 16 states and 22 transitions. [2022-11-16 11:25:50,522 INFO L428 stractBuchiCegarLoop]: Abstraction has 16 states and 22 transitions. [2022-11-16 11:25:50,522 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-11-16 11:25:50,522 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16 states and 22 transitions. [2022-11-16 11:25:50,523 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:25:50,523 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:25:50,523 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:25:50,524 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:25:50,524 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-16 11:25:50,524 INFO L748 eck$LassoCheckResult]: Stem: 241#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 242#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 252#L367 assume !(main_~length~0#1 < 1); 243#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 244#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 245#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 253#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 255#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 254#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 246#L370-4 main_~j~0#1 := 0; 247#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 248#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 249#L378-2 [2022-11-16 11:25:50,525 INFO L750 eck$LassoCheckResult]: Loop: 249#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 256#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 249#L378-2 [2022-11-16 11:25:50,525 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:25:50,525 INFO L85 PathProgramCache]: Analyzing trace with hash 1719996833, now seen corresponding path program 1 times [2022-11-16 11:25:50,525 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:25:50,526 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [405074095] [2022-11-16 11:25:50,526 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:25:50,526 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:25:50,548 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:25:50,799 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Forceful destruction successful, exit code 0 [2022-11-16 11:25:51,082 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:25:51,082 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:25:51,083 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [405074095] [2022-11-16 11:25:51,083 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [405074095] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:25:51,084 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2086821684] [2022-11-16 11:25:51,084 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:25:51,084 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:25:51,084 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:25:51,087 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:25:51,110 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Waiting until timeout for monitored process [2022-11-16 11:25:51,145 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:25:51,146 INFO L263 TraceCheckSpWp]: Trace formula consists of 59 conjuncts, 17 conjunts are in the unsatisfiable core [2022-11-16 11:25:51,148 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:25:51,186 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2022-11-16 11:25:51,259 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 11 [2022-11-16 11:25:51,271 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:25:51,272 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:25:51,392 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2022-11-16 11:25:51,398 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 20 [2022-11-16 11:25:51,417 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:25:51,417 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2086821684] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:25:51,417 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-16 11:25:51,417 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 7, 6] total 14 [2022-11-16 11:25:51,418 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1661208783] [2022-11-16 11:25:51,418 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-16 11:25:51,418 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:25:51,419 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:25:51,419 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 3 times [2022-11-16 11:25:51,419 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:25:51,423 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [646533447] [2022-11-16 11:25:51,423 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:25:51,423 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:25:51,434 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:25:51,434 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:25:51,438 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:25:51,442 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:25:51,501 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:25:51,503 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2022-11-16 11:25:51,503 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=51, Invalid=159, Unknown=0, NotChecked=0, Total=210 [2022-11-16 11:25:51,504 INFO L87 Difference]: Start difference. First operand 16 states and 22 transitions. cyclomatic complexity: 9 Second operand has 15 states, 14 states have (on average 1.7857142857142858) internal successors, (25), 15 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:25:51,715 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:25:51,715 INFO L93 Difference]: Finished difference Result 30 states and 41 transitions. [2022-11-16 11:25:51,715 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 30 states and 41 transitions. [2022-11-16 11:25:51,716 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-16 11:25:51,717 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 30 states to 29 states and 40 transitions. [2022-11-16 11:25:51,717 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16 [2022-11-16 11:25:51,717 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16 [2022-11-16 11:25:51,717 INFO L73 IsDeterministic]: Start isDeterministic. Operand 29 states and 40 transitions. [2022-11-16 11:25:51,717 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-16 11:25:51,717 INFO L218 hiAutomatonCegarLoop]: Abstraction has 29 states and 40 transitions. [2022-11-16 11:25:51,718 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29 states and 40 transitions. [2022-11-16 11:25:51,719 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29 to 22. [2022-11-16 11:25:51,719 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22 states, 22 states have (on average 1.4090909090909092) internal successors, (31), 21 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:25:51,719 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22 states to 22 states and 31 transitions. [2022-11-16 11:25:51,720 INFO L240 hiAutomatonCegarLoop]: Abstraction has 22 states and 31 transitions. [2022-11-16 11:25:51,720 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2022-11-16 11:25:51,721 INFO L428 stractBuchiCegarLoop]: Abstraction has 22 states and 31 transitions. [2022-11-16 11:25:51,721 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-11-16 11:25:51,721 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22 states and 31 transitions. [2022-11-16 11:25:51,722 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:25:51,722 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:25:51,722 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:25:51,723 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:25:51,723 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-16 11:25:51,723 INFO L748 eck$LassoCheckResult]: Stem: 377#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 378#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 388#L367 assume !(main_~length~0#1 < 1); 379#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 380#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 381#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 389#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 392#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 397#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 396#L370-4 main_~j~0#1 := 0; 395#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 386#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 387#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 384#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 385#L378-2 [2022-11-16 11:25:51,723 INFO L750 eck$LassoCheckResult]: Loop: 385#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 393#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 385#L378-2 [2022-11-16 11:25:51,724 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:25:51,724 INFO L85 PathProgramCache]: Analyzing trace with hash -645453020, now seen corresponding path program 1 times [2022-11-16 11:25:51,724 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:25:51,724 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1495466453] [2022-11-16 11:25:51,725 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:25:51,725 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:25:51,736 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:25:51,845 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 1 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:25:51,845 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:25:51,845 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1495466453] [2022-11-16 11:25:51,845 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1495466453] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:25:51,846 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1586502264] [2022-11-16 11:25:51,846 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:25:51,846 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:25:51,846 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:25:51,847 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:25:51,882 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Waiting until timeout for monitored process [2022-11-16 11:25:51,920 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:25:51,921 INFO L263 TraceCheckSpWp]: Trace formula consists of 71 conjuncts, 6 conjunts are in the unsatisfiable core [2022-11-16 11:25:51,922 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:25:51,973 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 2 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:25:51,973 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:25:52,013 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 2 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:25:52,014 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1586502264] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:25:52,014 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-16 11:25:52,014 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7] total 11 [2022-11-16 11:25:52,014 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [102798904] [2022-11-16 11:25:52,015 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-16 11:25:52,015 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:25:52,015 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:25:52,016 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 4 times [2022-11-16 11:25:52,016 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:25:52,016 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [656280609] [2022-11-16 11:25:52,016 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:25:52,016 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:25:52,020 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:25:52,020 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:25:52,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:25:52,025 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:25:52,082 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:25:52,083 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2022-11-16 11:25:52,083 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=32, Invalid=78, Unknown=0, NotChecked=0, Total=110 [2022-11-16 11:25:52,084 INFO L87 Difference]: Start difference. First operand 22 states and 31 transitions. cyclomatic complexity: 13 Second operand has 11 states, 11 states have (on average 2.272727272727273) internal successors, (25), 11 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:25:52,198 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:25:52,198 INFO L93 Difference]: Finished difference Result 48 states and 64 transitions. [2022-11-16 11:25:52,198 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 48 states and 64 transitions. [2022-11-16 11:25:52,199 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-16 11:25:52,200 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 48 states to 43 states and 57 transitions. [2022-11-16 11:25:52,200 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21 [2022-11-16 11:25:52,200 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21 [2022-11-16 11:25:52,200 INFO L73 IsDeterministic]: Start isDeterministic. Operand 43 states and 57 transitions. [2022-11-16 11:25:52,201 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-16 11:25:52,201 INFO L218 hiAutomatonCegarLoop]: Abstraction has 43 states and 57 transitions. [2022-11-16 11:25:52,201 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43 states and 57 transitions. [2022-11-16 11:25:52,203 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43 to 37. [2022-11-16 11:25:52,204 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 37 states, 37 states have (on average 1.3513513513513513) internal successors, (50), 36 states have internal predecessors, (50), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:25:52,204 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37 states to 37 states and 50 transitions. [2022-11-16 11:25:52,205 INFO L240 hiAutomatonCegarLoop]: Abstraction has 37 states and 50 transitions. [2022-11-16 11:25:52,205 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2022-11-16 11:25:52,206 INFO L428 stractBuchiCegarLoop]: Abstraction has 37 states and 50 transitions. [2022-11-16 11:25:52,206 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-11-16 11:25:52,206 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 37 states and 50 transitions. [2022-11-16 11:25:52,207 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-16 11:25:52,207 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:25:52,207 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:25:52,208 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:25:52,208 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-16 11:25:52,208 INFO L748 eck$LassoCheckResult]: Stem: 549#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 550#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 560#L367 assume main_~length~0#1 < 1;main_~length~0#1 := 1; 551#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 552#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 580#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 578#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 576#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 577#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 575#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 574#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 572#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 555#L370-4 main_~j~0#1 := 0; 556#L378-2 [2022-11-16 11:25:52,208 INFO L750 eck$LassoCheckResult]: Loop: 556#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 557#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 556#L378-2 [2022-11-16 11:25:52,209 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:25:52,209 INFO L85 PathProgramCache]: Analyzing trace with hash 1080825110, now seen corresponding path program 1 times [2022-11-16 11:25:52,209 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:25:52,209 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [795746092] [2022-11-16 11:25:52,209 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:25:52,210 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:25:52,219 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:25:52,260 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 4 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:25:52,261 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:25:52,261 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [795746092] [2022-11-16 11:25:52,261 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [795746092] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:25:52,261 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [857784514] [2022-11-16 11:25:52,261 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:25:52,262 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:25:52,262 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:25:52,265 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:25:52,296 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Waiting until timeout for monitored process [2022-11-16 11:25:52,336 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:25:52,337 INFO L263 TraceCheckSpWp]: Trace formula consists of 72 conjuncts, 4 conjunts are in the unsatisfiable core [2022-11-16 11:25:52,338 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:25:52,376 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:25:52,377 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-16 11:25:52,377 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [857784514] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:25:52,377 INFO L184 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2022-11-16 11:25:52,377 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [5] total 7 [2022-11-16 11:25:52,378 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [870409103] [2022-11-16 11:25:52,378 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:25:52,378 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:25:52,379 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:25:52,379 INFO L85 PathProgramCache]: Analyzing trace with hash 2310, now seen corresponding path program 1 times [2022-11-16 11:25:52,379 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:25:52,379 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1963952636] [2022-11-16 11:25:52,379 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:25:52,379 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:25:52,383 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:25:52,384 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:25:52,386 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:25:52,388 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:25:52,443 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:25:52,444 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-16 11:25:52,444 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2022-11-16 11:25:52,444 INFO L87 Difference]: Start difference. First operand 37 states and 50 transitions. cyclomatic complexity: 20 Second operand has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:25:52,471 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:25:52,471 INFO L93 Difference]: Finished difference Result 30 states and 39 transitions. [2022-11-16 11:25:52,471 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 30 states and 39 transitions. [2022-11-16 11:25:52,472 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:25:52,472 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 30 states to 24 states and 32 transitions. [2022-11-16 11:25:52,472 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-16 11:25:52,473 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-16 11:25:52,473 INFO L73 IsDeterministic]: Start isDeterministic. Operand 24 states and 32 transitions. [2022-11-16 11:25:52,473 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-16 11:25:52,473 INFO L218 hiAutomatonCegarLoop]: Abstraction has 24 states and 32 transitions. [2022-11-16 11:25:52,473 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24 states and 32 transitions. [2022-11-16 11:25:52,475 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24 to 24. [2022-11-16 11:25:52,475 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24 states, 24 states have (on average 1.3333333333333333) internal successors, (32), 23 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:25:52,475 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24 states to 24 states and 32 transitions. [2022-11-16 11:25:52,476 INFO L240 hiAutomatonCegarLoop]: Abstraction has 24 states and 32 transitions. [2022-11-16 11:25:52,476 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-11-16 11:25:52,477 INFO L428 stractBuchiCegarLoop]: Abstraction has 24 states and 32 transitions. [2022-11-16 11:25:52,477 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-11-16 11:25:52,477 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 24 states and 32 transitions. [2022-11-16 11:25:52,478 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:25:52,478 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:25:52,478 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:25:52,478 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:25:52,479 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-16 11:25:52,479 INFO L748 eck$LassoCheckResult]: Stem: 662#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 663#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 673#L367 assume !(main_~length~0#1 < 1); 664#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 665#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 666#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 674#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 683#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 675#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 676#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 677#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 684#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 682#L370-4 main_~j~0#1 := 0; 681#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 669#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 670#L378-2 [2022-11-16 11:25:52,479 INFO L750 eck$LassoCheckResult]: Loop: 670#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 679#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 670#L378-2 [2022-11-16 11:25:52,479 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:25:52,480 INFO L85 PathProgramCache]: Analyzing trace with hash -1295959587, now seen corresponding path program 1 times [2022-11-16 11:25:52,480 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:25:52,480 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1010266952] [2022-11-16 11:25:52,480 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:25:52,480 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:25:52,500 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:25:52,977 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:25:52,977 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:25:52,977 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1010266952] [2022-11-16 11:25:52,977 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1010266952] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:25:52,978 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1258736422] [2022-11-16 11:25:52,978 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:25:52,978 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:25:52,978 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:25:52,982 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:25:53,014 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Waiting until timeout for monitored process [2022-11-16 11:25:53,047 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:25:53,048 INFO L263 TraceCheckSpWp]: Trace formula consists of 81 conjuncts, 22 conjunts are in the unsatisfiable core [2022-11-16 11:25:53,051 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:25:53,071 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-16 11:25:53,158 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:25:53,159 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 31 treesize of output 26 [2022-11-16 11:25:53,177 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:25:53,178 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 31 treesize of output 26 [2022-11-16 11:25:53,227 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 11 [2022-11-16 11:25:53,240 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:25:53,240 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:25:53,537 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 47 treesize of output 43 [2022-11-16 11:25:53,544 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 146 treesize of output 138 [2022-11-16 11:25:53,638 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:25:53,638 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1258736422] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:25:53,638 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-16 11:25:53,638 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 8] total 18 [2022-11-16 11:25:53,639 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [985332783] [2022-11-16 11:25:53,639 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-16 11:25:53,639 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:25:53,640 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:25:53,640 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 5 times [2022-11-16 11:25:53,641 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:25:53,641 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [122132082] [2022-11-16 11:25:53,641 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:25:53,641 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:25:53,646 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:25:53,647 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:25:53,650 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:25:53,652 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:25:53,709 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:25:53,710 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2022-11-16 11:25:53,711 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=74, Invalid=268, Unknown=0, NotChecked=0, Total=342 [2022-11-16 11:25:53,711 INFO L87 Difference]: Start difference. First operand 24 states and 32 transitions. cyclomatic complexity: 12 Second operand has 19 states, 18 states have (on average 1.8333333333333333) internal successors, (33), 19 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:25:53,988 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:25:53,988 INFO L93 Difference]: Finished difference Result 51 states and 68 transitions. [2022-11-16 11:25:53,988 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 51 states and 68 transitions. [2022-11-16 11:25:53,989 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 6 [2022-11-16 11:25:53,990 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 51 states to 50 states and 67 transitions. [2022-11-16 11:25:53,990 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 25 [2022-11-16 11:25:53,990 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 25 [2022-11-16 11:25:53,990 INFO L73 IsDeterministic]: Start isDeterministic. Operand 50 states and 67 transitions. [2022-11-16 11:25:53,990 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-16 11:25:53,990 INFO L218 hiAutomatonCegarLoop]: Abstraction has 50 states and 67 transitions. [2022-11-16 11:25:53,991 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50 states and 67 transitions. [2022-11-16 11:25:53,992 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50 to 30. [2022-11-16 11:25:53,993 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 30 states, 30 states have (on average 1.4) internal successors, (42), 29 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:25:53,993 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30 states to 30 states and 42 transitions. [2022-11-16 11:25:53,993 INFO L240 hiAutomatonCegarLoop]: Abstraction has 30 states and 42 transitions. [2022-11-16 11:25:53,994 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2022-11-16 11:25:53,994 INFO L428 stractBuchiCegarLoop]: Abstraction has 30 states and 42 transitions. [2022-11-16 11:25:53,995 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-11-16 11:25:53,995 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 30 states and 42 transitions. [2022-11-16 11:25:53,995 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:25:53,995 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:25:53,996 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:25:53,996 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:25:53,996 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-16 11:25:53,997 INFO L748 eck$LassoCheckResult]: Stem: 850#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 851#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 861#L367 assume !(main_~length~0#1 < 1); 852#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 853#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 854#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 862#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 871#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 863#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 864#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 866#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 878#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 855#L370-4 main_~j~0#1 := 0; 856#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 859#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 860#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 857#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 858#L378-2 [2022-11-16 11:25:53,997 INFO L750 eck$LassoCheckResult]: Loop: 858#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 868#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 858#L378-2 [2022-11-16 11:25:53,997 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:25:53,998 INFO L85 PathProgramCache]: Analyzing trace with hash 123352160, now seen corresponding path program 1 times [2022-11-16 11:25:53,998 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:25:53,998 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1319990038] [2022-11-16 11:25:53,998 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:25:53,998 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:25:54,015 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:25:54,243 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:25:54,243 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:25:54,243 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1319990038] [2022-11-16 11:25:54,243 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1319990038] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:25:54,243 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [326372451] [2022-11-16 11:25:54,244 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:25:54,244 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:25:54,244 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:25:54,247 INFO L229 MonitoredProcess]: Starting monitored process 22 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:25:54,249 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (22)] Waiting until timeout for monitored process [2022-11-16 11:25:54,318 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:25:54,320 INFO L263 TraceCheckSpWp]: Trace formula consists of 93 conjuncts, 19 conjunts are in the unsatisfiable core [2022-11-16 11:25:54,322 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:25:54,381 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 9 [2022-11-16 11:25:54,465 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-16 11:25:54,467 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:25:54,467 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:25:54,551 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 16 [2022-11-16 11:25:54,562 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 18 [2022-11-16 11:25:54,600 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:25:54,601 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [326372451] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:25:54,601 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-16 11:25:54,601 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 7] total 18 [2022-11-16 11:25:54,601 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1605765317] [2022-11-16 11:25:54,602 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-16 11:25:54,603 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:25:54,603 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:25:54,603 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 6 times [2022-11-16 11:25:54,604 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:25:54,604 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1515851251] [2022-11-16 11:25:54,604 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:25:54,604 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:25:54,610 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:25:54,610 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:25:54,614 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:25:54,616 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:25:54,670 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:25:54,671 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2022-11-16 11:25:54,671 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=63, Invalid=279, Unknown=0, NotChecked=0, Total=342 [2022-11-16 11:25:54,671 INFO L87 Difference]: Start difference. First operand 30 states and 42 transitions. cyclomatic complexity: 16 Second operand has 19 states, 18 states have (on average 2.111111111111111) internal successors, (38), 19 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:25:54,808 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:25:54,809 INFO L93 Difference]: Finished difference Result 43 states and 58 transitions. [2022-11-16 11:25:54,809 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 43 states and 58 transitions. [2022-11-16 11:25:54,810 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-16 11:25:54,812 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 43 states to 42 states and 57 transitions. [2022-11-16 11:25:54,813 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18 [2022-11-16 11:25:54,813 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18 [2022-11-16 11:25:54,813 INFO L73 IsDeterministic]: Start isDeterministic. Operand 42 states and 57 transitions. [2022-11-16 11:25:54,813 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-16 11:25:54,813 INFO L218 hiAutomatonCegarLoop]: Abstraction has 42 states and 57 transitions. [2022-11-16 11:25:54,814 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42 states and 57 transitions. [2022-11-16 11:25:54,821 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42 to 36. [2022-11-16 11:25:54,821 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 36 states, 36 states have (on average 1.3611111111111112) internal successors, (49), 35 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:25:54,825 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 49 transitions. [2022-11-16 11:25:54,826 INFO L240 hiAutomatonCegarLoop]: Abstraction has 36 states and 49 transitions. [2022-11-16 11:25:54,826 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2022-11-16 11:25:54,830 INFO L428 stractBuchiCegarLoop]: Abstraction has 36 states and 49 transitions. [2022-11-16 11:25:54,830 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-11-16 11:25:54,830 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 36 states and 49 transitions. [2022-11-16 11:25:54,831 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:25:54,831 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:25:54,831 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:25:54,834 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:25:54,834 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-16 11:25:54,835 INFO L748 eck$LassoCheckResult]: Stem: 1045#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1046#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 1056#L367 assume !(main_~length~0#1 < 1); 1047#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 1048#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 1049#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1057#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 1069#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1058#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1059#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 1064#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1065#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 1054#L370-4 main_~j~0#1 := 0; 1055#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1052#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 1053#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1050#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 1051#L378-2 [2022-11-16 11:25:54,835 INFO L750 eck$LassoCheckResult]: Loop: 1051#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1068#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 1051#L378-2 [2022-11-16 11:25:54,836 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:25:54,836 INFO L85 PathProgramCache]: Analyzing trace with hash -685994466, now seen corresponding path program 2 times [2022-11-16 11:25:54,836 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:25:54,837 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [51989786] [2022-11-16 11:25:54,837 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:25:54,837 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:25:54,880 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:25:55,237 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:25:55,237 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:25:55,237 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [51989786] [2022-11-16 11:25:55,238 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [51989786] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:25:55,238 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1187108395] [2022-11-16 11:25:55,238 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-16 11:25:55,238 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:25:55,238 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:25:55,246 INFO L229 MonitoredProcess]: Starting monitored process 23 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:25:55,280 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Waiting until timeout for monitored process [2022-11-16 11:25:55,325 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-16 11:25:55,326 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-16 11:25:55,327 INFO L263 TraceCheckSpWp]: Trace formula consists of 86 conjuncts, 21 conjunts are in the unsatisfiable core [2022-11-16 11:25:55,330 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:25:55,404 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 9 [2022-11-16 11:25:55,571 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 9 [2022-11-16 11:25:55,585 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:25:55,585 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:25:55,682 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2022-11-16 11:25:55,686 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 20 [2022-11-16 11:25:55,704 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:25:55,705 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1187108395] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:25:55,705 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-16 11:25:55,705 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 8] total 18 [2022-11-16 11:25:55,705 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [753376538] [2022-11-16 11:25:55,706 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-16 11:25:55,706 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:25:55,706 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:25:55,706 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 7 times [2022-11-16 11:25:55,707 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:25:55,707 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [938258479] [2022-11-16 11:25:55,707 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:25:55,707 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:25:55,711 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:25:55,711 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:25:55,713 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:25:55,715 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:25:55,768 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:25:55,769 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2022-11-16 11:25:55,769 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=63, Invalid=279, Unknown=0, NotChecked=0, Total=342 [2022-11-16 11:25:55,769 INFO L87 Difference]: Start difference. First operand 36 states and 49 transitions. cyclomatic complexity: 17 Second operand has 19 states, 18 states have (on average 2.0) internal successors, (36), 19 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:25:56,019 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:25:56,019 INFO L93 Difference]: Finished difference Result 53 states and 71 transitions. [2022-11-16 11:25:56,019 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 53 states and 71 transitions. [2022-11-16 11:25:56,020 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-16 11:25:56,020 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 53 states to 52 states and 70 transitions. [2022-11-16 11:25:56,021 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 23 [2022-11-16 11:25:56,021 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23 [2022-11-16 11:25:56,021 INFO L73 IsDeterministic]: Start isDeterministic. Operand 52 states and 70 transitions. [2022-11-16 11:25:56,021 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-16 11:25:56,021 INFO L218 hiAutomatonCegarLoop]: Abstraction has 52 states and 70 transitions. [2022-11-16 11:25:56,021 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52 states and 70 transitions. [2022-11-16 11:25:56,024 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52 to 41. [2022-11-16 11:25:56,024 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 41 states, 41 states have (on average 1.3902439024390243) internal successors, (57), 40 states have internal predecessors, (57), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:25:56,024 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41 states to 41 states and 57 transitions. [2022-11-16 11:25:56,024 INFO L240 hiAutomatonCegarLoop]: Abstraction has 41 states and 57 transitions. [2022-11-16 11:25:56,025 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2022-11-16 11:25:56,026 INFO L428 stractBuchiCegarLoop]: Abstraction has 41 states and 57 transitions. [2022-11-16 11:25:56,026 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-11-16 11:25:56,026 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 41 states and 57 transitions. [2022-11-16 11:25:56,027 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:25:56,027 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:25:56,027 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:25:56,027 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:25:56,027 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-16 11:25:56,028 INFO L748 eck$LassoCheckResult]: Stem: 1260#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1261#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 1271#L367 assume !(main_~length~0#1 < 1); 1262#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 1263#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 1264#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1272#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 1284#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1273#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1274#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1298#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1296#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1288#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1276#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1290#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 1289#L370-4 main_~j~0#1 := 0; 1283#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1267#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 1268#L378-2 [2022-11-16 11:25:56,028 INFO L750 eck$LassoCheckResult]: Loop: 1268#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1278#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 1268#L378-2 [2022-11-16 11:25:56,028 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:25:56,028 INFO L85 PathProgramCache]: Analyzing trace with hash 1062164513, now seen corresponding path program 2 times [2022-11-16 11:25:56,029 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:25:56,029 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1132864752] [2022-11-16 11:25:56,029 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:25:56,029 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:25:56,051 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:25:56,723 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:25:56,723 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:25:56,724 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1132864752] [2022-11-16 11:25:56,724 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1132864752] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:25:56,724 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [274938114] [2022-11-16 11:25:56,724 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-16 11:25:56,724 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:25:56,725 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:25:56,730 INFO L229 MonitoredProcess]: Starting monitored process 24 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:25:56,735 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (24)] Waiting until timeout for monitored process [2022-11-16 11:25:56,803 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-16 11:25:56,803 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-16 11:25:56,805 INFO L263 TraceCheckSpWp]: Trace formula consists of 103 conjuncts, 26 conjunts are in the unsatisfiable core [2022-11-16 11:25:56,808 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:25:56,839 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-16 11:25:56,910 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:25:56,911 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-16 11:25:56,928 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:25:56,929 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-16 11:25:56,982 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:25:56,983 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-16 11:25:57,000 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:25:57,004 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-16 11:25:57,064 INFO L173 IndexEqualityManager]: detected equality via solver [2022-11-16 11:25:57,066 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-16 11:25:57,067 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 21 treesize of output 12 [2022-11-16 11:25:57,078 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 2 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:25:57,078 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:25:57,801 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 55 treesize of output 51 [2022-11-16 11:25:57,812 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 86 treesize of output 74 [2022-11-16 11:25:57,883 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 1 proven. 10 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-16 11:25:57,884 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [274938114] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:25:57,884 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-16 11:25:57,884 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 9] total 25 [2022-11-16 11:25:57,884 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [797328677] [2022-11-16 11:25:57,884 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-16 11:25:57,885 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:25:57,885 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:25:57,885 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 8 times [2022-11-16 11:25:57,885 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:25:57,886 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [30448982] [2022-11-16 11:25:57,886 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:25:57,886 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:25:57,890 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:25:57,890 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:25:57,892 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:25:57,894 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:25:57,945 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:25:57,945 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2022-11-16 11:25:57,946 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=141, Invalid=509, Unknown=0, NotChecked=0, Total=650 [2022-11-16 11:25:57,946 INFO L87 Difference]: Start difference. First operand 41 states and 57 transitions. cyclomatic complexity: 21 Second operand has 26 states, 25 states have (on average 1.84) internal successors, (46), 26 states have internal predecessors, (46), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:25:58,181 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:25:58,181 INFO L93 Difference]: Finished difference Result 43 states and 58 transitions. [2022-11-16 11:25:58,181 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 43 states and 58 transitions. [2022-11-16 11:25:58,182 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:25:58,182 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 43 states to 42 states and 56 transitions. [2022-11-16 11:25:58,182 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17 [2022-11-16 11:25:58,183 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17 [2022-11-16 11:25:58,183 INFO L73 IsDeterministic]: Start isDeterministic. Operand 42 states and 56 transitions. [2022-11-16 11:25:58,183 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-16 11:25:58,183 INFO L218 hiAutomatonCegarLoop]: Abstraction has 42 states and 56 transitions. [2022-11-16 11:25:58,183 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42 states and 56 transitions. [2022-11-16 11:25:58,184 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42 to 27. [2022-11-16 11:25:58,184 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27 states, 27 states have (on average 1.2962962962962963) internal successors, (35), 26 states have internal predecessors, (35), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:25:58,185 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 35 transitions. [2022-11-16 11:25:58,185 INFO L240 hiAutomatonCegarLoop]: Abstraction has 27 states and 35 transitions. [2022-11-16 11:25:58,186 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2022-11-16 11:25:58,186 INFO L428 stractBuchiCegarLoop]: Abstraction has 27 states and 35 transitions. [2022-11-16 11:25:58,186 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-11-16 11:25:58,186 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27 states and 35 transitions. [2022-11-16 11:25:58,187 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:25:58,187 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:25:58,187 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:25:58,187 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:25:58,187 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-16 11:25:58,187 INFO L748 eck$LassoCheckResult]: Stem: 1484#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1485#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 1495#L367 assume !(main_~length~0#1 < 1); 1486#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 1487#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 1488#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1496#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 1510#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1497#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1498#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 1499#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1501#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 1505#L370-4 main_~j~0#1 := 0; 1504#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1503#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 1500#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1493#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 1494#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1491#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 1492#L378-2 [2022-11-16 11:25:58,188 INFO L750 eck$LassoCheckResult]: Loop: 1492#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1502#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 1492#L378-2 [2022-11-16 11:25:58,188 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:25:58,188 INFO L85 PathProgramCache]: Analyzing trace with hash -2110686111, now seen corresponding path program 3 times [2022-11-16 11:25:58,188 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:25:58,188 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [54926931] [2022-11-16 11:25:58,188 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:25:58,188 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:25:58,202 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:25:58,305 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 3 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:25:58,305 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:25:58,305 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [54926931] [2022-11-16 11:25:58,306 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [54926931] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:25:58,306 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1129303638] [2022-11-16 11:25:58,306 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-16 11:25:58,306 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:25:58,306 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:25:58,310 INFO L229 MonitoredProcess]: Starting monitored process 25 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:25:58,319 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (25)] Waiting until timeout for monitored process [2022-11-16 11:25:58,386 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2022-11-16 11:25:58,386 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-16 11:25:58,387 INFO L263 TraceCheckSpWp]: Trace formula consists of 98 conjuncts, 8 conjunts are in the unsatisfiable core [2022-11-16 11:25:58,388 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:25:58,457 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 6 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:25:58,458 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:25:58,514 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 6 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:25:58,514 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1129303638] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:25:58,515 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-16 11:25:58,515 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9] total 14 [2022-11-16 11:25:58,515 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [649940566] [2022-11-16 11:25:58,515 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-16 11:25:58,515 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:25:58,516 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:25:58,516 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 9 times [2022-11-16 11:25:58,516 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:25:58,517 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1305963828] [2022-11-16 11:25:58,517 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:25:58,517 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:25:58,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:25:58,521 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:25:58,523 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:25:58,531 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:25:58,583 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:25:58,583 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2022-11-16 11:25:58,584 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=49, Invalid=133, Unknown=0, NotChecked=0, Total=182 [2022-11-16 11:25:58,584 INFO L87 Difference]: Start difference. First operand 27 states and 35 transitions. cyclomatic complexity: 12 Second operand has 14 states, 14 states have (on average 2.2857142857142856) internal successors, (32), 14 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:25:58,695 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:25:58,695 INFO L93 Difference]: Finished difference Result 38 states and 47 transitions. [2022-11-16 11:25:58,696 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 38 states and 47 transitions. [2022-11-16 11:25:58,696 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:25:58,696 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 38 states to 32 states and 41 transitions. [2022-11-16 11:25:58,697 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-16 11:25:58,697 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-16 11:25:58,697 INFO L73 IsDeterministic]: Start isDeterministic. Operand 32 states and 41 transitions. [2022-11-16 11:25:58,697 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-16 11:25:58,697 INFO L218 hiAutomatonCegarLoop]: Abstraction has 32 states and 41 transitions. [2022-11-16 11:25:58,697 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32 states and 41 transitions. [2022-11-16 11:25:58,700 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32 to 29. [2022-11-16 11:25:58,700 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 29 states, 29 states have (on average 1.2758620689655173) internal successors, (37), 28 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:25:58,701 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29 states to 29 states and 37 transitions. [2022-11-16 11:25:58,701 INFO L240 hiAutomatonCegarLoop]: Abstraction has 29 states and 37 transitions. [2022-11-16 11:25:58,701 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2022-11-16 11:25:58,702 INFO L428 stractBuchiCegarLoop]: Abstraction has 29 states and 37 transitions. [2022-11-16 11:25:58,702 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-11-16 11:25:58,702 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 29 states and 37 transitions. [2022-11-16 11:25:58,702 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:25:58,703 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:25:58,703 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:25:58,704 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:25:58,704 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-16 11:25:58,705 INFO L748 eck$LassoCheckResult]: Stem: 1682#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1683#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 1693#L367 assume !(main_~length~0#1 < 1); 1684#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 1685#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 1686#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1694#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 1700#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1695#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1696#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 1710#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1709#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1702#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1698#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1708#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 1707#L370-4 main_~j~0#1 := 0; 1706#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1699#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 1705#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1689#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 1690#L378-2 [2022-11-16 11:25:58,706 INFO L750 eck$LassoCheckResult]: Loop: 1690#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1704#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 1690#L378-2 [2022-11-16 11:25:58,706 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:25:58,706 INFO L85 PathProgramCache]: Analyzing trace with hash -761055450, now seen corresponding path program 2 times [2022-11-16 11:25:58,706 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:25:58,707 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1912284870] [2022-11-16 11:25:58,707 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:25:58,707 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:25:58,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:25:59,218 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:25:59,218 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:25:59,219 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1912284870] [2022-11-16 11:25:59,219 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1912284870] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:25:59,219 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1821092064] [2022-11-16 11:25:59,219 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-16 11:25:59,219 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:25:59,219 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:25:59,226 INFO L229 MonitoredProcess]: Starting monitored process 26 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:25:59,244 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (26)] Waiting until timeout for monitored process [2022-11-16 11:25:59,297 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-16 11:25:59,297 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-16 11:25:59,298 INFO L263 TraceCheckSpWp]: Trace formula consists of 108 conjuncts, 26 conjunts are in the unsatisfiable core [2022-11-16 11:25:59,301 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:25:59,369 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-16 11:25:59,473 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:25:59,475 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 26 [2022-11-16 11:25:59,487 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:25:59,488 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 26 [2022-11-16 11:25:59,602 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 9 [2022-11-16 11:25:59,616 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:25:59,616 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:25:59,797 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2022-11-16 11:25:59,801 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 20 [2022-11-16 11:25:59,818 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:25:59,819 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1821092064] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:25:59,819 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-16 11:25:59,819 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 11, 10] total 22 [2022-11-16 11:25:59,819 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1898679308] [2022-11-16 11:25:59,819 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-16 11:25:59,820 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:25:59,820 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:25:59,821 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 10 times [2022-11-16 11:25:59,821 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:25:59,821 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [360204389] [2022-11-16 11:25:59,821 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:25:59,821 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:25:59,830 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:25:59,830 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:25:59,834 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:25:59,836 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:25:59,892 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:25:59,892 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2022-11-16 11:25:59,893 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=87, Invalid=419, Unknown=0, NotChecked=0, Total=506 [2022-11-16 11:25:59,893 INFO L87 Difference]: Start difference. First operand 29 states and 37 transitions. cyclomatic complexity: 12 Second operand has 23 states, 22 states have (on average 1.9090909090909092) internal successors, (42), 23 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:26:00,151 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:26:00,152 INFO L93 Difference]: Finished difference Result 33 states and 41 transitions. [2022-11-16 11:26:00,152 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 33 states and 41 transitions. [2022-11-16 11:26:00,152 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:26:00,152 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 33 states to 32 states and 40 transitions. [2022-11-16 11:26:00,153 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-16 11:26:00,153 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-16 11:26:00,153 INFO L73 IsDeterministic]: Start isDeterministic. Operand 32 states and 40 transitions. [2022-11-16 11:26:00,153 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-16 11:26:00,153 INFO L218 hiAutomatonCegarLoop]: Abstraction has 32 states and 40 transitions. [2022-11-16 11:26:00,153 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32 states and 40 transitions. [2022-11-16 11:26:00,154 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32 to 24. [2022-11-16 11:26:00,154 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24 states, 24 states have (on average 1.25) internal successors, (30), 23 states have internal predecessors, (30), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:26:00,155 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24 states to 24 states and 30 transitions. [2022-11-16 11:26:00,155 INFO L240 hiAutomatonCegarLoop]: Abstraction has 24 states and 30 transitions. [2022-11-16 11:26:00,159 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2022-11-16 11:26:00,159 INFO L428 stractBuchiCegarLoop]: Abstraction has 24 states and 30 transitions. [2022-11-16 11:26:00,160 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-11-16 11:26:00,160 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 24 states and 30 transitions. [2022-11-16 11:26:00,160 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:26:00,160 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:26:00,160 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:26:00,161 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [3, 3, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:26:00,161 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-16 11:26:00,161 INFO L748 eck$LassoCheckResult]: Stem: 1890#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1891#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 1901#L367 assume !(main_~length~0#1 < 1); 1892#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 1893#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 1894#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1902#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 1905#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1903#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1904#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 1907#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1908#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1910#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 1913#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1909#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 1895#L370-4 main_~j~0#1 := 0; 1896#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1899#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 1900#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1906#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 1912#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1897#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 1898#L378-2 [2022-11-16 11:26:00,161 INFO L750 eck$LassoCheckResult]: Loop: 1898#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1911#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 1898#L378-2 [2022-11-16 11:26:00,162 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:26:00,162 INFO L85 PathProgramCache]: Analyzing trace with hash -1622874713, now seen corresponding path program 4 times [2022-11-16 11:26:00,162 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:26:00,162 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [156380562] [2022-11-16 11:26:00,162 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:26:00,162 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:26:00,197 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:26:00,682 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:26:00,683 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:26:00,683 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [156380562] [2022-11-16 11:26:00,683 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [156380562] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:26:00,683 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [784511802] [2022-11-16 11:26:00,683 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-16 11:26:00,684 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:26:00,684 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:26:00,689 INFO L229 MonitoredProcess]: Starting monitored process 27 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:26:00,706 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (27)] Waiting until timeout for monitored process [2022-11-16 11:26:00,759 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-16 11:26:00,759 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-16 11:26:00,761 INFO L263 TraceCheckSpWp]: Trace formula consists of 97 conjuncts, 21 conjunts are in the unsatisfiable core [2022-11-16 11:26:00,762 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:26:00,800 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-16 11:26:00,952 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 11 [2022-11-16 11:26:00,955 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:26:00,956 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:26:01,058 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2022-11-16 11:26:01,062 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 20 [2022-11-16 11:26:01,088 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:26:01,089 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [784511802] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:26:01,089 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-16 11:26:01,089 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 10, 10] total 16 [2022-11-16 11:26:01,089 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1428470710] [2022-11-16 11:26:01,090 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-16 11:26:01,090 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:26:01,090 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:26:01,091 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 11 times [2022-11-16 11:26:01,091 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:26:01,091 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1204097226] [2022-11-16 11:26:01,091 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:26:01,091 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:26:01,095 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:26:01,095 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:26:01,099 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:26:01,100 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:26:01,150 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:26:01,151 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2022-11-16 11:26:01,151 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=48, Invalid=224, Unknown=0, NotChecked=0, Total=272 [2022-11-16 11:26:01,151 INFO L87 Difference]: Start difference. First operand 24 states and 30 transitions. cyclomatic complexity: 9 Second operand has 17 states, 16 states have (on average 2.125) internal successors, (34), 17 states have internal predecessors, (34), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:26:01,354 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:26:01,354 INFO L93 Difference]: Finished difference Result 42 states and 53 transitions. [2022-11-16 11:26:01,354 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 42 states and 53 transitions. [2022-11-16 11:26:01,355 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-16 11:26:01,356 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 42 states to 41 states and 52 transitions. [2022-11-16 11:26:01,356 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16 [2022-11-16 11:26:01,356 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16 [2022-11-16 11:26:01,356 INFO L73 IsDeterministic]: Start isDeterministic. Operand 41 states and 52 transitions. [2022-11-16 11:26:01,356 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-16 11:26:01,356 INFO L218 hiAutomatonCegarLoop]: Abstraction has 41 states and 52 transitions. [2022-11-16 11:26:01,357 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41 states and 52 transitions. [2022-11-16 11:26:01,358 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41 to 32. [2022-11-16 11:26:01,358 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 32 states, 32 states have (on average 1.28125) internal successors, (41), 31 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:26:01,358 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32 states to 32 states and 41 transitions. [2022-11-16 11:26:01,359 INFO L240 hiAutomatonCegarLoop]: Abstraction has 32 states and 41 transitions. [2022-11-16 11:26:01,359 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2022-11-16 11:26:01,360 INFO L428 stractBuchiCegarLoop]: Abstraction has 32 states and 41 transitions. [2022-11-16 11:26:01,360 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-11-16 11:26:01,360 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 32 states and 41 transitions. [2022-11-16 11:26:01,361 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:26:01,361 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:26:01,361 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:26:01,361 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:26:01,362 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-16 11:26:01,362 INFO L748 eck$LassoCheckResult]: Stem: 2104#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 2105#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 2115#L367 assume !(main_~length~0#1 < 1); 2106#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 2107#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 2108#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2116#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 2126#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2127#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2128#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 2129#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2117#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2118#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 2119#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2122#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 2109#L370-4 main_~j~0#1 := 0; 2110#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2133#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 2132#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2113#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 2114#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2121#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 2131#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2111#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 2112#L378-2 [2022-11-16 11:26:01,362 INFO L750 eck$LassoCheckResult]: Loop: 2112#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2130#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 2112#L378-2 [2022-11-16 11:26:01,363 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:26:01,363 INFO L85 PathProgramCache]: Analyzing trace with hash -509471318, now seen corresponding path program 5 times [2022-11-16 11:26:01,363 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:26:01,363 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1157021399] [2022-11-16 11:26:01,363 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:26:01,364 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:26:01,378 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:26:01,508 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 7 proven. 17 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:26:01,509 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:26:01,509 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1157021399] [2022-11-16 11:26:01,509 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1157021399] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:26:01,509 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1709066820] [2022-11-16 11:26:01,509 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-16 11:26:01,510 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:26:01,510 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:26:01,517 INFO L229 MonitoredProcess]: Starting monitored process 28 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:26:01,538 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (28)] Waiting until timeout for monitored process [2022-11-16 11:26:01,598 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 4 check-sat command(s) [2022-11-16 11:26:01,598 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-16 11:26:01,599 INFO L263 TraceCheckSpWp]: Trace formula consists of 125 conjuncts, 10 conjunts are in the unsatisfiable core [2022-11-16 11:26:01,600 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:26:01,701 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 12 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:26:01,701 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:26:01,780 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 9 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:26:01,780 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1709066820] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:26:01,780 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-16 11:26:01,781 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11, 11] total 17 [2022-11-16 11:26:01,781 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1347773381] [2022-11-16 11:26:01,781 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-16 11:26:01,781 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:26:01,782 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:26:01,782 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 12 times [2022-11-16 11:26:01,782 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:26:01,782 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1106713907] [2022-11-16 11:26:01,782 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:26:01,782 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:26:01,785 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:26:01,785 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:26:01,787 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:26:01,790 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:26:01,843 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:26:01,843 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2022-11-16 11:26:01,843 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=70, Invalid=202, Unknown=0, NotChecked=0, Total=272 [2022-11-16 11:26:01,844 INFO L87 Difference]: Start difference. First operand 32 states and 41 transitions. cyclomatic complexity: 13 Second operand has 17 states, 17 states have (on average 2.235294117647059) internal successors, (38), 17 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:26:01,987 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:26:01,987 INFO L93 Difference]: Finished difference Result 45 states and 55 transitions. [2022-11-16 11:26:01,987 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 45 states and 55 transitions. [2022-11-16 11:26:01,987 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:26:01,988 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 45 states to 37 states and 47 transitions. [2022-11-16 11:26:01,988 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-16 11:26:01,988 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-16 11:26:01,988 INFO L73 IsDeterministic]: Start isDeterministic. Operand 37 states and 47 transitions. [2022-11-16 11:26:01,988 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-16 11:26:01,988 INFO L218 hiAutomatonCegarLoop]: Abstraction has 37 states and 47 transitions. [2022-11-16 11:26:01,989 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37 states and 47 transitions. [2022-11-16 11:26:01,989 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37 to 34. [2022-11-16 11:26:01,990 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 34 states, 34 states have (on average 1.2647058823529411) internal successors, (43), 33 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:26:01,990 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34 states to 34 states and 43 transitions. [2022-11-16 11:26:01,990 INFO L240 hiAutomatonCegarLoop]: Abstraction has 34 states and 43 transitions. [2022-11-16 11:26:01,992 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2022-11-16 11:26:01,992 INFO L428 stractBuchiCegarLoop]: Abstraction has 34 states and 43 transitions. [2022-11-16 11:26:01,992 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-11-16 11:26:01,992 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 34 states and 43 transitions. [2022-11-16 11:26:01,993 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:26:01,993 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:26:01,993 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:26:01,994 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 4, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:26:01,996 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-16 11:26:01,996 INFO L748 eck$LassoCheckResult]: Stem: 2349#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 2350#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 2360#L367 assume !(main_~length~0#1 < 1); 2351#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 2352#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 2353#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2361#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 2382#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2362#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2363#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 2364#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2366#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2381#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 2380#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2379#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2376#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2378#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2367#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 2368#L370-4 main_~j~0#1 := 0; 2374#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2365#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 2373#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2371#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 2370#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2356#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 2357#L378-2 [2022-11-16 11:26:01,998 INFO L750 eck$LassoCheckResult]: Loop: 2357#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2372#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 2357#L378-2 [2022-11-16 11:26:01,998 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:26:01,998 INFO L85 PathProgramCache]: Analyzing trace with hash 1285147747, now seen corresponding path program 3 times [2022-11-16 11:26:01,998 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:26:01,999 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [828671307] [2022-11-16 11:26:01,999 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:26:01,999 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:26:02,029 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:26:02,607 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:26:02,607 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:26:02,607 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [828671307] [2022-11-16 11:26:02,607 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [828671307] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:26:02,607 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1172672872] [2022-11-16 11:26:02,607 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-16 11:26:02,608 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:26:02,608 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:26:02,612 INFO L229 MonitoredProcess]: Starting monitored process 29 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:26:02,626 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (29)] Waiting until timeout for monitored process [2022-11-16 11:26:02,730 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 5 check-sat command(s) [2022-11-16 11:26:02,730 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-16 11:26:02,732 INFO L263 TraceCheckSpWp]: Trace formula consists of 135 conjuncts, 25 conjunts are in the unsatisfiable core [2022-11-16 11:26:02,734 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:26:02,799 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-16 11:26:02,917 INFO L321 Elim1Store]: treesize reduction 21, result has 47.5 percent of original size [2022-11-16 11:26:02,917 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 29 treesize of output 36 [2022-11-16 11:26:03,007 INFO L321 Elim1Store]: treesize reduction 21, result has 47.5 percent of original size [2022-11-16 11:26:03,008 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 49 [2022-11-16 11:26:03,582 INFO L321 Elim1Store]: treesize reduction 12, result has 67.6 percent of original size [2022-11-16 11:26:03,583 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 36 treesize of output 36 [2022-11-16 11:26:03,637 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 4 proven. 24 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:26:03,637 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:26:04,390 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 41 treesize of output 37 [2022-11-16 11:26:04,404 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 24 [2022-11-16 11:26:04,460 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 2 proven. 24 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-11-16 11:26:04,461 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1172672872] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:26:04,461 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-16 11:26:04,461 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 15, 12] total 32 [2022-11-16 11:26:04,461 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [904937466] [2022-11-16 11:26:04,461 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-16 11:26:04,462 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:26:04,462 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:26:04,462 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 13 times [2022-11-16 11:26:04,463 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:26:04,463 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [801131818] [2022-11-16 11:26:04,463 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:26:04,463 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:26:04,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:26:04,468 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:26:04,471 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:26:04,473 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:26:04,523 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:26:04,523 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2022-11-16 11:26:04,524 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=144, Invalid=912, Unknown=0, NotChecked=0, Total=1056 [2022-11-16 11:26:04,524 INFO L87 Difference]: Start difference. First operand 34 states and 43 transitions. cyclomatic complexity: 13 Second operand has 33 states, 32 states have (on average 1.78125) internal successors, (57), 33 states have internal predecessors, (57), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:26:05,605 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:26:05,605 INFO L93 Difference]: Finished difference Result 84 states and 103 transitions. [2022-11-16 11:26:05,605 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 84 states and 103 transitions. [2022-11-16 11:26:05,606 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:26:05,607 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 84 states to 67 states and 83 transitions. [2022-11-16 11:26:05,607 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15 [2022-11-16 11:26:05,607 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15 [2022-11-16 11:26:05,607 INFO L73 IsDeterministic]: Start isDeterministic. Operand 67 states and 83 transitions. [2022-11-16 11:26:05,608 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-16 11:26:05,608 INFO L218 hiAutomatonCegarLoop]: Abstraction has 67 states and 83 transitions. [2022-11-16 11:26:05,608 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67 states and 83 transitions. [2022-11-16 11:26:05,610 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67 to 49. [2022-11-16 11:26:05,610 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 49 states, 49 states have (on average 1.2857142857142858) internal successors, (63), 48 states have internal predecessors, (63), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:26:05,610 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49 states to 49 states and 63 transitions. [2022-11-16 11:26:05,611 INFO L240 hiAutomatonCegarLoop]: Abstraction has 49 states and 63 transitions. [2022-11-16 11:26:05,611 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2022-11-16 11:26:05,612 INFO L428 stractBuchiCegarLoop]: Abstraction has 49 states and 63 transitions. [2022-11-16 11:26:05,612 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-11-16 11:26:05,612 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 49 states and 63 transitions. [2022-11-16 11:26:05,612 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:26:05,612 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:26:05,613 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:26:05,613 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 4, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:26:05,613 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-16 11:26:05,613 INFO L748 eck$LassoCheckResult]: Stem: 2691#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 2692#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 2702#L367 assume !(main_~length~0#1 < 1); 2693#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 2694#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 2695#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2703#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2734#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2733#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2731#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2732#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2729#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2727#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 2725#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2724#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2714#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2720#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2718#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 2717#L370-4 main_~j~0#1 := 0; 2716#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2706#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 2712#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2711#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 2710#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2696#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 2697#L378-2 [2022-11-16 11:26:05,614 INFO L750 eck$LassoCheckResult]: Loop: 2697#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2709#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 2697#L378-2 [2022-11-16 11:26:05,614 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:26:05,614 INFO L85 PathProgramCache]: Analyzing trace with hash -299807453, now seen corresponding path program 4 times [2022-11-16 11:26:05,614 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:26:05,615 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1643227419] [2022-11-16 11:26:05,615 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:26:05,615 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:26:05,639 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:26:06,212 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:26:06,212 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:26:06,212 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1643227419] [2022-11-16 11:26:06,212 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1643227419] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:26:06,212 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1200197348] [2022-11-16 11:26:06,212 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-16 11:26:06,213 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:26:06,213 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:26:06,217 INFO L229 MonitoredProcess]: Starting monitored process 30 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:26:06,234 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (30)] Waiting until timeout for monitored process [2022-11-16 11:26:06,295 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-16 11:26:06,295 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-16 11:26:06,297 INFO L263 TraceCheckSpWp]: Trace formula consists of 133 conjuncts, 26 conjunts are in the unsatisfiable core [2022-11-16 11:26:06,306 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:26:06,334 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-16 11:26:06,442 INFO L321 Elim1Store]: treesize reduction 29, result has 27.5 percent of original size [2022-11-16 11:26:06,442 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 30 [2022-11-16 11:26:06,474 INFO L321 Elim1Store]: treesize reduction 29, result has 27.5 percent of original size [2022-11-16 11:26:06,475 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 30 [2022-11-16 11:26:06,596 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 11 [2022-11-16 11:26:06,600 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:26:06,600 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:26:06,803 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2022-11-16 11:26:06,812 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 20 [2022-11-16 11:26:06,859 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:26:06,859 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1200197348] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:26:06,860 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-16 11:26:06,860 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12] total 19 [2022-11-16 11:26:06,860 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [246628426] [2022-11-16 11:26:06,860 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-16 11:26:06,861 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:26:06,861 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:26:06,861 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 14 times [2022-11-16 11:26:06,861 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:26:06,861 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1593354931] [2022-11-16 11:26:06,862 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:26:06,862 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:26:06,865 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:26:06,865 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:26:06,867 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:26:06,868 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:26:06,923 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:26:06,924 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2022-11-16 11:26:06,924 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=58, Invalid=322, Unknown=0, NotChecked=0, Total=380 [2022-11-16 11:26:06,924 INFO L87 Difference]: Start difference. First operand 49 states and 63 transitions. cyclomatic complexity: 19 Second operand has 20 states, 19 states have (on average 2.1052631578947367) internal successors, (40), 20 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:26:07,257 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:26:07,257 INFO L93 Difference]: Finished difference Result 90 states and 113 transitions. [2022-11-16 11:26:07,257 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 90 states and 113 transitions. [2022-11-16 11:26:07,258 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 6 [2022-11-16 11:26:07,260 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 90 states to 89 states and 112 transitions. [2022-11-16 11:26:07,260 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 25 [2022-11-16 11:26:07,260 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 25 [2022-11-16 11:26:07,260 INFO L73 IsDeterministic]: Start isDeterministic. Operand 89 states and 112 transitions. [2022-11-16 11:26:07,261 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-16 11:26:07,261 INFO L218 hiAutomatonCegarLoop]: Abstraction has 89 states and 112 transitions. [2022-11-16 11:26:07,261 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 89 states and 112 transitions. [2022-11-16 11:26:07,263 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 89 to 55. [2022-11-16 11:26:07,263 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 55 states, 55 states have (on average 1.3272727272727274) internal successors, (73), 54 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:26:07,263 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55 states to 55 states and 73 transitions. [2022-11-16 11:26:07,264 INFO L240 hiAutomatonCegarLoop]: Abstraction has 55 states and 73 transitions. [2022-11-16 11:26:07,264 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2022-11-16 11:26:07,265 INFO L428 stractBuchiCegarLoop]: Abstraction has 55 states and 73 transitions. [2022-11-16 11:26:07,265 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-11-16 11:26:07,265 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 55 states and 73 transitions. [2022-11-16 11:26:07,266 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:26:07,266 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:26:07,266 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:26:07,266 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 4, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:26:07,267 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-16 11:26:07,267 INFO L748 eck$LassoCheckResult]: Stem: 3007#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 3008#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 3018#L367 assume !(main_~length~0#1 < 1); 3009#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 3010#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 3011#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3019#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3047#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3045#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3043#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3041#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3039#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3036#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3037#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3060#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3032#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 3029#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3027#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 3012#L370-4 main_~j~0#1 := 0; 3013#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3016#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 3017#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3024#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 3052#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3050#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 3049#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3014#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 3015#L378-2 [2022-11-16 11:26:07,267 INFO L750 eck$LassoCheckResult]: Loop: 3015#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3051#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 3015#L378-2 [2022-11-16 11:26:07,267 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:26:07,268 INFO L85 PathProgramCache]: Analyzing trace with hash 1185875042, now seen corresponding path program 5 times [2022-11-16 11:26:07,268 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:26:07,268 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1341491134] [2022-11-16 11:26:07,268 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:26:07,268 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:26:07,298 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:26:07,752 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 0 proven. 34 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:26:07,752 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:26:07,752 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1341491134] [2022-11-16 11:26:07,753 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1341491134] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:26:07,753 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1507168536] [2022-11-16 11:26:07,753 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-16 11:26:07,753 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:26:07,753 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:26:07,756 INFO L229 MonitoredProcess]: Starting monitored process 31 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:26:07,763 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (31)] Waiting until timeout for monitored process [2022-11-16 11:26:07,881 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 5 check-sat command(s) [2022-11-16 11:26:07,881 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-16 11:26:07,883 INFO L263 TraceCheckSpWp]: Trace formula consists of 161 conjuncts, 29 conjunts are in the unsatisfiable core [2022-11-16 11:26:07,884 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:26:08,020 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 9 [2022-11-16 11:26:08,364 INFO L173 IndexEqualityManager]: detected equality via solver [2022-11-16 11:26:08,366 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-16 11:26:08,366 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 19 treesize of output 12 [2022-11-16 11:26:08,384 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 0 proven. 34 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:26:08,385 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:26:08,568 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2022-11-16 11:26:08,571 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 20 [2022-11-16 11:26:08,611 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 0 proven. 34 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:26:08,612 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1507168536] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:26:08,612 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-16 11:26:08,612 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 14, 13] total 28 [2022-11-16 11:26:08,612 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1396353390] [2022-11-16 11:26:08,612 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-16 11:26:08,614 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:26:08,614 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:26:08,615 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 15 times [2022-11-16 11:26:08,615 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:26:08,615 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [976488404] [2022-11-16 11:26:08,615 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:26:08,615 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:26:08,619 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:26:08,620 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:26:08,623 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:26:08,624 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:26:08,677 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:26:08,677 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2022-11-16 11:26:08,677 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=106, Invalid=706, Unknown=0, NotChecked=0, Total=812 [2022-11-16 11:26:08,678 INFO L87 Difference]: Start difference. First operand 55 states and 73 transitions. cyclomatic complexity: 23 Second operand has 29 states, 28 states have (on average 2.0) internal successors, (56), 29 states have internal predecessors, (56), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:26:09,181 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:26:09,181 INFO L93 Difference]: Finished difference Result 94 states and 122 transitions. [2022-11-16 11:26:09,181 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 94 states and 122 transitions. [2022-11-16 11:26:09,182 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 11 [2022-11-16 11:26:09,183 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 94 states to 93 states and 121 transitions. [2022-11-16 11:26:09,183 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 30 [2022-11-16 11:26:09,183 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 30 [2022-11-16 11:26:09,183 INFO L73 IsDeterministic]: Start isDeterministic. Operand 93 states and 121 transitions. [2022-11-16 11:26:09,183 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-16 11:26:09,183 INFO L218 hiAutomatonCegarLoop]: Abstraction has 93 states and 121 transitions. [2022-11-16 11:26:09,184 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 93 states and 121 transitions. [2022-11-16 11:26:09,186 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 93 to 82. [2022-11-16 11:26:09,186 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 82 states, 82 states have (on average 1.3170731707317074) internal successors, (108), 81 states have internal predecessors, (108), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:26:09,186 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 82 states to 82 states and 108 transitions. [2022-11-16 11:26:09,187 INFO L240 hiAutomatonCegarLoop]: Abstraction has 82 states and 108 transitions. [2022-11-16 11:26:09,187 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2022-11-16 11:26:09,187 INFO L428 stractBuchiCegarLoop]: Abstraction has 82 states and 108 transitions. [2022-11-16 11:26:09,187 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2022-11-16 11:26:09,188 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 82 states and 108 transitions. [2022-11-16 11:26:09,188 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 8 [2022-11-16 11:26:09,188 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:26:09,188 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:26:09,189 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 5, 4, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:26:09,189 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 1, 1] [2022-11-16 11:26:09,189 INFO L748 eck$LassoCheckResult]: Stem: 3352#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 3353#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 3363#L367 assume !(main_~length~0#1 < 1); 3354#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 3355#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 3356#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3364#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3392#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3390#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3388#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3387#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3385#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3383#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3368#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3394#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3395#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3415#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3412#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3411#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 3410#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3408#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 3407#L370-4 main_~j~0#1 := 0; 3406#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3405#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 3404#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3403#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 3397#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3398#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 3429#L378-2 [2022-11-16 11:26:09,189 INFO L750 eck$LassoCheckResult]: Loop: 3429#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3431#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 3430#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3428#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 3429#L378-2 [2022-11-16 11:26:09,189 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:26:09,189 INFO L85 PathProgramCache]: Analyzing trace with hash -1799910937, now seen corresponding path program 6 times [2022-11-16 11:26:09,189 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:26:09,190 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [668508686] [2022-11-16 11:26:09,190 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:26:09,190 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:26:09,209 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:26:09,659 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 0 proven. 41 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:26:09,659 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:26:09,659 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [668508686] [2022-11-16 11:26:09,660 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [668508686] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:26:09,660 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1431163425] [2022-11-16 11:26:09,660 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-11-16 11:26:09,660 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:26:09,660 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:26:09,666 INFO L229 MonitoredProcess]: Starting monitored process 32 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:26:09,672 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (32)] Waiting until timeout for monitored process [2022-11-16 11:26:09,781 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 6 check-sat command(s) [2022-11-16 11:26:09,782 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-16 11:26:09,783 INFO L263 TraceCheckSpWp]: Trace formula consists of 171 conjuncts, 42 conjunts are in the unsatisfiable core [2022-11-16 11:26:09,790 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:26:09,858 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-16 11:26:09,926 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-16 11:26:09,935 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-16 11:26:10,017 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:26:10,020 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:26:10,023 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-16 11:26:10,023 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 34 treesize of output 36 [2022-11-16 11:26:10,043 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:26:10,044 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:26:10,046 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-16 11:26:10,047 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 34 treesize of output 36 [2022-11-16 11:26:10,096 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:26:10,097 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:26:10,100 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-16 11:26:10,100 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 34 treesize of output 36 [2022-11-16 11:26:10,332 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-16 11:26:10,333 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 22 treesize of output 10 [2022-11-16 11:26:10,335 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 1 proven. 40 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:26:10,336 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:26:26,928 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 82 treesize of output 78 [2022-11-16 11:26:26,954 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 4664 treesize of output 4600 [2022-11-16 11:26:31,592 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 1 proven. 40 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:26:31,592 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1431163425] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:26:31,592 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-16 11:26:31,592 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 15, 15] total 39 [2022-11-16 11:26:31,592 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1880828625] [2022-11-16 11:26:31,592 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-16 11:26:31,593 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:26:31,593 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:26:31,593 INFO L85 PathProgramCache]: Analyzing trace with hash 2219337, now seen corresponding path program 1 times [2022-11-16 11:26:31,594 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:26:31,594 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1361212142] [2022-11-16 11:26:31,594 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:26:31,594 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:26:31,599 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:26:31,599 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:26:31,601 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:26:31,603 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:26:31,729 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:26:31,729 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2022-11-16 11:26:31,731 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=213, Invalid=1346, Unknown=1, NotChecked=0, Total=1560 [2022-11-16 11:26:31,731 INFO L87 Difference]: Start difference. First operand 82 states and 108 transitions. cyclomatic complexity: 33 Second operand has 40 states, 39 states have (on average 1.9487179487179487) internal successors, (76), 40 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:26:32,854 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:26:32,854 INFO L93 Difference]: Finished difference Result 196 states and 250 transitions. [2022-11-16 11:26:32,854 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 196 states and 250 transitions. [2022-11-16 11:26:32,855 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 10 [2022-11-16 11:26:32,857 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 196 states to 192 states and 246 transitions. [2022-11-16 11:26:32,857 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 45 [2022-11-16 11:26:32,857 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 45 [2022-11-16 11:26:32,857 INFO L73 IsDeterministic]: Start isDeterministic. Operand 192 states and 246 transitions. [2022-11-16 11:26:32,857 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-16 11:26:32,857 INFO L218 hiAutomatonCegarLoop]: Abstraction has 192 states and 246 transitions. [2022-11-16 11:26:32,858 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 192 states and 246 transitions. [2022-11-16 11:26:32,860 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 192 to 100. [2022-11-16 11:26:32,860 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 100 states, 100 states have (on average 1.34) internal successors, (134), 99 states have internal predecessors, (134), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:26:32,861 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 100 states to 100 states and 134 transitions. [2022-11-16 11:26:32,861 INFO L240 hiAutomatonCegarLoop]: Abstraction has 100 states and 134 transitions. [2022-11-16 11:26:32,861 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2022-11-16 11:26:32,862 INFO L428 stractBuchiCegarLoop]: Abstraction has 100 states and 134 transitions. [2022-11-16 11:26:32,862 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2022-11-16 11:26:32,862 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 100 states and 134 transitions. [2022-11-16 11:26:32,862 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 8 [2022-11-16 11:26:32,863 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:26:32,863 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:26:32,863 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 5, 4, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:26:32,863 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-16 11:26:32,863 INFO L748 eck$LassoCheckResult]: Stem: 3863#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 3864#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 3874#L367 assume !(main_~length~0#1 < 1); 3865#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 3866#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 3867#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3875#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3916#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3917#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3912#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3913#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3962#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3906#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 3908#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3940#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3937#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3936#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3898#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3894#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3931#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3929#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 3928#L370-4 main_~j~0#1 := 0; 3927#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3883#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 3887#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3885#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 3886#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3868#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 3869#L378-2 [2022-11-16 11:26:32,863 INFO L750 eck$LassoCheckResult]: Loop: 3869#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3884#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 3869#L378-2 [2022-11-16 11:26:32,864 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:26:32,864 INFO L85 PathProgramCache]: Analyzing trace with hash 1867015015, now seen corresponding path program 7 times [2022-11-16 11:26:32,864 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:26:32,864 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [333431061] [2022-11-16 11:26:32,864 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:26:32,864 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:26:32,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:26:33,657 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 0 proven. 41 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:26:33,658 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:26:33,658 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [333431061] [2022-11-16 11:26:33,658 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [333431061] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:26:33,658 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [209650581] [2022-11-16 11:26:33,658 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-11-16 11:26:33,658 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:26:33,659 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:26:33,665 INFO L229 MonitoredProcess]: Starting monitored process 33 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:26:33,681 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (33)] Waiting until timeout for monitored process [2022-11-16 11:26:33,759 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:26:33,761 INFO L263 TraceCheckSpWp]: Trace formula consists of 171 conjuncts, 42 conjunts are in the unsatisfiable core [2022-11-16 11:26:33,764 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:26:33,773 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 9 [2022-11-16 11:26:33,843 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 5 treesize of output 3 [2022-11-16 11:26:33,942 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-16 11:26:34,095 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:26:34,096 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 26 [2022-11-16 11:26:34,111 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:26:34,112 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 26 [2022-11-16 11:26:34,184 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:26:34,184 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 26 [2022-11-16 11:26:34,198 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:26:34,199 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 26 [2022-11-16 11:26:34,420 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 9 [2022-11-16 11:26:34,441 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 2 proven. 39 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:26:34,441 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:26:34,817 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2022-11-16 11:26:34,820 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 20 [2022-11-16 11:26:34,891 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 1 proven. 39 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-16 11:26:34,891 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [209650581] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:26:34,891 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-16 11:26:34,892 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 14, 14] total 29 [2022-11-16 11:26:34,892 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1501966069] [2022-11-16 11:26:34,892 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-16 11:26:34,892 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:26:34,892 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:26:34,893 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 16 times [2022-11-16 11:26:34,893 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:26:34,893 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [720151604] [2022-11-16 11:26:34,893 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:26:34,893 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:26:34,896 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:26:34,897 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:26:34,898 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:26:34,900 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:26:34,970 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:26:34,971 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2022-11-16 11:26:34,971 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=122, Invalid=748, Unknown=0, NotChecked=0, Total=870 [2022-11-16 11:26:34,971 INFO L87 Difference]: Start difference. First operand 100 states and 134 transitions. cyclomatic complexity: 44 Second operand has 30 states, 29 states have (on average 2.1379310344827585) internal successors, (62), 30 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:26:35,543 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:26:35,543 INFO L93 Difference]: Finished difference Result 103 states and 133 transitions. [2022-11-16 11:26:35,543 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 103 states and 133 transitions. [2022-11-16 11:26:35,544 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:26:35,545 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 103 states to 101 states and 131 transitions. [2022-11-16 11:26:35,545 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17 [2022-11-16 11:26:35,545 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17 [2022-11-16 11:26:35,545 INFO L73 IsDeterministic]: Start isDeterministic. Operand 101 states and 131 transitions. [2022-11-16 11:26:35,550 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-16 11:26:35,550 INFO L218 hiAutomatonCegarLoop]: Abstraction has 101 states and 131 transitions. [2022-11-16 11:26:35,551 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 101 states and 131 transitions. [2022-11-16 11:26:35,552 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 101 to 55. [2022-11-16 11:26:35,552 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 55 states, 55 states have (on average 1.290909090909091) internal successors, (71), 54 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:26:35,553 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55 states to 55 states and 71 transitions. [2022-11-16 11:26:35,553 INFO L240 hiAutomatonCegarLoop]: Abstraction has 55 states and 71 transitions. [2022-11-16 11:26:35,563 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2022-11-16 11:26:35,563 INFO L428 stractBuchiCegarLoop]: Abstraction has 55 states and 71 transitions. [2022-11-16 11:26:35,563 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2022-11-16 11:26:35,563 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 55 states and 71 transitions. [2022-11-16 11:26:35,564 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:26:35,564 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:26:35,564 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:26:35,567 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 4, 4, 4, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:26:35,567 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-16 11:26:35,567 INFO L748 eck$LassoCheckResult]: Stem: 4269#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 4270#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 4280#L367 assume !(main_~length~0#1 < 1); 4271#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 4272#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 4273#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4281#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4320#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4318#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4315#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4313#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4311#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4308#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4307#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4306#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4305#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 4284#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4286#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 4292#L370-4 main_~j~0#1 := 0; 4295#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4294#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 4285#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4278#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 4279#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4291#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 4290#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4288#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 4287#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4276#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 4277#L378-2 [2022-11-16 11:26:35,567 INFO L750 eck$LassoCheckResult]: Loop: 4277#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4289#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 4277#L378-2 [2022-11-16 11:26:35,569 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:26:35,570 INFO L85 PathProgramCache]: Analyzing trace with hash 1459581349, now seen corresponding path program 8 times [2022-11-16 11:26:35,570 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:26:35,570 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [5552070] [2022-11-16 11:26:35,571 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:26:35,571 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:26:35,585 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:26:35,797 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 13 proven. 29 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:26:35,797 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:26:35,797 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [5552070] [2022-11-16 11:26:35,797 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [5552070] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:26:35,797 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [388779522] [2022-11-16 11:26:35,797 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-16 11:26:35,797 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:26:35,798 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:26:35,802 INFO L229 MonitoredProcess]: Starting monitored process 34 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:26:35,822 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (34)] Waiting until timeout for monitored process [2022-11-16 11:26:35,923 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-16 11:26:35,923 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-16 11:26:35,924 INFO L263 TraceCheckSpWp]: Trace formula consists of 173 conjuncts, 12 conjunts are in the unsatisfiable core [2022-11-16 11:26:35,925 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:26:36,108 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 20 proven. 22 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:26:36,109 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:26:36,278 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 20 proven. 22 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:26:36,278 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [388779522] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:26:36,279 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-16 11:26:36,279 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13] total 20 [2022-11-16 11:26:36,279 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [602921967] [2022-11-16 11:26:36,279 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-16 11:26:36,279 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:26:36,279 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:26:36,279 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 17 times [2022-11-16 11:26:36,280 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:26:36,280 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [26475241] [2022-11-16 11:26:36,280 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:26:36,280 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:26:36,282 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:26:36,283 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:26:36,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:26:36,285 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:26:36,359 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:26:36,359 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2022-11-16 11:26:36,360 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=95, Invalid=285, Unknown=0, NotChecked=0, Total=380 [2022-11-16 11:26:36,360 INFO L87 Difference]: Start difference. First operand 55 states and 71 transitions. cyclomatic complexity: 21 Second operand has 20 states, 20 states have (on average 2.3) internal successors, (46), 20 states have internal predecessors, (46), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:26:36,598 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:26:36,599 INFO L93 Difference]: Finished difference Result 71 states and 88 transitions. [2022-11-16 11:26:36,599 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 71 states and 88 transitions. [2022-11-16 11:26:36,599 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:26:36,600 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 71 states to 61 states and 78 transitions. [2022-11-16 11:26:36,600 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-16 11:26:36,600 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-16 11:26:36,600 INFO L73 IsDeterministic]: Start isDeterministic. Operand 61 states and 78 transitions. [2022-11-16 11:26:36,600 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-16 11:26:36,600 INFO L218 hiAutomatonCegarLoop]: Abstraction has 61 states and 78 transitions. [2022-11-16 11:26:36,600 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61 states and 78 transitions. [2022-11-16 11:26:36,601 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61 to 57. [2022-11-16 11:26:36,602 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 57 states, 57 states have (on average 1.280701754385965) internal successors, (73), 56 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:26:36,602 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 57 states to 57 states and 73 transitions. [2022-11-16 11:26:36,602 INFO L240 hiAutomatonCegarLoop]: Abstraction has 57 states and 73 transitions. [2022-11-16 11:26:36,603 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2022-11-16 11:26:36,603 INFO L428 stractBuchiCegarLoop]: Abstraction has 57 states and 73 transitions. [2022-11-16 11:26:36,603 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2022-11-16 11:26:36,603 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 57 states and 73 transitions. [2022-11-16 11:26:36,604 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:26:36,604 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:26:36,604 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:26:36,604 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 5, 4, 4, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:26:36,604 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-16 11:26:36,605 INFO L748 eck$LassoCheckResult]: Stem: 4598#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 4599#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 4609#L367 assume !(main_~length~0#1 < 1); 4600#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 4601#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 4602#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4610#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4653#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4654#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4647#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4645#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4643#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4641#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4639#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4637#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4635#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 4633#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4632#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4629#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4625#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4617#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 4603#L370-4 main_~j~0#1 := 0; 4604#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4615#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 4624#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4623#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 4622#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4620#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 4619#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4605#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 4606#L378-2 [2022-11-16 11:26:36,605 INFO L750 eck$LassoCheckResult]: Loop: 4606#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4621#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 4606#L378-2 [2022-11-16 11:26:36,605 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:26:36,605 INFO L85 PathProgramCache]: Analyzing trace with hash -380619858, now seen corresponding path program 9 times [2022-11-16 11:26:36,605 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:26:36,605 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1147815613] [2022-11-16 11:26:36,605 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:26:36,605 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:26:36,632 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:26:37,295 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 0 proven. 47 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:26:37,295 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:26:37,295 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1147815613] [2022-11-16 11:26:37,295 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1147815613] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:26:37,295 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1210236432] [2022-11-16 11:26:37,295 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-16 11:26:37,295 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:26:37,295 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:26:37,298 INFO L229 MonitoredProcess]: Starting monitored process 35 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:26:37,299 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (35)] Waiting until timeout for monitored process [2022-11-16 11:26:37,434 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2022-11-16 11:26:37,434 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-16 11:26:37,435 INFO L263 TraceCheckSpWp]: Trace formula consists of 183 conjuncts, 32 conjunts are in the unsatisfiable core [2022-11-16 11:26:37,439 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:26:37,485 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-16 11:26:37,657 INFO L321 Elim1Store]: treesize reduction 29, result has 27.5 percent of original size [2022-11-16 11:26:37,657 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 30 [2022-11-16 11:26:37,697 INFO L321 Elim1Store]: treesize reduction 29, result has 27.5 percent of original size [2022-11-16 11:26:37,697 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 30 [2022-11-16 11:26:38,363 INFO L321 Elim1Store]: treesize reduction 30, result has 9.1 percent of original size [2022-11-16 11:26:38,363 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 44 treesize of output 17 [2022-11-16 11:26:38,367 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 0 proven. 47 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:26:38,368 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:26:38,640 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2022-11-16 11:26:38,644 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 20 [2022-11-16 11:26:38,700 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 1 proven. 45 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-16 11:26:38,700 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1210236432] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:26:38,701 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-16 11:26:38,701 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 13] total 24 [2022-11-16 11:26:38,701 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [687901293] [2022-11-16 11:26:38,701 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-16 11:26:38,701 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:26:38,701 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:26:38,702 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 18 times [2022-11-16 11:26:38,702 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:26:38,702 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1393347284] [2022-11-16 11:26:38,702 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:26:38,702 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:26:38,705 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:26:38,705 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:26:38,707 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:26:38,708 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:26:38,784 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:26:38,784 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2022-11-16 11:26:38,785 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=94, Invalid=506, Unknown=0, NotChecked=0, Total=600 [2022-11-16 11:26:38,785 INFO L87 Difference]: Start difference. First operand 57 states and 73 transitions. cyclomatic complexity: 21 Second operand has 25 states, 24 states have (on average 2.2083333333333335) internal successors, (53), 25 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:26:39,403 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:26:39,403 INFO L93 Difference]: Finished difference Result 101 states and 126 transitions. [2022-11-16 11:26:39,403 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 101 states and 126 transitions. [2022-11-16 11:26:39,405 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-16 11:26:39,410 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 101 states to 100 states and 124 transitions. [2022-11-16 11:26:39,411 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22 [2022-11-16 11:26:39,411 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22 [2022-11-16 11:26:39,411 INFO L73 IsDeterministic]: Start isDeterministic. Operand 100 states and 124 transitions. [2022-11-16 11:26:39,413 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-16 11:26:39,413 INFO L218 hiAutomatonCegarLoop]: Abstraction has 100 states and 124 transitions. [2022-11-16 11:26:39,413 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 100 states and 124 transitions. [2022-11-16 11:26:39,414 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 100 to 64. [2022-11-16 11:26:39,414 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 64 states, 64 states have (on average 1.328125) internal successors, (85), 63 states have internal predecessors, (85), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:26:39,415 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 64 states to 64 states and 85 transitions. [2022-11-16 11:26:39,415 INFO L240 hiAutomatonCegarLoop]: Abstraction has 64 states and 85 transitions. [2022-11-16 11:26:39,415 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2022-11-16 11:26:39,416 INFO L428 stractBuchiCegarLoop]: Abstraction has 64 states and 85 transitions. [2022-11-16 11:26:39,416 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2022-11-16 11:26:39,416 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 64 states and 85 transitions. [2022-11-16 11:26:39,416 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:26:39,416 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:26:39,416 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:26:39,417 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 5, 5, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:26:39,417 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-16 11:26:39,417 INFO L748 eck$LassoCheckResult]: Stem: 4966#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 4967#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 4977#L367 assume !(main_~length~0#1 < 1); 4968#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 4969#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 4970#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4978#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4981#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4979#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4980#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5026#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5023#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5019#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5017#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5015#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5013#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5011#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5008#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5009#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 5005#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4990#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 4971#L370-4 main_~j~0#1 := 0; 4972#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4992#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 4984#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4975#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 4976#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4989#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 4988#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4987#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 4986#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4973#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 4974#L378-2 [2022-11-16 11:26:39,417 INFO L750 eck$LassoCheckResult]: Loop: 4974#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4985#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 4974#L378-2 [2022-11-16 11:26:39,417 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:26:39,418 INFO L85 PathProgramCache]: Analyzing trace with hash -126233299, now seen corresponding path program 10 times [2022-11-16 11:26:39,418 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:26:39,418 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2139037651] [2022-11-16 11:26:39,418 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:26:39,418 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:26:39,458 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:26:40,159 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:26:40,159 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:26:40,159 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2139037651] [2022-11-16 11:26:40,160 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2139037651] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:26:40,160 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [667208320] [2022-11-16 11:26:40,160 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-16 11:26:40,160 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:26:40,160 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:26:40,166 INFO L229 MonitoredProcess]: Starting monitored process 36 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:26:40,186 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (36)] Waiting until timeout for monitored process [2022-11-16 11:26:40,274 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-16 11:26:40,274 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-16 11:26:40,276 INFO L263 TraceCheckSpWp]: Trace formula consists of 179 conjuncts, 29 conjunts are in the unsatisfiable core [2022-11-16 11:26:40,278 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:26:40,344 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-16 11:26:40,711 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 11 [2022-11-16 11:26:40,715 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:26:40,715 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:26:40,882 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2022-11-16 11:26:40,888 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 20 [2022-11-16 11:26:40,948 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:26:40,948 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [667208320] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:26:40,948 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-16 11:26:40,948 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 14, 14] total 22 [2022-11-16 11:26:40,949 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2020065387] [2022-11-16 11:26:40,949 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-16 11:26:40,949 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:26:40,949 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:26:40,949 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 19 times [2022-11-16 11:26:40,949 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:26:40,950 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1179426923] [2022-11-16 11:26:40,950 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:26:40,950 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:26:40,953 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:26:40,953 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:26:40,954 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:26:40,956 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:26:41,026 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:26:41,026 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2022-11-16 11:26:41,026 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=64, Invalid=442, Unknown=0, NotChecked=0, Total=506 [2022-11-16 11:26:41,027 INFO L87 Difference]: Start difference. First operand 64 states and 85 transitions. cyclomatic complexity: 27 Second operand has 23 states, 22 states have (on average 2.1818181818181817) internal successors, (48), 23 states have internal predecessors, (48), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:26:41,704 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:26:41,704 INFO L93 Difference]: Finished difference Result 81 states and 104 transitions. [2022-11-16 11:26:41,704 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 81 states and 104 transitions. [2022-11-16 11:26:41,705 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-16 11:26:41,705 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 81 states to 80 states and 103 transitions. [2022-11-16 11:26:41,705 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18 [2022-11-16 11:26:41,706 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18 [2022-11-16 11:26:41,706 INFO L73 IsDeterministic]: Start isDeterministic. Operand 80 states and 103 transitions. [2022-11-16 11:26:41,706 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-16 11:26:41,706 INFO L218 hiAutomatonCegarLoop]: Abstraction has 80 states and 103 transitions. [2022-11-16 11:26:41,706 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 80 states and 103 transitions. [2022-11-16 11:26:41,707 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 80 to 68. [2022-11-16 11:26:41,707 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 68 states, 68 states have (on average 1.3088235294117647) internal successors, (89), 67 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:26:41,708 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 68 states to 68 states and 89 transitions. [2022-11-16 11:26:41,708 INFO L240 hiAutomatonCegarLoop]: Abstraction has 68 states and 89 transitions. [2022-11-16 11:26:41,716 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2022-11-16 11:26:41,717 INFO L428 stractBuchiCegarLoop]: Abstraction has 68 states and 89 transitions. [2022-11-16 11:26:41,717 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2022-11-16 11:26:41,717 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 68 states and 89 transitions. [2022-11-16 11:26:41,717 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:26:41,717 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:26:41,717 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:26:41,718 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 5, 5, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:26:41,718 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-16 11:26:41,718 INFO L748 eck$LassoCheckResult]: Stem: 5327#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 5328#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 5338#L367 assume !(main_~length~0#1 < 1); 5329#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 5330#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 5331#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5339#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5342#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5394#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5393#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5391#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5388#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5385#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5383#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5381#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5377#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 5375#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5374#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5371#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5364#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5346#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 5347#L370-4 main_~j~0#1 := 0; 5344#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5336#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 5337#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5355#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 5354#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5353#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 5352#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5350#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 5349#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5334#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 5335#L378-2 [2022-11-16 11:26:41,718 INFO L750 eck$LassoCheckResult]: Loop: 5335#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5351#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 5335#L378-2 [2022-11-16 11:26:41,718 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:26:41,718 INFO L85 PathProgramCache]: Analyzing trace with hash -703463951, now seen corresponding path program 11 times [2022-11-16 11:26:41,719 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:26:41,719 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [457756695] [2022-11-16 11:26:41,719 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:26:41,719 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:26:41,748 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:26:42,280 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:26:42,280 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:26:42,280 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [457756695] [2022-11-16 11:26:42,281 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [457756695] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:26:42,281 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [878313816] [2022-11-16 11:26:42,281 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-16 11:26:42,281 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:26:42,281 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:26:42,285 INFO L229 MonitoredProcess]: Starting monitored process 37 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:26:42,306 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (37)] Waiting until timeout for monitored process [2022-11-16 11:26:42,416 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 6 check-sat command(s) [2022-11-16 11:26:42,417 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-16 11:26:42,419 INFO L263 TraceCheckSpWp]: Trace formula consists of 195 conjuncts, 43 conjunts are in the unsatisfiable core [2022-11-16 11:26:42,421 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:26:42,600 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-16 11:26:42,687 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:26:42,687 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-16 11:26:42,757 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:26:42,757 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-16 11:26:42,766 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2022-11-16 11:26:43,339 INFO L173 IndexEqualityManager]: detected equality via solver [2022-11-16 11:26:43,340 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:26:43,343 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-16 11:26:43,343 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 1 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 24 treesize of output 13 [2022-11-16 11:26:43,348 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:26:43,348 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:26:44,634 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 76 treesize of output 72 [2022-11-16 11:26:44,645 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-16 11:26:44,645 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 1327 treesize of output 1264 [2022-11-16 11:26:45,017 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:26:45,017 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [878313816] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:26:45,017 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-16 11:26:45,018 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 17, 17] total 45 [2022-11-16 11:26:45,018 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [273043606] [2022-11-16 11:26:45,018 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-16 11:26:45,018 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:26:45,019 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:26:45,019 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 20 times [2022-11-16 11:26:45,019 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:26:45,019 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [507094366] [2022-11-16 11:26:45,019 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:26:45,019 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:26:45,023 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:26:45,023 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:26:45,025 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:26:45,026 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:26:45,098 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:26:45,098 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 46 interpolants. [2022-11-16 11:26:45,099 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=225, Invalid=1845, Unknown=0, NotChecked=0, Total=2070 [2022-11-16 11:26:45,099 INFO L87 Difference]: Start difference. First operand 68 states and 89 transitions. cyclomatic complexity: 27 Second operand has 46 states, 45 states have (on average 1.9555555555555555) internal successors, (88), 46 states have internal predecessors, (88), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:26:48,143 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:26:48,143 INFO L93 Difference]: Finished difference Result 169 states and 214 transitions. [2022-11-16 11:26:48,143 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 169 states and 214 transitions. [2022-11-16 11:26:48,145 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 15 [2022-11-16 11:26:48,146 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 169 states to 166 states and 211 transitions. [2022-11-16 11:26:48,146 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 41 [2022-11-16 11:26:48,146 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 41 [2022-11-16 11:26:48,146 INFO L73 IsDeterministic]: Start isDeterministic. Operand 166 states and 211 transitions. [2022-11-16 11:26:48,146 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-16 11:26:48,147 INFO L218 hiAutomatonCegarLoop]: Abstraction has 166 states and 211 transitions. [2022-11-16 11:26:48,147 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 166 states and 211 transitions. [2022-11-16 11:26:48,149 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 166 to 108. [2022-11-16 11:26:48,149 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 108 states, 108 states have (on average 1.3425925925925926) internal successors, (145), 107 states have internal predecessors, (145), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:26:48,149 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 108 states to 108 states and 145 transitions. [2022-11-16 11:26:48,150 INFO L240 hiAutomatonCegarLoop]: Abstraction has 108 states and 145 transitions. [2022-11-16 11:26:48,158 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2022-11-16 11:26:48,159 INFO L428 stractBuchiCegarLoop]: Abstraction has 108 states and 145 transitions. [2022-11-16 11:26:48,159 INFO L335 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2022-11-16 11:26:48,159 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 108 states and 145 transitions. [2022-11-16 11:26:48,160 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2022-11-16 11:26:48,160 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:26:48,160 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:26:48,161 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 5, 5, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:26:48,161 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-16 11:26:48,161 INFO L748 eck$LassoCheckResult]: Stem: 5873#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 5874#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 5882#L367 assume !(main_~length~0#1 < 1); 5871#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 5872#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 5875#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5883#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5957#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5955#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5953#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5950#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5947#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5944#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 5943#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5941#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5939#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5937#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5935#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5933#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5930#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5927#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 5928#L370-4 main_~j~0#1 := 0; 5889#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5880#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 5881#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5962#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 5961#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5898#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 5902#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5900#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 5901#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5878#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 5879#L378-2 [2022-11-16 11:26:48,161 INFO L750 eck$LassoCheckResult]: Loop: 5879#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5896#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 5879#L378-2 [2022-11-16 11:26:48,161 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:26:48,162 INFO L85 PathProgramCache]: Analyzing trace with hash 67235501, now seen corresponding path program 12 times [2022-11-16 11:26:48,162 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:26:48,162 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [99108191] [2022-11-16 11:26:48,162 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:26:48,162 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:26:48,193 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:26:48,685 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:26:48,686 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:26:48,686 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [99108191] [2022-11-16 11:26:48,686 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [99108191] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:26:48,686 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [147624498] [2022-11-16 11:26:48,686 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-11-16 11:26:48,686 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:26:48,686 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:26:48,693 INFO L229 MonitoredProcess]: Starting monitored process 38 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:26:48,709 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (38)] Waiting until timeout for monitored process [2022-11-16 11:26:48,966 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 6 check-sat command(s) [2022-11-16 11:26:48,967 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-16 11:26:48,969 INFO L263 TraceCheckSpWp]: Trace formula consists of 195 conjuncts, 32 conjunts are in the unsatisfiable core [2022-11-16 11:26:48,970 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:26:49,070 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-16 11:26:49,149 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-16 11:26:49,163 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-16 11:26:49,899 INFO L321 Elim1Store]: treesize reduction 46, result has 13.2 percent of original size [2022-11-16 11:26:49,900 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 4 select indices, 4 select index equivalence classes, 0 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 6 case distinctions, treesize of input 49 treesize of output 21 [2022-11-16 11:26:49,905 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 16 proven. 39 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:26:49,905 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:26:51,003 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 43 treesize of output 39 [2022-11-16 11:26:51,011 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-16 11:26:51,012 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 62 treesize of output 49 [2022-11-16 11:26:51,150 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 6 proven. 47 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-11-16 11:26:51,150 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [147624498] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:26:51,151 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-16 11:26:51,151 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 17, 15] total 40 [2022-11-16 11:26:51,151 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [581089870] [2022-11-16 11:26:51,151 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-16 11:26:51,151 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:26:51,152 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:26:51,152 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 21 times [2022-11-16 11:26:51,152 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:26:51,152 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [425205358] [2022-11-16 11:26:51,152 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:26:51,153 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:26:51,155 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:26:51,156 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:26:51,157 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:26:51,159 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:26:51,237 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:26:51,237 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2022-11-16 11:26:51,238 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=203, Invalid=1437, Unknown=0, NotChecked=0, Total=1640 [2022-11-16 11:26:51,238 INFO L87 Difference]: Start difference. First operand 108 states and 145 transitions. cyclomatic complexity: 44 Second operand has 41 states, 40 states have (on average 2.0) internal successors, (80), 41 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:26:54,720 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:26:54,720 INFO L93 Difference]: Finished difference Result 175 states and 217 transitions. [2022-11-16 11:26:54,721 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 175 states and 217 transitions. [2022-11-16 11:26:54,722 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2022-11-16 11:26:54,723 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 175 states to 129 states and 166 transitions. [2022-11-16 11:26:54,723 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 28 [2022-11-16 11:26:54,723 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 28 [2022-11-16 11:26:54,723 INFO L73 IsDeterministic]: Start isDeterministic. Operand 129 states and 166 transitions. [2022-11-16 11:26:54,723 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-16 11:26:54,723 INFO L218 hiAutomatonCegarLoop]: Abstraction has 129 states and 166 transitions. [2022-11-16 11:26:54,724 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 129 states and 166 transitions. [2022-11-16 11:26:54,725 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 129 to 88. [2022-11-16 11:26:54,726 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 88 states, 88 states have (on average 1.3181818181818181) internal successors, (116), 87 states have internal predecessors, (116), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:26:54,726 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 88 states to 88 states and 116 transitions. [2022-11-16 11:26:54,726 INFO L240 hiAutomatonCegarLoop]: Abstraction has 88 states and 116 transitions. [2022-11-16 11:26:54,727 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2022-11-16 11:26:54,727 INFO L428 stractBuchiCegarLoop]: Abstraction has 88 states and 116 transitions. [2022-11-16 11:26:54,727 INFO L335 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2022-11-16 11:26:54,727 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 88 states and 116 transitions. [2022-11-16 11:26:54,728 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2022-11-16 11:26:54,728 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:26:54,728 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:26:54,729 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [6, 6, 4, 4, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:26:54,729 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-16 11:26:54,729 INFO L748 eck$LassoCheckResult]: Stem: 6466#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 6467#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 6477#L367 assume !(main_~length~0#1 < 1); 6468#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 6469#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 6470#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6478#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 6543#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6542#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6482#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 6483#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6479#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6480#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 6541#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6540#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6536#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6537#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6535#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6533#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6534#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6532#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6528#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 6526#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6524#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 6505#L370-4 main_~j~0#1 := 0; 6503#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6501#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 6499#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6490#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 6496#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6492#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 6493#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6471#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 6472#L378-2 [2022-11-16 11:26:54,729 INFO L750 eck$LassoCheckResult]: Loop: 6472#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6488#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 6472#L378-2 [2022-11-16 11:26:54,730 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:26:54,730 INFO L85 PathProgramCache]: Analyzing trace with hash 1453711780, now seen corresponding path program 13 times [2022-11-16 11:26:54,730 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:26:54,730 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1741130178] [2022-11-16 11:26:54,730 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:26:54,730 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:26:54,759 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:26:55,387 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 0 proven. 63 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:26:55,387 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:26:55,387 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1741130178] [2022-11-16 11:26:55,387 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1741130178] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:26:55,387 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [540781317] [2022-11-16 11:26:55,388 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-11-16 11:26:55,388 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:26:55,388 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:26:55,391 INFO L229 MonitoredProcess]: Starting monitored process 39 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:26:55,394 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (39)] Waiting until timeout for monitored process [2022-11-16 11:26:55,512 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:26:55,514 INFO L263 TraceCheckSpWp]: Trace formula consists of 184 conjuncts, 35 conjunts are in the unsatisfiable core [2022-11-16 11:26:55,516 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:26:55,720 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-16 11:26:55,816 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:26:55,817 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-16 11:26:55,832 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:26:55,833 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-16 11:26:55,885 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:26:55,886 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-16 11:26:56,123 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-16 11:26:56,125 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 1 proven. 62 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:26:56,125 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:27:09,830 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 23 [2022-11-16 11:27:09,834 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 60 treesize of output 56 [2022-11-16 11:27:09,900 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 0 proven. 62 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-16 11:27:09,900 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [540781317] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:27:09,900 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-16 11:27:09,900 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 15, 14] total 36 [2022-11-16 11:27:09,900 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1291925730] [2022-11-16 11:27:09,901 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-16 11:27:09,901 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:27:09,901 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:27:09,901 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 22 times [2022-11-16 11:27:09,902 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:27:09,902 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1837238816] [2022-11-16 11:27:09,902 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:27:09,902 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:27:09,905 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:27:09,905 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:27:09,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:27:09,908 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:27:09,968 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:27:09,969 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2022-11-16 11:27:09,969 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=159, Invalid=1172, Unknown=1, NotChecked=0, Total=1332 [2022-11-16 11:27:09,970 INFO L87 Difference]: Start difference. First operand 88 states and 116 transitions. cyclomatic complexity: 35 Second operand has 37 states, 36 states have (on average 2.2222222222222223) internal successors, (80), 37 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:27:10,606 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:27:10,606 INFO L93 Difference]: Finished difference Result 148 states and 189 transitions. [2022-11-16 11:27:10,606 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 148 states and 189 transitions. [2022-11-16 11:27:10,607 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 12 [2022-11-16 11:27:10,608 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 148 states to 146 states and 187 transitions. [2022-11-16 11:27:10,609 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 39 [2022-11-16 11:27:10,609 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 39 [2022-11-16 11:27:10,609 INFO L73 IsDeterministic]: Start isDeterministic. Operand 146 states and 187 transitions. [2022-11-16 11:27:10,609 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-16 11:27:10,609 INFO L218 hiAutomatonCegarLoop]: Abstraction has 146 states and 187 transitions. [2022-11-16 11:27:10,609 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 146 states and 187 transitions. [2022-11-16 11:27:10,611 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 146 to 100. [2022-11-16 11:27:10,611 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 100 states, 100 states have (on average 1.35) internal successors, (135), 99 states have internal predecessors, (135), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:27:10,612 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 100 states to 100 states and 135 transitions. [2022-11-16 11:27:10,612 INFO L240 hiAutomatonCegarLoop]: Abstraction has 100 states and 135 transitions. [2022-11-16 11:27:10,622 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2022-11-16 11:27:10,622 INFO L428 stractBuchiCegarLoop]: Abstraction has 100 states and 135 transitions. [2022-11-16 11:27:10,622 INFO L335 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2022-11-16 11:27:10,622 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 100 states and 135 transitions. [2022-11-16 11:27:10,623 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2022-11-16 11:27:10,623 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:27:10,623 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:27:10,624 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [6, 6, 5, 4, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:27:10,624 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 1, 1] [2022-11-16 11:27:10,624 INFO L748 eck$LassoCheckResult]: Stem: 6944#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 6945#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 6955#L367 assume !(main_~length~0#1 < 1); 6946#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 6947#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 6948#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6956#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 7001#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7000#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6999#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 6998#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6997#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6996#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 6995#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6994#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6992#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 6991#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6990#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6988#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6987#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6986#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6984#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 6979#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6980#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 6976#L370-4 main_~j~0#1 := 0; 6975#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6974#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 6973#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6972#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 6971#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6970#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 6964#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6966#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 7037#L378-2 [2022-11-16 11:27:10,624 INFO L750 eck$LassoCheckResult]: Loop: 7037#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7039#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 7040#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7041#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 7037#L378-2 [2022-11-16 11:27:10,624 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:27:10,625 INFO L85 PathProgramCache]: Analyzing trace with hash -540432926, now seen corresponding path program 14 times [2022-11-16 11:27:10,625 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:27:10,625 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1988680442] [2022-11-16 11:27:10,625 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:27:10,625 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:27:10,650 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:27:11,427 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 0 proven. 63 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:27:11,427 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:27:11,427 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1988680442] [2022-11-16 11:27:11,427 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1988680442] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:27:11,427 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [437008444] [2022-11-16 11:27:11,427 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-16 11:27:11,427 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:27:11,427 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:27:11,430 INFO L229 MonitoredProcess]: Starting monitored process 40 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:27:11,431 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (40)] Waiting until timeout for monitored process [2022-11-16 11:27:11,545 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-16 11:27:11,545 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-16 11:27:11,546 INFO L263 TraceCheckSpWp]: Trace formula consists of 177 conjuncts, 37 conjunts are in the unsatisfiable core [2022-11-16 11:27:11,548 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:27:11,731 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-16 11:27:11,888 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:27:11,889 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 26 [2022-11-16 11:27:11,902 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:27:11,903 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 26 [2022-11-16 11:27:11,965 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:27:11,965 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 26 [2022-11-16 11:27:12,246 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 9 [2022-11-16 11:27:12,276 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 1 proven. 62 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:27:12,276 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:27:12,647 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2022-11-16 11:27:12,651 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 20 [2022-11-16 11:27:12,693 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 1 proven. 61 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-16 11:27:12,693 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [437008444] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:27:12,693 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-16 11:27:12,694 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 16, 15] total 32 [2022-11-16 11:27:12,694 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [578228071] [2022-11-16 11:27:12,694 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-16 11:27:12,694 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:27:12,694 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:27:12,694 INFO L85 PathProgramCache]: Analyzing trace with hash 2221257, now seen corresponding path program 2 times [2022-11-16 11:27:12,694 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:27:12,694 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [133620690] [2022-11-16 11:27:12,695 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:27:12,695 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:27:12,699 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:27:12,699 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:27:12,702 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:27:12,704 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:27:12,825 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:27:12,826 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2022-11-16 11:27:12,826 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=132, Invalid=924, Unknown=0, NotChecked=0, Total=1056 [2022-11-16 11:27:12,827 INFO L87 Difference]: Start difference. First operand 100 states and 135 transitions. cyclomatic complexity: 45 Second operand has 33 states, 32 states have (on average 2.1875) internal successors, (70), 33 states have internal predecessors, (70), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:27:13,563 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:27:13,564 INFO L93 Difference]: Finished difference Result 105 states and 135 transitions. [2022-11-16 11:27:13,564 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 105 states and 135 transitions. [2022-11-16 11:27:13,564 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:27:13,565 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 105 states to 103 states and 133 transitions. [2022-11-16 11:27:13,565 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17 [2022-11-16 11:27:13,565 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17 [2022-11-16 11:27:13,565 INFO L73 IsDeterministic]: Start isDeterministic. Operand 103 states and 133 transitions. [2022-11-16 11:27:13,566 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-16 11:27:13,566 INFO L218 hiAutomatonCegarLoop]: Abstraction has 103 states and 133 transitions. [2022-11-16 11:27:13,566 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 103 states and 133 transitions. [2022-11-16 11:27:13,567 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 103 to 61. [2022-11-16 11:27:13,567 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 61 states, 61 states have (on average 1.3114754098360655) internal successors, (80), 60 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:27:13,567 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 61 states to 61 states and 80 transitions. [2022-11-16 11:27:13,567 INFO L240 hiAutomatonCegarLoop]: Abstraction has 61 states and 80 transitions. [2022-11-16 11:27:13,570 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2022-11-16 11:27:13,570 INFO L428 stractBuchiCegarLoop]: Abstraction has 61 states and 80 transitions. [2022-11-16 11:27:13,570 INFO L335 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2022-11-16 11:27:13,570 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 61 states and 80 transitions. [2022-11-16 11:27:13,571 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:27:13,571 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:27:13,571 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:27:13,571 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [6, 5, 5, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:27:13,571 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-16 11:27:13,572 INFO L748 eck$LassoCheckResult]: Stem: 7387#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 7388#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 7398#L367 assume !(main_~length~0#1 < 1); 7389#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 7390#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 7391#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7399#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 7441#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7440#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7439#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 7438#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7437#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7436#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 7435#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7434#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7433#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7432#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7431#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7430#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 7403#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7418#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 7392#L370-4 main_~j~0#1 := 0; 7393#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7417#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 7405#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7396#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 7397#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7416#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 7412#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7411#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 7410#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7408#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 7407#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7394#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 7395#L378-2 [2022-11-16 11:27:13,572 INFO L750 eck$LassoCheckResult]: Loop: 7395#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7409#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 7395#L378-2 [2022-11-16 11:27:13,572 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:27:13,572 INFO L85 PathProgramCache]: Analyzing trace with hash -1201186386, now seen corresponding path program 15 times [2022-11-16 11:27:13,573 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:27:13,573 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1705430996] [2022-11-16 11:27:13,573 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:27:13,573 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:27:13,587 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:27:13,853 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 21 proven. 44 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:27:13,853 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:27:13,853 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1705430996] [2022-11-16 11:27:13,853 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1705430996] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:27:13,853 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [37025889] [2022-11-16 11:27:13,853 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-16 11:27:13,853 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:27:13,854 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:27:13,857 INFO L229 MonitoredProcess]: Starting monitored process 41 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:27:13,878 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (41)] Waiting until timeout for monitored process [2022-11-16 11:27:14,023 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2022-11-16 11:27:14,023 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-16 11:27:14,025 INFO L263 TraceCheckSpWp]: Trace formula consists of 186 conjuncts, 14 conjunts are in the unsatisfiable core [2022-11-16 11:27:14,025 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:27:14,230 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 30 proven. 35 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:27:14,230 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:27:14,389 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 30 proven. 35 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:27:14,389 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [37025889] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:27:14,389 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-16 11:27:14,389 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15] total 23 [2022-11-16 11:27:14,390 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [187843801] [2022-11-16 11:27:14,390 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-16 11:27:14,390 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:27:14,390 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:27:14,390 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 23 times [2022-11-16 11:27:14,391 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:27:14,391 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [730804592] [2022-11-16 11:27:14,391 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:27:14,391 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:27:14,394 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:27:14,394 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:27:14,396 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:27:14,397 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:27:14,456 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:27:14,456 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2022-11-16 11:27:14,456 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=124, Invalid=382, Unknown=0, NotChecked=0, Total=506 [2022-11-16 11:27:14,457 INFO L87 Difference]: Start difference. First operand 61 states and 80 transitions. cyclomatic complexity: 24 Second operand has 23 states, 23 states have (on average 2.3043478260869565) internal successors, (53), 23 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:27:14,687 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:27:14,687 INFO L93 Difference]: Finished difference Result 79 states and 99 transitions. [2022-11-16 11:27:14,687 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 79 states and 99 transitions. [2022-11-16 11:27:14,688 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:27:14,688 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 79 states to 67 states and 87 transitions. [2022-11-16 11:27:14,688 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-16 11:27:14,689 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-16 11:27:14,689 INFO L73 IsDeterministic]: Start isDeterministic. Operand 67 states and 87 transitions. [2022-11-16 11:27:14,689 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-16 11:27:14,689 INFO L218 hiAutomatonCegarLoop]: Abstraction has 67 states and 87 transitions. [2022-11-16 11:27:14,689 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67 states and 87 transitions. [2022-11-16 11:27:14,690 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67 to 63. [2022-11-16 11:27:14,690 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 63 states, 63 states have (on average 1.3015873015873016) internal successors, (82), 62 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:27:14,691 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63 states to 63 states and 82 transitions. [2022-11-16 11:27:14,691 INFO L240 hiAutomatonCegarLoop]: Abstraction has 63 states and 82 transitions. [2022-11-16 11:27:14,696 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2022-11-16 11:27:14,696 INFO L428 stractBuchiCegarLoop]: Abstraction has 63 states and 82 transitions. [2022-11-16 11:27:14,697 INFO L335 stractBuchiCegarLoop]: ======== Iteration 28 ============ [2022-11-16 11:27:14,697 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 63 states and 82 transitions. [2022-11-16 11:27:14,697 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:27:14,697 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:27:14,697 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:27:14,698 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [6, 6, 5, 4, 4, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:27:14,698 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-16 11:27:14,698 INFO L748 eck$LassoCheckResult]: Stem: 7765#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 7766#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 7776#L367 assume !(main_~length~0#1 < 1); 7767#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 7768#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 7769#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7777#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 7780#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7826#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7825#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 7824#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7823#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7822#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 7821#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7819#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7816#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7814#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7812#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7810#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7809#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7808#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7807#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 7805#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7784#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 7770#L370-4 main_~j~0#1 := 0; 7771#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7782#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 7793#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7792#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 7791#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7790#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 7789#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7787#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 7786#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7772#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 7773#L378-2 [2022-11-16 11:27:14,699 INFO L750 eck$LassoCheckResult]: Loop: 7773#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7788#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 7773#L378-2 [2022-11-16 11:27:14,699 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:27:14,699 INFO L85 PathProgramCache]: Analyzing trace with hash 1152648807, now seen corresponding path program 16 times [2022-11-16 11:27:14,699 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:27:14,699 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1817494378] [2022-11-16 11:27:14,700 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:27:14,700 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:27:14,745 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:27:15,373 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 71 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:27:15,373 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:27:15,373 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1817494378] [2022-11-16 11:27:15,373 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1817494378] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:27:15,374 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1808963442] [2022-11-16 11:27:15,374 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-16 11:27:15,374 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:27:15,374 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:27:15,378 INFO L229 MonitoredProcess]: Starting monitored process 42 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:27:15,394 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (42)] Waiting until timeout for monitored process [2022-11-16 11:27:15,498 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-16 11:27:15,499 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-16 11:27:15,500 INFO L263 TraceCheckSpWp]: Trace formula consists of 180 conjuncts, 40 conjunts are in the unsatisfiable core [2022-11-16 11:27:15,503 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:27:15,557 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-16 11:27:15,653 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-16 11:27:15,673 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-16 11:27:15,838 INFO L321 Elim1Store]: treesize reduction 61, result has 28.2 percent of original size [2022-11-16 11:27:15,838 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 3 case distinctions, treesize of input 39 treesize of output 41 [2022-11-16 11:27:16,510 INFO L321 Elim1Store]: treesize reduction 18, result has 14.3 percent of original size [2022-11-16 11:27:16,510 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 33 treesize of output 13 [2022-11-16 11:27:16,515 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 71 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:27:16,515 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:27:22,037 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 68 treesize of output 64 [2022-11-16 11:27:22,048 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-16 11:27:22,048 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 508 treesize of output 492 [2022-11-16 11:27:22,441 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 71 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:27:22,442 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1808963442] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:27:22,442 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-16 11:27:22,442 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 17, 17] total 42 [2022-11-16 11:27:22,442 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1599758856] [2022-11-16 11:27:22,442 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-16 11:27:22,443 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:27:22,443 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:27:22,443 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 24 times [2022-11-16 11:27:22,443 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:27:22,443 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1864024049] [2022-11-16 11:27:22,443 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:27:22,444 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:27:22,447 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:27:22,447 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:27:22,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:27:22,451 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:27:22,527 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:27:22,527 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 43 interpolants. [2022-11-16 11:27:22,528 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=188, Invalid=1617, Unknown=1, NotChecked=0, Total=1806 [2022-11-16 11:27:22,528 INFO L87 Difference]: Start difference. First operand 63 states and 82 transitions. cyclomatic complexity: 24 Second operand has 43 states, 42 states have (on average 2.0238095238095237) internal successors, (85), 43 states have internal predecessors, (85), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:27:23,999 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:27:23,999 INFO L93 Difference]: Finished difference Result 122 states and 149 transitions. [2022-11-16 11:27:23,999 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 122 states and 149 transitions. [2022-11-16 11:27:24,000 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:27:24,000 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 122 states to 120 states and 147 transitions. [2022-11-16 11:27:24,000 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21 [2022-11-16 11:27:24,001 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21 [2022-11-16 11:27:24,001 INFO L73 IsDeterministic]: Start isDeterministic. Operand 120 states and 147 transitions. [2022-11-16 11:27:24,001 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-16 11:27:24,001 INFO L218 hiAutomatonCegarLoop]: Abstraction has 120 states and 147 transitions. [2022-11-16 11:27:24,001 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 120 states and 147 transitions. [2022-11-16 11:27:24,002 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 120 to 70. [2022-11-16 11:27:24,003 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 70 states, 70 states have (on average 1.3285714285714285) internal successors, (93), 69 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:27:24,003 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 70 states to 70 states and 93 transitions. [2022-11-16 11:27:24,003 INFO L240 hiAutomatonCegarLoop]: Abstraction has 70 states and 93 transitions. [2022-11-16 11:27:24,004 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2022-11-16 11:27:24,004 INFO L428 stractBuchiCegarLoop]: Abstraction has 70 states and 93 transitions. [2022-11-16 11:27:24,004 INFO L335 stractBuchiCegarLoop]: ======== Iteration 29 ============ [2022-11-16 11:27:24,005 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 70 states and 93 transitions. [2022-11-16 11:27:24,005 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:27:24,005 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:27:24,005 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:27:24,006 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [6, 6, 5, 4, 4, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:27:24,006 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-16 11:27:24,006 INFO L748 eck$LassoCheckResult]: Stem: 8214#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 8215#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 8225#L367 assume !(main_~length~0#1 < 1); 8216#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 8217#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 8218#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8226#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 8283#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8227#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8228#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 8282#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8281#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8280#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 8279#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8278#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8277#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8275#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8273#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8264#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 8261#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8260#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8248#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8247#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8245#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 8244#L370-4 main_~j~0#1 := 0; 8243#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8229#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 8241#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8240#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 8239#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8238#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 8237#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8236#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 8235#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8219#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 8220#L378-2 [2022-11-16 11:27:24,006 INFO L750 eck$LassoCheckResult]: Loop: 8220#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8234#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 8220#L378-2 [2022-11-16 11:27:24,006 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:27:24,007 INFO L85 PathProgramCache]: Analyzing trace with hash 575418155, now seen corresponding path program 17 times [2022-11-16 11:27:24,007 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:27:24,007 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1686808699] [2022-11-16 11:27:24,007 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:27:24,007 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:27:24,047 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:27:24,881 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 71 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:27:24,881 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:27:24,882 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1686808699] [2022-11-16 11:27:24,882 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1686808699] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:27:24,882 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1036102523] [2022-11-16 11:27:24,882 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-16 11:27:24,882 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:27:24,882 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:27:24,886 INFO L229 MonitoredProcess]: Starting monitored process 43 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:27:24,914 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (43)] Waiting until timeout for monitored process [2022-11-16 11:27:25,054 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) [2022-11-16 11:27:25,054 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-16 11:27:25,056 INFO L263 TraceCheckSpWp]: Trace formula consists of 196 conjuncts, 38 conjunts are in the unsatisfiable core [2022-11-16 11:27:25,058 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:27:25,305 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-16 11:27:25,464 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:27:25,464 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 26 [2022-11-16 11:27:25,475 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:27:25,476 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 26 [2022-11-16 11:27:25,973 INFO L173 IndexEqualityManager]: detected equality via solver [2022-11-16 11:27:25,976 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-16 11:27:25,976 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 19 treesize of output 12 [2022-11-16 11:27:26,005 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 71 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:27:26,005 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:27:26,425 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2022-11-16 11:27:26,429 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 20 [2022-11-16 11:27:26,489 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 71 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:27:26,489 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1036102523] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:27:26,489 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-16 11:27:26,489 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 18, 17] total 36 [2022-11-16 11:27:26,490 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1400778664] [2022-11-16 11:27:26,490 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-16 11:27:26,491 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:27:26,491 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:27:26,491 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 25 times [2022-11-16 11:27:26,491 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:27:26,491 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1220111250] [2022-11-16 11:27:26,491 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:27:26,491 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:27:26,494 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:27:26,495 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:27:26,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:27:26,498 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:27:26,577 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:27:26,577 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2022-11-16 11:27:26,578 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=141, Invalid=1191, Unknown=0, NotChecked=0, Total=1332 [2022-11-16 11:27:26,578 INFO L87 Difference]: Start difference. First operand 70 states and 93 transitions. cyclomatic complexity: 29 Second operand has 37 states, 36 states have (on average 2.0) internal successors, (72), 37 states have internal predecessors, (72), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:27:27,423 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:27:27,423 INFO L93 Difference]: Finished difference Result 80 states and 103 transitions. [2022-11-16 11:27:27,423 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 80 states and 103 transitions. [2022-11-16 11:27:27,424 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:27:27,424 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 80 states to 79 states and 102 transitions. [2022-11-16 11:27:27,425 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-16 11:27:27,425 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-16 11:27:27,425 INFO L73 IsDeterministic]: Start isDeterministic. Operand 79 states and 102 transitions. [2022-11-16 11:27:27,425 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-16 11:27:27,425 INFO L218 hiAutomatonCegarLoop]: Abstraction has 79 states and 102 transitions. [2022-11-16 11:27:27,426 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 79 states and 102 transitions. [2022-11-16 11:27:27,427 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 79 to 42. [2022-11-16 11:27:27,427 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 42 states, 42 states have (on average 1.2380952380952381) internal successors, (52), 41 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:27:27,427 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42 states to 42 states and 52 transitions. [2022-11-16 11:27:27,427 INFO L240 hiAutomatonCegarLoop]: Abstraction has 42 states and 52 transitions. [2022-11-16 11:27:27,428 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2022-11-16 11:27:27,428 INFO L428 stractBuchiCegarLoop]: Abstraction has 42 states and 52 transitions. [2022-11-16 11:27:27,429 INFO L335 stractBuchiCegarLoop]: ======== Iteration 30 ============ [2022-11-16 11:27:27,429 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 42 states and 52 transitions. [2022-11-16 11:27:27,429 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:27:27,429 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:27:27,429 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:27:27,430 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [6, 6, 6, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:27:27,430 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-16 11:27:27,430 INFO L748 eck$LassoCheckResult]: Stem: 8620#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 8621#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 8631#L367 assume !(main_~length~0#1 < 1); 8622#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 8623#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 8624#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8632#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 8636#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8661#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8660#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 8659#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8658#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8657#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 8656#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8655#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8654#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 8653#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8652#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8651#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8637#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8633#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8634#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 8648#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8641#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 8629#L370-4 main_~j~0#1 := 0; 8630#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8627#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 8628#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8635#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 8647#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8646#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 8645#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8644#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 8643#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8639#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 8638#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8625#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 8626#L378-2 [2022-11-16 11:27:27,430 INFO L750 eck$LassoCheckResult]: Loop: 8626#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8640#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 8626#L378-2 [2022-11-16 11:27:27,430 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:27:27,430 INFO L85 PathProgramCache]: Analyzing trace with hash -187204696, now seen corresponding path program 18 times [2022-11-16 11:27:27,430 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:27:27,430 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1039696394] [2022-11-16 11:27:27,430 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:27:27,431 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:27:27,462 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:27:28,256 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 0 proven. 81 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:27:28,256 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:27:28,256 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1039696394] [2022-11-16 11:27:28,257 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1039696394] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:27:28,257 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1536621665] [2022-11-16 11:27:28,257 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-11-16 11:27:28,257 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:27:28,257 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:27:28,261 INFO L229 MonitoredProcess]: Starting monitored process 44 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:27:28,277 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (44)] Waiting until timeout for monitored process [2022-11-16 11:27:28,471 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) [2022-11-16 11:27:28,471 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-16 11:27:28,472 INFO L263 TraceCheckSpWp]: Trace formula consists of 201 conjuncts, 24 conjunts are in the unsatisfiable core [2022-11-16 11:27:28,473 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:27:28,683 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-16 11:27:29,507 INFO L321 Elim1Store]: treesize reduction 9, result has 25.0 percent of original size [2022-11-16 11:27:29,507 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 12 [2022-11-16 11:27:29,539 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 25 proven. 56 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:27:29,540 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:27:30,653 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 41 treesize of output 37 [2022-11-16 11:27:30,659 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 24 [2022-11-16 11:27:30,865 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 20 proven. 61 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:27:30,865 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1536621665] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:27:30,865 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-16 11:27:30,865 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 18, 18] total 43 [2022-11-16 11:27:30,865 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [937850160] [2022-11-16 11:27:30,865 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-16 11:27:30,866 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:27:30,866 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:27:30,866 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 26 times [2022-11-16 11:27:30,866 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:27:30,866 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2140874135] [2022-11-16 11:27:30,866 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:27:30,866 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:27:30,869 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:27:30,870 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:27:30,871 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:27:30,873 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:27:30,938 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:27:30,938 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2022-11-16 11:27:30,939 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=234, Invalid=1658, Unknown=0, NotChecked=0, Total=1892 [2022-11-16 11:27:30,939 INFO L87 Difference]: Start difference. First operand 42 states and 52 transitions. cyclomatic complexity: 14 Second operand has 44 states, 43 states have (on average 1.9767441860465116) internal successors, (85), 44 states have internal predecessors, (85), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:27:32,830 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:27:32,830 INFO L93 Difference]: Finished difference Result 112 states and 134 transitions. [2022-11-16 11:27:32,830 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 112 states and 134 transitions. [2022-11-16 11:27:32,831 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:27:32,831 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 112 states to 96 states and 116 transitions. [2022-11-16 11:27:32,832 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-16 11:27:32,832 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-16 11:27:32,832 INFO L73 IsDeterministic]: Start isDeterministic. Operand 96 states and 116 transitions. [2022-11-16 11:27:32,832 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-16 11:27:32,832 INFO L218 hiAutomatonCegarLoop]: Abstraction has 96 states and 116 transitions. [2022-11-16 11:27:32,833 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 96 states and 116 transitions. [2022-11-16 11:27:32,834 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 96 to 63. [2022-11-16 11:27:32,834 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 63 states, 63 states have (on average 1.253968253968254) internal successors, (79), 62 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:27:32,834 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63 states to 63 states and 79 transitions. [2022-11-16 11:27:32,835 INFO L240 hiAutomatonCegarLoop]: Abstraction has 63 states and 79 transitions. [2022-11-16 11:27:32,838 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2022-11-16 11:27:32,839 INFO L428 stractBuchiCegarLoop]: Abstraction has 63 states and 79 transitions. [2022-11-16 11:27:32,839 INFO L335 stractBuchiCegarLoop]: ======== Iteration 31 ============ [2022-11-16 11:27:32,839 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 63 states and 79 transitions. [2022-11-16 11:27:32,839 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:27:32,840 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:27:32,840 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:27:32,840 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [6, 6, 6, 5, 4, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:27:32,840 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-16 11:27:32,841 INFO L748 eck$LassoCheckResult]: Stem: 9092#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 9093#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 9103#L367 assume !(main_~length~0#1 < 1); 9094#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 9095#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 9096#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9104#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9144#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9154#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9109#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 9110#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9105#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9106#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 9138#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9153#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9152#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 9131#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9151#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9147#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9124#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9126#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9123#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 9125#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9114#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 9115#L370-4 main_~j~0#1 := 0; 9107#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9108#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 9150#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9149#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 9148#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9146#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 9145#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9120#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 9117#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9113#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 9112#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9097#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 9098#L378-2 [2022-11-16 11:27:32,841 INFO L750 eck$LassoCheckResult]: Loop: 9098#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9111#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 9098#L378-2 [2022-11-16 11:27:32,841 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:27:32,841 INFO L85 PathProgramCache]: Analyzing trace with hash -888804570, now seen corresponding path program 19 times [2022-11-16 11:27:32,841 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:27:32,842 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [61041584] [2022-11-16 11:27:32,842 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:27:32,842 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:27:32,876 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:27:33,586 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 0 proven. 81 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:27:33,586 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:27:33,586 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [61041584] [2022-11-16 11:27:33,586 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [61041584] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:27:33,586 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [712702745] [2022-11-16 11:27:33,587 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-11-16 11:27:33,587 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:27:33,587 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:27:33,589 INFO L229 MonitoredProcess]: Starting monitored process 45 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:27:33,590 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (45)] Waiting until timeout for monitored process [2022-11-16 11:27:33,704 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:27:33,706 INFO L263 TraceCheckSpWp]: Trace formula consists of 208 conjuncts, 37 conjunts are in the unsatisfiable core [2022-11-16 11:27:33,708 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:27:34,000 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 9 [2022-11-16 11:27:34,568 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 9 [2022-11-16 11:27:34,599 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 0 proven. 81 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:27:34,599 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:27:34,788 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2022-11-16 11:27:34,791 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 20 [2022-11-16 11:27:34,857 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 0 proven. 81 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:27:34,858 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [712702745] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:27:34,858 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-16 11:27:34,858 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 16] total 34 [2022-11-16 11:27:34,858 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [368178918] [2022-11-16 11:27:34,858 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-16 11:27:34,859 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:27:34,859 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:27:34,859 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 27 times [2022-11-16 11:27:34,859 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:27:34,859 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [981507431] [2022-11-16 11:27:34,859 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:27:34,860 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:27:34,862 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:27:34,863 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:27:34,864 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:27:34,865 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:27:34,928 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:27:34,928 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2022-11-16 11:27:34,929 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=123, Invalid=1067, Unknown=0, NotChecked=0, Total=1190 [2022-11-16 11:27:34,929 INFO L87 Difference]: Start difference. First operand 63 states and 79 transitions. cyclomatic complexity: 20 Second operand has 35 states, 34 states have (on average 2.235294117647059) internal successors, (76), 35 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:27:36,049 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:27:36,049 INFO L93 Difference]: Finished difference Result 106 states and 130 transitions. [2022-11-16 11:27:36,049 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 106 states and 130 transitions. [2022-11-16 11:27:36,050 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-16 11:27:36,050 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 106 states to 105 states and 129 transitions. [2022-11-16 11:27:36,050 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18 [2022-11-16 11:27:36,051 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18 [2022-11-16 11:27:36,051 INFO L73 IsDeterministic]: Start isDeterministic. Operand 105 states and 129 transitions. [2022-11-16 11:27:36,051 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-16 11:27:36,051 INFO L218 hiAutomatonCegarLoop]: Abstraction has 105 states and 129 transitions. [2022-11-16 11:27:36,051 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 105 states and 129 transitions. [2022-11-16 11:27:36,052 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 105 to 76. [2022-11-16 11:27:36,053 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 76 states, 76 states have (on average 1.2763157894736843) internal successors, (97), 75 states have internal predecessors, (97), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:27:36,053 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 76 states to 76 states and 97 transitions. [2022-11-16 11:27:36,053 INFO L240 hiAutomatonCegarLoop]: Abstraction has 76 states and 97 transitions. [2022-11-16 11:27:36,054 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2022-11-16 11:27:36,054 INFO L428 stractBuchiCegarLoop]: Abstraction has 76 states and 97 transitions. [2022-11-16 11:27:36,054 INFO L335 stractBuchiCegarLoop]: ======== Iteration 32 ============ [2022-11-16 11:27:36,054 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 76 states and 97 transitions. [2022-11-16 11:27:36,055 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:27:36,055 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:27:36,055 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:27:36,055 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [7, 6, 6, 6, 4, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:27:36,055 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-16 11:27:36,055 INFO L748 eck$LassoCheckResult]: Stem: 9523#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 9524#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 9534#L367 assume !(main_~length~0#1 < 1); 9525#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 9526#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 9527#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9535#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9597#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9595#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9593#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 9591#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9589#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9587#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 9585#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9583#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9581#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 9579#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9577#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9574#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9572#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9570#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9567#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 9541#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9543#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 9532#L370-4 main_~j~0#1 := 0; 9533#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9530#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 9531#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9539#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 9554#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9553#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 9552#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9551#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 9550#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9549#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 9548#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9547#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 9546#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9528#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 9529#L378-2 [2022-11-16 11:27:36,056 INFO L750 eck$LassoCheckResult]: Loop: 9529#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9545#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 9529#L378-2 [2022-11-16 11:27:36,056 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:27:36,056 INFO L85 PathProgramCache]: Analyzing trace with hash 557299561, now seen corresponding path program 20 times [2022-11-16 11:27:36,056 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:27:36,056 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [152612472] [2022-11-16 11:27:36,056 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:27:36,056 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:27:36,072 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:27:36,372 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 31 proven. 62 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:27:36,372 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:27:36,372 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [152612472] [2022-11-16 11:27:36,372 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [152612472] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:27:36,372 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2033881670] [2022-11-16 11:27:36,372 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-16 11:27:36,373 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:27:36,373 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:27:36,377 INFO L229 MonitoredProcess]: Starting monitored process 46 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:27:36,378 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (46)] Waiting until timeout for monitored process [2022-11-16 11:27:36,498 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-16 11:27:36,499 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-16 11:27:36,500 INFO L263 TraceCheckSpWp]: Trace formula consists of 220 conjuncts, 16 conjunts are in the unsatisfiable core [2022-11-16 11:27:36,501 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:27:36,766 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 42 proven. 51 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:27:36,766 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:27:36,974 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 42 proven. 51 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:27:36,975 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2033881670] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:27:36,975 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-16 11:27:36,975 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17] total 26 [2022-11-16 11:27:36,975 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1743397794] [2022-11-16 11:27:36,975 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-16 11:27:36,975 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:27:36,976 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:27:36,976 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 28 times [2022-11-16 11:27:36,976 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:27:36,976 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2108155777] [2022-11-16 11:27:36,976 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:27:36,976 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:27:36,979 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:27:36,979 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:27:36,980 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:27:36,982 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:27:37,045 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:27:37,046 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2022-11-16 11:27:37,046 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=157, Invalid=493, Unknown=0, NotChecked=0, Total=650 [2022-11-16 11:27:37,047 INFO L87 Difference]: Start difference. First operand 76 states and 97 transitions. cyclomatic complexity: 26 Second operand has 26 states, 26 states have (on average 2.3076923076923075) internal successors, (60), 26 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:27:37,353 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:27:37,353 INFO L93 Difference]: Finished difference Result 96 states and 118 transitions. [2022-11-16 11:27:37,354 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 96 states and 118 transitions. [2022-11-16 11:27:37,354 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:27:37,355 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 96 states to 82 states and 104 transitions. [2022-11-16 11:27:37,355 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-16 11:27:37,355 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-16 11:27:37,355 INFO L73 IsDeterministic]: Start isDeterministic. Operand 82 states and 104 transitions. [2022-11-16 11:27:37,355 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-16 11:27:37,355 INFO L218 hiAutomatonCegarLoop]: Abstraction has 82 states and 104 transitions. [2022-11-16 11:27:37,356 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 82 states and 104 transitions. [2022-11-16 11:27:37,357 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 82 to 58. [2022-11-16 11:27:37,357 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 58 states, 58 states have (on average 1.2586206896551724) internal successors, (73), 57 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:27:37,357 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 58 states to 58 states and 73 transitions. [2022-11-16 11:27:37,357 INFO L240 hiAutomatonCegarLoop]: Abstraction has 58 states and 73 transitions. [2022-11-16 11:27:37,358 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2022-11-16 11:27:37,358 INFO L428 stractBuchiCegarLoop]: Abstraction has 58 states and 73 transitions. [2022-11-16 11:27:37,359 INFO L335 stractBuchiCegarLoop]: ======== Iteration 33 ============ [2022-11-16 11:27:37,359 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 58 states and 73 transitions. [2022-11-16 11:27:37,359 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:27:37,359 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:27:37,359 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:27:37,360 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [7, 7, 6, 5, 5, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:27:37,360 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-16 11:27:37,360 INFO L748 eck$LassoCheckResult]: Stem: 9968#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 9969#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 9979#L367 assume !(main_~length~0#1 < 1); 9970#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 9971#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 9972#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9980#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 9983#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9981#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9982#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 10025#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10024#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10023#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 10022#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10021#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10020#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 10019#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10018#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10015#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10013#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10012#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10010#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 10011#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10006#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10001#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9997#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9985#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 9973#L370-4 main_~j~0#1 := 0; 9974#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9984#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 9996#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9995#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 9994#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9993#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 9992#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9991#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 9990#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9988#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 9987#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9975#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 9976#L378-2 [2022-11-16 11:27:37,360 INFO L750 eck$LassoCheckResult]: Loop: 9976#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9989#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 9976#L378-2 [2022-11-16 11:27:37,360 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:27:37,361 INFO L85 PathProgramCache]: Analyzing trace with hash -50400780, now seen corresponding path program 21 times [2022-11-16 11:27:37,361 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:27:37,361 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [40998465] [2022-11-16 11:27:37,361 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:27:37,361 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:27:37,443 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:27:38,312 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:27:38,312 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:27:38,312 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [40998465] [2022-11-16 11:27:38,312 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [40998465] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:27:38,313 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [890591666] [2022-11-16 11:27:38,313 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-16 11:27:38,313 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:27:38,313 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:27:38,314 INFO L229 MonitoredProcess]: Starting monitored process 47 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:27:38,316 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (47)] Waiting until timeout for monitored process [2022-11-16 11:27:38,803 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 8 check-sat command(s) [2022-11-16 11:27:38,803 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-16 11:27:38,805 INFO L263 TraceCheckSpWp]: Trace formula consists of 223 conjuncts, 40 conjunts are in the unsatisfiable core [2022-11-16 11:27:38,808 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:27:38,876 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-16 11:27:39,037 INFO L321 Elim1Store]: treesize reduction 29, result has 27.5 percent of original size [2022-11-16 11:27:39,037 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 30 [2022-11-16 11:27:39,066 INFO L321 Elim1Store]: treesize reduction 29, result has 27.5 percent of original size [2022-11-16 11:27:39,066 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 30 [2022-11-16 11:27:39,834 INFO L321 Elim1Store]: treesize reduction 30, result has 9.1 percent of original size [2022-11-16 11:27:39,834 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 44 treesize of output 17 [2022-11-16 11:27:39,838 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:27:39,838 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:27:40,110 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2022-11-16 11:27:40,115 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 20 [2022-11-16 11:27:40,185 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 1 proven. 98 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-16 11:27:40,185 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [890591666] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:27:40,185 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-16 11:27:40,185 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18, 17] total 30 [2022-11-16 11:27:40,185 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1143632290] [2022-11-16 11:27:40,185 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-16 11:27:40,186 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:27:40,186 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:27:40,186 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 29 times [2022-11-16 11:27:40,186 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:27:40,187 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2147003415] [2022-11-16 11:27:40,187 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:27:40,187 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:27:40,190 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:27:40,190 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:27:40,192 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:27:40,194 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:27:40,269 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:27:40,269 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2022-11-16 11:27:40,270 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=116, Invalid=814, Unknown=0, NotChecked=0, Total=930 [2022-11-16 11:27:40,270 INFO L87 Difference]: Start difference. First operand 58 states and 73 transitions. cyclomatic complexity: 20 Second operand has 31 states, 30 states have (on average 2.2333333333333334) internal successors, (67), 31 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:27:42,363 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:27:42,363 INFO L93 Difference]: Finished difference Result 109 states and 131 transitions. [2022-11-16 11:27:42,363 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 109 states and 131 transitions. [2022-11-16 11:27:42,364 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:27:42,364 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 109 states to 108 states and 129 transitions. [2022-11-16 11:27:42,364 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19 [2022-11-16 11:27:42,365 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19 [2022-11-16 11:27:42,365 INFO L73 IsDeterministic]: Start isDeterministic. Operand 108 states and 129 transitions. [2022-11-16 11:27:42,365 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-16 11:27:42,365 INFO L218 hiAutomatonCegarLoop]: Abstraction has 108 states and 129 transitions. [2022-11-16 11:27:42,365 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 108 states and 129 transitions. [2022-11-16 11:27:42,366 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 108 to 65. [2022-11-16 11:27:42,367 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 65 states, 65 states have (on average 1.3076923076923077) internal successors, (85), 64 states have internal predecessors, (85), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:27:42,367 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 65 states to 65 states and 85 transitions. [2022-11-16 11:27:42,367 INFO L240 hiAutomatonCegarLoop]: Abstraction has 65 states and 85 transitions. [2022-11-16 11:27:42,368 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2022-11-16 11:27:42,368 INFO L428 stractBuchiCegarLoop]: Abstraction has 65 states and 85 transitions. [2022-11-16 11:27:42,368 INFO L335 stractBuchiCegarLoop]: ======== Iteration 34 ============ [2022-11-16 11:27:42,368 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 65 states and 85 transitions. [2022-11-16 11:27:42,369 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:27:42,369 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:27:42,369 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:27:42,369 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [7, 7, 7, 6, 5, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:27:42,370 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-16 11:27:42,370 INFO L748 eck$LassoCheckResult]: Stem: 10413#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 10414#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 10424#L367 assume !(main_~length~0#1 < 1); 10415#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 10416#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 10417#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10425#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 10428#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10426#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10427#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 10470#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10469#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10468#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 10467#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10466#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10465#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 10464#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10463#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10461#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10462#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10477#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10476#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10475#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10474#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10473#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 10454#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10453#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 10418#L370-4 main_~j~0#1 := 0; 10419#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10422#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 10423#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10429#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 10439#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10438#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 10437#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10436#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 10435#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10434#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 10433#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10431#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 10430#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10420#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 10421#L378-2 [2022-11-16 11:27:42,370 INFO L750 eck$LassoCheckResult]: Loop: 10421#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10432#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 10421#L378-2 [2022-11-16 11:27:42,370 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:27:42,371 INFO L85 PathProgramCache]: Analyzing trace with hash 687610867, now seen corresponding path program 22 times [2022-11-16 11:27:42,371 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:27:42,371 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1486941363] [2022-11-16 11:27:42,371 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:27:42,371 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:27:42,404 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:27:43,239 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 0 proven. 112 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:27:43,239 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:27:43,239 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1486941363] [2022-11-16 11:27:43,239 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1486941363] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:27:43,239 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1978397145] [2022-11-16 11:27:43,239 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-16 11:27:43,240 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:27:43,240 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:27:43,242 INFO L229 MonitoredProcess]: Starting monitored process 48 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:27:43,243 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (48)] Waiting until timeout for monitored process [2022-11-16 11:27:43,367 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-16 11:27:43,367 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-16 11:27:43,369 INFO L263 TraceCheckSpWp]: Trace formula consists of 219 conjuncts, 37 conjunts are in the unsatisfiable core [2022-11-16 11:27:43,371 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:27:43,456 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-16 11:27:43,914 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 11 [2022-11-16 11:27:43,918 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 0 proven. 112 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:27:43,918 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:27:44,133 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2022-11-16 11:27:44,137 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 20 [2022-11-16 11:27:44,225 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 0 proven. 112 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:27:44,226 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1978397145] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:27:44,226 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-16 11:27:44,226 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 18, 18] total 28 [2022-11-16 11:27:44,226 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [647027974] [2022-11-16 11:27:44,226 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-16 11:27:44,226 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:27:44,226 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:27:44,226 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 30 times [2022-11-16 11:27:44,227 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:27:44,227 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1867538883] [2022-11-16 11:27:44,227 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:27:44,227 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:27:44,229 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:27:44,230 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:27:44,231 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:27:44,232 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:27:44,291 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:27:44,292 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2022-11-16 11:27:44,292 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=82, Invalid=730, Unknown=0, NotChecked=0, Total=812 [2022-11-16 11:27:44,292 INFO L87 Difference]: Start difference. First operand 65 states and 85 transitions. cyclomatic complexity: 26 Second operand has 29 states, 28 states have (on average 2.2142857142857144) internal successors, (62), 29 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:27:45,143 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:27:45,143 INFO L93 Difference]: Finished difference Result 86 states and 108 transitions. [2022-11-16 11:27:45,143 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 86 states and 108 transitions. [2022-11-16 11:27:45,143 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-16 11:27:45,144 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 86 states to 85 states and 107 transitions. [2022-11-16 11:27:45,144 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18 [2022-11-16 11:27:45,144 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18 [2022-11-16 11:27:45,144 INFO L73 IsDeterministic]: Start isDeterministic. Operand 85 states and 107 transitions. [2022-11-16 11:27:45,144 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-16 11:27:45,144 INFO L218 hiAutomatonCegarLoop]: Abstraction has 85 states and 107 transitions. [2022-11-16 11:27:45,145 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 85 states and 107 transitions. [2022-11-16 11:27:45,146 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 85 to 69. [2022-11-16 11:27:45,146 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 69 states, 69 states have (on average 1.289855072463768) internal successors, (89), 68 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:27:45,146 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 69 states to 69 states and 89 transitions. [2022-11-16 11:27:45,146 INFO L240 hiAutomatonCegarLoop]: Abstraction has 69 states and 89 transitions. [2022-11-16 11:27:45,147 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2022-11-16 11:27:45,147 INFO L428 stractBuchiCegarLoop]: Abstraction has 69 states and 89 transitions. [2022-11-16 11:27:45,147 INFO L335 stractBuchiCegarLoop]: ======== Iteration 35 ============ [2022-11-16 11:27:45,147 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 69 states and 89 transitions. [2022-11-16 11:27:45,148 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:27:45,148 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:27:45,148 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:27:45,148 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [7, 7, 7, 6, 5, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:27:45,148 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-16 11:27:45,149 INFO L748 eck$LassoCheckResult]: Stem: 10846#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 10847#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 10857#L367 assume !(main_~length~0#1 < 1); 10848#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 10849#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 10850#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10858#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 10914#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10859#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10860#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 10861#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10863#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10913#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 10912#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10911#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10910#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 10908#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10907#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10905#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10903#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10902#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10900#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 10897#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10895#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10893#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10892#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10864#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 10851#L370-4 main_~j~0#1 := 0; 10852#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10855#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 10856#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10876#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 10875#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10874#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 10873#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10872#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 10871#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10870#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 10869#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10867#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 10866#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10853#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 10854#L378-2 [2022-11-16 11:27:45,149 INFO L750 eck$LassoCheckResult]: Loop: 10854#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10868#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 10854#L378-2 [2022-11-16 11:27:45,149 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:27:45,149 INFO L85 PathProgramCache]: Analyzing trace with hash -1190509897, now seen corresponding path program 23 times [2022-11-16 11:27:45,149 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:27:45,149 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1518297640] [2022-11-16 11:27:45,150 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:27:45,150 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:27:45,189 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:27:45,882 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 0 proven. 112 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:27:45,882 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:27:45,882 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1518297640] [2022-11-16 11:27:45,882 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1518297640] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:27:45,882 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [834321293] [2022-11-16 11:27:45,882 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-16 11:27:45,882 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:27:45,882 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:27:45,886 INFO L229 MonitoredProcess]: Starting monitored process 49 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:27:45,898 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (49)] Waiting until timeout for monitored process [2022-11-16 11:27:46,142 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 8 check-sat command(s) [2022-11-16 11:27:46,143 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-16 11:27:46,145 INFO L263 TraceCheckSpWp]: Trace formula consists of 235 conjuncts, 51 conjunts are in the unsatisfiable core [2022-11-16 11:27:46,148 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:27:46,424 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-16 11:27:46,524 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-16 11:27:46,591 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-16 11:27:46,605 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2022-11-16 11:27:47,341 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:27:47,342 INFO L173 IndexEqualityManager]: detected equality via solver [2022-11-16 11:27:47,344 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-16 11:27:47,344 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 1 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 24 treesize of output 13 [2022-11-16 11:27:47,347 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 0 proven. 112 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:27:47,348 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:27:48,858 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 76 treesize of output 72 [2022-11-16 11:27:48,869 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-16 11:27:48,869 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 1532 treesize of output 1462 [2022-11-16 11:27:49,432 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 0 proven. 112 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:27:49,432 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [834321293] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:27:49,432 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-16 11:27:49,433 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 21, 21] total 57 [2022-11-16 11:27:49,433 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1102661275] [2022-11-16 11:27:49,433 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-16 11:27:49,433 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:27:49,434 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:27:49,434 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 31 times [2022-11-16 11:27:49,434 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:27:49,434 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1338052850] [2022-11-16 11:27:49,434 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:27:49,434 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:27:49,437 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:27:49,437 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:27:49,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:27:49,441 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:27:49,503 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:27:49,503 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 58 interpolants. [2022-11-16 11:27:49,505 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=283, Invalid=3023, Unknown=0, NotChecked=0, Total=3306 [2022-11-16 11:27:49,505 INFO L87 Difference]: Start difference. First operand 69 states and 89 transitions. cyclomatic complexity: 26 Second operand has 58 states, 57 states have (on average 2.0701754385964914) internal successors, (118), 58 states have internal predecessors, (118), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:27:54,604 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:27:54,604 INFO L93 Difference]: Finished difference Result 188 states and 227 transitions. [2022-11-16 11:27:54,604 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 188 states and 227 transitions. [2022-11-16 11:27:54,605 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 10 [2022-11-16 11:27:54,606 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 188 states to 184 states and 223 transitions. [2022-11-16 11:27:54,606 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 39 [2022-11-16 11:27:54,607 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 39 [2022-11-16 11:27:54,607 INFO L73 IsDeterministic]: Start isDeterministic. Operand 184 states and 223 transitions. [2022-11-16 11:27:54,607 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-16 11:27:54,607 INFO L218 hiAutomatonCegarLoop]: Abstraction has 184 states and 223 transitions. [2022-11-16 11:27:54,608 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 184 states and 223 transitions. [2022-11-16 11:27:54,609 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 184 to 94. [2022-11-16 11:27:54,610 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 94 states, 94 states have (on average 1.297872340425532) internal successors, (122), 93 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:27:54,610 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 94 states to 94 states and 122 transitions. [2022-11-16 11:27:54,610 INFO L240 hiAutomatonCegarLoop]: Abstraction has 94 states and 122 transitions. [2022-11-16 11:27:54,610 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 60 states. [2022-11-16 11:27:54,611 INFO L428 stractBuchiCegarLoop]: Abstraction has 94 states and 122 transitions. [2022-11-16 11:27:54,611 INFO L335 stractBuchiCegarLoop]: ======== Iteration 36 ============ [2022-11-16 11:27:54,611 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 94 states and 122 transitions. [2022-11-16 11:27:54,612 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:27:54,612 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:27:54,612 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:27:54,612 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [7, 7, 7, 6, 5, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:27:54,612 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-16 11:27:54,613 INFO L748 eck$LassoCheckResult]: Stem: 11493#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 11494#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 11504#L367 assume !(main_~length~0#1 < 1); 11495#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 11496#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 11497#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11505#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 11544#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11543#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11542#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 11541#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11540#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11539#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 11538#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11537#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11536#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 11535#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11534#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11532#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 11533#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11545#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11524#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11525#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11506#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11507#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11508#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11516#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 11586#L370-4 main_~j~0#1 := 0; 11585#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11502#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 11503#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11575#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 11574#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11573#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 11572#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11571#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 11570#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11518#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 11546#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11520#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 11521#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11500#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 11501#L378-2 [2022-11-16 11:27:54,613 INFO L750 eck$LassoCheckResult]: Loop: 11501#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11519#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 11501#L378-2 [2022-11-16 11:27:54,613 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:27:54,613 INFO L85 PathProgramCache]: Analyzing trace with hash -1747225229, now seen corresponding path program 24 times [2022-11-16 11:27:54,614 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:27:54,614 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1544898405] [2022-11-16 11:27:54,614 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:27:54,614 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:27:54,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:27:55,327 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 0 proven. 112 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:27:55,327 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:27:55,328 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1544898405] [2022-11-16 11:27:55,328 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1544898405] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:27:55,328 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [229774618] [2022-11-16 11:27:55,328 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-11-16 11:27:55,328 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:27:55,328 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:27:55,334 INFO L229 MonitoredProcess]: Starting monitored process 50 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:27:55,350 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (50)] Waiting until timeout for monitored process [2022-11-16 11:27:55,836 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 8 check-sat command(s) [2022-11-16 11:27:55,836 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-16 11:27:55,838 INFO L263 TraceCheckSpWp]: Trace formula consists of 235 conjuncts, 24 conjunts are in the unsatisfiable core [2022-11-16 11:27:55,840 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:27:56,074 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-16 11:27:56,834 INFO L321 Elim1Store]: treesize reduction 9, result has 25.0 percent of original size [2022-11-16 11:27:56,834 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 10 [2022-11-16 11:27:56,838 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 36 proven. 76 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:27:56,838 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:27:57,799 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2022-11-16 11:27:57,804 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 22 [2022-11-16 11:27:58,017 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 30 proven. 82 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:27:58,017 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [229774618] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:27:58,017 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-16 11:27:58,017 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 19, 19] total 46 [2022-11-16 11:27:58,017 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1086779959] [2022-11-16 11:27:58,018 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-16 11:27:58,018 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:27:58,018 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:27:58,018 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 32 times [2022-11-16 11:27:58,018 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:27:58,018 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [851480104] [2022-11-16 11:27:58,018 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:27:58,018 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:27:58,020 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:27:58,021 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:27:58,022 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:27:58,024 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:27:58,084 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:27:58,085 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 47 interpolants. [2022-11-16 11:27:58,086 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=261, Invalid=1901, Unknown=0, NotChecked=0, Total=2162 [2022-11-16 11:27:58,086 INFO L87 Difference]: Start difference. First operand 94 states and 122 transitions. cyclomatic complexity: 34 Second operand has 47 states, 46 states have (on average 2.108695652173913) internal successors, (97), 47 states have internal predecessors, (97), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:27:59,444 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:27:59,444 INFO L93 Difference]: Finished difference Result 139 states and 168 transitions. [2022-11-16 11:27:59,445 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 139 states and 168 transitions. [2022-11-16 11:27:59,445 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:27:59,446 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 139 states to 106 states and 133 transitions. [2022-11-16 11:27:59,446 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17 [2022-11-16 11:27:59,446 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17 [2022-11-16 11:27:59,447 INFO L73 IsDeterministic]: Start isDeterministic. Operand 106 states and 133 transitions. [2022-11-16 11:27:59,447 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-16 11:27:59,447 INFO L218 hiAutomatonCegarLoop]: Abstraction has 106 states and 133 transitions. [2022-11-16 11:27:59,447 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 106 states and 133 transitions. [2022-11-16 11:27:59,448 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 106 to 96. [2022-11-16 11:27:59,449 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 96 states, 96 states have (on average 1.28125) internal successors, (123), 95 states have internal predecessors, (123), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:27:59,449 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 96 states to 96 states and 123 transitions. [2022-11-16 11:27:59,449 INFO L240 hiAutomatonCegarLoop]: Abstraction has 96 states and 123 transitions. [2022-11-16 11:27:59,449 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2022-11-16 11:27:59,450 INFO L428 stractBuchiCegarLoop]: Abstraction has 96 states and 123 transitions. [2022-11-16 11:27:59,450 INFO L335 stractBuchiCegarLoop]: ======== Iteration 37 ============ [2022-11-16 11:27:59,450 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 96 states and 123 transitions. [2022-11-16 11:27:59,451 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:27:59,451 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:27:59,451 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:27:59,451 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [8, 8, 6, 5, 5, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:27:59,451 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-16 11:27:59,452 INFO L748 eck$LassoCheckResult]: Stem: 12074#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 12075#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 12085#L367 assume !(main_~length~0#1 < 1); 12076#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 12077#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 12078#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12086#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 12090#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12087#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12088#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 12169#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12168#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12167#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 12166#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12165#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12164#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 12163#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12162#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12159#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12158#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12157#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12152#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12153#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12156#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12138#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12128#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12140#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12127#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 12123#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12119#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 12117#L370-4 main_~j~0#1 := 0; 12113#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12111#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 12109#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12107#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 12105#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12103#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 12101#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12092#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 12098#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12094#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 12095#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12079#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 12080#L378-2 [2022-11-16 11:27:59,452 INFO L750 eck$LassoCheckResult]: Loop: 12080#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12093#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 12080#L378-2 [2022-11-16 11:27:59,452 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:27:59,453 INFO L85 PathProgramCache]: Analyzing trace with hash -1688826200, now seen corresponding path program 25 times [2022-11-16 11:27:59,453 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:27:59,453 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [826943581] [2022-11-16 11:27:59,453 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:27:59,453 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:27:59,493 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:28:00,294 INFO L134 CoverageAnalysis]: Checked inductivity of 122 backedges. 0 proven. 122 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:28:00,294 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:28:00,294 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [826943581] [2022-11-16 11:28:00,294 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [826943581] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:28:00,294 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1845308432] [2022-11-16 11:28:00,294 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-11-16 11:28:00,294 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:28:00,294 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:28:00,297 INFO L229 MonitoredProcess]: Starting monitored process 51 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:28:00,298 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (51)] Waiting until timeout for monitored process [2022-11-16 11:28:00,435 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:28:00,437 INFO L263 TraceCheckSpWp]: Trace formula consists of 245 conjuncts, 60 conjunts are in the unsatisfiable core [2022-11-16 11:28:00,440 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:28:00,444 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 9 [2022-11-16 11:28:00,516 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 5 treesize of output 3 [2022-11-16 11:28:00,737 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-16 11:28:00,852 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-16 11:28:00,866 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-16 11:28:00,996 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:28:01,000 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:28:01,002 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-16 11:28:01,003 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 34 treesize of output 36 [2022-11-16 11:28:01,019 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:28:01,021 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:28:01,023 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-16 11:28:01,024 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 34 treesize of output 36 [2022-11-16 11:28:01,110 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:28:01,111 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:28:01,113 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-16 11:28:01,114 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 34 treesize of output 36 [2022-11-16 11:28:01,714 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-16 11:28:01,714 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 22 treesize of output 10 [2022-11-16 11:28:01,717 INFO L134 CoverageAnalysis]: Checked inductivity of 122 backedges. 1 proven. 121 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:28:01,717 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:28:03,721 WARN L833 $PredicateComparison]: unable to prove that (forall ((|v_ULTIMATE.start_main_~i~0#1_351| Int)) (or (not (<= (+ |c_ULTIMATE.start_main_~i~0#1| 1) |v_ULTIMATE.start_main_~i~0#1_351|)) (forall ((v_ArrVal_1189 Int)) (let ((.cse0 (store (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |v_ULTIMATE.start_main_~i~0#1_351| 4)) v_ArrVal_1189))) (or (= (mod (select .cse0 (+ |c_ULTIMATE.start_main_~arr~0#1.offset| 20)) 2) 0) (not (= (mod (select .cse0 (+ |c_ULTIMATE.start_main_~arr~0#1.offset| 16)) 2) 0))))))) is different from false [2022-11-16 11:28:37,577 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 82 treesize of output 78 [2022-11-16 11:28:37,594 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-16 11:28:37,595 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 2660 treesize of output 2624 [2022-11-16 11:28:38,481 INFO L134 CoverageAnalysis]: Checked inductivity of 122 backedges. 1 proven. 114 refuted. 0 times theorem prover too weak. 0 trivial. 7 not checked. [2022-11-16 11:28:38,481 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1845308432] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:28:38,481 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-16 11:28:38,482 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 21, 22] total 58 [2022-11-16 11:28:38,482 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1953638835] [2022-11-16 11:28:38,482 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-16 11:28:38,482 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:28:38,482 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:28:38,482 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 33 times [2022-11-16 11:28:38,482 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:28:38,483 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1782052596] [2022-11-16 11:28:38,483 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:28:38,483 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:28:38,485 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:28:38,486 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:28:38,487 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:28:38,489 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:28:38,556 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:28:38,556 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 59 interpolants. [2022-11-16 11:28:38,557 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=293, Invalid=3013, Unknown=4, NotChecked=112, Total=3422 [2022-11-16 11:28:38,558 INFO L87 Difference]: Start difference. First operand 96 states and 123 transitions. cyclomatic complexity: 33 Second operand has 59 states, 58 states have (on average 2.086206896551724) internal successors, (121), 59 states have internal predecessors, (121), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:28:40,762 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:28:40,762 INFO L93 Difference]: Finished difference Result 211 states and 258 transitions. [2022-11-16 11:28:40,762 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 211 states and 258 transitions. [2022-11-16 11:28:40,763 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 6 [2022-11-16 11:28:40,764 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 211 states to 209 states and 256 transitions. [2022-11-16 11:28:40,764 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 35 [2022-11-16 11:28:40,764 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 35 [2022-11-16 11:28:40,764 INFO L73 IsDeterministic]: Start isDeterministic. Operand 209 states and 256 transitions. [2022-11-16 11:28:40,764 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-16 11:28:40,765 INFO L218 hiAutomatonCegarLoop]: Abstraction has 209 states and 256 transitions. [2022-11-16 11:28:40,765 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 209 states and 256 transitions. [2022-11-16 11:28:40,767 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 209 to 102. [2022-11-16 11:28:40,767 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 102 states, 102 states have (on average 1.303921568627451) internal successors, (133), 101 states have internal predecessors, (133), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:28:40,767 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 102 states to 102 states and 133 transitions. [2022-11-16 11:28:40,767 INFO L240 hiAutomatonCegarLoop]: Abstraction has 102 states and 133 transitions. [2022-11-16 11:28:40,775 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2022-11-16 11:28:40,776 INFO L428 stractBuchiCegarLoop]: Abstraction has 102 states and 133 transitions. [2022-11-16 11:28:40,776 INFO L335 stractBuchiCegarLoop]: ======== Iteration 38 ============ [2022-11-16 11:28:40,776 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 102 states and 133 transitions. [2022-11-16 11:28:40,777 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:28:40,777 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:28:40,777 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:28:40,778 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [8, 8, 6, 6, 5, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:28:40,780 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-16 11:28:40,780 INFO L748 eck$LassoCheckResult]: Stem: 12735#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 12736#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 12746#L367 assume !(main_~length~0#1 < 1); 12737#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 12738#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 12739#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12747#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 12803#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12802#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12801#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 12800#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12799#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12798#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 12797#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12796#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12795#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 12794#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12793#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12791#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12790#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12789#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12788#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 12787#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12786#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12784#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12783#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12782#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12780#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 12775#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12776#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 12772#L370-4 main_~j~0#1 := 0; 12771#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12770#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 12769#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12768#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 12767#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12766#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 12765#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12764#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 12763#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12762#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 12756#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12742#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 12743#L378-2 [2022-11-16 11:28:40,780 INFO L750 eck$LassoCheckResult]: Loop: 12743#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12758#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 12743#L378-2 [2022-11-16 11:28:40,781 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:28:40,781 INFO L85 PathProgramCache]: Analyzing trace with hash -1469971482, now seen corresponding path program 26 times [2022-11-16 11:28:40,781 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:28:40,781 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1397529741] [2022-11-16 11:28:40,781 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:28:40,781 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:28:40,827 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:28:41,953 INFO L134 CoverageAnalysis]: Checked inductivity of 122 backedges. 0 proven. 122 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:28:41,953 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:28:41,953 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1397529741] [2022-11-16 11:28:41,953 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1397529741] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:28:41,953 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [600749392] [2022-11-16 11:28:41,953 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-16 11:28:41,953 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:28:41,954 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:28:41,956 INFO L229 MonitoredProcess]: Starting monitored process 52 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:28:41,960 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (52)] Waiting until timeout for monitored process [2022-11-16 11:28:42,101 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-16 11:28:42,101 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-16 11:28:42,103 INFO L263 TraceCheckSpWp]: Trace formula consists of 238 conjuncts, 45 conjunts are in the unsatisfiable core [2022-11-16 11:28:42,106 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:28:42,428 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-16 11:28:42,625 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:28:42,626 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 26 [2022-11-16 11:28:42,640 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:28:42,640 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 26 [2022-11-16 11:28:42,734 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:28:42,735 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 26 [2022-11-16 11:28:43,243 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 9 [2022-11-16 11:28:43,277 INFO L134 CoverageAnalysis]: Checked inductivity of 122 backedges. 1 proven. 121 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:28:43,278 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:28:43,741 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2022-11-16 11:28:43,744 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 20 [2022-11-16 11:28:43,813 INFO L134 CoverageAnalysis]: Checked inductivity of 122 backedges. 1 proven. 120 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-16 11:28:43,813 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [600749392] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:28:43,813 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-16 11:28:43,813 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 20, 19] total 40 [2022-11-16 11:28:43,814 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1590424336] [2022-11-16 11:28:43,814 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-16 11:28:43,814 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:28:43,814 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:28:43,814 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 34 times [2022-11-16 11:28:43,815 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:28:43,815 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [84144047] [2022-11-16 11:28:43,815 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:28:43,815 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:28:43,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:28:43,819 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:28:43,820 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:28:43,822 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:28:43,899 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:28:43,900 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2022-11-16 11:28:43,901 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=160, Invalid=1480, Unknown=0, NotChecked=0, Total=1640 [2022-11-16 11:28:43,901 INFO L87 Difference]: Start difference. First operand 102 states and 133 transitions. cyclomatic complexity: 39 Second operand has 41 states, 40 states have (on average 2.25) internal successors, (90), 41 states have internal predecessors, (90), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:28:45,160 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:28:45,160 INFO L93 Difference]: Finished difference Result 126 states and 157 transitions. [2022-11-16 11:28:45,160 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 126 states and 157 transitions. [2022-11-16 11:28:45,161 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:28:45,161 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 126 states to 125 states and 155 transitions. [2022-11-16 11:28:45,161 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17 [2022-11-16 11:28:45,161 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17 [2022-11-16 11:28:45,161 INFO L73 IsDeterministic]: Start isDeterministic. Operand 125 states and 155 transitions. [2022-11-16 11:28:45,162 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-16 11:28:45,162 INFO L218 hiAutomatonCegarLoop]: Abstraction has 125 states and 155 transitions. [2022-11-16 11:28:45,162 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 125 states and 155 transitions. [2022-11-16 11:28:45,163 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 125 to 74. [2022-11-16 11:28:45,164 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 74 states, 74 states have (on average 1.2837837837837838) internal successors, (95), 73 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:28:45,164 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74 states to 74 states and 95 transitions. [2022-11-16 11:28:45,164 INFO L240 hiAutomatonCegarLoop]: Abstraction has 74 states and 95 transitions. [2022-11-16 11:28:45,166 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2022-11-16 11:28:45,167 INFO L428 stractBuchiCegarLoop]: Abstraction has 74 states and 95 transitions. [2022-11-16 11:28:45,167 INFO L335 stractBuchiCegarLoop]: ======== Iteration 39 ============ [2022-11-16 11:28:45,167 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 74 states and 95 transitions. [2022-11-16 11:28:45,168 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:28:45,168 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:28:45,168 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:28:45,168 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [8, 7, 7, 7, 5, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:28:45,168 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-16 11:28:45,169 INFO L748 eck$LassoCheckResult]: Stem: 13273#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 13274#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 13284#L367 assume !(main_~length~0#1 < 1); 13275#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 13276#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 13277#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13285#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 13344#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13343#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13342#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 13341#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13340#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13339#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 13338#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13337#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13336#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 13335#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13334#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13333#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13332#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13330#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13328#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13327#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13326#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13325#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 13290#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13293#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 13278#L370-4 main_~j~0#1 := 0; 13279#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13307#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 13292#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13282#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 13283#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13306#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 13305#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13304#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 13303#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13302#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 13299#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13298#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 13297#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13295#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 13294#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13280#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 13281#L378-2 [2022-11-16 11:28:45,169 INFO L750 eck$LassoCheckResult]: Loop: 13281#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13296#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 13281#L378-2 [2022-11-16 11:28:45,169 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:28:45,169 INFO L85 PathProgramCache]: Analyzing trace with hash -630920970, now seen corresponding path program 27 times [2022-11-16 11:28:45,169 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:28:45,170 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1352230512] [2022-11-16 11:28:45,170 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:28:45,170 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:28:45,185 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:28:45,590 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 43 proven. 83 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:28:45,590 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:28:45,590 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1352230512] [2022-11-16 11:28:45,590 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1352230512] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:28:45,591 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [250954482] [2022-11-16 11:28:45,591 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-16 11:28:45,591 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:28:45,591 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:28:45,592 INFO L229 MonitoredProcess]: Starting monitored process 53 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:28:45,594 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (53)] Waiting until timeout for monitored process [2022-11-16 11:28:45,972 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 8 check-sat command(s) [2022-11-16 11:28:45,973 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-16 11:28:45,975 INFO L263 TraceCheckSpWp]: Trace formula consists of 247 conjuncts, 18 conjunts are in the unsatisfiable core [2022-11-16 11:28:45,976 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:28:46,302 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 56 proven. 70 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:28:46,302 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:28:46,543 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 56 proven. 70 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:28:46,543 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [250954482] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:28:46,543 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-16 11:28:46,543 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19] total 29 [2022-11-16 11:28:46,543 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [605148755] [2022-11-16 11:28:46,543 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-16 11:28:46,544 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:28:46,544 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:28:46,544 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 35 times [2022-11-16 11:28:46,544 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:28:46,545 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [111710671] [2022-11-16 11:28:46,545 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:28:46,545 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:28:46,548 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:28:46,548 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:28:46,549 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:28:46,551 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:28:46,617 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:28:46,618 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2022-11-16 11:28:46,618 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=194, Invalid=618, Unknown=0, NotChecked=0, Total=812 [2022-11-16 11:28:46,618 INFO L87 Difference]: Start difference. First operand 74 states and 95 transitions. cyclomatic complexity: 26 Second operand has 29 states, 29 states have (on average 2.310344827586207) internal successors, (67), 29 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:28:46,961 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:28:46,961 INFO L93 Difference]: Finished difference Result 101 states and 125 transitions. [2022-11-16 11:28:46,961 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 101 states and 125 transitions. [2022-11-16 11:28:46,962 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:28:46,963 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 101 states to 85 states and 109 transitions. [2022-11-16 11:28:46,963 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-16 11:28:46,963 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-16 11:28:46,963 INFO L73 IsDeterministic]: Start isDeterministic. Operand 85 states and 109 transitions. [2022-11-16 11:28:46,963 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-16 11:28:46,963 INFO L218 hiAutomatonCegarLoop]: Abstraction has 85 states and 109 transitions. [2022-11-16 11:28:46,963 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 85 states and 109 transitions. [2022-11-16 11:28:46,964 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 85 to 76. [2022-11-16 11:28:46,965 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 76 states, 76 states have (on average 1.2763157894736843) internal successors, (97), 75 states have internal predecessors, (97), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:28:46,965 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 76 states to 76 states and 97 transitions. [2022-11-16 11:28:46,965 INFO L240 hiAutomatonCegarLoop]: Abstraction has 76 states and 97 transitions. [2022-11-16 11:28:46,970 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2022-11-16 11:28:46,972 INFO L428 stractBuchiCegarLoop]: Abstraction has 76 states and 97 transitions. [2022-11-16 11:28:46,972 INFO L335 stractBuchiCegarLoop]: ======== Iteration 40 ============ [2022-11-16 11:28:46,972 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 76 states and 97 transitions. [2022-11-16 11:28:46,973 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:28:46,973 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:28:46,973 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:28:46,973 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [8, 8, 7, 6, 5, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:28:46,973 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-16 11:28:46,973 INFO L748 eck$LassoCheckResult]: Stem: 13756#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 13757#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 13767#L367 assume !(main_~length~0#1 < 1); 13758#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 13759#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 13760#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13768#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 13819#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13818#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13817#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 13816#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13815#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13814#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 13813#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13812#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13811#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 13810#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13809#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13807#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13808#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13830#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13828#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13829#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13831#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13771#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13772#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13776#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13795#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 13793#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13777#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 13761#L370-4 main_~j~0#1 := 0; 13762#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13775#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 13790#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13789#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 13788#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13787#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 13786#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13785#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 13784#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13783#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 13782#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13780#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 13779#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13763#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 13764#L378-2 [2022-11-16 11:28:46,974 INFO L750 eck$LassoCheckResult]: Loop: 13764#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13781#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 13764#L378-2 [2022-11-16 11:28:46,974 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:28:46,974 INFO L85 PathProgramCache]: Analyzing trace with hash 535659115, now seen corresponding path program 28 times [2022-11-16 11:28:46,974 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:28:46,974 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [264926840] [2022-11-16 11:28:46,974 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:28:46,974 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:28:47,020 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:28:47,723 INFO L134 CoverageAnalysis]: Checked inductivity of 134 backedges. 0 proven. 134 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:28:47,723 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:28:47,723 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [264926840] [2022-11-16 11:28:47,724 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [264926840] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:28:47,724 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [551610606] [2022-11-16 11:28:47,724 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-16 11:28:47,724 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:28:47,724 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:28:47,726 INFO L229 MonitoredProcess]: Starting monitored process 54 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:28:47,728 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (54)] Waiting until timeout for monitored process [2022-11-16 11:28:47,873 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-16 11:28:47,873 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-16 11:28:47,875 INFO L263 TraceCheckSpWp]: Trace formula consists of 241 conjuncts, 48 conjunts are in the unsatisfiable core [2022-11-16 11:28:47,877 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:28:47,946 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-16 11:28:48,045 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-16 11:28:48,058 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-16 11:28:48,205 INFO L321 Elim1Store]: treesize reduction 61, result has 28.2 percent of original size [2022-11-16 11:28:48,206 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 3 case distinctions, treesize of input 39 treesize of output 41 [2022-11-16 11:28:49,108 INFO L321 Elim1Store]: treesize reduction 18, result has 14.3 percent of original size [2022-11-16 11:28:49,109 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 33 treesize of output 13 [2022-11-16 11:28:49,118 INFO L134 CoverageAnalysis]: Checked inductivity of 134 backedges. 0 proven. 134 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:28:49,118 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:29:11,929 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 68 treesize of output 64 [2022-11-16 11:29:11,940 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-16 11:29:11,940 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 508 treesize of output 492 [2022-11-16 11:29:12,560 INFO L134 CoverageAnalysis]: Checked inductivity of 134 backedges. 0 proven. 134 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:29:12,560 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [551610606] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:29:12,560 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-16 11:29:12,560 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 21, 21] total 52 [2022-11-16 11:29:12,560 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [499794232] [2022-11-16 11:29:12,561 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-16 11:29:12,561 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:29:12,561 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:29:12,561 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 36 times [2022-11-16 11:29:12,561 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:29:12,561 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1855000391] [2022-11-16 11:29:12,561 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:29:12,562 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:29:12,565 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:29:12,565 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:29:12,567 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:29:12,568 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:29:12,643 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:29:12,643 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 53 interpolants. [2022-11-16 11:29:12,644 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=228, Invalid=2524, Unknown=4, NotChecked=0, Total=2756 [2022-11-16 11:29:12,645 INFO L87 Difference]: Start difference. First operand 76 states and 97 transitions. cyclomatic complexity: 26 Second operand has 53 states, 52 states have (on average 2.0961538461538463) internal successors, (109), 53 states have internal predecessors, (109), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:29:14,781 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:29:14,781 INFO L93 Difference]: Finished difference Result 153 states and 182 transitions. [2022-11-16 11:29:14,781 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 153 states and 182 transitions. [2022-11-16 11:29:14,782 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:29:14,782 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 153 states to 151 states and 180 transitions. [2022-11-16 11:29:14,783 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21 [2022-11-16 11:29:14,783 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21 [2022-11-16 11:29:14,783 INFO L73 IsDeterministic]: Start isDeterministic. Operand 151 states and 180 transitions. [2022-11-16 11:29:14,783 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-16 11:29:14,783 INFO L218 hiAutomatonCegarLoop]: Abstraction has 151 states and 180 transitions. [2022-11-16 11:29:14,783 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 151 states and 180 transitions. [2022-11-16 11:29:14,785 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 151 to 88. [2022-11-16 11:29:14,785 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 88 states, 88 states have (on average 1.3068181818181819) internal successors, (115), 87 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:29:14,786 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 88 states to 88 states and 115 transitions. [2022-11-16 11:29:14,786 INFO L240 hiAutomatonCegarLoop]: Abstraction has 88 states and 115 transitions. [2022-11-16 11:29:14,786 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2022-11-16 11:29:14,787 INFO L428 stractBuchiCegarLoop]: Abstraction has 88 states and 115 transitions. [2022-11-16 11:29:14,787 INFO L335 stractBuchiCegarLoop]: ======== Iteration 41 ============ [2022-11-16 11:29:14,787 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 88 states and 115 transitions. [2022-11-16 11:29:14,787 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:29:14,788 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:29:14,788 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:29:14,788 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [8, 8, 7, 6, 5, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:29:14,788 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-16 11:29:14,788 INFO L748 eck$LassoCheckResult]: Stem: 14318#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 14319#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 14329#L367 assume !(main_~length~0#1 < 1); 14320#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 14321#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 14322#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14330#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 14387#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14386#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14385#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 14384#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14383#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14382#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 14381#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14380#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14379#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 14378#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14377#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14375#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14374#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14373#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14371#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14370#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14369#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14368#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 14334#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14392#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14354#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14353#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14351#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 14350#L370-4 main_~j~0#1 := 0; 14349#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14335#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 14348#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14347#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 14346#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14345#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 14344#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14343#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 14342#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14341#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 14340#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14338#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 14337#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14325#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 14326#L378-2 [2022-11-16 11:29:14,789 INFO L750 eck$LassoCheckResult]: Loop: 14326#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14339#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 14326#L378-2 [2022-11-16 11:29:14,789 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:29:14,789 INFO L85 PathProgramCache]: Analyzing trace with hash -1342461649, now seen corresponding path program 29 times [2022-11-16 11:29:14,789 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:29:14,789 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [246664563] [2022-11-16 11:29:14,790 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:29:14,790 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:29:14,821 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:29:15,856 INFO L134 CoverageAnalysis]: Checked inductivity of 134 backedges. 0 proven. 134 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:29:15,857 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:29:15,857 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [246664563] [2022-11-16 11:29:15,858 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [246664563] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:29:15,858 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [701112729] [2022-11-16 11:29:15,858 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-16 11:29:15,858 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:29:15,858 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:29:15,861 INFO L229 MonitoredProcess]: Starting monitored process 55 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:29:15,862 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (55)] Waiting until timeout for monitored process [2022-11-16 11:29:16,072 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 9 check-sat command(s) [2022-11-16 11:29:16,072 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-16 11:29:16,075 INFO L263 TraceCheckSpWp]: Trace formula consists of 257 conjuncts, 46 conjunts are in the unsatisfiable core [2022-11-16 11:29:16,077 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:29:16,507 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-16 11:29:16,723 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:29:16,724 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 26 [2022-11-16 11:29:16,737 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:29:16,738 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 26 [2022-11-16 11:29:17,576 INFO L173 IndexEqualityManager]: detected equality via solver [2022-11-16 11:29:17,579 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-16 11:29:17,579 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 19 treesize of output 12 [2022-11-16 11:29:17,620 INFO L134 CoverageAnalysis]: Checked inductivity of 134 backedges. 0 proven. 134 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:29:17,620 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:29:18,189 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2022-11-16 11:29:18,192 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 20 [2022-11-16 11:29:18,286 INFO L134 CoverageAnalysis]: Checked inductivity of 134 backedges. 0 proven. 134 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:29:18,287 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [701112729] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:29:18,287 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-16 11:29:18,287 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 22, 21] total 44 [2022-11-16 11:29:18,287 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1755057408] [2022-11-16 11:29:18,287 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-16 11:29:18,287 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:29:18,287 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:29:18,288 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 37 times [2022-11-16 11:29:18,288 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:29:18,288 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [912896343] [2022-11-16 11:29:18,288 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:29:18,288 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:29:18,291 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:29:18,291 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:29:18,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:29:18,294 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:29:18,388 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:29:18,388 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 45 interpolants. [2022-11-16 11:29:18,389 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=170, Invalid=1810, Unknown=0, NotChecked=0, Total=1980 [2022-11-16 11:29:18,389 INFO L87 Difference]: Start difference. First operand 88 states and 115 transitions. cyclomatic complexity: 33 Second operand has 45 states, 44 states have (on average 2.090909090909091) internal successors, (92), 45 states have internal predecessors, (92), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:29:19,894 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:29:19,894 INFO L93 Difference]: Finished difference Result 102 states and 129 transitions. [2022-11-16 11:29:19,894 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 102 states and 129 transitions. [2022-11-16 11:29:19,897 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:29:19,897 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 102 states to 101 states and 128 transitions. [2022-11-16 11:29:19,897 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-16 11:29:19,898 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-16 11:29:19,898 INFO L73 IsDeterministic]: Start isDeterministic. Operand 101 states and 128 transitions. [2022-11-16 11:29:19,898 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-16 11:29:19,898 INFO L218 hiAutomatonCegarLoop]: Abstraction has 101 states and 128 transitions. [2022-11-16 11:29:19,898 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 101 states and 128 transitions. [2022-11-16 11:29:19,899 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 101 to 58. [2022-11-16 11:29:19,899 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 58 states, 58 states have (on average 1.2413793103448276) internal successors, (72), 57 states have internal predecessors, (72), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:29:19,899 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 58 states to 58 states and 72 transitions. [2022-11-16 11:29:19,899 INFO L240 hiAutomatonCegarLoop]: Abstraction has 58 states and 72 transitions. [2022-11-16 11:29:19,900 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2022-11-16 11:29:19,900 INFO L428 stractBuchiCegarLoop]: Abstraction has 58 states and 72 transitions. [2022-11-16 11:29:19,900 INFO L335 stractBuchiCegarLoop]: ======== Iteration 42 ============ [2022-11-16 11:29:19,900 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 58 states and 72 transitions. [2022-11-16 11:29:19,901 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:29:19,901 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:29:19,901 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:29:19,901 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [8, 8, 8, 7, 5, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:29:19,901 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-16 11:29:19,902 INFO L748 eck$LassoCheckResult]: Stem: 14836#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 14837#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 14847#L367 assume !(main_~length~0#1 < 1); 14838#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 14839#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 14840#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14848#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 14893#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14892#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14891#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 14890#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14889#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14888#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 14887#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14886#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14885#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 14884#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14883#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14882#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14881#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14880#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14879#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14878#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14877#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14875#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14870#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14872#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14869#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 14868#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14854#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 14841#L370-4 main_~j~0#1 := 0; 14842#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14845#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 14846#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14852#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 14867#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14866#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 14865#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14864#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 14863#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14862#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 14861#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14860#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 14859#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14858#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 14857#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14843#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 14844#L378-2 [2022-11-16 11:29:19,902 INFO L750 eck$LassoCheckResult]: Loop: 14844#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14856#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 14844#L378-2 [2022-11-16 11:29:19,902 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:29:19,902 INFO L85 PathProgramCache]: Analyzing trace with hash -627666578, now seen corresponding path program 30 times [2022-11-16 11:29:19,903 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:29:19,903 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1996471893] [2022-11-16 11:29:19,903 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:29:19,903 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:29:19,947 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:29:20,962 INFO L134 CoverageAnalysis]: Checked inductivity of 148 backedges. 0 proven. 148 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:29:20,962 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:29:20,962 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1996471893] [2022-11-16 11:29:20,962 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1996471893] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:29:20,962 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1610484271] [2022-11-16 11:29:20,963 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-11-16 11:29:20,963 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:29:20,963 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:29:20,966 INFO L229 MonitoredProcess]: Starting monitored process 56 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:29:20,967 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (56)] Waiting until timeout for monitored process [2022-11-16 11:29:21,565 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 9 check-sat command(s) [2022-11-16 11:29:21,565 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-16 11:29:21,568 INFO L263 TraceCheckSpWp]: Trace formula consists of 269 conjuncts, 30 conjunts are in the unsatisfiable core [2022-11-16 11:29:21,570 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:29:21,960 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-16 11:29:23,313 INFO L321 Elim1Store]: treesize reduction 9, result has 25.0 percent of original size [2022-11-16 11:29:23,313 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 12 [2022-11-16 11:29:23,362 INFO L134 CoverageAnalysis]: Checked inductivity of 148 backedges. 49 proven. 99 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:29:23,363 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:29:25,064 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 41 treesize of output 37 [2022-11-16 11:29:25,069 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 24 [2022-11-16 11:29:25,441 INFO L134 CoverageAnalysis]: Checked inductivity of 148 backedges. 42 proven. 106 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:29:25,441 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1610484271] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:29:25,441 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-16 11:29:25,441 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 22, 22] total 53 [2022-11-16 11:29:25,441 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1208183449] [2022-11-16 11:29:25,441 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-16 11:29:25,442 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:29:25,442 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:29:25,442 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 38 times [2022-11-16 11:29:25,442 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:29:25,442 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1708629705] [2022-11-16 11:29:25,442 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:29:25,442 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:29:25,445 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:29:25,445 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:29:25,446 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:29:25,448 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:29:25,519 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:29:25,519 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 54 interpolants. [2022-11-16 11:29:25,520 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=337, Invalid=2525, Unknown=0, NotChecked=0, Total=2862 [2022-11-16 11:29:25,521 INFO L87 Difference]: Start difference. First operand 58 states and 72 transitions. cyclomatic complexity: 18 Second operand has 54 states, 53 states have (on average 2.056603773584906) internal successors, (109), 54 states have internal predecessors, (109), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:29:29,558 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:29:29,559 INFO L93 Difference]: Finished difference Result 154 states and 187 transitions. [2022-11-16 11:29:29,559 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 154 states and 187 transitions. [2022-11-16 11:29:29,559 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:29:29,560 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 154 states to 135 states and 166 transitions. [2022-11-16 11:29:29,560 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11 [2022-11-16 11:29:29,560 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11 [2022-11-16 11:29:29,560 INFO L73 IsDeterministic]: Start isDeterministic. Operand 135 states and 166 transitions. [2022-11-16 11:29:29,561 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-16 11:29:29,561 INFO L218 hiAutomatonCegarLoop]: Abstraction has 135 states and 166 transitions. [2022-11-16 11:29:29,561 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 135 states and 166 transitions. [2022-11-16 11:29:29,562 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 135 to 73. [2022-11-16 11:29:29,562 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 73 states, 73 states have (on average 1.2602739726027397) internal successors, (92), 72 states have internal predecessors, (92), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:29:29,563 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 73 states to 73 states and 92 transitions. [2022-11-16 11:29:29,563 INFO L240 hiAutomatonCegarLoop]: Abstraction has 73 states and 92 transitions. [2022-11-16 11:29:29,563 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 58 states. [2022-11-16 11:29:29,564 INFO L428 stractBuchiCegarLoop]: Abstraction has 73 states and 92 transitions. [2022-11-16 11:29:29,564 INFO L335 stractBuchiCegarLoop]: ======== Iteration 43 ============ [2022-11-16 11:29:29,564 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 73 states and 92 transitions. [2022-11-16 11:29:29,565 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:29:29,565 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:29:29,565 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:29:29,565 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [8, 8, 8, 7, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:29:29,565 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-16 11:29:29,566 INFO L748 eck$LassoCheckResult]: Stem: 15469#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 15470#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 15480#L367 assume !(main_~length~0#1 < 1); 15471#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 15472#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 15473#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15481#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15538#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15541#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15540#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 15535#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15539#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15484#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 15485#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15482#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15483#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 15525#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15518#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15516#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15515#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15514#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15512#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15511#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15509#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15497#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15492#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15494#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15491#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 15490#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15488#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 15474#L370-4 main_~j~0#1 := 0; 15475#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15486#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 15487#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15478#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 15479#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15508#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 15507#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15506#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 15505#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15504#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 15503#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15502#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 15501#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15499#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 15498#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15476#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 15477#L378-2 [2022-11-16 11:29:29,566 INFO L750 eck$LassoCheckResult]: Loop: 15477#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15500#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 15477#L378-2 [2022-11-16 11:29:29,566 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:29:29,566 INFO L85 PathProgramCache]: Analyzing trace with hash -1051313300, now seen corresponding path program 31 times [2022-11-16 11:29:29,566 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:29:29,567 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2147325263] [2022-11-16 11:29:29,567 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:29:29,567 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:29:29,605 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:29:30,650 INFO L134 CoverageAnalysis]: Checked inductivity of 148 backedges. 0 proven. 148 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:29:30,650 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:29:30,650 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2147325263] [2022-11-16 11:29:30,650 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2147325263] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:29:30,650 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1433601153] [2022-11-16 11:29:30,650 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-11-16 11:29:30,650 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:29:30,651 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:29:30,653 INFO L229 MonitoredProcess]: Starting monitored process 57 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:29:30,654 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (57)] Waiting until timeout for monitored process [2022-11-16 11:29:30,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:29:30,811 INFO L263 TraceCheckSpWp]: Trace formula consists of 276 conjuncts, 45 conjunts are in the unsatisfiable core [2022-11-16 11:29:30,813 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:29:31,384 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 9 [2022-11-16 11:29:32,273 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 9 [2022-11-16 11:29:32,317 INFO L134 CoverageAnalysis]: Checked inductivity of 148 backedges. 0 proven. 148 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:29:32,317 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:29:32,579 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2022-11-16 11:29:32,582 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 20 [2022-11-16 11:29:32,689 INFO L134 CoverageAnalysis]: Checked inductivity of 148 backedges. 0 proven. 148 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:29:32,689 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1433601153] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:29:32,689 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-16 11:29:32,689 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21, 20] total 42 [2022-11-16 11:29:32,690 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1023437296] [2022-11-16 11:29:32,690 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-16 11:29:32,690 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:29:32,690 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:29:32,690 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 39 times [2022-11-16 11:29:32,690 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:29:32,690 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [294594527] [2022-11-16 11:29:32,691 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:29:32,691 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:29:32,694 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:29:32,694 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:29:32,695 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:29:32,697 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:29:32,774 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:29:32,774 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 43 interpolants. [2022-11-16 11:29:32,775 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=153, Invalid=1653, Unknown=0, NotChecked=0, Total=1806 [2022-11-16 11:29:32,776 INFO L87 Difference]: Start difference. First operand 73 states and 92 transitions. cyclomatic complexity: 23 Second operand has 43 states, 42 states have (on average 2.2857142857142856) internal successors, (96), 43 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:29:34,211 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:29:34,211 INFO L93 Difference]: Finished difference Result 124 states and 155 transitions. [2022-11-16 11:29:34,211 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 124 states and 155 transitions. [2022-11-16 11:29:34,212 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-16 11:29:34,212 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 124 states to 123 states and 154 transitions. [2022-11-16 11:29:34,212 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16 [2022-11-16 11:29:34,213 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16 [2022-11-16 11:29:34,213 INFO L73 IsDeterministic]: Start isDeterministic. Operand 123 states and 154 transitions. [2022-11-16 11:29:34,213 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-16 11:29:34,213 INFO L218 hiAutomatonCegarLoop]: Abstraction has 123 states and 154 transitions. [2022-11-16 11:29:34,213 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 123 states and 154 transitions. [2022-11-16 11:29:34,215 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 123 to 104. [2022-11-16 11:29:34,215 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 104 states, 104 states have (on average 1.2788461538461537) internal successors, (133), 103 states have internal predecessors, (133), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:29:34,215 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 104 states to 104 states and 133 transitions. [2022-11-16 11:29:34,215 INFO L240 hiAutomatonCegarLoop]: Abstraction has 104 states and 133 transitions. [2022-11-16 11:29:34,216 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2022-11-16 11:29:34,216 INFO L428 stractBuchiCegarLoop]: Abstraction has 104 states and 133 transitions. [2022-11-16 11:29:34,216 INFO L335 stractBuchiCegarLoop]: ======== Iteration 44 ============ [2022-11-16 11:29:34,217 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 104 states and 133 transitions. [2022-11-16 11:29:34,217 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:29:34,217 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:29:34,217 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:29:34,218 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [9, 8, 8, 8, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:29:34,218 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-16 11:29:34,218 INFO L748 eck$LassoCheckResult]: Stem: 15996#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 15997#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 16007#L367 assume !(main_~length~0#1 < 1); 15998#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 15999#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 16000#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16008#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16014#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16009#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16010#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 16011#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16061#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16060#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 16050#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16059#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16057#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 16058#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16093#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16092#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16091#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16090#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16089#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16088#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16087#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16086#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16063#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16062#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16019#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 16017#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16015#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 16001#L370-4 main_~j~0#1 := 0; 16002#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16077#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 16013#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16005#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 16006#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16076#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 16075#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16074#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 16073#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16072#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 16071#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16070#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 16069#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16068#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 16067#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16065#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 16064#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16003#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 16004#L378-2 [2022-11-16 11:29:34,218 INFO L750 eck$LassoCheckResult]: Loop: 16004#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16066#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 16004#L378-2 [2022-11-16 11:29:34,218 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:29:34,218 INFO L85 PathProgramCache]: Analyzing trace with hash -994767313, now seen corresponding path program 32 times [2022-11-16 11:29:34,218 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:29:34,218 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1817524544] [2022-11-16 11:29:34,219 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:29:34,219 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:29:34,239 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:29:34,650 INFO L134 CoverageAnalysis]: Checked inductivity of 164 backedges. 57 proven. 107 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:29:34,650 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:29:34,651 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1817524544] [2022-11-16 11:29:34,651 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1817524544] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:29:34,651 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [336582356] [2022-11-16 11:29:34,651 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-16 11:29:34,651 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:29:34,651 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:29:34,654 INFO L229 MonitoredProcess]: Starting monitored process 58 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:29:34,655 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (58)] Waiting until timeout for monitored process [2022-11-16 11:29:34,813 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-16 11:29:34,813 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-16 11:29:34,815 INFO L263 TraceCheckSpWp]: Trace formula consists of 288 conjuncts, 20 conjunts are in the unsatisfiable core [2022-11-16 11:29:34,816 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:29:35,275 INFO L134 CoverageAnalysis]: Checked inductivity of 164 backedges. 72 proven. 92 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:29:35,275 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:29:35,610 INFO L134 CoverageAnalysis]: Checked inductivity of 164 backedges. 72 proven. 92 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:29:35,610 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [336582356] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:29:35,611 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-16 11:29:35,611 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21, 21] total 32 [2022-11-16 11:29:35,611 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1746396807] [2022-11-16 11:29:35,611 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-16 11:29:35,612 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:29:35,612 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:29:35,612 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 40 times [2022-11-16 11:29:35,612 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:29:35,612 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1387154915] [2022-11-16 11:29:35,612 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:29:35,612 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:29:35,615 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:29:35,616 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:29:35,617 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:29:35,619 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:29:35,696 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:29:35,697 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2022-11-16 11:29:35,697 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=235, Invalid=757, Unknown=0, NotChecked=0, Total=992 [2022-11-16 11:29:35,698 INFO L87 Difference]: Start difference. First operand 104 states and 133 transitions. cyclomatic complexity: 34 Second operand has 32 states, 32 states have (on average 2.3125) internal successors, (74), 32 states have internal predecessors, (74), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:29:36,151 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:29:36,151 INFO L93 Difference]: Finished difference Result 128 states and 158 transitions. [2022-11-16 11:29:36,151 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 128 states and 158 transitions. [2022-11-16 11:29:36,152 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:29:36,152 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 128 states to 110 states and 140 transitions. [2022-11-16 11:29:36,152 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-16 11:29:36,152 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-16 11:29:36,153 INFO L73 IsDeterministic]: Start isDeterministic. Operand 110 states and 140 transitions. [2022-11-16 11:29:36,153 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-16 11:29:36,153 INFO L218 hiAutomatonCegarLoop]: Abstraction has 110 states and 140 transitions. [2022-11-16 11:29:36,153 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 110 states and 140 transitions. [2022-11-16 11:29:36,154 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 110 to 74. [2022-11-16 11:29:36,154 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 74 states, 74 states have (on average 1.2567567567567568) internal successors, (93), 73 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:29:36,155 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74 states to 74 states and 93 transitions. [2022-11-16 11:29:36,155 INFO L240 hiAutomatonCegarLoop]: Abstraction has 74 states and 93 transitions. [2022-11-16 11:29:36,155 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2022-11-16 11:29:36,155 INFO L428 stractBuchiCegarLoop]: Abstraction has 74 states and 93 transitions. [2022-11-16 11:29:36,155 INFO L335 stractBuchiCegarLoop]: ======== Iteration 45 ============ [2022-11-16 11:29:36,156 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 74 states and 93 transitions. [2022-11-16 11:29:36,156 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:29:36,156 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:29:36,156 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:29:36,156 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [9, 9, 8, 7, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:29:36,157 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-16 11:29:36,157 INFO L748 eck$LassoCheckResult]: Stem: 16571#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 16572#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 16582#L367 assume !(main_~length~0#1 < 1); 16573#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 16574#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 16575#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16583#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 16586#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16584#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16585#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 16644#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16643#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16642#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 16641#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16640#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16639#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 16638#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16637#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16634#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16632#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16631#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16628#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16626#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16625#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16622#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16620#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16619#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16616#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 16617#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16618#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16608#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16604#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16588#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 16576#L370-4 main_~j~0#1 := 0; 16577#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16587#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 16603#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16602#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 16601#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16600#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 16599#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16598#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 16597#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16596#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 16595#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16594#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 16593#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16591#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 16590#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16578#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 16579#L378-2 [2022-11-16 11:29:36,157 INFO L750 eck$LassoCheckResult]: Loop: 16579#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16592#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 16579#L378-2 [2022-11-16 11:29:36,157 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:29:36,157 INFO L85 PathProgramCache]: Analyzing trace with hash 846855098, now seen corresponding path program 33 times [2022-11-16 11:29:36,158 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:29:36,158 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1597827009] [2022-11-16 11:29:36,158 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:29:36,158 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:29:36,201 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:29:37,683 INFO L134 CoverageAnalysis]: Checked inductivity of 173 backedges. 0 proven. 173 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:29:37,683 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:29:37,683 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1597827009] [2022-11-16 11:29:37,683 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1597827009] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:29:37,684 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1817874880] [2022-11-16 11:29:37,684 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-16 11:29:37,684 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:29:37,684 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:29:37,690 INFO L229 MonitoredProcess]: Starting monitored process 59 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:29:37,709 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (59)] Waiting until timeout for monitored process [2022-11-16 11:29:38,320 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 10 check-sat command(s) [2022-11-16 11:29:38,320 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-16 11:29:38,323 INFO L263 TraceCheckSpWp]: Trace formula consists of 291 conjuncts, 36 conjunts are in the unsatisfiable core [2022-11-16 11:29:38,325 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:29:38,726 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-16 11:29:38,996 INFO L321 Elim1Store]: treesize reduction 21, result has 47.5 percent of original size [2022-11-16 11:29:38,997 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 29 treesize of output 36 [2022-11-16 11:29:39,163 INFO L321 Elim1Store]: treesize reduction 21, result has 47.5 percent of original size [2022-11-16 11:29:39,164 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 49 [2022-11-16 11:29:43,761 INFO L321 Elim1Store]: treesize reduction 14, result has 65.9 percent of original size [2022-11-16 11:29:43,762 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 37 treesize of output 38 [2022-11-16 11:29:43,861 INFO L134 CoverageAnalysis]: Checked inductivity of 173 backedges. 49 proven. 124 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:29:43,861 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:29:46,178 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 41 treesize of output 37 [2022-11-16 11:29:46,184 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 24 [2022-11-16 11:29:46,679 INFO L134 CoverageAnalysis]: Checked inductivity of 173 backedges. 42 proven. 129 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-11-16 11:29:46,679 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1817874880] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:29:46,679 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-16 11:29:46,679 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 25, 22] total 57 [2022-11-16 11:29:46,679 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [936574665] [2022-11-16 11:29:46,679 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-16 11:29:46,680 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:29:46,680 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:29:46,680 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 41 times [2022-11-16 11:29:46,680 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:29:46,680 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [65939418] [2022-11-16 11:29:46,680 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:29:46,680 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:29:46,685 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:29:46,685 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:29:46,687 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:29:46,689 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:29:46,762 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:29:46,763 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 58 interpolants. [2022-11-16 11:29:46,763 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=373, Invalid=2932, Unknown=1, NotChecked=0, Total=3306 [2022-11-16 11:29:46,763 INFO L87 Difference]: Start difference. First operand 74 states and 93 transitions. cyclomatic complexity: 24 Second operand has 58 states, 57 states have (on average 2.0526315789473686) internal successors, (117), 58 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:30:20,891 WARN L233 SmtUtils]: Spent 13.35s on a formula simplification. DAG size of input: 36 DAG size of output: 29 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-11-16 11:30:38,160 WARN L233 SmtUtils]: Spent 14.16s on a formula simplification. DAG size of input: 35 DAG size of output: 28 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-11-16 11:30:46,082 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:30:46,082 INFO L93 Difference]: Finished difference Result 189 states and 220 transitions. [2022-11-16 11:30:46,082 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 189 states and 220 transitions. [2022-11-16 11:30:46,083 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:30:46,083 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 189 states to 137 states and 164 transitions. [2022-11-16 11:30:46,083 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15 [2022-11-16 11:30:46,083 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15 [2022-11-16 11:30:46,084 INFO L73 IsDeterministic]: Start isDeterministic. Operand 137 states and 164 transitions. [2022-11-16 11:30:46,084 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-16 11:30:46,084 INFO L218 hiAutomatonCegarLoop]: Abstraction has 137 states and 164 transitions. [2022-11-16 11:30:46,084 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 137 states and 164 transitions. [2022-11-16 11:30:46,085 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 137 to 74. [2022-11-16 11:30:46,085 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 74 states, 74 states have (on average 1.2567567567567568) internal successors, (93), 73 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:30:46,086 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74 states to 74 states and 93 transitions. [2022-11-16 11:30:46,086 INFO L240 hiAutomatonCegarLoop]: Abstraction has 74 states and 93 transitions. [2022-11-16 11:30:46,086 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 102 states. [2022-11-16 11:30:46,087 INFO L428 stractBuchiCegarLoop]: Abstraction has 74 states and 93 transitions. [2022-11-16 11:30:46,087 INFO L335 stractBuchiCegarLoop]: ======== Iteration 46 ============ [2022-11-16 11:30:46,087 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 74 states and 93 transitions. [2022-11-16 11:30:46,087 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:30:46,087 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:30:46,087 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:30:46,088 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [9, 9, 8, 7, 7, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:30:46,088 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-16 11:30:46,088 INFO L748 eck$LassoCheckResult]: Stem: 17324#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 17325#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 17335#L367 assume !(main_~length~0#1 < 1); 17326#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 17327#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 17328#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17336#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 17391#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17390#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17389#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 17388#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17387#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17386#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 17385#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17384#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17383#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 17382#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17381#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17379#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17378#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17377#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17376#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 17375#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17374#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17373#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 17372#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17371#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17369#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 17368#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17367#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17357#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17363#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17361#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 17360#L370-4 main_~j~0#1 := 0; 17341#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17333#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 17334#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17355#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 17354#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17353#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 17352#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17351#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 17350#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17349#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 17348#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17347#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 17346#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17345#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 17344#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17331#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 17332#L378-2 [2022-11-16 11:30:46,088 INFO L750 eck$LassoCheckResult]: Loop: 17332#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17343#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 17332#L378-2 [2022-11-16 11:30:46,088 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:30:46,088 INFO L85 PathProgramCache]: Analyzing trace with hash -1999869190, now seen corresponding path program 34 times [2022-11-16 11:30:46,089 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:30:46,089 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1317884541] [2022-11-16 11:30:46,089 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:30:46,089 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:30:46,130 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:30:47,630 INFO L134 CoverageAnalysis]: Checked inductivity of 173 backedges. 0 proven. 173 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:30:47,630 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:30:47,630 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1317884541] [2022-11-16 11:30:47,630 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1317884541] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:30:47,630 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1012191500] [2022-11-16 11:30:47,630 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-16 11:30:47,631 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:30:47,631 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:30:47,638 INFO L229 MonitoredProcess]: Starting monitored process 60 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:30:47,660 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (60)] Waiting until timeout for monitored process [2022-11-16 11:30:47,828 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-16 11:30:47,828 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-16 11:30:47,831 INFO L263 TraceCheckSpWp]: Trace formula consists of 261 conjuncts, 46 conjunts are in the unsatisfiable core [2022-11-16 11:30:47,833 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:30:47,960 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-16 11:30:48,223 INFO L321 Elim1Store]: treesize reduction 29, result has 27.5 percent of original size [2022-11-16 11:30:48,223 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 30 [2022-11-16 11:30:48,263 INFO L321 Elim1Store]: treesize reduction 29, result has 27.5 percent of original size [2022-11-16 11:30:48,263 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 30 [2022-11-16 11:30:48,924 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 11 [2022-11-16 11:30:48,927 INFO L134 CoverageAnalysis]: Checked inductivity of 173 backedges. 0 proven. 173 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:30:48,928 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:30:49,399 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2022-11-16 11:30:49,403 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 20 [2022-11-16 11:30:49,524 INFO L134 CoverageAnalysis]: Checked inductivity of 173 backedges. 0 proven. 173 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:30:49,524 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1012191500] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:30:49,524 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-16 11:30:49,524 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 22, 22] total 34 [2022-11-16 11:30:49,524 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1851588602] [2022-11-16 11:30:49,524 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-16 11:30:49,525 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:30:49,525 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:30:49,525 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 42 times [2022-11-16 11:30:49,525 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:30:49,525 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [746531699] [2022-11-16 11:30:49,525 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:30:49,525 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:30:49,528 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:30:49,528 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:30:49,529 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:30:49,531 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:30:49,603 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:30:49,604 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2022-11-16 11:30:49,604 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=98, Invalid=1092, Unknown=0, NotChecked=0, Total=1190 [2022-11-16 11:30:49,604 INFO L87 Difference]: Start difference. First operand 74 states and 93 transitions. cyclomatic complexity: 24 Second operand has 35 states, 34 states have (on average 2.2058823529411766) internal successors, (75), 35 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:30:51,180 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:30:51,181 INFO L93 Difference]: Finished difference Result 109 states and 130 transitions. [2022-11-16 11:30:51,181 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 109 states and 130 transitions. [2022-11-16 11:30:51,181 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:30:51,182 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 109 states to 108 states and 129 transitions. [2022-11-16 11:30:51,182 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15 [2022-11-16 11:30:51,182 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15 [2022-11-16 11:30:51,182 INFO L73 IsDeterministic]: Start isDeterministic. Operand 108 states and 129 transitions. [2022-11-16 11:30:51,183 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-16 11:30:51,183 INFO L218 hiAutomatonCegarLoop]: Abstraction has 108 states and 129 transitions. [2022-11-16 11:30:51,183 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 108 states and 129 transitions. [2022-11-16 11:30:51,184 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 108 to 76. [2022-11-16 11:30:51,185 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 76 states, 76 states have (on average 1.263157894736842) internal successors, (96), 75 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:30:51,185 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 76 states to 76 states and 96 transitions. [2022-11-16 11:30:51,185 INFO L240 hiAutomatonCegarLoop]: Abstraction has 76 states and 96 transitions. [2022-11-16 11:30:51,186 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2022-11-16 11:30:51,187 INFO L428 stractBuchiCegarLoop]: Abstraction has 76 states and 96 transitions. [2022-11-16 11:30:51,187 INFO L335 stractBuchiCegarLoop]: ======== Iteration 47 ============ [2022-11-16 11:30:51,187 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 76 states and 96 transitions. [2022-11-16 11:30:51,188 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:30:51,188 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:30:51,188 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:30:51,188 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [9, 9, 9, 8, 7, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:30:51,188 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-16 11:30:51,189 INFO L748 eck$LassoCheckResult]: Stem: 17846#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 17847#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 17857#L367 assume !(main_~length~0#1 < 1); 17848#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 17849#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 17850#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17858#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 17904#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17903#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17902#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 17901#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17900#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17899#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 17898#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17897#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17896#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 17895#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17894#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17893#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17892#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17891#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17890#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 17889#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17888#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17886#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17887#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17909#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17908#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 17883#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17921#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17878#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 17877#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17920#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 17851#L370-4 main_~j~0#1 := 0; 17852#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17916#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 17864#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17855#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 17856#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17915#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 17914#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17913#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 17912#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17911#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 17910#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17907#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 17875#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17873#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 17870#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17868#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 17867#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17853#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 17854#L378-2 [2022-11-16 11:30:51,189 INFO L750 eck$LassoCheckResult]: Loop: 17854#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17869#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 17854#L378-2 [2022-11-16 11:30:51,189 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:30:51,189 INFO L85 PathProgramCache]: Analyzing trace with hash -1295583043, now seen corresponding path program 35 times [2022-11-16 11:30:51,190 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:30:51,190 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [472237433] [2022-11-16 11:30:51,190 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:30:51,190 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:30:51,238 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:30:52,598 INFO L134 CoverageAnalysis]: Checked inductivity of 189 backedges. 0 proven. 189 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:30:52,598 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:30:52,598 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [472237433] [2022-11-16 11:30:52,598 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [472237433] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:30:52,598 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2067260189] [2022-11-16 11:30:52,598 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-16 11:30:52,598 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:30:52,599 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:30:52,600 INFO L229 MonitoredProcess]: Starting monitored process 61 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:30:52,603 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (61)] Waiting until timeout for monitored process [2022-11-16 11:30:52,874 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) [2022-11-16 11:30:52,874 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-16 11:30:52,877 INFO L263 TraceCheckSpWp]: Trace formula consists of 289 conjuncts, 49 conjunts are in the unsatisfiable core [2022-11-16 11:30:52,878 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:30:53,551 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 9 [2022-11-16 11:30:54,799 INFO L173 IndexEqualityManager]: detected equality via solver [2022-11-16 11:30:54,802 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-16 11:30:54,802 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 19 treesize of output 12 [2022-11-16 11:30:54,850 INFO L134 CoverageAnalysis]: Checked inductivity of 189 backedges. 0 proven. 189 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:30:54,850 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:30:55,299 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2022-11-16 11:30:55,303 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 20 [2022-11-16 11:30:55,434 INFO L134 CoverageAnalysis]: Checked inductivity of 189 backedges. 0 proven. 189 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:30:55,434 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2067260189] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:30:55,434 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-16 11:30:55,434 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 24, 23] total 48 [2022-11-16 11:30:55,435 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1572663822] [2022-11-16 11:30:55,435 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-16 11:30:55,435 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:30:55,435 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:30:55,435 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 43 times [2022-11-16 11:30:55,435 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:30:55,435 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [80221448] [2022-11-16 11:30:55,436 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:30:55,436 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:30:55,438 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:30:55,439 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:30:55,440 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:30:55,442 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:30:55,526 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:30:55,526 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2022-11-16 11:30:55,527 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=181, Invalid=2171, Unknown=0, NotChecked=0, Total=2352 [2022-11-16 11:30:55,527 INFO L87 Difference]: Start difference. First operand 76 states and 96 transitions. cyclomatic complexity: 25 Second operand has 49 states, 48 states have (on average 2.2083333333333335) internal successors, (106), 49 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:30:57,839 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:30:57,839 INFO L93 Difference]: Finished difference Result 147 states and 183 transitions. [2022-11-16 11:30:57,839 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 147 states and 183 transitions. [2022-11-16 11:30:57,839 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 21 [2022-11-16 11:30:57,840 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 147 states to 146 states and 182 transitions. [2022-11-16 11:30:57,840 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 40 [2022-11-16 11:30:57,840 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 40 [2022-11-16 11:30:57,840 INFO L73 IsDeterministic]: Start isDeterministic. Operand 146 states and 182 transitions. [2022-11-16 11:30:57,840 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-16 11:30:57,840 INFO L218 hiAutomatonCegarLoop]: Abstraction has 146 states and 182 transitions. [2022-11-16 11:30:57,840 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 146 states and 182 transitions. [2022-11-16 11:30:57,842 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 146 to 124. [2022-11-16 11:30:57,842 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 124 states, 124 states have (on average 1.2741935483870968) internal successors, (158), 123 states have internal predecessors, (158), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:30:57,843 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 124 states to 124 states and 158 transitions. [2022-11-16 11:30:57,843 INFO L240 hiAutomatonCegarLoop]: Abstraction has 124 states and 158 transitions. [2022-11-16 11:30:57,854 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2022-11-16 11:30:57,855 INFO L428 stractBuchiCegarLoop]: Abstraction has 124 states and 158 transitions. [2022-11-16 11:30:57,855 INFO L335 stractBuchiCegarLoop]: ======== Iteration 48 ============ [2022-11-16 11:30:57,855 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 124 states and 158 transitions. [2022-11-16 11:30:57,855 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 18 [2022-11-16 11:30:57,855 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:30:57,855 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:30:57,856 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [10, 10, 8, 7, 7, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:30:57,856 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 1, 1] [2022-11-16 11:30:57,856 INFO L748 eck$LassoCheckResult]: Stem: 18435#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 18436#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 18446#L367 assume !(main_~length~0#1 < 1); 18437#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 18438#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 18439#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18447#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 18451#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18452#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18492#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 18491#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18490#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18489#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 18488#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18487#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18486#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 18485#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18484#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18483#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18481#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18479#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18477#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 18475#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18473#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18471#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18470#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18468#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18466#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 18464#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18524#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18523#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18522#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18520#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18518#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 18517#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18515#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 18514#L370-4 main_~j~0#1 := 0; 18513#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18512#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 18511#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18510#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 18509#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18508#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 18507#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18506#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 18505#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18504#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 18503#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18502#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 18501#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18500#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 18494#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18496#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 18544#L378-2 [2022-11-16 11:30:57,856 INFO L750 eck$LassoCheckResult]: Loop: 18544#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18546#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 18545#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18543#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 18544#L378-2 [2022-11-16 11:30:57,856 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:30:57,856 INFO L85 PathProgramCache]: Analyzing trace with hash -1146287510, now seen corresponding path program 36 times [2022-11-16 11:30:57,857 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:30:57,857 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1062256971] [2022-11-16 11:30:57,857 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:30:57,857 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:30:57,917 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:30:59,207 INFO L134 CoverageAnalysis]: Checked inductivity of 201 backedges. 0 proven. 201 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:30:59,207 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:30:59,207 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1062256971] [2022-11-16 11:30:59,207 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1062256971] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:30:59,207 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1813484391] [2022-11-16 11:30:59,207 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-11-16 11:30:59,207 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:30:59,207 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:30:59,220 INFO L229 MonitoredProcess]: Starting monitored process 62 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:30:59,221 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (62)] Waiting until timeout for monitored process [2022-11-16 11:31:00,469 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 11 check-sat command(s) [2022-11-16 11:31:00,469 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-16 11:31:00,472 INFO L263 TraceCheckSpWp]: Trace formula consists of 299 conjuncts, 53 conjunts are in the unsatisfiable core [2022-11-16 11:31:00,475 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:31:01,043 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-16 11:31:01,288 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:31:01,289 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 26 [2022-11-16 11:31:01,305 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:31:01,305 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 26 [2022-11-16 11:31:01,405 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:31:01,405 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 26 [2022-11-16 11:31:02,300 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 9 [2022-11-16 11:31:02,348 INFO L134 CoverageAnalysis]: Checked inductivity of 201 backedges. 1 proven. 200 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:31:02,348 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:31:02,991 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2022-11-16 11:31:02,995 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 20 [2022-11-16 11:31:03,102 INFO L134 CoverageAnalysis]: Checked inductivity of 201 backedges. 1 proven. 199 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-16 11:31:03,102 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1813484391] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:31:03,103 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-16 11:31:03,103 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 24, 23] total 48 [2022-11-16 11:31:03,103 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [868933158] [2022-11-16 11:31:03,103 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-16 11:31:03,103 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:31:03,103 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:31:03,103 INFO L85 PathProgramCache]: Analyzing trace with hash 2219337, now seen corresponding path program 3 times [2022-11-16 11:31:03,104 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:31:03,104 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1246522332] [2022-11-16 11:31:03,104 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:31:03,104 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:31:03,108 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:31:03,108 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:31:03,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:31:03,112 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:31:03,266 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:31:03,267 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2022-11-16 11:31:03,268 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=188, Invalid=2164, Unknown=0, NotChecked=0, Total=2352 [2022-11-16 11:31:03,268 INFO L87 Difference]: Start difference. First operand 124 states and 158 transitions. cyclomatic complexity: 41 Second operand has 49 states, 48 states have (on average 2.2916666666666665) internal successors, (110), 49 states have internal predecessors, (110), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:31:05,246 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:31:05,246 INFO L93 Difference]: Finished difference Result 137 states and 162 transitions. [2022-11-16 11:31:05,246 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 137 states and 162 transitions. [2022-11-16 11:31:05,247 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:31:05,248 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 137 states to 135 states and 160 transitions. [2022-11-16 11:31:05,248 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17 [2022-11-16 11:31:05,248 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17 [2022-11-16 11:31:05,248 INFO L73 IsDeterministic]: Start isDeterministic. Operand 135 states and 160 transitions. [2022-11-16 11:31:05,248 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-16 11:31:05,248 INFO L218 hiAutomatonCegarLoop]: Abstraction has 135 states and 160 transitions. [2022-11-16 11:31:05,249 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 135 states and 160 transitions. [2022-11-16 11:31:05,250 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 135 to 80. [2022-11-16 11:31:05,250 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 80 states, 80 states have (on average 1.2625) internal successors, (101), 79 states have internal predecessors, (101), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:31:05,250 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 80 states to 80 states and 101 transitions. [2022-11-16 11:31:05,250 INFO L240 hiAutomatonCegarLoop]: Abstraction has 80 states and 101 transitions. [2022-11-16 11:31:05,251 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2022-11-16 11:31:05,251 INFO L428 stractBuchiCegarLoop]: Abstraction has 80 states and 101 transitions. [2022-11-16 11:31:05,251 INFO L335 stractBuchiCegarLoop]: ======== Iteration 49 ============ [2022-11-16 11:31:05,252 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 80 states and 101 transitions. [2022-11-16 11:31:05,252 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:31:05,252 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:31:05,252 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:31:05,253 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [10, 9, 9, 9, 7, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:31:05,253 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-16 11:31:05,253 INFO L748 eck$LassoCheckResult]: Stem: 19078#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 19079#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 19089#L367 assume !(main_~length~0#1 < 1); 19080#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 19081#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 19082#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19090#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 19157#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19156#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19155#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 19154#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19153#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19152#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 19151#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19150#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19149#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 19148#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19147#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19146#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19144#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19142#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19140#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 19138#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19136#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19134#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19133#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19131#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19129#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 19127#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19126#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19125#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 19093#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19115#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 19083#L370-4 main_~j~0#1 := 0; 19084#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19116#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 19095#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19087#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 19088#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19114#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 19113#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19112#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 19111#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19110#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 19109#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19108#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 19107#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19106#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 19102#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19101#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 19100#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19098#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 19097#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19085#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 19086#L378-2 [2022-11-16 11:31:05,253 INFO L750 eck$LassoCheckResult]: Loop: 19086#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19099#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 19086#L378-2 [2022-11-16 11:31:05,253 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:31:05,254 INFO L85 PathProgramCache]: Analyzing trace with hash 485210944, now seen corresponding path program 37 times [2022-11-16 11:31:05,254 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:31:05,254 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [519466636] [2022-11-16 11:31:05,254 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:31:05,254 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:31:05,275 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:31:05,733 INFO L134 CoverageAnalysis]: Checked inductivity of 207 backedges. 73 proven. 134 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:31:05,733 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:31:05,733 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [519466636] [2022-11-16 11:31:05,734 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [519466636] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:31:05,734 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [153469892] [2022-11-16 11:31:05,734 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-11-16 11:31:05,734 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:31:05,734 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:31:05,741 INFO L229 MonitoredProcess]: Starting monitored process 63 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:31:05,742 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (63)] Waiting until timeout for monitored process [2022-11-16 11:31:05,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:31:05,915 INFO L263 TraceCheckSpWp]: Trace formula consists of 301 conjuncts, 22 conjunts are in the unsatisfiable core [2022-11-16 11:31:05,916 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:31:06,425 INFO L134 CoverageAnalysis]: Checked inductivity of 207 backedges. 90 proven. 117 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:31:06,425 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:31:06,819 INFO L134 CoverageAnalysis]: Checked inductivity of 207 backedges. 90 proven. 117 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:31:06,819 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [153469892] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:31:06,819 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-16 11:31:06,819 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23, 23] total 35 [2022-11-16 11:31:06,819 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [780063450] [2022-11-16 11:31:06,819 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-16 11:31:06,820 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:31:06,820 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:31:06,820 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 44 times [2022-11-16 11:31:06,820 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:31:06,820 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2118037838] [2022-11-16 11:31:06,820 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:31:06,820 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:31:06,823 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:31:06,824 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:31:06,825 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:31:06,827 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:31:06,908 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:31:06,908 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2022-11-16 11:31:06,909 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=280, Invalid=910, Unknown=0, NotChecked=0, Total=1190 [2022-11-16 11:31:06,909 INFO L87 Difference]: Start difference. First operand 80 states and 101 transitions. cyclomatic complexity: 26 Second operand has 35 states, 35 states have (on average 2.3142857142857145) internal successors, (81), 35 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:31:07,438 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:31:07,439 INFO L93 Difference]: Finished difference Result 106 states and 128 transitions. [2022-11-16 11:31:07,439 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 106 states and 128 transitions. [2022-11-16 11:31:07,439 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:31:07,439 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 106 states to 86 states and 108 transitions. [2022-11-16 11:31:07,439 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-16 11:31:07,439 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-16 11:31:07,440 INFO L73 IsDeterministic]: Start isDeterministic. Operand 86 states and 108 transitions. [2022-11-16 11:31:07,440 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-16 11:31:07,440 INFO L218 hiAutomatonCegarLoop]: Abstraction has 86 states and 108 transitions. [2022-11-16 11:31:07,440 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 86 states and 108 transitions. [2022-11-16 11:31:07,440 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 86 to 82. [2022-11-16 11:31:07,441 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 82 states, 82 states have (on average 1.2560975609756098) internal successors, (103), 81 states have internal predecessors, (103), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:31:07,441 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 82 states to 82 states and 103 transitions. [2022-11-16 11:31:07,441 INFO L240 hiAutomatonCegarLoop]: Abstraction has 82 states and 103 transitions. [2022-11-16 11:31:07,441 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2022-11-16 11:31:07,442 INFO L428 stractBuchiCegarLoop]: Abstraction has 82 states and 103 transitions. [2022-11-16 11:31:07,442 INFO L335 stractBuchiCegarLoop]: ======== Iteration 50 ============ [2022-11-16 11:31:07,442 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 82 states and 103 transitions. [2022-11-16 11:31:07,442 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:31:07,442 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:31:07,442 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:31:07,443 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [10, 10, 9, 8, 7, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:31:07,443 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-16 11:31:07,443 INFO L748 eck$LassoCheckResult]: Stem: 19642#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 19643#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 19653#L367 assume !(main_~length~0#1 < 1); 19644#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 19645#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 19646#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19654#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 19717#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19716#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19715#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 19714#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19713#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19712#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 19711#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19710#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19709#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 19708#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19707#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19705#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19706#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19723#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19721#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 19720#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19718#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19697#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19696#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19695#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19694#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 19691#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19690#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19689#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 19660#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19655#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19656#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19682#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19679#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 19678#L370-4 main_~j~0#1 := 0; 19657#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19649#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 19650#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19675#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 19674#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19673#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 19672#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19671#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 19670#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19669#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 19668#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19667#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 19666#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19665#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 19664#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19662#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 19661#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19647#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 19648#L378-2 [2022-11-16 11:31:07,443 INFO L750 eck$LassoCheckResult]: Loop: 19648#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19663#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 19648#L378-2 [2022-11-16 11:31:07,443 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:31:07,444 INFO L85 PathProgramCache]: Analyzing trace with hash 2145991281, now seen corresponding path program 38 times [2022-11-16 11:31:07,444 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:31:07,444 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1068507525] [2022-11-16 11:31:07,444 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:31:07,444 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:31:07,481 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:31:09,104 INFO L134 CoverageAnalysis]: Checked inductivity of 217 backedges. 0 proven. 217 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:31:09,104 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:31:09,104 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1068507525] [2022-11-16 11:31:09,104 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1068507525] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:31:09,104 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [800091765] [2022-11-16 11:31:09,104 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-16 11:31:09,104 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:31:09,105 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:31:09,106 INFO L229 MonitoredProcess]: Starting monitored process 64 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:31:09,108 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (64)] Waiting until timeout for monitored process [2022-11-16 11:31:09,292 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-16 11:31:09,292 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-16 11:31:09,294 INFO L263 TraceCheckSpWp]: Trace formula consists of 311 conjuncts, 54 conjunts are in the unsatisfiable core [2022-11-16 11:31:09,296 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:31:09,980 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-16 11:31:10,221 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:31:10,221 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 26 [2022-11-16 11:31:10,233 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:31:10,234 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 26 [2022-11-16 11:31:11,230 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 9 [2022-11-16 11:31:11,281 INFO L134 CoverageAnalysis]: Checked inductivity of 217 backedges. 0 proven. 217 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:31:11,281 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:31:11,794 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2022-11-16 11:31:11,797 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 20 [2022-11-16 11:31:11,917 INFO L134 CoverageAnalysis]: Checked inductivity of 217 backedges. 0 proven. 217 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:31:11,917 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [800091765] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:31:11,918 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-16 11:31:11,918 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 25, 24] total 50 [2022-11-16 11:31:11,918 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [283527789] [2022-11-16 11:31:11,918 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-16 11:31:11,918 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:31:11,918 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:31:11,919 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 45 times [2022-11-16 11:31:11,919 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:31:11,919 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1609379436] [2022-11-16 11:31:11,919 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:31:11,919 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:31:11,922 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:31:11,922 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:31:11,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:31:11,924 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:31:11,993 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:31:11,993 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 51 interpolants. [2022-11-16 11:31:11,994 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=185, Invalid=2365, Unknown=0, NotChecked=0, Total=2550 [2022-11-16 11:31:11,994 INFO L87 Difference]: Start difference. First operand 82 states and 103 transitions. cyclomatic complexity: 26 Second operand has 51 states, 50 states have (on average 2.24) internal successors, (112), 51 states have internal predecessors, (112), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:31:14,580 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:31:14,580 INFO L93 Difference]: Finished difference Result 100 states and 121 transitions. [2022-11-16 11:31:14,580 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 100 states and 121 transitions. [2022-11-16 11:31:14,581 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:31:14,581 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 100 states to 99 states and 120 transitions. [2022-11-16 11:31:14,582 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-16 11:31:14,582 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-16 11:31:14,582 INFO L73 IsDeterministic]: Start isDeterministic. Operand 99 states and 120 transitions. [2022-11-16 11:31:14,582 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-16 11:31:14,582 INFO L218 hiAutomatonCegarLoop]: Abstraction has 99 states and 120 transitions. [2022-11-16 11:31:14,582 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 99 states and 120 transitions. [2022-11-16 11:31:14,583 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 99 to 74. [2022-11-16 11:31:14,583 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 74 states, 74 states have (on average 1.2432432432432432) internal successors, (92), 73 states have internal predecessors, (92), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:31:14,583 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74 states to 74 states and 92 transitions. [2022-11-16 11:31:14,584 INFO L240 hiAutomatonCegarLoop]: Abstraction has 74 states and 92 transitions. [2022-11-16 11:31:14,590 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2022-11-16 11:31:14,591 INFO L428 stractBuchiCegarLoop]: Abstraction has 74 states and 92 transitions. [2022-11-16 11:31:14,591 INFO L335 stractBuchiCegarLoop]: ======== Iteration 51 ============ [2022-11-16 11:31:14,591 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 74 states and 92 transitions. [2022-11-16 11:31:14,592 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:31:14,593 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:31:14,593 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:31:14,593 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [10, 10, 10, 9, 7, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:31:14,594 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-16 11:31:14,594 INFO L748 eck$LassoCheckResult]: Stem: 20222#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 20223#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 20233#L367 assume !(main_~length~0#1 < 1); 20224#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 20225#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 20226#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20234#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 20237#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20286#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20285#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 20284#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20283#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20282#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 20281#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20280#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20279#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 20278#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20277#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20276#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20274#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20272#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20270#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 20268#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20266#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20264#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20263#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20261#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20259#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 20257#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20255#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20253#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20240#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20235#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20236#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 20247#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20241#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 20227#L370-4 main_~j~0#1 := 0; 20228#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20238#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 20239#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20231#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 20232#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20295#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 20294#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20293#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 20292#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20291#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 20290#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20289#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 20288#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20287#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 20249#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20248#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 20246#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20244#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 20243#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20229#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 20230#L378-2 [2022-11-16 11:31:14,594 INFO L750 eck$LassoCheckResult]: Loop: 20230#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20245#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 20230#L378-2 [2022-11-16 11:31:14,594 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:31:14,595 INFO L85 PathProgramCache]: Analyzing trace with hash -1343923152, now seen corresponding path program 39 times [2022-11-16 11:31:14,595 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:31:14,595 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2090178549] [2022-11-16 11:31:14,595 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:31:14,595 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:31:14,643 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:31:16,167 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 0 proven. 235 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:31:16,167 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:31:16,167 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2090178549] [2022-11-16 11:31:16,167 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2090178549] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:31:16,167 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1751671540] [2022-11-16 11:31:16,167 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-16 11:31:16,167 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:31:16,168 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:31:16,170 INFO L229 MonitoredProcess]: Starting monitored process 65 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:31:16,171 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (65)] Waiting until timeout for monitored process [2022-11-16 11:31:16,833 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2022-11-16 11:31:16,833 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-16 11:31:16,836 INFO L263 TraceCheckSpWp]: Trace formula consists of 323 conjuncts, 32 conjunts are in the unsatisfiable core [2022-11-16 11:31:16,837 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:31:17,412 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-16 11:31:19,291 INFO L321 Elim1Store]: treesize reduction 9, result has 25.0 percent of original size [2022-11-16 11:31:19,291 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 12 [2022-11-16 11:31:19,348 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 81 proven. 154 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:31:19,348 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:31:21,675 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 41 treesize of output 37 [2022-11-16 11:31:21,680 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 24 [2022-11-16 11:31:22,234 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 72 proven. 163 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:31:22,234 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1751671540] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:31:22,234 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-16 11:31:22,235 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 26, 26] total 63 [2022-11-16 11:31:22,235 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [354061949] [2022-11-16 11:31:22,235 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-16 11:31:22,235 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:31:22,235 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:31:22,235 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 46 times [2022-11-16 11:31:22,235 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:31:22,236 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1391342230] [2022-11-16 11:31:22,236 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:31:22,236 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:31:22,239 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:31:22,239 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:31:22,240 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:31:22,241 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:31:22,316 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:31:22,316 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 64 interpolants. [2022-11-16 11:31:22,317 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=460, Invalid=3572, Unknown=0, NotChecked=0, Total=4032 [2022-11-16 11:31:22,318 INFO L87 Difference]: Start difference. First operand 74 states and 92 transitions. cyclomatic complexity: 22 Second operand has 64 states, 63 states have (on average 2.111111111111111) internal successors, (133), 64 states have internal predecessors, (133), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:31:27,123 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:31:27,124 INFO L93 Difference]: Finished difference Result 223 states and 276 transitions. [2022-11-16 11:31:27,124 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 223 states and 276 transitions. [2022-11-16 11:31:27,125 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:31:27,126 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 223 states to 198 states and 250 transitions. [2022-11-16 11:31:27,126 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11 [2022-11-16 11:31:27,126 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11 [2022-11-16 11:31:27,126 INFO L73 IsDeterministic]: Start isDeterministic. Operand 198 states and 250 transitions. [2022-11-16 11:31:27,126 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-16 11:31:27,126 INFO L218 hiAutomatonCegarLoop]: Abstraction has 198 states and 250 transitions. [2022-11-16 11:31:27,127 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 198 states and 250 transitions. [2022-11-16 11:31:27,128 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 198 to 98. [2022-11-16 11:31:27,129 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 98 states, 98 states have (on average 1.2653061224489797) internal successors, (124), 97 states have internal predecessors, (124), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:31:27,129 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 98 states to 98 states and 124 transitions. [2022-11-16 11:31:27,129 INFO L240 hiAutomatonCegarLoop]: Abstraction has 98 states and 124 transitions. [2022-11-16 11:31:27,129 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 67 states. [2022-11-16 11:31:27,130 INFO L428 stractBuchiCegarLoop]: Abstraction has 98 states and 124 transitions. [2022-11-16 11:31:27,130 INFO L335 stractBuchiCegarLoop]: ======== Iteration 52 ============ [2022-11-16 11:31:27,130 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 98 states and 124 transitions. [2022-11-16 11:31:27,130 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:31:27,131 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:31:27,131 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:31:27,131 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [10, 10, 10, 9, 6, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:31:27,131 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-16 11:31:27,132 INFO L748 eck$LassoCheckResult]: Stem: 21021#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 21022#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 21032#L367 assume !(main_~length~0#1 < 1); 21023#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 21024#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 21025#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21033#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21097#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21118#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21117#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 21094#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21116#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21038#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 21039#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21034#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21035#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 21087#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21115#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21112#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21111#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21110#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21109#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 21079#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21103#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21101#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21102#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21105#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21104#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 21067#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21064#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21062#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21044#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21046#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21043#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 21042#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21040#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 21030#L370-4 main_~j~0#1 := 0; 21031#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21036#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 21037#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21028#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 21029#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21061#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 21060#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21059#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 21058#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21057#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 21056#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21055#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 21054#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21053#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 21052#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21051#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 21050#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21049#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 21048#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21026#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 21027#L378-2 [2022-11-16 11:31:27,132 INFO L750 eck$LassoCheckResult]: Loop: 21027#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21047#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 21027#L378-2 [2022-11-16 11:31:27,132 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:31:27,132 INFO L85 PathProgramCache]: Analyzing trace with hash 684662958, now seen corresponding path program 40 times [2022-11-16 11:31:27,132 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:31:27,133 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1438884977] [2022-11-16 11:31:27,133 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:31:27,133 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:31:27,187 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:31:28,676 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 0 proven. 235 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:31:28,677 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:31:28,677 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1438884977] [2022-11-16 11:31:28,677 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1438884977] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:31:28,677 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1412486023] [2022-11-16 11:31:28,677 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-16 11:31:28,677 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:31:28,677 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:31:28,678 INFO L229 MonitoredProcess]: Starting monitored process 66 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:31:28,681 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (66)] Waiting until timeout for monitored process [2022-11-16 11:31:28,877 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-16 11:31:28,878 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-16 11:31:28,880 INFO L263 TraceCheckSpWp]: Trace formula consists of 314 conjuncts, 49 conjunts are in the unsatisfiable core [2022-11-16 11:31:28,881 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:31:29,002 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-16 11:31:29,959 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 11 [2022-11-16 11:31:29,962 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 0 proven. 235 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:31:29,962 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:31:30,257 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2022-11-16 11:31:30,260 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 20 [2022-11-16 11:31:30,403 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 0 proven. 235 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:31:30,403 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1412486023] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:31:30,403 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-16 11:31:30,403 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 24, 24] total 37 [2022-11-16 11:31:30,404 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1796938964] [2022-11-16 11:31:30,404 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-16 11:31:30,404 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:31:30,404 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:31:30,404 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 47 times [2022-11-16 11:31:30,404 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:31:30,404 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [513710778] [2022-11-16 11:31:30,404 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:31:30,405 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:31:30,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:31:30,408 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:31:30,409 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:31:30,410 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:31:30,485 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:31:30,486 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2022-11-16 11:31:30,486 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=109, Invalid=1297, Unknown=0, NotChecked=0, Total=1406 [2022-11-16 11:31:30,487 INFO L87 Difference]: Start difference. First operand 98 states and 124 transitions. cyclomatic complexity: 30 Second operand has 38 states, 37 states have (on average 2.2432432432432434) internal successors, (83), 38 states have internal predecessors, (83), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:31:32,528 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:31:32,528 INFO L93 Difference]: Finished difference Result 138 states and 171 transitions. [2022-11-16 11:31:32,528 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 138 states and 171 transitions. [2022-11-16 11:31:32,529 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-16 11:31:32,530 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 138 states to 137 states and 170 transitions. [2022-11-16 11:31:32,530 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16 [2022-11-16 11:31:32,530 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16 [2022-11-16 11:31:32,531 INFO L73 IsDeterministic]: Start isDeterministic. Operand 137 states and 170 transitions. [2022-11-16 11:31:32,531 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-16 11:31:32,531 INFO L218 hiAutomatonCegarLoop]: Abstraction has 137 states and 170 transitions. [2022-11-16 11:31:32,531 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 137 states and 170 transitions. [2022-11-16 11:31:32,533 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 137 to 111. [2022-11-16 11:31:32,533 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 111 states, 111 states have (on average 1.2702702702702702) internal successors, (141), 110 states have internal predecessors, (141), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:31:32,534 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 111 states to 111 states and 141 transitions. [2022-11-16 11:31:32,534 INFO L240 hiAutomatonCegarLoop]: Abstraction has 111 states and 141 transitions. [2022-11-16 11:31:32,537 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2022-11-16 11:31:32,537 INFO L428 stractBuchiCegarLoop]: Abstraction has 111 states and 141 transitions. [2022-11-16 11:31:32,537 INFO L335 stractBuchiCegarLoop]: ======== Iteration 53 ============ [2022-11-16 11:31:32,537 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 111 states and 141 transitions. [2022-11-16 11:31:32,538 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:31:32,538 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:31:32,538 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:31:32,539 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [10, 10, 10, 9, 6, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:31:32,539 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-16 11:31:32,539 INFO L748 eck$LassoCheckResult]: Stem: 21638#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 21639#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 21649#L367 assume !(main_~length~0#1 < 1); 21640#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 21641#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 21642#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21650#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21714#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21712#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21710#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 21708#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21706#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21704#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 21702#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21700#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21698#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 21696#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21694#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21692#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21689#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21686#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21683#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 21679#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21677#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21675#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21674#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21673#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21672#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 21669#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21668#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21666#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 21667#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21715#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21659#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21661#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21743#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 21742#L370-4 main_~j~0#1 := 0; 21655#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21647#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 21648#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21740#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 21739#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21738#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 21737#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21736#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 21735#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21734#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 21733#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21732#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 21731#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21730#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 21729#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21728#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 21727#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21726#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 21725#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21645#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 21646#L378-2 [2022-11-16 11:31:32,539 INFO L750 eck$LassoCheckResult]: Loop: 21646#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21724#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 21646#L378-2 [2022-11-16 11:31:32,540 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:31:32,540 INFO L85 PathProgramCache]: Analyzing trace with hash -1553062798, now seen corresponding path program 41 times [2022-11-16 11:31:32,540 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:31:32,540 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [227782559] [2022-11-16 11:31:32,540 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:31:32,540 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:31:32,594 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:31:33,733 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 0 proven. 235 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:31:33,734 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:31:33,734 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [227782559] [2022-11-16 11:31:33,734 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [227782559] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:31:33,734 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [100678440] [2022-11-16 11:31:33,734 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-16 11:31:33,734 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:31:33,734 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:31:33,738 INFO L229 MonitoredProcess]: Starting monitored process 67 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:31:33,739 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (67)] Waiting until timeout for monitored process [2022-11-16 11:31:34,151 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 11 check-sat command(s) [2022-11-16 11:31:34,151 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-16 11:31:34,154 INFO L263 TraceCheckSpWp]: Trace formula consists of 330 conjuncts, 65 conjunts are in the unsatisfiable core [2022-11-16 11:31:34,157 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:31:34,604 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-16 11:31:34,746 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-16 11:31:34,833 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:31:34,833 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-16 11:31:34,917 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:31:34,918 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-16 11:31:34,930 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2022-11-16 11:31:36,340 INFO L173 IndexEqualityManager]: detected equality via solver [2022-11-16 11:31:36,344 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-16 11:31:36,344 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 1 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 24 treesize of output 13 [2022-11-16 11:31:36,348 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 0 proven. 235 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:31:36,349 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:31:39,760 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 92 treesize of output 88 [2022-11-16 11:31:39,777 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-16 11:31:39,777 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 5787 treesize of output 5661 [2022-11-16 11:31:41,439 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 0 proven. 235 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:31:41,439 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [100678440] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:31:41,439 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-16 11:31:41,439 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 27, 28] total 76 [2022-11-16 11:31:41,439 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1002275820] [2022-11-16 11:31:41,439 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-16 11:31:41,440 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:31:41,440 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:31:41,440 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 48 times [2022-11-16 11:31:41,440 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:31:41,440 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [753493773] [2022-11-16 11:31:41,440 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:31:41,440 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:31:41,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:31:41,444 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:31:41,446 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:31:41,447 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:31:41,521 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:31:41,522 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 77 interpolants. [2022-11-16 11:31:41,522 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=372, Invalid=5480, Unknown=0, NotChecked=0, Total=5852 [2022-11-16 11:31:41,522 INFO L87 Difference]: Start difference. First operand 111 states and 141 transitions. cyclomatic complexity: 35 Second operand has 77 states, 76 states have (on average 2.1447368421052633) internal successors, (163), 77 states have internal predecessors, (163), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:32:01,510 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:32:01,511 INFO L93 Difference]: Finished difference Result 370 states and 441 transitions. [2022-11-16 11:32:01,511 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 370 states and 441 transitions. [2022-11-16 11:32:01,512 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 8 [2022-11-16 11:32:01,513 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 370 states to 366 states and 436 transitions. [2022-11-16 11:32:01,513 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 40 [2022-11-16 11:32:01,513 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 40 [2022-11-16 11:32:01,513 INFO L73 IsDeterministic]: Start isDeterministic. Operand 366 states and 436 transitions. [2022-11-16 11:32:01,513 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-16 11:32:01,513 INFO L218 hiAutomatonCegarLoop]: Abstraction has 366 states and 436 transitions. [2022-11-16 11:32:01,514 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 366 states and 436 transitions. [2022-11-16 11:32:01,516 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 366 to 151. [2022-11-16 11:32:01,516 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 151 states, 151 states have (on average 1.3245033112582782) internal successors, (200), 150 states have internal predecessors, (200), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:32:01,517 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 151 states to 151 states and 200 transitions. [2022-11-16 11:32:01,517 INFO L240 hiAutomatonCegarLoop]: Abstraction has 151 states and 200 transitions. [2022-11-16 11:32:01,517 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 108 states. [2022-11-16 11:32:01,518 INFO L428 stractBuchiCegarLoop]: Abstraction has 151 states and 200 transitions. [2022-11-16 11:32:01,518 INFO L335 stractBuchiCegarLoop]: ======== Iteration 54 ============ [2022-11-16 11:32:01,518 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 151 states and 200 transitions. [2022-11-16 11:32:01,518 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:32:01,519 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:32:01,519 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:32:01,519 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [10, 10, 10, 9, 6, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:32:01,519 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-16 11:32:01,520 INFO L748 eck$LassoCheckResult]: Stem: 22713#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 22714#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 22724#L367 assume !(main_~length~0#1 < 1); 22715#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 22716#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 22717#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22725#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22831#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22848#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22847#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 22828#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22846#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22845#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 22824#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22844#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22843#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 22820#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22842#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22840#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22841#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22835#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22836#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 22812#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22832#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22777#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 22779#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22773#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22774#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22772#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22768#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22766#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 22765#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22762#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22763#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22793#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22791#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 22750#L370-4 main_~j~0#1 := 0; 22749#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22728#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 22748#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22747#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 22746#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22745#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 22744#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22743#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 22742#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22741#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 22740#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22739#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 22738#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22737#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 22736#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22735#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 22734#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22732#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 22731#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22718#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 22719#L378-2 [2022-11-16 11:32:01,520 INFO L750 eck$LassoCheckResult]: Loop: 22719#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22733#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 22719#L378-2 [2022-11-16 11:32:01,520 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:32:01,520 INFO L85 PathProgramCache]: Analyzing trace with hash -1648081610, now seen corresponding path program 42 times [2022-11-16 11:32:01,520 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:32:01,521 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1780998598] [2022-11-16 11:32:01,521 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:32:01,521 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:32:01,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:32:02,746 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 0 proven. 235 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:32:02,746 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:32:02,746 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1780998598] [2022-11-16 11:32:02,747 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1780998598] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:32:02,747 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1875351425] [2022-11-16 11:32:02,747 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-11-16 11:32:02,747 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:32:02,747 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:32:02,750 INFO L229 MonitoredProcess]: Starting monitored process 68 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:32:02,751 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (68)] Waiting until timeout for monitored process [2022-11-16 11:32:03,312 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 11 check-sat command(s) [2022-11-16 11:32:03,312 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-16 11:32:03,316 INFO L263 TraceCheckSpWp]: Trace formula consists of 330 conjuncts, 68 conjunts are in the unsatisfiable core [2022-11-16 11:32:03,320 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:32:03,671 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-16 11:32:03,813 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:32:03,813 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-16 11:32:03,903 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:32:03,906 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-16 11:32:04,017 INFO L321 Elim1Store]: treesize reduction 17, result has 46.9 percent of original size [2022-11-16 11:32:04,017 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 30 [2022-11-16 11:32:04,123 INFO L321 Elim1Store]: treesize reduction 17, result has 46.9 percent of original size [2022-11-16 11:32:04,123 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 31 treesize of output 36 [2022-11-16 11:32:04,249 INFO L321 Elim1Store]: treesize reduction 17, result has 46.9 percent of original size [2022-11-16 11:32:04,249 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 33 treesize of output 38 [2022-11-16 11:32:04,451 INFO L321 Elim1Store]: treesize reduction 17, result has 46.9 percent of original size [2022-11-16 11:32:04,451 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 33 treesize of output 38 [2022-11-16 11:32:04,494 INFO L321 Elim1Store]: treesize reduction 17, result has 46.9 percent of original size [2022-11-16 11:32:04,495 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 33 treesize of output 38 [2022-11-16 11:32:08,102 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:32:08,143 INFO L321 Elim1Store]: treesize reduction 31, result has 45.6 percent of original size [2022-11-16 11:32:08,143 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 4 select indices, 4 select index equivalence classes, 1 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 6 case distinctions, treesize of input 63 treesize of output 62 [2022-11-16 11:32:08,265 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 12 proven. 223 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:32:08,265 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:32:13,901 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 54 treesize of output 50 [2022-11-16 11:32:13,915 INFO L321 Elim1Store]: treesize reduction 9, result has 10.0 percent of original size [2022-11-16 11:32:13,916 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 137 treesize of output 127 [2022-11-16 11:32:14,541 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 52 proven. 181 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-11-16 11:32:14,541 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1875351425] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:32:14,541 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-16 11:32:14,541 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 31, 26] total 78 [2022-11-16 11:32:14,542 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1531590084] [2022-11-16 11:32:14,542 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-16 11:32:14,542 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:32:14,542 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:32:14,542 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 49 times [2022-11-16 11:32:14,542 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:32:14,543 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2049341216] [2022-11-16 11:32:14,543 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:32:14,543 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:32:14,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:32:14,546 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:32:14,547 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:32:14,549 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:32:14,623 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:32:14,624 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 79 interpolants. [2022-11-16 11:32:14,624 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=606, Invalid=5556, Unknown=0, NotChecked=0, Total=6162 [2022-11-16 11:32:14,625 INFO L87 Difference]: Start difference. First operand 151 states and 200 transitions. cyclomatic complexity: 54 Second operand has 79 states, 78 states have (on average 2.076923076923077) internal successors, (162), 79 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:32:22,721 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:32:22,721 INFO L93 Difference]: Finished difference Result 384 states and 465 transitions. [2022-11-16 11:32:22,721 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 384 states and 465 transitions. [2022-11-16 11:32:22,722 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:32:22,723 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 384 states to 257 states and 331 transitions. [2022-11-16 11:32:22,724 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-16 11:32:22,724 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-16 11:32:22,724 INFO L73 IsDeterministic]: Start isDeterministic. Operand 257 states and 331 transitions. [2022-11-16 11:32:22,724 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-16 11:32:22,724 INFO L218 hiAutomatonCegarLoop]: Abstraction has 257 states and 331 transitions. [2022-11-16 11:32:22,725 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 257 states and 331 transitions. [2022-11-16 11:32:22,727 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 257 to 160. [2022-11-16 11:32:22,727 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 160 states, 160 states have (on average 1.325) internal successors, (212), 159 states have internal predecessors, (212), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:32:22,728 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 160 states to 160 states and 212 transitions. [2022-11-16 11:32:22,728 INFO L240 hiAutomatonCegarLoop]: Abstraction has 160 states and 212 transitions. [2022-11-16 11:32:22,728 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 98 states. [2022-11-16 11:32:22,728 INFO L428 stractBuchiCegarLoop]: Abstraction has 160 states and 212 transitions. [2022-11-16 11:32:22,729 INFO L335 stractBuchiCegarLoop]: ======== Iteration 55 ============ [2022-11-16 11:32:22,729 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 160 states and 212 transitions. [2022-11-16 11:32:22,729 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:32:22,729 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:32:22,729 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:32:22,730 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [10, 10, 10, 9, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:32:22,730 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-16 11:32:22,730 INFO L748 eck$LassoCheckResult]: Stem: 23809#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 23810#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 23820#L367 assume !(main_~length~0#1 < 1); 23811#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 23812#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 23813#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23821#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23935#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 23951#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23950#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 23932#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 23948#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23947#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 23928#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 23945#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23943#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 23924#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 23921#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23919#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23916#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 23914#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23908#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23883#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 23884#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23878#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 23880#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 23874#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23875#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23870#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 23871#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23865#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 23867#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 23860#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23854#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23851#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 23852#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 23818#L370-4 main_~j~0#1 := 0; 23819#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 23827#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 23845#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 23844#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 23843#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 23842#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 23841#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 23840#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 23839#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 23838#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 23837#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 23836#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 23835#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 23834#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 23833#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 23832#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 23831#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 23830#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 23829#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 23814#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 23815#L378-2 [2022-11-16 11:32:22,731 INFO L750 eck$LassoCheckResult]: Loop: 23815#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 23828#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 23815#L378-2 [2022-11-16 11:32:22,731 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:32:22,731 INFO L85 PathProgramCache]: Analyzing trace with hash -1253714824, now seen corresponding path program 43 times [2022-11-16 11:32:22,731 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:32:22,731 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [832095950] [2022-11-16 11:32:22,731 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:32:22,732 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:32:22,778 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:32:23,717 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 0 proven. 235 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:32:23,718 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:32:23,718 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [832095950] [2022-11-16 11:32:23,718 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [832095950] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:32:23,718 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1303851273] [2022-11-16 11:32:23,718 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-11-16 11:32:23,718 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:32:23,718 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:32:23,722 INFO L229 MonitoredProcess]: Starting monitored process 69 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:32:23,722 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (69)] Waiting until timeout for monitored process [2022-11-16 11:32:23,926 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:32:23,929 INFO L263 TraceCheckSpWp]: Trace formula consists of 337 conjuncts, 63 conjunts are in the unsatisfiable core [2022-11-16 11:32:23,931 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:32:24,470 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-16 11:32:24,626 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-16 11:32:24,739 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:32:24,740 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-16 11:32:24,757 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2022-11-16 11:32:26,017 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-16 11:32:26,018 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 22 treesize of output 10 [2022-11-16 11:32:26,021 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 0 proven. 235 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:32:26,021 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:32:28,191 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 70 treesize of output 66 [2022-11-16 11:32:28,199 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-16 11:32:28,199 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 404 treesize of output 388 [2022-11-16 11:32:29,083 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 0 proven. 235 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:32:29,083 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1303851273] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:32:29,083 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-16 11:32:29,084 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 26, 26] total 73 [2022-11-16 11:32:29,084 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1565042354] [2022-11-16 11:32:29,084 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-16 11:32:29,084 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:32:29,085 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:32:29,085 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 50 times [2022-11-16 11:32:29,085 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:32:29,085 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [301756258] [2022-11-16 11:32:29,085 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:32:29,085 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:32:29,089 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:32:29,089 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:32:29,090 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:32:29,092 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:32:29,165 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:32:29,165 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 74 interpolants. [2022-11-16 11:32:29,166 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=355, Invalid=5047, Unknown=0, NotChecked=0, Total=5402 [2022-11-16 11:32:29,166 INFO L87 Difference]: Start difference. First operand 160 states and 212 transitions. cyclomatic complexity: 57 Second operand has 74 states, 73 states have (on average 2.232876712328767) internal successors, (163), 74 states have internal predecessors, (163), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:32:37,254 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:32:37,255 INFO L93 Difference]: Finished difference Result 416 states and 504 transitions. [2022-11-16 11:32:37,255 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 416 states and 504 transitions. [2022-11-16 11:32:37,256 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 12 [2022-11-16 11:32:37,257 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 416 states to 413 states and 501 transitions. [2022-11-16 11:32:37,257 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 46 [2022-11-16 11:32:37,258 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 46 [2022-11-16 11:32:37,258 INFO L73 IsDeterministic]: Start isDeterministic. Operand 413 states and 501 transitions. [2022-11-16 11:32:37,258 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-16 11:32:37,258 INFO L218 hiAutomatonCegarLoop]: Abstraction has 413 states and 501 transitions. [2022-11-16 11:32:37,259 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 413 states and 501 transitions. [2022-11-16 11:32:37,261 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 413 to 160. [2022-11-16 11:32:37,262 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 160 states, 160 states have (on average 1.325) internal successors, (212), 159 states have internal predecessors, (212), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:32:37,262 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 160 states to 160 states and 212 transitions. [2022-11-16 11:32:37,262 INFO L240 hiAutomatonCegarLoop]: Abstraction has 160 states and 212 transitions. [2022-11-16 11:32:37,263 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 77 states. [2022-11-16 11:32:37,264 INFO L428 stractBuchiCegarLoop]: Abstraction has 160 states and 212 transitions. [2022-11-16 11:32:37,264 INFO L335 stractBuchiCegarLoop]: ======== Iteration 56 ============ [2022-11-16 11:32:37,264 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 160 states and 212 transitions. [2022-11-16 11:32:37,264 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:32:37,264 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:32:37,265 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:32:37,265 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [11, 10, 10, 10, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:32:37,265 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-16 11:32:37,265 INFO L748 eck$LassoCheckResult]: Stem: 24899#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 24900#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 24910#L367 assume !(main_~length~0#1 < 1); 24901#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 24902#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 24903#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24911#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24987#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25037#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25036#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 24984#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25035#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25034#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 24980#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25033#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25032#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 24976#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25031#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25030#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25029#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25027#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25025#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24968#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25022#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25018#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25019#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25050#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25046#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 25047#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25058#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25056#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24956#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25041#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25038#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 24945#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24949#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 24904#L370-4 main_~j~0#1 := 0; 24905#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24908#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 24909#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24917#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 24938#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24937#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 24936#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24935#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 24934#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24933#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 24932#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24931#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 24930#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24929#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 24928#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24927#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 24926#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24925#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 24924#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24922#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 24921#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24906#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 24907#L378-2 [2022-11-16 11:32:37,266 INFO L750 eck$LassoCheckResult]: Loop: 24907#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24923#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 24907#L378-2 [2022-11-16 11:32:37,266 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:32:37,266 INFO L85 PathProgramCache]: Analyzing trace with hash 1860465075, now seen corresponding path program 44 times [2022-11-16 11:32:37,266 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:32:37,266 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1150858267] [2022-11-16 11:32:37,267 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:32:37,267 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:32:37,291 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:32:37,865 INFO L134 CoverageAnalysis]: Checked inductivity of 255 backedges. 91 proven. 164 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:32:37,865 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:32:37,866 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1150858267] [2022-11-16 11:32:37,866 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1150858267] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:32:37,866 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1144772013] [2022-11-16 11:32:37,866 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-16 11:32:37,866 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:32:37,866 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:32:37,869 INFO L229 MonitoredProcess]: Starting monitored process 70 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:32:37,870 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (70)] Waiting until timeout for monitored process [2022-11-16 11:32:38,075 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-16 11:32:38,075 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-16 11:32:38,077 INFO L263 TraceCheckSpWp]: Trace formula consists of 349 conjuncts, 24 conjunts are in the unsatisfiable core [2022-11-16 11:32:38,078 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:32:38,674 INFO L134 CoverageAnalysis]: Checked inductivity of 255 backedges. 110 proven. 145 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:32:38,674 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:32:39,136 INFO L134 CoverageAnalysis]: Checked inductivity of 255 backedges. 110 proven. 145 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:32:39,136 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1144772013] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:32:39,136 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-16 11:32:39,136 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25] total 38 [2022-11-16 11:32:39,136 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1341604188] [2022-11-16 11:32:39,137 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-16 11:32:39,137 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:32:39,137 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:32:39,137 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 51 times [2022-11-16 11:32:39,137 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:32:39,138 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2121445744] [2022-11-16 11:32:39,138 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:32:39,138 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:32:39,142 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:32:39,142 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:32:39,143 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:32:39,145 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:32:39,221 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:32:39,222 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2022-11-16 11:32:39,222 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=329, Invalid=1077, Unknown=0, NotChecked=0, Total=1406 [2022-11-16 11:32:39,222 INFO L87 Difference]: Start difference. First operand 160 states and 212 transitions. cyclomatic complexity: 57 Second operand has 38 states, 38 states have (on average 2.3157894736842106) internal successors, (88), 38 states have internal predecessors, (88), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:32:39,868 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:32:39,868 INFO L93 Difference]: Finished difference Result 189 states and 242 transitions. [2022-11-16 11:32:39,868 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 189 states and 242 transitions. [2022-11-16 11:32:39,869 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:32:39,870 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 189 states to 167 states and 218 transitions. [2022-11-16 11:32:39,870 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-16 11:32:39,870 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-16 11:32:39,871 INFO L73 IsDeterministic]: Start isDeterministic. Operand 167 states and 218 transitions. [2022-11-16 11:32:39,871 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-16 11:32:39,871 INFO L218 hiAutomatonCegarLoop]: Abstraction has 167 states and 218 transitions. [2022-11-16 11:32:39,871 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 167 states and 218 transitions. [2022-11-16 11:32:39,873 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 167 to 133. [2022-11-16 11:32:39,873 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 133 states, 133 states have (on average 1.3082706766917294) internal successors, (174), 132 states have internal predecessors, (174), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:32:39,874 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 133 states to 133 states and 174 transitions. [2022-11-16 11:32:39,875 INFO L240 hiAutomatonCegarLoop]: Abstraction has 133 states and 174 transitions. [2022-11-16 11:32:39,875 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2022-11-16 11:32:39,876 INFO L428 stractBuchiCegarLoop]: Abstraction has 133 states and 174 transitions. [2022-11-16 11:32:39,876 INFO L335 stractBuchiCegarLoop]: ======== Iteration 57 ============ [2022-11-16 11:32:39,876 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 133 states and 174 transitions. [2022-11-16 11:32:39,878 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:32:39,878 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:32:39,878 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:32:39,879 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [11, 11, 10, 9, 6, 5, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:32:39,879 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-16 11:32:39,879 INFO L748 eck$LassoCheckResult]: Stem: 25661#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 25662#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 25672#L367 assume !(main_~length~0#1 < 1); 25663#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 25664#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 25665#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25673#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 25783#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25782#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25780#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 25779#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25778#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25776#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 25774#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25772#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25770#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 25766#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25764#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25761#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25759#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25757#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25754#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25753#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25752#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25749#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25750#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25777#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25775#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 25773#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25771#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25768#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25769#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25788#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25786#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 25729#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25791#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25698#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25703#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25704#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 25700#L370-4 main_~j~0#1 := 0; 25676#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25668#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 25669#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25696#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 25695#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25694#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 25693#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25692#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 25691#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25690#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 25689#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25688#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 25687#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25686#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 25685#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25684#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 25683#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25681#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 25680#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25666#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 25667#L378-2 [2022-11-16 11:32:39,880 INFO L750 eck$LassoCheckResult]: Loop: 25667#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25682#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 25667#L378-2 [2022-11-16 11:32:39,880 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:32:39,880 INFO L85 PathProgramCache]: Analyzing trace with hash 1074915970, now seen corresponding path program 45 times [2022-11-16 11:32:39,880 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:32:39,881 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [690515092] [2022-11-16 11:32:39,881 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:32:39,881 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:32:39,939 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:32:41,569 INFO L134 CoverageAnalysis]: Checked inductivity of 266 backedges. 0 proven. 266 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:32:41,569 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:32:41,569 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [690515092] [2022-11-16 11:32:41,569 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [690515092] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:32:41,569 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1778707571] [2022-11-16 11:32:41,569 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-16 11:32:41,570 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:32:41,570 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:32:41,573 INFO L229 MonitoredProcess]: Starting monitored process 71 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:32:41,574 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (71)] Waiting until timeout for monitored process [2022-11-16 11:32:42,161 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) [2022-11-16 11:32:42,161 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-16 11:32:42,166 INFO L263 TraceCheckSpWp]: Trace formula consists of 352 conjuncts, 55 conjunts are in the unsatisfiable core [2022-11-16 11:32:42,168 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:32:42,302 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-16 11:32:42,488 INFO L321 Elim1Store]: treesize reduction 17, result has 46.9 percent of original size [2022-11-16 11:32:42,488 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 35 treesize of output 34 [2022-11-16 11:32:42,603 INFO L321 Elim1Store]: treesize reduction 17, result has 46.9 percent of original size [2022-11-16 11:32:42,603 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 45 treesize of output 44 [2022-11-16 11:33:10,461 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-16 11:33:10,462 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 44 treesize of output 28 [2022-11-16 11:33:10,528 INFO L134 CoverageAnalysis]: Checked inductivity of 266 backedges. 2 proven. 264 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:33:10,528 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:33:10,997 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2022-11-16 11:33:11,000 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 20 [2022-11-16 11:33:11,144 INFO L134 CoverageAnalysis]: Checked inductivity of 266 backedges. 0 proven. 264 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-11-16 11:33:11,144 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1778707571] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:33:11,144 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-16 11:33:11,145 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 26, 25] total 41 [2022-11-16 11:33:11,145 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2076155577] [2022-11-16 11:33:11,145 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-16 11:33:11,145 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:33:11,145 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:33:11,145 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 52 times [2022-11-16 11:33:11,145 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:33:11,145 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1579125422] [2022-11-16 11:33:11,145 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:33:11,146 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:33:11,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:33:11,149 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:33:11,150 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:33:11,151 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:33:11,223 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:33:11,224 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2022-11-16 11:33:11,224 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=151, Invalid=1571, Unknown=0, NotChecked=0, Total=1722 [2022-11-16 11:33:11,224 INFO L87 Difference]: Start difference. First operand 133 states and 174 transitions. cyclomatic complexity: 46 Second operand has 42 states, 41 states have (on average 2.2439024390243905) internal successors, (92), 42 states have internal predecessors, (92), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:33:14,282 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:33:14,282 INFO L93 Difference]: Finished difference Result 204 states and 251 transitions. [2022-11-16 11:33:14,282 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 204 states and 251 transitions. [2022-11-16 11:33:14,282 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:33:14,283 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 204 states to 203 states and 250 transitions. [2022-11-16 11:33:14,283 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19 [2022-11-16 11:33:14,283 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19 [2022-11-16 11:33:14,283 INFO L73 IsDeterministic]: Start isDeterministic. Operand 203 states and 250 transitions. [2022-11-16 11:33:14,283 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-16 11:33:14,283 INFO L218 hiAutomatonCegarLoop]: Abstraction has 203 states and 250 transitions. [2022-11-16 11:33:14,284 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 203 states and 250 transitions. [2022-11-16 11:33:14,286 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 203 to 136. [2022-11-16 11:33:14,286 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 136 states, 136 states have (on average 1.3161764705882353) internal successors, (179), 135 states have internal predecessors, (179), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:33:14,286 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 136 states to 136 states and 179 transitions. [2022-11-16 11:33:14,287 INFO L240 hiAutomatonCegarLoop]: Abstraction has 136 states and 179 transitions. [2022-11-16 11:33:14,294 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2022-11-16 11:33:14,295 INFO L428 stractBuchiCegarLoop]: Abstraction has 136 states and 179 transitions. [2022-11-16 11:33:14,295 INFO L335 stractBuchiCegarLoop]: ======== Iteration 58 ============ [2022-11-16 11:33:14,295 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 136 states and 179 transitions. [2022-11-16 11:33:14,296 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-16 11:33:14,296 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:33:14,296 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:33:14,302 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [11, 11, 11, 10, 6, 5, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:33:14,302 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-16 11:33:14,302 INFO L748 eck$LassoCheckResult]: Stem: 26407#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 26408#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 26418#L367 assume !(main_~length~0#1 < 1); 26409#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 26410#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 26411#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26419#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 26517#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26516#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26515#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 26514#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26513#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26512#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 26511#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26510#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26509#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 26508#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26507#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26505#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26506#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26542#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26541#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26540#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26498#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26499#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26523#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26524#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26538#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 26536#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26534#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26533#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26481#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26478#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26475#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26471#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26467#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26468#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 26463#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26462#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 26412#L370-4 main_~j~0#1 := 0; 26413#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26416#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 26417#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26424#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 26443#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26442#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 26441#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26440#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 26439#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26438#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 26437#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26436#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 26435#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26434#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 26433#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26432#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 26431#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26430#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 26429#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26427#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 26426#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26414#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 26415#L378-2 [2022-11-16 11:33:14,302 INFO L750 eck$LassoCheckResult]: Loop: 26415#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26428#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 26415#L378-2 [2022-11-16 11:33:14,303 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:33:14,303 INFO L85 PathProgramCache]: Analyzing trace with hash 877931777, now seen corresponding path program 46 times [2022-11-16 11:33:14,303 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:33:14,303 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1376722550] [2022-11-16 11:33:14,303 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:33:14,304 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:33:14,363 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:33:15,841 INFO L134 CoverageAnalysis]: Checked inductivity of 286 backedges. 0 proven. 286 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:33:15,841 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:33:15,841 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1376722550] [2022-11-16 11:33:15,841 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1376722550] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:33:15,841 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [21690064] [2022-11-16 11:33:15,841 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-16 11:33:15,841 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:33:15,841 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:33:15,844 INFO L229 MonitoredProcess]: Starting monitored process 72 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:33:15,846 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (72)] Waiting until timeout for monitored process [2022-11-16 11:33:16,071 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-16 11:33:16,071 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-16 11:33:16,074 INFO L263 TraceCheckSpWp]: Trace formula consists of 348 conjuncts, 53 conjunts are in the unsatisfiable core [2022-11-16 11:33:16,076 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:33:16,220 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-16 11:33:17,315 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 11 [2022-11-16 11:33:17,318 INFO L134 CoverageAnalysis]: Checked inductivity of 286 backedges. 0 proven. 286 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:33:17,318 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:33:17,629 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2022-11-16 11:33:17,635 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 20 [2022-11-16 11:33:17,788 INFO L134 CoverageAnalysis]: Checked inductivity of 286 backedges. 0 proven. 286 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:33:17,788 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [21690064] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:33:17,788 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-16 11:33:17,788 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 26, 26] total 40 [2022-11-16 11:33:17,788 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1945025593] [2022-11-16 11:33:17,788 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-16 11:33:17,789 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:33:17,789 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:33:17,789 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 53 times [2022-11-16 11:33:17,789 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:33:17,789 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [958312123] [2022-11-16 11:33:17,789 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:33:17,789 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:33:17,792 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:33:17,792 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:33:17,793 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:33:17,794 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:33:17,867 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:33:17,867 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2022-11-16 11:33:17,867 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=118, Invalid=1522, Unknown=0, NotChecked=0, Total=1640 [2022-11-16 11:33:17,868 INFO L87 Difference]: Start difference. First operand 136 states and 179 transitions. cyclomatic complexity: 49 Second operand has 41 states, 40 states have (on average 2.25) internal successors, (90), 41 states have internal predecessors, (90), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:33:20,185 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:33:20,185 INFO L93 Difference]: Finished difference Result 213 states and 272 transitions. [2022-11-16 11:33:20,185 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 213 states and 272 transitions. [2022-11-16 11:33:20,185 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 24 [2022-11-16 11:33:20,186 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 213 states to 212 states and 271 transitions. [2022-11-16 11:33:20,187 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 43 [2022-11-16 11:33:20,187 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 43 [2022-11-16 11:33:20,187 INFO L73 IsDeterministic]: Start isDeterministic. Operand 212 states and 271 transitions. [2022-11-16 11:33:20,187 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-16 11:33:20,187 INFO L218 hiAutomatonCegarLoop]: Abstraction has 212 states and 271 transitions. [2022-11-16 11:33:20,187 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 212 states and 271 transitions. [2022-11-16 11:33:20,190 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 212 to 186. [2022-11-16 11:33:20,190 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 186 states, 186 states have (on average 1.3010752688172043) internal successors, (242), 185 states have internal predecessors, (242), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:33:20,191 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 186 states to 186 states and 242 transitions. [2022-11-16 11:33:20,191 INFO L240 hiAutomatonCegarLoop]: Abstraction has 186 states and 242 transitions. [2022-11-16 11:33:20,192 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2022-11-16 11:33:20,193 INFO L428 stractBuchiCegarLoop]: Abstraction has 186 states and 242 transitions. [2022-11-16 11:33:20,193 INFO L335 stractBuchiCegarLoop]: ======== Iteration 59 ============ [2022-11-16 11:33:20,193 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 186 states and 242 transitions. [2022-11-16 11:33:20,193 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 22 [2022-11-16 11:33:20,194 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:33:20,194 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:33:20,194 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [11, 11, 11, 10, 6, 5, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:33:20,194 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-16 11:33:20,195 INFO L748 eck$LassoCheckResult]: Stem: 27170#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 27171#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 27181#L367 assume !(main_~length~0#1 < 1); 27172#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 27173#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 27174#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27182#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 27240#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27239#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27238#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 27237#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27236#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27235#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 27234#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27233#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27232#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 27231#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27230#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27228#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27227#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27226#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27224#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27223#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27222#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27221#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27220#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27218#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27213#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 27214#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27325#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27323#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27324#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27329#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27328#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 27187#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27248#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27191#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27306#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27308#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 27179#L370-4 main_~j~0#1 := 0; 27180#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27177#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 27178#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27296#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 27295#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27294#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 27293#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27292#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 27291#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27290#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 27289#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27288#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 27287#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27286#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 27285#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27284#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 27283#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27255#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 27259#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27257#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 27258#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27175#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 27176#L378-2 [2022-11-16 11:33:20,195 INFO L750 eck$LassoCheckResult]: Loop: 27176#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27253#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 27176#L378-2 [2022-11-16 11:33:20,195 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:33:20,195 INFO L85 PathProgramCache]: Analyzing trace with hash -2092871739, now seen corresponding path program 47 times [2022-11-16 11:33:20,195 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:33:20,196 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1798485684] [2022-11-16 11:33:20,196 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:33:20,196 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:33:20,254 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:33:21,416 INFO L134 CoverageAnalysis]: Checked inductivity of 286 backedges. 0 proven. 286 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:33:21,417 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:33:21,417 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1798485684] [2022-11-16 11:33:21,417 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1798485684] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:33:21,417 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [138406758] [2022-11-16 11:33:21,417 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-16 11:33:21,417 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:33:21,417 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:33:21,420 INFO L229 MonitoredProcess]: Starting monitored process 73 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:33:21,421 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (73)] Waiting until timeout for monitored process [2022-11-16 11:33:21,801 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 12 check-sat command(s) [2022-11-16 11:33:21,801 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-16 11:33:21,804 INFO L263 TraceCheckSpWp]: Trace formula consists of 364 conjuncts, 67 conjunts are in the unsatisfiable core [2022-11-16 11:33:21,812 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:33:22,559 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-16 11:33:22,711 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-16 11:33:22,805 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-16 11:33:22,819 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2022-11-16 11:33:24,404 INFO L173 IndexEqualityManager]: detected equality via solver [2022-11-16 11:33:24,406 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:33:24,408 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-16 11:33:24,409 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 1 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 24 treesize of output 13 [2022-11-16 11:33:24,412 INFO L134 CoverageAnalysis]: Checked inductivity of 286 backedges. 0 proven. 286 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:33:24,412 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:33:27,299 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 76 treesize of output 72 [2022-11-16 11:33:27,315 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-16 11:33:27,316 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 2375 treesize of output 2263 [2022-11-16 11:33:28,781 INFO L134 CoverageAnalysis]: Checked inductivity of 286 backedges. 0 proven. 286 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:33:28,781 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [138406758] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:33:28,782 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-16 11:33:28,782 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 29, 29] total 81 [2022-11-16 11:33:28,782 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [609126340] [2022-11-16 11:33:28,782 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-16 11:33:28,783 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:33:28,783 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:33:28,783 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 54 times [2022-11-16 11:33:28,783 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:33:28,783 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [172226647] [2022-11-16 11:33:28,783 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:33:28,783 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:33:28,786 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:33:28,787 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:33:28,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:33:28,790 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:33:28,867 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:33:28,868 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 82 interpolants. [2022-11-16 11:33:28,868 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=399, Invalid=6243, Unknown=0, NotChecked=0, Total=6642 [2022-11-16 11:33:28,869 INFO L87 Difference]: Start difference. First operand 186 states and 242 transitions. cyclomatic complexity: 64 Second operand has 82 states, 81 states have (on average 2.197530864197531) internal successors, (178), 82 states have internal predecessors, (178), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:33:38,006 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:33:38,006 INFO L93 Difference]: Finished difference Result 347 states and 423 transitions. [2022-11-16 11:33:38,006 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 347 states and 423 transitions. [2022-11-16 11:33:38,007 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 28 [2022-11-16 11:33:38,008 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 347 states to 343 states and 419 transitions. [2022-11-16 11:33:38,008 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 61 [2022-11-16 11:33:38,008 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 61 [2022-11-16 11:33:38,009 INFO L73 IsDeterministic]: Start isDeterministic. Operand 343 states and 419 transitions. [2022-11-16 11:33:38,009 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-16 11:33:38,009 INFO L218 hiAutomatonCegarLoop]: Abstraction has 343 states and 419 transitions. [2022-11-16 11:33:38,009 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 343 states and 419 transitions. [2022-11-16 11:33:38,012 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 343 to 217. [2022-11-16 11:33:38,013 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 217 states, 217 states have (on average 1.294930875576037) internal successors, (281), 216 states have internal predecessors, (281), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:33:38,013 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 217 states to 217 states and 281 transitions. [2022-11-16 11:33:38,014 INFO L240 hiAutomatonCegarLoop]: Abstraction has 217 states and 281 transitions. [2022-11-16 11:33:38,014 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 80 states. [2022-11-16 11:33:38,014 INFO L428 stractBuchiCegarLoop]: Abstraction has 217 states and 281 transitions. [2022-11-16 11:33:38,014 INFO L335 stractBuchiCegarLoop]: ======== Iteration 60 ============ [2022-11-16 11:33:38,014 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 217 states and 281 transitions. [2022-11-16 11:33:38,015 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 22 [2022-11-16 11:33:38,015 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:33:38,015 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:33:38,016 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [11, 11, 11, 10, 6, 5, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:33:38,016 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-16 11:33:38,016 INFO L748 eck$LassoCheckResult]: Stem: 28264#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 28265#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 28275#L367 assume !(main_~length~0#1 < 1); 28266#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 28267#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 28268#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 28276#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 28333#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 28332#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 28331#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 28330#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 28329#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 28328#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 28327#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 28326#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 28325#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 28324#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 28323#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 28321#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 28320#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 28319#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 28318#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 28317#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 28316#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 28314#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 28315#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 28339#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 28338#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 28336#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 28337#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 28306#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 28304#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 28303#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 28301#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 28302#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 28293#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 28294#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 28286#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 28287#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 28435#L370-4 main_~j~0#1 := 0; 28279#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 28271#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 28272#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 28427#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 28426#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 28425#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 28424#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 28423#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 28422#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 28421#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 28420#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 28419#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 28418#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 28417#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 28416#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 28415#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 28414#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 28356#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 28359#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 28357#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 28358#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 28269#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 28270#L378-2 [2022-11-16 11:33:38,016 INFO L750 eck$LassoCheckResult]: Loop: 28270#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 28354#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 28270#L378-2 [2022-11-16 11:33:38,017 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:33:38,017 INFO L85 PathProgramCache]: Analyzing trace with hash 1090651777, now seen corresponding path program 48 times [2022-11-16 11:33:38,017 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:33:38,017 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [42436998] [2022-11-16 11:33:38,017 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:33:38,017 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:33:38,061 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:33:39,193 INFO L134 CoverageAnalysis]: Checked inductivity of 286 backedges. 0 proven. 286 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:33:39,193 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:33:39,193 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [42436998] [2022-11-16 11:33:39,193 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [42436998] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:33:39,194 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [740686876] [2022-11-16 11:33:39,194 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-11-16 11:33:39,194 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:33:39,194 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:33:39,198 INFO L229 MonitoredProcess]: Starting monitored process 74 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:33:39,205 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (74)] Waiting until timeout for monitored process [2022-11-16 11:33:40,766 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 12 check-sat command(s) [2022-11-16 11:33:40,767 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-16 11:33:40,770 INFO L263 TraceCheckSpWp]: Trace formula consists of 364 conjuncts, 41 conjunts are in the unsatisfiable core [2022-11-16 11:33:40,774 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:33:41,320 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-16 11:33:41,458 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-16 11:33:41,470 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-16 11:33:43,348 INFO L321 Elim1Store]: treesize reduction 26, result has 10.3 percent of original size [2022-11-16 11:33:43,348 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 36 treesize of output 13 [2022-11-16 11:33:43,352 INFO L134 CoverageAnalysis]: Checked inductivity of 286 backedges. 100 proven. 186 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:33:43,352 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:33:45,949 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 19 [2022-11-16 11:33:45,954 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 26 [2022-11-16 11:33:46,534 INFO L134 CoverageAnalysis]: Checked inductivity of 286 backedges. 72 proven. 212 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-11-16 11:33:46,534 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [740686876] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:33:46,534 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-16 11:33:46,534 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 28, 26] total 68 [2022-11-16 11:33:46,534 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1859168173] [2022-11-16 11:33:46,535 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-16 11:33:46,535 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:33:46,535 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:33:46,535 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 55 times [2022-11-16 11:33:46,535 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:33:46,536 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1433460731] [2022-11-16 11:33:46,536 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:33:46,536 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:33:46,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:33:46,540 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:33:46,541 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:33:46,544 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:33:46,619 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:33:46,619 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 69 interpolants. [2022-11-16 11:33:46,620 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=509, Invalid=4183, Unknown=0, NotChecked=0, Total=4692 [2022-11-16 11:33:46,620 INFO L87 Difference]: Start difference. First operand 217 states and 281 transitions. cyclomatic complexity: 72 Second operand has 69 states, 68 states have (on average 2.25) internal successors, (153), 69 states have internal predecessors, (153), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:33:56,041 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:33:56,041 INFO L93 Difference]: Finished difference Result 514 states and 638 transitions. [2022-11-16 11:33:56,041 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 514 states and 638 transitions. [2022-11-16 11:33:56,042 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 22 [2022-11-16 11:33:56,043 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 514 states to 420 states and 539 transitions. [2022-11-16 11:33:56,044 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 42 [2022-11-16 11:33:56,044 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 42 [2022-11-16 11:33:56,044 INFO L73 IsDeterministic]: Start isDeterministic. Operand 420 states and 539 transitions. [2022-11-16 11:33:56,045 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-16 11:33:56,045 INFO L218 hiAutomatonCegarLoop]: Abstraction has 420 states and 539 transitions. [2022-11-16 11:33:56,045 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 420 states and 539 transitions. [2022-11-16 11:33:56,048 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 420 to 217. [2022-11-16 11:33:56,049 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 217 states, 217 states have (on average 1.294930875576037) internal successors, (281), 216 states have internal predecessors, (281), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:33:56,049 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 217 states to 217 states and 281 transitions. [2022-11-16 11:33:56,050 INFO L240 hiAutomatonCegarLoop]: Abstraction has 217 states and 281 transitions. [2022-11-16 11:33:56,054 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 129 states. [2022-11-16 11:33:56,057 INFO L428 stractBuchiCegarLoop]: Abstraction has 217 states and 281 transitions. [2022-11-16 11:33:56,057 INFO L335 stractBuchiCegarLoop]: ======== Iteration 61 ============ [2022-11-16 11:33:56,057 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 217 states and 281 transitions. [2022-11-16 11:33:56,058 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 22 [2022-11-16 11:33:56,058 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:33:56,058 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:33:56,059 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [12, 12, 10, 9, 8, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:33:56,059 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-16 11:33:56,060 INFO L748 eck$LassoCheckResult]: Stem: 29663#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 29664#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 29674#L367 assume !(main_~length~0#1 < 1); 29665#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 29666#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 29667#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 29675#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 29836#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 29835#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 29834#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 29833#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 29832#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 29831#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 29824#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 29823#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 29821#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 29822#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 29826#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 29825#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 29814#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 29813#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 29812#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 29810#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 29808#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 29804#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 29805#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 29841#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 29842#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 29795#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 29840#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 29839#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 29830#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 29828#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 29780#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 29681#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 29676#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 29677#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 29748#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 29782#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 29747#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 29716#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 29712#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 29710#L370-4 main_~j~0#1 := 0; 29708#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 29707#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 29706#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 29705#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 29704#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 29703#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 29702#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 29701#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 29700#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 29699#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 29698#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 29697#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 29696#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 29695#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 29694#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 29687#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 29693#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 29691#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 29690#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 29670#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 29671#L378-2 [2022-11-16 11:33:56,060 INFO L750 eck$LassoCheckResult]: Loop: 29671#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 29685#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 29671#L378-2 [2022-11-16 11:33:56,060 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:33:56,060 INFO L85 PathProgramCache]: Analyzing trace with hash 1172945782, now seen corresponding path program 49 times [2022-11-16 11:33:56,060 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:33:56,061 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [781316871] [2022-11-16 11:33:56,061 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:33:56,061 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:33:56,121 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:33:57,453 INFO L134 CoverageAnalysis]: Checked inductivity of 300 backedges. 0 proven. 300 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:33:57,453 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:33:57,454 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [781316871] [2022-11-16 11:33:57,454 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [781316871] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:33:57,454 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [54453433] [2022-11-16 11:33:57,454 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-11-16 11:33:57,454 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:33:57,454 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:33:57,458 INFO L229 MonitoredProcess]: Starting monitored process 75 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:33:57,459 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (75)] Waiting until timeout for monitored process [2022-11-16 11:33:57,690 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:33:57,693 INFO L263 TraceCheckSpWp]: Trace formula consists of 360 conjuncts, 80 conjunts are in the unsatisfiable core [2022-11-16 11:33:57,696 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:33:57,701 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 9 [2022-11-16 11:33:57,820 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 5 treesize of output 3 [2022-11-16 11:33:58,218 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-16 11:33:58,374 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:33:58,375 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-16 11:33:58,479 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:33:58,480 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-16 11:33:58,584 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:33:58,585 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-16 11:33:58,607 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:33:58,608 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-16 11:33:58,791 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:33:58,793 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:33:58,795 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-16 11:33:58,796 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 34 treesize of output 36 [2022-11-16 11:33:58,821 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:33:58,828 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:33:58,830 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-16 11:33:58,831 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 34 treesize of output 36 [2022-11-16 11:33:58,998 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:33:59,000 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:33:59,002 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-16 11:33:59,002 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 34 treesize of output 36 [2022-11-16 11:34:00,301 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-16 11:34:00,301 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 22 treesize of output 10 [2022-11-16 11:34:00,304 INFO L134 CoverageAnalysis]: Checked inductivity of 300 backedges. 1 proven. 299 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:34:00,304 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:35:35,107 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 114 treesize of output 110 [2022-11-16 11:35:35,154 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-16 11:35:35,155 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96356 treesize of output 96036 [2022-11-16 11:37:01,556 INFO L134 CoverageAnalysis]: Checked inductivity of 300 backedges. 3 proven. 297 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:37:01,557 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [54453433] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:37:01,557 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-16 11:37:01,557 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 29, 32] total 84 [2022-11-16 11:37:01,557 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [213884829] [2022-11-16 11:37:01,557 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-16 11:37:01,558 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:37:01,558 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:37:01,558 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 56 times [2022-11-16 11:37:01,558 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:37:01,558 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1177784131] [2022-11-16 11:37:01,558 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:37:01,558 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:37:01,561 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:37:01,561 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:37:01,562 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:37:01,564 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:37:01,638 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:37:01,638 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 85 interpolants. [2022-11-16 11:37:01,639 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=428, Invalid=6700, Unknown=12, NotChecked=0, Total=7140 [2022-11-16 11:37:01,639 INFO L87 Difference]: Start difference. First operand 217 states and 281 transitions. cyclomatic complexity: 72 Second operand has 85 states, 84 states have (on average 2.1547619047619047) internal successors, (181), 85 states have internal predecessors, (181), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:38:26,546 WARN L233 SmtUtils]: Spent 12.27s on a formula simplification. DAG size of input: 95 DAG size of output: 60 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-11-16 11:38:40,783 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:38:40,783 INFO L93 Difference]: Finished difference Result 519 states and 622 transitions. [2022-11-16 11:38:40,784 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 519 states and 622 transitions. [2022-11-16 11:38:40,785 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 28 [2022-11-16 11:38:40,786 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 519 states to 514 states and 617 transitions. [2022-11-16 11:38:40,786 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 71 [2022-11-16 11:38:40,787 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 71 [2022-11-16 11:38:40,787 INFO L73 IsDeterministic]: Start isDeterministic. Operand 514 states and 617 transitions. [2022-11-16 11:38:40,787 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-16 11:38:40,787 INFO L218 hiAutomatonCegarLoop]: Abstraction has 514 states and 617 transitions. [2022-11-16 11:38:40,787 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 514 states and 617 transitions. [2022-11-16 11:38:40,791 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 514 to 221. [2022-11-16 11:38:40,791 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 221 states, 221 states have (on average 1.2986425339366516) internal successors, (287), 220 states have internal predecessors, (287), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:38:40,792 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 221 states to 221 states and 287 transitions. [2022-11-16 11:38:40,792 INFO L240 hiAutomatonCegarLoop]: Abstraction has 221 states and 287 transitions. [2022-11-16 11:38:40,793 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 71 states. [2022-11-16 11:38:40,794 INFO L428 stractBuchiCegarLoop]: Abstraction has 221 states and 287 transitions. [2022-11-16 11:38:40,794 INFO L335 stractBuchiCegarLoop]: ======== Iteration 62 ============ [2022-11-16 11:38:40,794 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 221 states and 287 transitions. [2022-11-16 11:38:40,795 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 22 [2022-11-16 11:38:40,795 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:38:40,795 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:38:40,796 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [12, 12, 10, 9, 7, 5, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:38:40,796 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-16 11:38:40,796 INFO L748 eck$LassoCheckResult]: Stem: 30946#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 30947#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 30957#L367 assume !(main_~length~0#1 < 1); 30948#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 30949#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 30950#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 30958#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 31077#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 31076#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 31075#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 31074#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 31073#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 31072#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 31071#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 31070#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 31068#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 31067#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 31066#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 31065#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 31064#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 31063#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 31062#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 31061#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 31060#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 31058#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 31057#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 31056#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 31054#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 31053#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 31052#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 31051#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 31050#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 31048#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 31049#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 31046#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 31045#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 31043#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 31044#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 31134#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 31131#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 31017#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 31128#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 31127#L370-4 main_~j~0#1 := 0; 31126#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 31125#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 31124#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 31123#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 31122#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 31121#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 31120#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 31119#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 31118#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 31117#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 31116#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 31115#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 31114#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 31113#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 31111#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 30970#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 30973#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 30971#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 30972#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 30951#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 30952#L378-2 [2022-11-16 11:38:40,796 INFO L750 eck$LassoCheckResult]: Loop: 30952#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 30968#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 30952#L378-2 [2022-11-16 11:38:40,796 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:38:40,797 INFO L85 PathProgramCache]: Analyzing trace with hash 1567312568, now seen corresponding path program 50 times [2022-11-16 11:38:40,797 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:38:40,797 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [567255561] [2022-11-16 11:38:40,797 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:38:40,797 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:38:40,846 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:38:42,139 INFO L134 CoverageAnalysis]: Checked inductivity of 300 backedges. 0 proven. 300 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:38:42,139 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:38:42,139 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [567255561] [2022-11-16 11:38:42,139 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [567255561] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:38:42,139 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1448211735] [2022-11-16 11:38:42,139 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-16 11:38:42,139 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:38:42,140 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:38:42,142 INFO L229 MonitoredProcess]: Starting monitored process 76 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:38:42,144 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8bc1acb2-a57e-4917-8da0-7da2f49dec69/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (76)] Waiting until timeout for monitored process [2022-11-16 11:38:42,391 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-16 11:38:42,391 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-16 11:38:42,394 INFO L263 TraceCheckSpWp]: Trace formula consists of 367 conjuncts, 78 conjunts are in the unsatisfiable core [2022-11-16 11:38:42,397 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:38:42,407 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 9 [2022-11-16 11:38:43,036 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-16 11:38:43,207 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-16 11:38:43,321 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-16 11:38:43,338 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-16 11:38:43,540 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:38:43,541 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:38:43,544 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-16 11:38:43,544 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 34 treesize of output 36 [2022-11-16 11:38:43,561 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:38:43,562 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:38:43,565 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-16 11:38:43,565 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 34 treesize of output 36 [2022-11-16 11:38:43,680 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:38:43,682 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:38:43,684 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-16 11:38:43,685 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 34 treesize of output 36 [2022-11-16 11:38:45,037 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 10 [2022-11-16 11:38:45,041 INFO L134 CoverageAnalysis]: Checked inductivity of 300 backedges. 1 proven. 299 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:38:45,042 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:39:48,183 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 98 treesize of output 94 [2022-11-16 11:39:48,252 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-16 11:39:48,254 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 668224 treesize of output 663616