./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/array-examples/data_structures_set_multi_proc_trivial_ground.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version e04fb08f Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/array-examples/data_structures_set_multi_proc_trivial_ground.i -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8 --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 0286582125bb2879636b8cf3b934bed172850a3a3b0d880c07306d10439134a7 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-e04fb08 [2022-11-16 11:30:31,954 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-11-16 11:30:31,957 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-11-16 11:30:32,001 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-11-16 11:30:32,001 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-11-16 11:30:32,005 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-11-16 11:30:32,008 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-11-16 11:30:32,011 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-11-16 11:30:32,015 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-11-16 11:30:32,019 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-11-16 11:30:32,021 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-11-16 11:30:32,024 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-11-16 11:30:32,024 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-11-16 11:30:32,030 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-11-16 11:30:32,036 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-11-16 11:30:32,037 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-11-16 11:30:32,039 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-11-16 11:30:32,040 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-11-16 11:30:32,042 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-11-16 11:30:32,045 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-11-16 11:30:32,049 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-11-16 11:30:32,050 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-11-16 11:30:32,051 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-11-16 11:30:32,052 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-11-16 11:30:32,058 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-11-16 11:30:32,059 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-11-16 11:30:32,059 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-11-16 11:30:32,060 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-11-16 11:30:32,060 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-11-16 11:30:32,061 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-11-16 11:30:32,061 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-11-16 11:30:32,062 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-11-16 11:30:32,063 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-11-16 11:30:32,064 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-11-16 11:30:32,065 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-11-16 11:30:32,065 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-11-16 11:30:32,066 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-11-16 11:30:32,066 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-11-16 11:30:32,066 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-11-16 11:30:32,072 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-11-16 11:30:32,074 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-11-16 11:30:32,075 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-11-16 11:30:32,103 INFO L113 SettingsManager]: Loading preferences was successful [2022-11-16 11:30:32,103 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-11-16 11:30:32,104 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-11-16 11:30:32,104 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-11-16 11:30:32,105 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-11-16 11:30:32,105 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-11-16 11:30:32,105 INFO L138 SettingsManager]: * Use SBE=true [2022-11-16 11:30:32,105 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-11-16 11:30:32,105 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-11-16 11:30:32,106 INFO L138 SettingsManager]: * Use old map elimination=false [2022-11-16 11:30:32,106 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-11-16 11:30:32,106 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-11-16 11:30:32,106 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-11-16 11:30:32,106 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-11-16 11:30:32,106 INFO L138 SettingsManager]: * sizeof long=4 [2022-11-16 11:30:32,107 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-11-16 11:30:32,107 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-11-16 11:30:32,107 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-11-16 11:30:32,107 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-11-16 11:30:32,107 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-11-16 11:30:32,107 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-11-16 11:30:32,107 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-11-16 11:30:32,108 INFO L138 SettingsManager]: * sizeof long double=12 [2022-11-16 11:30:32,108 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-11-16 11:30:32,108 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-11-16 11:30:32,108 INFO L138 SettingsManager]: * Use constant arrays=true [2022-11-16 11:30:32,108 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-11-16 11:30:32,108 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-11-16 11:30:32,109 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-11-16 11:30:32,109 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-11-16 11:30:32,109 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-11-16 11:30:32,110 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-11-16 11:30:32,110 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 0286582125bb2879636b8cf3b934bed172850a3a3b0d880c07306d10439134a7 [2022-11-16 11:30:32,449 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-11-16 11:30:32,478 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-11-16 11:30:32,481 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-11-16 11:30:32,482 INFO L271 PluginConnector]: Initializing CDTParser... [2022-11-16 11:30:32,483 INFO L275 PluginConnector]: CDTParser initialized [2022-11-16 11:30:32,485 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/../../sv-benchmarks/c/array-examples/data_structures_set_multi_proc_trivial_ground.i [2022-11-16 11:30:32,563 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/data/04681fef7/0ba3cf842a5d4324853a4868a9f63c21/FLAGc8a17ae26 [2022-11-16 11:30:33,124 INFO L306 CDTParser]: Found 1 translation units. [2022-11-16 11:30:33,125 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/sv-benchmarks/c/array-examples/data_structures_set_multi_proc_trivial_ground.i [2022-11-16 11:30:33,132 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/data/04681fef7/0ba3cf842a5d4324853a4868a9f63c21/FLAGc8a17ae26 [2022-11-16 11:30:33,473 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/data/04681fef7/0ba3cf842a5d4324853a4868a9f63c21 [2022-11-16 11:30:33,477 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-11-16 11:30:33,481 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-11-16 11:30:33,485 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-11-16 11:30:33,485 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-11-16 11:30:33,489 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-11-16 11:30:33,490 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.11 11:30:33" (1/1) ... [2022-11-16 11:30:33,492 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@64720f9a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:30:33, skipping insertion in model container [2022-11-16 11:30:33,493 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.11 11:30:33" (1/1) ... [2022-11-16 11:30:33,501 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-11-16 11:30:33,521 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-11-16 11:30:33,695 WARN L229 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/sv-benchmarks/c/array-examples/data_structures_set_multi_proc_trivial_ground.i[838,851] [2022-11-16 11:30:33,744 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-16 11:30:33,756 INFO L203 MainTranslator]: Completed pre-run [2022-11-16 11:30:33,776 WARN L229 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/sv-benchmarks/c/array-examples/data_structures_set_multi_proc_trivial_ground.i[838,851] [2022-11-16 11:30:33,813 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-16 11:30:33,828 INFO L208 MainTranslator]: Completed translation [2022-11-16 11:30:33,829 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:30:33 WrapperNode [2022-11-16 11:30:33,829 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-11-16 11:30:33,830 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-11-16 11:30:33,830 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-11-16 11:30:33,830 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-11-16 11:30:33,838 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:30:33" (1/1) ... [2022-11-16 11:30:33,858 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:30:33" (1/1) ... [2022-11-16 11:30:33,899 INFO L138 Inliner]: procedures = 18, calls = 29, calls flagged for inlining = 7, calls inlined = 7, statements flattened = 169 [2022-11-16 11:30:33,900 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-11-16 11:30:33,900 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-11-16 11:30:33,901 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-11-16 11:30:33,901 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-11-16 11:30:33,910 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:30:33" (1/1) ... [2022-11-16 11:30:33,911 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:30:33" (1/1) ... [2022-11-16 11:30:33,926 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:30:33" (1/1) ... [2022-11-16 11:30:33,927 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:30:33" (1/1) ... [2022-11-16 11:30:33,933 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:30:33" (1/1) ... [2022-11-16 11:30:33,948 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:30:33" (1/1) ... [2022-11-16 11:30:33,951 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:30:33" (1/1) ... [2022-11-16 11:30:33,959 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:30:33" (1/1) ... [2022-11-16 11:30:33,961 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-11-16 11:30:33,965 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-11-16 11:30:33,965 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-11-16 11:30:33,965 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-11-16 11:30:33,967 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:30:33" (1/1) ... [2022-11-16 11:30:33,975 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-16 11:30:33,986 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:30:34,007 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-16 11:30:34,015 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-11-16 11:30:34,059 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-11-16 11:30:34,060 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-11-16 11:30:34,060 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2022-11-16 11:30:34,060 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2022-11-16 11:30:34,060 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-11-16 11:30:34,061 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-11-16 11:30:34,061 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2022-11-16 11:30:34,061 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2022-11-16 11:30:34,182 INFO L235 CfgBuilder]: Building ICFG [2022-11-16 11:30:34,184 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-11-16 11:30:34,504 INFO L276 CfgBuilder]: Performing block encoding [2022-11-16 11:30:34,510 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-11-16 11:30:34,510 INFO L300 CfgBuilder]: Removed 10 assume(true) statements. [2022-11-16 11:30:34,512 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.11 11:30:34 BoogieIcfgContainer [2022-11-16 11:30:34,512 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-11-16 11:30:34,513 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-11-16 11:30:34,514 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-11-16 11:30:34,518 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-11-16 11:30:34,519 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-16 11:30:34,519 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 16.11 11:30:33" (1/3) ... [2022-11-16 11:30:34,536 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@cc1cc3a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 16.11 11:30:34, skipping insertion in model container [2022-11-16 11:30:34,536 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-16 11:30:34,536 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:30:33" (2/3) ... [2022-11-16 11:30:34,537 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@cc1cc3a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 16.11 11:30:34, skipping insertion in model container [2022-11-16 11:30:34,537 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-16 11:30:34,537 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.11 11:30:34" (3/3) ... [2022-11-16 11:30:34,539 INFO L332 chiAutomizerObserver]: Analyzing ICFG data_structures_set_multi_proc_trivial_ground.i [2022-11-16 11:30:34,596 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-11-16 11:30:34,596 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-11-16 11:30:34,596 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-11-16 11:30:34,596 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-11-16 11:30:34,597 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-11-16 11:30:34,597 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-11-16 11:30:34,597 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-11-16 11:30:34,597 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-11-16 11:30:34,602 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 45 states, 44 states have (on average 1.5681818181818181) internal successors, (69), 44 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:30:34,624 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 35 [2022-11-16 11:30:34,624 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:30:34,624 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:30:34,630 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-11-16 11:30:34,630 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-16 11:30:34,631 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-11-16 11:30:34,631 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 45 states, 44 states have (on average 1.5681818181818181) internal successors, (69), 44 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:30:34,635 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 35 [2022-11-16 11:30:34,635 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:30:34,635 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:30:34,636 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-11-16 11:30:34,636 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-16 11:30:34,644 INFO L748 eck$LassoCheckResult]: Stem: 29#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(48, 2); 9#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet4#1, main_#t~post3#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post6#1, main_#t~post5#1, main_#t~nondet10#1, main_#t~post9#1, main_#t~mem12#1, main_#t~ret13#1, main_#t~mem14#1, main_#t~ret15#1, main_#t~mem18#1, main_#t~mem19#1, main_#t~post17#1, main_#t~post16#1, main_#t~post11#1, main_#t~mem22#1, main_#t~mem23#1, main_#t~post21#1, main_#t~post20#1, main_~n~0#1, main_~#set~0#1.base, main_~#set~0#1.offset, main_~x~0#1, main_~y~0#1, main_~#values~0#1.base, main_~#values~0#1.offset, main_~v~0#1;main_~n~0#1 := 0;call main_~#set~0#1.base, main_~#set~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~x~0#1;havoc main_~y~0#1;main_~x~0#1 := 0; 44#L33-3true [2022-11-16 11:30:34,645 INFO L750 eck$LassoCheckResult]: Loop: 44#L33-3true assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 34#L33-2true main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 44#L33-3true [2022-11-16 11:30:34,651 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:30:34,652 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 1 times [2022-11-16 11:30:34,662 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:30:34,663 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1410401674] [2022-11-16 11:30:34,664 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:30:34,665 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:30:34,803 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:30:34,804 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:30:34,814 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:30:34,834 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:30:34,838 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:30:34,838 INFO L85 PathProgramCache]: Analyzing trace with hash 1283, now seen corresponding path program 1 times [2022-11-16 11:30:34,838 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:30:34,838 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1850137663] [2022-11-16 11:30:34,839 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:30:34,839 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:30:34,849 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:30:34,849 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:30:34,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:30:34,858 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:30:34,859 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:30:34,860 INFO L85 PathProgramCache]: Analyzing trace with hash 925765, now seen corresponding path program 1 times [2022-11-16 11:30:34,860 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:30:34,860 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [200964275] [2022-11-16 11:30:34,861 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:30:34,861 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:30:34,883 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:30:34,883 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:30:34,897 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:30:34,901 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:30:35,220 INFO L210 LassoAnalysis]: Preferences: [2022-11-16 11:30:35,220 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2022-11-16 11:30:35,220 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2022-11-16 11:30:35,220 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2022-11-16 11:30:35,221 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2022-11-16 11:30:35,221 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-16 11:30:35,221 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2022-11-16 11:30:35,221 INFO L132 ssoRankerPreferences]: Path of dumped script: [2022-11-16 11:30:35,221 INFO L133 ssoRankerPreferences]: Filename of dumped script: data_structures_set_multi_proc_trivial_ground.i_Iteration1_Lasso [2022-11-16 11:30:35,221 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2022-11-16 11:30:35,222 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2022-11-16 11:30:35,242 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-16 11:30:35,259 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-16 11:30:35,264 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-16 11:30:35,527 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-16 11:30:35,531 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-16 11:30:35,534 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-16 11:30:35,537 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-16 11:30:35,540 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-16 11:30:35,543 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-16 11:30:35,545 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-16 11:30:35,549 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-16 11:30:35,552 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-16 11:30:35,554 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-16 11:30:35,557 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-16 11:30:35,560 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-16 11:30:35,563 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-16 11:30:35,565 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-16 11:30:35,568 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-16 11:30:35,571 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-16 11:30:35,573 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-16 11:30:35,577 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-16 11:30:35,579 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-16 11:30:35,582 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-16 11:30:35,585 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-16 11:30:35,587 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-16 11:30:35,590 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-16 11:30:35,593 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-16 11:30:35,595 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-16 11:30:35,598 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-16 11:30:35,929 INFO L294 LassoAnalysis]: Preprocessing complete. [2022-11-16 11:30:35,933 INFO L490 LassoAnalysis]: Using template 'affine'. [2022-11-16 11:30:35,935 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-16 11:30:35,935 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:30:35,939 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-16 11:30:35,950 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-16 11:30:35,964 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-16 11:30:35,965 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-16 11:30:35,965 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-16 11:30:35,965 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-16 11:30:35,966 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-16 11:30:35,968 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-16 11:30:35,969 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-16 11:30:35,970 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2022-11-16 11:30:35,979 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-16 11:30:35,991 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Forceful destruction successful, exit code 0 [2022-11-16 11:30:35,991 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-16 11:30:35,992 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:30:35,996 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-16 11:30:36,009 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-16 11:30:36,022 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-16 11:30:36,022 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-16 11:30:36,022 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2022-11-16 11:30:36,022 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-16 11:30:36,023 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-16 11:30:36,023 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-16 11:30:36,024 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-16 11:30:36,024 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-16 11:30:36,039 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-16 11:30:36,047 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Forceful destruction successful, exit code 0 [2022-11-16 11:30:36,047 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-16 11:30:36,048 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:30:36,050 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-16 11:30:36,059 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-16 11:30:36,072 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-16 11:30:36,072 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-16 11:30:36,072 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-16 11:30:36,072 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-16 11:30:36,077 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-16 11:30:36,078 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-16 11:30:36,079 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2022-11-16 11:30:36,091 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-16 11:30:36,100 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Forceful destruction successful, exit code 0 [2022-11-16 11:30:36,100 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-16 11:30:36,100 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:30:36,102 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-16 11:30:36,107 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2022-11-16 11:30:36,108 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-16 11:30:36,119 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-16 11:30:36,119 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-16 11:30:36,119 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-16 11:30:36,119 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-16 11:30:36,123 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-16 11:30:36,123 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-16 11:30:36,136 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-16 11:30:36,143 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Forceful destruction successful, exit code 0 [2022-11-16 11:30:36,143 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-16 11:30:36,144 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:30:36,145 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-16 11:30:36,156 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-16 11:30:36,169 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-16 11:30:36,169 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-16 11:30:36,169 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-16 11:30:36,170 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-16 11:30:36,172 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2022-11-16 11:30:36,173 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-16 11:30:36,182 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-16 11:30:36,195 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-16 11:30:36,203 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Forceful destruction successful, exit code 0 [2022-11-16 11:30:36,204 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-16 11:30:36,204 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:30:36,205 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-16 11:30:36,214 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-16 11:30:36,227 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-16 11:30:36,227 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-16 11:30:36,227 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-16 11:30:36,227 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-16 11:30:36,228 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2022-11-16 11:30:36,237 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-16 11:30:36,238 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-16 11:30:36,259 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2022-11-16 11:30:36,298 INFO L443 ModelExtractionUtils]: Simplification made 13 calls to the SMT solver. [2022-11-16 11:30:36,298 INFO L444 ModelExtractionUtils]: 1 out of 13 variables were initially zero. Simplification set additionally 9 variables to zero. [2022-11-16 11:30:36,300 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-16 11:30:36,300 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:30:36,310 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-16 11:30:36,323 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2022-11-16 11:30:36,332 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2022-11-16 11:30:36,345 INFO L438 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2022-11-16 11:30:36,346 INFO L513 LassoAnalysis]: Proved termination. [2022-11-16 11:30:36,346 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~x~0#1, v_rep(select #length ULTIMATE.start_main_~#set~0#1.base)_1) = -8*ULTIMATE.start_main_~x~0#1 + 199999*v_rep(select #length ULTIMATE.start_main_~#set~0#1.base)_1 Supporting invariants [] [2022-11-16 11:30:36,353 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Ended with exit code 0 [2022-11-16 11:30:36,386 INFO L156 tatePredicateManager]: 5 out of 5 supporting invariants were superfluous and have been removed [2022-11-16 11:30:36,423 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:30:36,453 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:30:36,456 INFO L263 TraceCheckSpWp]: Trace formula consists of 37 conjuncts, 2 conjunts are in the unsatisfiable core [2022-11-16 11:30:36,457 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:30:36,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:30:36,482 INFO L263 TraceCheckSpWp]: Trace formula consists of 13 conjuncts, 6 conjunts are in the unsatisfiable core [2022-11-16 11:30:36,483 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:30:36,532 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:30:36,589 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2022-11-16 11:30:36,591 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand has 45 states, 44 states have (on average 1.5681818181818181) internal successors, (69), 44 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:30:36,697 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Ended with exit code 0 [2022-11-16 11:30:36,713 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand has 45 states, 44 states have (on average 1.5681818181818181) internal successors, (69), 44 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0). Second operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 89 states and 139 transitions. Complement of second has 8 states. [2022-11-16 11:30:36,716 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 5 states 1 stem states 2 non-accepting loop states 1 accepting loop states [2022-11-16 11:30:36,726 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:30:36,727 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 69 transitions. [2022-11-16 11:30:36,729 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 69 transitions. Stem has 2 letters. Loop has 2 letters. [2022-11-16 11:30:36,729 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-16 11:30:36,729 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 69 transitions. Stem has 4 letters. Loop has 2 letters. [2022-11-16 11:30:36,730 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-16 11:30:36,730 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 69 transitions. Stem has 2 letters. Loop has 4 letters. [2022-11-16 11:30:36,730 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-16 11:30:36,731 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 89 states and 139 transitions. [2022-11-16 11:30:36,746 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 33 [2022-11-16 11:30:36,749 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 89 states to 42 states and 65 transitions. [2022-11-16 11:30:36,751 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 39 [2022-11-16 11:30:36,751 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 40 [2022-11-16 11:30:36,752 INFO L73 IsDeterministic]: Start isDeterministic. Operand 42 states and 65 transitions. [2022-11-16 11:30:36,752 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:30:36,752 INFO L218 hiAutomatonCegarLoop]: Abstraction has 42 states and 65 transitions. [2022-11-16 11:30:36,772 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42 states and 65 transitions. [2022-11-16 11:30:36,785 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42 to 42. [2022-11-16 11:30:36,786 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 42 states, 42 states have (on average 1.5476190476190477) internal successors, (65), 41 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:30:36,789 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42 states to 42 states and 65 transitions. [2022-11-16 11:30:36,791 INFO L240 hiAutomatonCegarLoop]: Abstraction has 42 states and 65 transitions. [2022-11-16 11:30:36,792 INFO L428 stractBuchiCegarLoop]: Abstraction has 42 states and 65 transitions. [2022-11-16 11:30:36,792 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-11-16 11:30:36,792 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 42 states and 65 transitions. [2022-11-16 11:30:36,796 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 33 [2022-11-16 11:30:36,796 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:30:36,796 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:30:36,796 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1] [2022-11-16 11:30:36,802 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-11-16 11:30:36,803 INFO L748 eck$LassoCheckResult]: Stem: 229#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(48, 2); 205#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet4#1, main_#t~post3#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post6#1, main_#t~post5#1, main_#t~nondet10#1, main_#t~post9#1, main_#t~mem12#1, main_#t~ret13#1, main_#t~mem14#1, main_#t~ret15#1, main_#t~mem18#1, main_#t~mem19#1, main_#t~post17#1, main_#t~post16#1, main_#t~post11#1, main_#t~mem22#1, main_#t~mem23#1, main_#t~post21#1, main_#t~post20#1, main_~n~0#1, main_~#set~0#1.base, main_~#set~0#1.offset, main_~x~0#1, main_~y~0#1, main_~#values~0#1.base, main_~#values~0#1.offset, main_~v~0#1;main_~n~0#1 := 0;call main_~#set~0#1.base, main_~#set~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~x~0#1;havoc main_~y~0#1;main_~x~0#1 := 0; 206#L33-3 assume !(main_~x~0#1 < 100000); 199#L33-4 main_~x~0#1 := 0; 200#L39-3 [2022-11-16 11:30:36,803 INFO L750 eck$LassoCheckResult]: Loop: 200#L39-3 assume !!(main_~x~0#1 < main_~n~0#1);main_~y~0#1 := 1 + main_~x~0#1; 212#L40-3 assume !true; 214#L39-2 main_#t~post5#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 200#L39-3 [2022-11-16 11:30:36,807 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:30:36,807 INFO L85 PathProgramCache]: Analyzing trace with hash 925707, now seen corresponding path program 1 times [2022-11-16 11:30:36,807 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:30:36,808 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1720832424] [2022-11-16 11:30:36,808 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:30:36,808 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:30:36,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:30:36,911 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:30:36,912 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:30:36,912 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1720832424] [2022-11-16 11:30:36,913 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1720832424] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:30:36,913 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:30:36,913 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:30:36,913 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1957702958] [2022-11-16 11:30:36,914 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:30:36,916 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:30:36,917 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:30:36,917 INFO L85 PathProgramCache]: Analyzing trace with hash 54297, now seen corresponding path program 1 times [2022-11-16 11:30:36,917 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:30:36,918 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1539669800] [2022-11-16 11:30:36,918 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:30:36,918 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:30:36,922 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:30:36,925 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:30:36,926 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:30:36,926 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1539669800] [2022-11-16 11:30:36,926 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1539669800] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:30:36,926 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:30:36,926 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-16 11:30:36,927 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1110683] [2022-11-16 11:30:36,927 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:30:36,927 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:30:36,927 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:30:36,932 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2022-11-16 11:30:36,933 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2022-11-16 11:30:36,934 INFO L87 Difference]: Start difference. First operand 42 states and 65 transitions. cyclomatic complexity: 28 Second operand has 2 states, 2 states have (on average 1.5) internal successors, (3), 2 states have internal predecessors, (3), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:30:36,947 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:30:36,947 INFO L93 Difference]: Finished difference Result 42 states and 54 transitions. [2022-11-16 11:30:36,947 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 42 states and 54 transitions. [2022-11-16 11:30:36,952 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 30 [2022-11-16 11:30:36,953 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 42 states to 39 states and 51 transitions. [2022-11-16 11:30:36,953 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 37 [2022-11-16 11:30:36,953 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 37 [2022-11-16 11:30:36,954 INFO L73 IsDeterministic]: Start isDeterministic. Operand 39 states and 51 transitions. [2022-11-16 11:30:36,954 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:30:36,954 INFO L218 hiAutomatonCegarLoop]: Abstraction has 39 states and 51 transitions. [2022-11-16 11:30:36,954 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39 states and 51 transitions. [2022-11-16 11:30:36,956 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39 to 39. [2022-11-16 11:30:36,956 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 39 states, 39 states have (on average 1.3076923076923077) internal successors, (51), 38 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:30:36,957 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39 states to 39 states and 51 transitions. [2022-11-16 11:30:36,957 INFO L240 hiAutomatonCegarLoop]: Abstraction has 39 states and 51 transitions. [2022-11-16 11:30:36,957 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-11-16 11:30:36,958 INFO L428 stractBuchiCegarLoop]: Abstraction has 39 states and 51 transitions. [2022-11-16 11:30:36,958 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-11-16 11:30:36,958 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 39 states and 51 transitions. [2022-11-16 11:30:36,959 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 30 [2022-11-16 11:30:36,959 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:30:36,959 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:30:36,959 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1] [2022-11-16 11:30:36,960 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-11-16 11:30:36,960 INFO L748 eck$LassoCheckResult]: Stem: 316#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(48, 2); 293#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet4#1, main_#t~post3#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post6#1, main_#t~post5#1, main_#t~nondet10#1, main_#t~post9#1, main_#t~mem12#1, main_#t~ret13#1, main_#t~mem14#1, main_#t~ret15#1, main_#t~mem18#1, main_#t~mem19#1, main_#t~post17#1, main_#t~post16#1, main_#t~post11#1, main_#t~mem22#1, main_#t~mem23#1, main_#t~post21#1, main_#t~post20#1, main_~n~0#1, main_~#set~0#1.base, main_~#set~0#1.offset, main_~x~0#1, main_~y~0#1, main_~#values~0#1.base, main_~#values~0#1.offset, main_~v~0#1;main_~n~0#1 := 0;call main_~#set~0#1.base, main_~#set~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~x~0#1;havoc main_~y~0#1;main_~x~0#1 := 0; 294#L33-3 assume !(main_~x~0#1 < 100000); 289#L33-4 main_~x~0#1 := 0; 290#L39-3 [2022-11-16 11:30:36,960 INFO L750 eck$LassoCheckResult]: Loop: 290#L39-3 assume !!(main_~x~0#1 < main_~n~0#1);main_~y~0#1 := 1 + main_~x~0#1; 299#L40-3 assume !(main_~y~0#1 < main_~n~0#1); 301#L39-2 main_#t~post5#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 290#L39-3 [2022-11-16 11:30:36,960 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:30:36,961 INFO L85 PathProgramCache]: Analyzing trace with hash 925707, now seen corresponding path program 2 times [2022-11-16 11:30:36,961 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:30:36,961 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1947501920] [2022-11-16 11:30:36,961 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:30:36,962 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:30:36,988 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:30:37,025 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:30:37,025 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:30:37,025 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1947501920] [2022-11-16 11:30:37,025 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1947501920] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:30:37,026 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:30:37,026 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:30:37,026 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1113236154] [2022-11-16 11:30:37,026 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:30:37,027 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:30:37,027 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:30:37,027 INFO L85 PathProgramCache]: Analyzing trace with hash 53832, now seen corresponding path program 1 times [2022-11-16 11:30:37,027 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:30:37,028 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1000736845] [2022-11-16 11:30:37,028 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:30:37,028 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:30:37,032 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:30:37,032 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:30:37,034 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:30:37,036 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:30:37,060 INFO L210 LassoAnalysis]: Preferences: [2022-11-16 11:30:37,060 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2022-11-16 11:30:37,060 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2022-11-16 11:30:37,060 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2022-11-16 11:30:37,061 INFO L129 ssoRankerPreferences]: Use exernal solver: true [2022-11-16 11:30:37,061 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-16 11:30:37,061 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2022-11-16 11:30:37,061 INFO L132 ssoRankerPreferences]: Path of dumped script: [2022-11-16 11:30:37,061 INFO L133 ssoRankerPreferences]: Filename of dumped script: data_structures_set_multi_proc_trivial_ground.i_Iteration3_Loop [2022-11-16 11:30:37,061 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2022-11-16 11:30:37,061 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2022-11-16 11:30:37,062 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-16 11:30:37,064 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-16 11:30:37,104 INFO L294 LassoAnalysis]: Preprocessing complete. [2022-11-16 11:30:37,105 INFO L404 LassoAnalysis]: Checking for nontermination... [2022-11-16 11:30:37,107 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-16 11:30:37,107 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:30:37,109 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-16 11:30:37,125 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2022-11-16 11:30:37,125 INFO L160 nArgumentSynthesizer]: Using integer mode. [2022-11-16 11:30:37,138 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2022-11-16 11:30:37,156 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2022-11-16 11:30:37,156 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_main_#t~post5#1=0} Honda state: {ULTIMATE.start_main_#t~post5#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2022-11-16 11:30:37,165 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Forceful destruction successful, exit code 0 [2022-11-16 11:30:37,166 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-16 11:30:37,166 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:30:37,168 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-16 11:30:37,185 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2022-11-16 11:30:37,185 INFO L160 nArgumentSynthesizer]: Using integer mode. [2022-11-16 11:30:37,199 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2022-11-16 11:30:37,223 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Forceful destruction successful, exit code 0 [2022-11-16 11:30:37,224 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-16 11:30:37,224 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:30:37,225 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-16 11:30:37,236 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2022-11-16 11:30:37,236 INFO L160 nArgumentSynthesizer]: Using integer mode. [2022-11-16 11:30:37,249 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2022-11-16 11:30:37,571 INFO L444 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2022-11-16 11:30:37,575 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Forceful destruction successful, exit code 0 [2022-11-16 11:30:37,575 INFO L210 LassoAnalysis]: Preferences: [2022-11-16 11:30:37,575 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2022-11-16 11:30:37,576 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2022-11-16 11:30:37,576 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2022-11-16 11:30:37,576 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2022-11-16 11:30:37,576 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-16 11:30:37,576 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2022-11-16 11:30:37,576 INFO L132 ssoRankerPreferences]: Path of dumped script: [2022-11-16 11:30:37,576 INFO L133 ssoRankerPreferences]: Filename of dumped script: data_structures_set_multi_proc_trivial_ground.i_Iteration3_Loop [2022-11-16 11:30:37,576 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2022-11-16 11:30:37,576 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2022-11-16 11:30:37,577 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-16 11:30:37,589 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-16 11:30:37,650 INFO L294 LassoAnalysis]: Preprocessing complete. [2022-11-16 11:30:37,650 INFO L490 LassoAnalysis]: Using template 'affine'. [2022-11-16 11:30:37,651 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-16 11:30:37,651 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:30:37,655 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-16 11:30:37,664 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2022-11-16 11:30:37,664 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-16 11:30:37,677 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-16 11:30:37,677 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-16 11:30:37,677 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-16 11:30:37,677 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-16 11:30:37,677 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-16 11:30:37,678 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-16 11:30:37,678 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-16 11:30:37,699 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-16 11:30:37,703 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Forceful destruction successful, exit code 0 [2022-11-16 11:30:37,703 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-16 11:30:37,704 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:30:37,705 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-16 11:30:37,716 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-16 11:30:37,729 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-16 11:30:37,729 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-16 11:30:37,729 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-16 11:30:37,729 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-16 11:30:37,729 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-16 11:30:37,731 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-16 11:30:37,731 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-16 11:30:37,733 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Waiting until timeout for monitored process [2022-11-16 11:30:37,742 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2022-11-16 11:30:37,745 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2022-11-16 11:30:37,745 INFO L444 ModelExtractionUtils]: 2 out of 5 variables were initially zero. Simplification set additionally 0 variables to zero. [2022-11-16 11:30:37,746 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-16 11:30:37,746 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:30:37,747 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-16 11:30:37,756 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Waiting until timeout for monitored process [2022-11-16 11:30:37,757 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2022-11-16 11:30:37,758 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2022-11-16 11:30:37,758 INFO L513 LassoAnalysis]: Proved termination. [2022-11-16 11:30:37,758 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~x~0#1, ULTIMATE.start_main_~n~0#1) = -1*ULTIMATE.start_main_~x~0#1 + 1*ULTIMATE.start_main_~n~0#1 Supporting invariants [] [2022-11-16 11:30:37,767 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Forceful destruction successful, exit code 0 [2022-11-16 11:30:37,768 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2022-11-16 11:30:37,791 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:30:37,804 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:30:37,805 INFO L263 TraceCheckSpWp]: Trace formula consists of 40 conjuncts, 2 conjunts are in the unsatisfiable core [2022-11-16 11:30:37,805 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:30:37,817 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:30:37,817 WARN L261 TraceCheckSpWp]: Trace formula consists of 8 conjuncts, 4 conjunts are in the unsatisfiable core [2022-11-16 11:30:37,818 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:30:37,844 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:30:37,845 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2022-11-16 11:30:37,845 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 39 states and 51 transitions. cyclomatic complexity: 17 Second operand has 3 states, 3 states have (on average 2.3333333333333335) internal successors, (7), 3 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:30:37,895 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 39 states and 51 transitions. cyclomatic complexity: 17. Second operand has 3 states, 3 states have (on average 2.3333333333333335) internal successors, (7), 3 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 70 states and 94 transitions. Complement of second has 7 states. [2022-11-16 11:30:37,896 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 4 states 1 stem states 2 non-accepting loop states 1 accepting loop states [2022-11-16 11:30:37,896 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 2.3333333333333335) internal successors, (7), 3 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:30:37,897 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 30 transitions. [2022-11-16 11:30:37,897 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 30 transitions. Stem has 4 letters. Loop has 3 letters. [2022-11-16 11:30:37,898 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-16 11:30:37,898 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 30 transitions. Stem has 7 letters. Loop has 3 letters. [2022-11-16 11:30:37,898 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-16 11:30:37,898 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 30 transitions. Stem has 4 letters. Loop has 6 letters. [2022-11-16 11:30:37,898 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-16 11:30:37,899 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 70 states and 94 transitions. [2022-11-16 11:30:37,900 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 31 [2022-11-16 11:30:37,900 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 70 states to 55 states and 74 transitions. [2022-11-16 11:30:37,900 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 45 [2022-11-16 11:30:37,901 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 47 [2022-11-16 11:30:37,901 INFO L73 IsDeterministic]: Start isDeterministic. Operand 55 states and 74 transitions. [2022-11-16 11:30:37,901 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-16 11:30:37,901 INFO L218 hiAutomatonCegarLoop]: Abstraction has 55 states and 74 transitions. [2022-11-16 11:30:37,901 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55 states and 74 transitions. [2022-11-16 11:30:37,907 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55 to 44. [2022-11-16 11:30:37,907 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 44 states, 44 states have (on average 1.3409090909090908) internal successors, (59), 43 states have internal predecessors, (59), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:30:37,908 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44 states to 44 states and 59 transitions. [2022-11-16 11:30:37,908 INFO L240 hiAutomatonCegarLoop]: Abstraction has 44 states and 59 transitions. [2022-11-16 11:30:37,908 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:30:37,910 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 11:30:37,911 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 11:30:37,911 INFO L87 Difference]: Start difference. First operand 44 states and 59 transitions. Second operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:30:37,982 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:30:37,983 INFO L93 Difference]: Finished difference Result 81 states and 104 transitions. [2022-11-16 11:30:37,983 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 81 states and 104 transitions. [2022-11-16 11:30:37,984 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 54 [2022-11-16 11:30:37,985 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 81 states to 81 states and 104 transitions. [2022-11-16 11:30:37,985 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 67 [2022-11-16 11:30:37,985 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 67 [2022-11-16 11:30:37,985 INFO L73 IsDeterministic]: Start isDeterministic. Operand 81 states and 104 transitions. [2022-11-16 11:30:37,986 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-16 11:30:37,986 INFO L218 hiAutomatonCegarLoop]: Abstraction has 81 states and 104 transitions. [2022-11-16 11:30:37,986 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 81 states and 104 transitions. [2022-11-16 11:30:37,988 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 81 to 44. [2022-11-16 11:30:37,989 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 44 states, 44 states have (on average 1.3181818181818181) internal successors, (58), 43 states have internal predecessors, (58), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:30:37,989 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44 states to 44 states and 58 transitions. [2022-11-16 11:30:37,989 INFO L240 hiAutomatonCegarLoop]: Abstraction has 44 states and 58 transitions. [2022-11-16 11:30:37,990 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 11:30:37,991 INFO L428 stractBuchiCegarLoop]: Abstraction has 44 states and 58 transitions. [2022-11-16 11:30:37,991 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-11-16 11:30:37,991 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 44 states and 58 transitions. [2022-11-16 11:30:37,991 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 28 [2022-11-16 11:30:37,992 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:30:37,992 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:30:37,992 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:30:37,992 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2022-11-16 11:30:37,992 INFO L748 eck$LassoCheckResult]: Stem: 598#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(48, 2); 572#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet4#1, main_#t~post3#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post6#1, main_#t~post5#1, main_#t~nondet10#1, main_#t~post9#1, main_#t~mem12#1, main_#t~ret13#1, main_#t~mem14#1, main_#t~ret15#1, main_#t~mem18#1, main_#t~mem19#1, main_#t~post17#1, main_#t~post16#1, main_#t~post11#1, main_#t~mem22#1, main_#t~mem23#1, main_#t~post21#1, main_#t~post20#1, main_~n~0#1, main_~#set~0#1.base, main_~#set~0#1.offset, main_~x~0#1, main_~y~0#1, main_~#values~0#1.base, main_~#values~0#1.offset, main_~v~0#1;main_~n~0#1 := 0;call main_~#set~0#1.base, main_~#set~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~x~0#1;havoc main_~y~0#1;main_~x~0#1 := 0; 573#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 601#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 602#L33-3 assume !(main_~x~0#1 < 100000); 568#L33-4 main_~x~0#1 := 0; 569#L39-3 assume !!(main_~x~0#1 < main_~n~0#1);main_~y~0#1 := 1 + main_~x~0#1; 578#L40-3 [2022-11-16 11:30:37,993 INFO L750 eck$LassoCheckResult]: Loop: 578#L40-3 assume !!(main_~y~0#1 < main_~n~0#1);call main_#t~mem7#1 := read~int(main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);call main_#t~mem8#1 := read~int(main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~y~0#1, 4);assume { :begin_inline___VERIFIER_assert } true;__VERIFIER_assert_#in~cond#1 := (if main_#t~mem7#1 != main_#t~mem8#1 then 1 else 0);havoc __VERIFIER_assert_~cond#1;__VERIFIER_assert_~cond#1 := __VERIFIER_assert_#in~cond#1; 579#L13 assume !(0 == __VERIFIER_assert_~cond#1); 564#L13-3 assume { :end_inline___VERIFIER_assert } true;havoc main_#t~mem7#1;havoc main_#t~mem8#1; 565#L40-2 main_#t~post6#1 := main_~y~0#1;main_~y~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 578#L40-3 [2022-11-16 11:30:37,993 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:30:37,993 INFO L85 PathProgramCache]: Analyzing trace with hash 1809669547, now seen corresponding path program 1 times [2022-11-16 11:30:37,993 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:30:37,994 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [906484861] [2022-11-16 11:30:37,994 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:30:37,994 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:30:38,004 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:30:38,042 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:30:38,043 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:30:38,043 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [906484861] [2022-11-16 11:30:38,043 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [906484861] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:30:38,043 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1353972427] [2022-11-16 11:30:38,043 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:30:38,044 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:30:38,044 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:30:38,045 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:30:38,063 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Waiting until timeout for monitored process [2022-11-16 11:30:38,100 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:30:38,101 INFO L263 TraceCheckSpWp]: Trace formula consists of 54 conjuncts, 3 conjunts are in the unsatisfiable core [2022-11-16 11:30:38,102 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:30:38,117 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:30:38,117 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:30:38,142 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:30:38,143 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1353972427] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:30:38,143 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-16 11:30:38,143 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4] total 7 [2022-11-16 11:30:38,143 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1761663219] [2022-11-16 11:30:38,143 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-16 11:30:38,144 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:30:38,144 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:30:38,144 INFO L85 PathProgramCache]: Analyzing trace with hash 1915626, now seen corresponding path program 1 times [2022-11-16 11:30:38,144 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:30:38,144 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [448670951] [2022-11-16 11:30:38,145 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:30:38,145 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:30:38,154 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:30:38,154 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:30:38,159 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:30:38,161 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:30:38,282 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:30:38,283 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-11-16 11:30:38,283 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=21, Unknown=0, NotChecked=0, Total=42 [2022-11-16 11:30:38,283 INFO L87 Difference]: Start difference. First operand 44 states and 58 transitions. cyclomatic complexity: 20 Second operand has 7 states, 7 states have (on average 2.0) internal successors, (14), 7 states have internal predecessors, (14), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:30:38,464 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:30:38,464 INFO L93 Difference]: Finished difference Result 197 states and 253 transitions. [2022-11-16 11:30:38,464 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 197 states and 253 transitions. [2022-11-16 11:30:38,478 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 132 [2022-11-16 11:30:38,481 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 197 states to 197 states and 253 transitions. [2022-11-16 11:30:38,481 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 160 [2022-11-16 11:30:38,482 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 160 [2022-11-16 11:30:38,482 INFO L73 IsDeterministic]: Start isDeterministic. Operand 197 states and 253 transitions. [2022-11-16 11:30:38,482 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-16 11:30:38,482 INFO L218 hiAutomatonCegarLoop]: Abstraction has 197 states and 253 transitions. [2022-11-16 11:30:38,482 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 197 states and 253 transitions. [2022-11-16 11:30:38,495 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 197 to 50. [2022-11-16 11:30:38,499 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Ended with exit code 0 [2022-11-16 11:30:38,502 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 50 states, 50 states have (on average 1.28) internal successors, (64), 49 states have internal predecessors, (64), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:30:38,505 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 64 transitions. [2022-11-16 11:30:38,507 INFO L240 hiAutomatonCegarLoop]: Abstraction has 50 states and 64 transitions. [2022-11-16 11:30:38,507 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-11-16 11:30:38,508 INFO L428 stractBuchiCegarLoop]: Abstraction has 50 states and 64 transitions. [2022-11-16 11:30:38,509 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-11-16 11:30:38,510 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 50 states and 64 transitions. [2022-11-16 11:30:38,510 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 28 [2022-11-16 11:30:38,511 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:30:38,511 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:30:38,512 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 4, 1, 1, 1, 1, 1] [2022-11-16 11:30:38,512 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2022-11-16 11:30:38,513 INFO L748 eck$LassoCheckResult]: Stem: 885#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(48, 2); 857#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet4#1, main_#t~post3#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post6#1, main_#t~post5#1, main_#t~nondet10#1, main_#t~post9#1, main_#t~mem12#1, main_#t~ret13#1, main_#t~mem14#1, main_#t~ret15#1, main_#t~mem18#1, main_#t~mem19#1, main_#t~post17#1, main_#t~post16#1, main_#t~post11#1, main_#t~mem22#1, main_#t~mem23#1, main_#t~post21#1, main_#t~post20#1, main_~n~0#1, main_~#set~0#1.base, main_~#set~0#1.offset, main_~x~0#1, main_~y~0#1, main_~#values~0#1.base, main_~#values~0#1.offset, main_~v~0#1;main_~n~0#1 := 0;call main_~#set~0#1.base, main_~#set~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~x~0#1;havoc main_~y~0#1;main_~x~0#1 := 0; 858#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 891#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 892#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 888#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 889#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 896#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 895#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 894#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 893#L33-3 assume !(main_~x~0#1 < 100000); 851#L33-4 main_~x~0#1 := 0; 852#L39-3 assume !!(main_~x~0#1 < main_~n~0#1);main_~y~0#1 := 1 + main_~x~0#1; 865#L40-3 [2022-11-16 11:30:38,513 INFO L750 eck$LassoCheckResult]: Loop: 865#L40-3 assume !!(main_~y~0#1 < main_~n~0#1);call main_#t~mem7#1 := read~int(main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);call main_#t~mem8#1 := read~int(main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~y~0#1, 4);assume { :begin_inline___VERIFIER_assert } true;__VERIFIER_assert_#in~cond#1 := (if main_#t~mem7#1 != main_#t~mem8#1 then 1 else 0);havoc __VERIFIER_assert_~cond#1;__VERIFIER_assert_~cond#1 := __VERIFIER_assert_#in~cond#1; 866#L13 assume !(0 == __VERIFIER_assert_~cond#1); 853#L13-3 assume { :end_inline___VERIFIER_assert } true;havoc main_#t~mem7#1;havoc main_#t~mem8#1; 854#L40-2 main_#t~post6#1 := main_~y~0#1;main_~y~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1; 865#L40-3 [2022-11-16 11:30:38,513 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:30:38,514 INFO L85 PathProgramCache]: Analyzing trace with hash 82232677, now seen corresponding path program 2 times [2022-11-16 11:30:38,515 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:30:38,515 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1231027446] [2022-11-16 11:30:38,516 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:30:38,516 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:30:38,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:30:38,654 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2022-11-16 11:30:38,654 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:30:38,655 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1231027446] [2022-11-16 11:30:38,656 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1231027446] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:30:38,657 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:30:38,657 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:30:38,657 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [673564970] [2022-11-16 11:30:38,657 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:30:38,657 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:30:38,663 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:30:38,664 INFO L85 PathProgramCache]: Analyzing trace with hash 1915626, now seen corresponding path program 2 times [2022-11-16 11:30:38,664 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:30:38,664 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [955421865] [2022-11-16 11:30:38,664 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:30:38,664 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:30:38,679 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:30:38,682 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:30:38,686 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:30:38,691 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:30:38,806 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:30:38,807 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 11:30:38,808 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2022-11-16 11:30:38,808 INFO L87 Difference]: Start difference. First operand 50 states and 64 transitions. cyclomatic complexity: 20 Second operand has 4 states, 3 states have (on average 2.3333333333333335) internal successors, (7), 4 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:30:38,862 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:30:38,862 INFO L93 Difference]: Finished difference Result 53 states and 65 transitions. [2022-11-16 11:30:38,863 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 53 states and 65 transitions. [2022-11-16 11:30:38,863 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 34 [2022-11-16 11:30:38,864 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 53 states to 51 states and 63 transitions. [2022-11-16 11:30:38,864 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 43 [2022-11-16 11:30:38,865 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 43 [2022-11-16 11:30:38,865 INFO L73 IsDeterministic]: Start isDeterministic. Operand 51 states and 63 transitions. [2022-11-16 11:30:38,866 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:30:38,866 INFO L218 hiAutomatonCegarLoop]: Abstraction has 51 states and 63 transitions. [2022-11-16 11:30:38,867 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51 states and 63 transitions. [2022-11-16 11:30:38,879 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51 to 50. [2022-11-16 11:30:38,880 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 50 states, 50 states have (on average 1.24) internal successors, (62), 49 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:30:38,880 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 62 transitions. [2022-11-16 11:30:38,880 INFO L240 hiAutomatonCegarLoop]: Abstraction has 50 states and 62 transitions. [2022-11-16 11:30:38,881 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-16 11:30:38,883 INFO L428 stractBuchiCegarLoop]: Abstraction has 50 states and 62 transitions. [2022-11-16 11:30:38,883 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-11-16 11:30:38,883 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 50 states and 62 transitions. [2022-11-16 11:30:38,884 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 34 [2022-11-16 11:30:38,884 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:30:38,884 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:30:38,885 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 4, 1, 1, 1, 1, 1, 1] [2022-11-16 11:30:38,885 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-16 11:30:38,885 INFO L748 eck$LassoCheckResult]: Stem: 985#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(48, 2); 962#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet4#1, main_#t~post3#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post6#1, main_#t~post5#1, main_#t~nondet10#1, main_#t~post9#1, main_#t~mem12#1, main_#t~ret13#1, main_#t~mem14#1, main_#t~ret15#1, main_#t~mem18#1, main_#t~mem19#1, main_#t~post17#1, main_#t~post16#1, main_#t~post11#1, main_#t~mem22#1, main_#t~mem23#1, main_#t~post21#1, main_#t~post20#1, main_~n~0#1, main_~#set~0#1.base, main_~#set~0#1.offset, main_~x~0#1, main_~y~0#1, main_~#values~0#1.base, main_~#values~0#1.offset, main_~v~0#1;main_~n~0#1 := 0;call main_~#set~0#1.base, main_~#set~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~x~0#1;havoc main_~y~0#1;main_~x~0#1 := 0; 963#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 988#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 989#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 993#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 999#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 998#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 997#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 995#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 994#L33-3 assume !(main_~x~0#1 < 100000); 960#L33-4 main_~x~0#1 := 0; 961#L39-3 assume !(main_~x~0#1 < main_~n~0#1); 977#L39-4 call main_~#values~0#1.base, main_~#values~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~v~0#1;main_~v~0#1 := 0; 978#L47-3 [2022-11-16 11:30:38,886 INFO L750 eck$LassoCheckResult]: Loop: 978#L47-3 assume !!(main_~v~0#1 < 100000);call write~int(main_#t~nondet10#1, main_~#values~0#1.base, main_~#values~0#1.offset + 4 * main_~v~0#1, 4);havoc main_#t~nondet10#1; 979#L47-2 main_#t~post9#1 := main_~v~0#1;main_~v~0#1 := 1 + main_#t~post9#1;havoc main_#t~post9#1; 978#L47-3 [2022-11-16 11:30:38,886 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:30:38,886 INFO L85 PathProgramCache]: Analyzing trace with hash -1745754320, now seen corresponding path program 1 times [2022-11-16 11:30:38,886 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:30:38,887 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1099522503] [2022-11-16 11:30:38,887 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:30:38,887 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:30:38,916 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:30:39,053 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:30:39,054 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:30:39,054 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1099522503] [2022-11-16 11:30:39,054 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1099522503] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:30:39,054 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2085010862] [2022-11-16 11:30:39,055 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:30:39,055 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:30:39,055 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:30:39,059 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:30:39,083 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Waiting until timeout for monitored process [2022-11-16 11:30:39,135 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:30:39,136 INFO L263 TraceCheckSpWp]: Trace formula consists of 99 conjuncts, 6 conjunts are in the unsatisfiable core [2022-11-16 11:30:39,138 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:30:39,167 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:30:39,168 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:30:39,238 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:30:39,238 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2085010862] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:30:39,238 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-16 11:30:39,238 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7] total 13 [2022-11-16 11:30:39,239 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [417977092] [2022-11-16 11:30:39,239 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-16 11:30:39,239 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:30:39,240 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:30:39,240 INFO L85 PathProgramCache]: Analyzing trace with hash 2851, now seen corresponding path program 1 times [2022-11-16 11:30:39,240 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:30:39,240 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [161052127] [2022-11-16 11:30:39,240 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:30:39,241 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:30:39,245 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:30:39,245 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:30:39,249 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:30:39,250 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:30:39,288 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:30:39,288 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2022-11-16 11:30:39,289 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=78, Unknown=0, NotChecked=0, Total=156 [2022-11-16 11:30:39,289 INFO L87 Difference]: Start difference. First operand 50 states and 62 transitions. cyclomatic complexity: 17 Second operand has 13 states, 13 states have (on average 2.076923076923077) internal successors, (27), 13 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:30:39,528 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:30:39,528 INFO L93 Difference]: Finished difference Result 292 states and 374 transitions. [2022-11-16 11:30:39,528 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 292 states and 374 transitions. [2022-11-16 11:30:39,530 INFO L131 ngComponentsAnalysis]: Automaton has 14 accepting balls. 234 [2022-11-16 11:30:39,532 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 292 states to 292 states and 374 transitions. [2022-11-16 11:30:39,533 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 272 [2022-11-16 11:30:39,533 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 272 [2022-11-16 11:30:39,533 INFO L73 IsDeterministic]: Start isDeterministic. Operand 292 states and 374 transitions. [2022-11-16 11:30:39,534 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:30:39,534 INFO L218 hiAutomatonCegarLoop]: Abstraction has 292 states and 374 transitions. [2022-11-16 11:30:39,535 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 292 states and 374 transitions. [2022-11-16 11:30:39,538 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 292 to 62. [2022-11-16 11:30:39,539 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 62 states, 62 states have (on average 1.1935483870967742) internal successors, (74), 61 states have internal predecessors, (74), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:30:39,539 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 62 states to 62 states and 74 transitions. [2022-11-16 11:30:39,539 INFO L240 hiAutomatonCegarLoop]: Abstraction has 62 states and 74 transitions. [2022-11-16 11:30:39,540 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2022-11-16 11:30:39,540 INFO L428 stractBuchiCegarLoop]: Abstraction has 62 states and 74 transitions. [2022-11-16 11:30:39,540 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-11-16 11:30:39,540 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 62 states and 74 transitions. [2022-11-16 11:30:39,541 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 34 [2022-11-16 11:30:39,541 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:30:39,541 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:30:39,542 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [10, 10, 1, 1, 1, 1, 1, 1] [2022-11-16 11:30:39,542 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-16 11:30:39,542 INFO L748 eck$LassoCheckResult]: Stem: 1421#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(48, 2); 1398#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet4#1, main_#t~post3#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post6#1, main_#t~post5#1, main_#t~nondet10#1, main_#t~post9#1, main_#t~mem12#1, main_#t~ret13#1, main_#t~mem14#1, main_#t~ret15#1, main_#t~mem18#1, main_#t~mem19#1, main_#t~post17#1, main_#t~post16#1, main_#t~post11#1, main_#t~mem22#1, main_#t~mem23#1, main_#t~post21#1, main_#t~post20#1, main_~n~0#1, main_~#set~0#1.base, main_~#set~0#1.offset, main_~x~0#1, main_~y~0#1, main_~#values~0#1.base, main_~#values~0#1.offset, main_~v~0#1;main_~n~0#1 := 0;call main_~#set~0#1.base, main_~#set~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~x~0#1;havoc main_~y~0#1;main_~x~0#1 := 0; 1399#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 1429#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1430#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 1424#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1425#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 1446#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1445#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 1444#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1443#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 1442#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1441#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 1440#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1439#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 1438#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1437#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 1436#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1435#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 1434#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1433#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 1432#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1431#L33-3 assume !(main_~x~0#1 < 100000); 1396#L33-4 main_~x~0#1 := 0; 1397#L39-3 assume !(main_~x~0#1 < main_~n~0#1); 1413#L39-4 call main_~#values~0#1.base, main_~#values~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~v~0#1;main_~v~0#1 := 0; 1414#L47-3 [2022-11-16 11:30:39,542 INFO L750 eck$LassoCheckResult]: Loop: 1414#L47-3 assume !!(main_~v~0#1 < 100000);call write~int(main_#t~nondet10#1, main_~#values~0#1.base, main_~#values~0#1.offset + 4 * main_~v~0#1, 4);havoc main_#t~nondet10#1; 1415#L47-2 main_#t~post9#1 := main_~v~0#1;main_~v~0#1 := 1 + main_#t~post9#1;havoc main_#t~post9#1; 1414#L47-3 [2022-11-16 11:30:39,543 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:30:39,543 INFO L85 PathProgramCache]: Analyzing trace with hash -95702852, now seen corresponding path program 2 times [2022-11-16 11:30:39,543 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:30:39,543 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1495314131] [2022-11-16 11:30:39,543 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:30:39,544 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:30:39,562 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:30:39,790 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:30:39,791 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:30:39,793 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1495314131] [2022-11-16 11:30:39,796 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1495314131] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:30:39,796 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [753524979] [2022-11-16 11:30:39,796 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-16 11:30:39,797 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:30:39,797 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:30:39,803 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:30:39,835 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Waiting until timeout for monitored process [2022-11-16 11:30:39,907 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-16 11:30:39,908 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-16 11:30:39,909 INFO L263 TraceCheckSpWp]: Trace formula consists of 165 conjuncts, 12 conjunts are in the unsatisfiable core [2022-11-16 11:30:39,912 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:30:39,977 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:30:39,978 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:30:40,214 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:30:40,214 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [753524979] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:30:40,214 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-16 11:30:40,214 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13] total 25 [2022-11-16 11:30:40,217 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1309062166] [2022-11-16 11:30:40,217 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-16 11:30:40,217 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:30:40,218 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:30:40,218 INFO L85 PathProgramCache]: Analyzing trace with hash 2851, now seen corresponding path program 2 times [2022-11-16 11:30:40,218 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:30:40,218 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1320059987] [2022-11-16 11:30:40,218 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:30:40,218 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:30:40,222 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:30:40,223 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:30:40,225 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:30:40,228 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:30:40,276 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:30:40,277 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2022-11-16 11:30:40,278 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=300, Invalid=300, Unknown=0, NotChecked=0, Total=600 [2022-11-16 11:30:40,279 INFO L87 Difference]: Start difference. First operand 62 states and 74 transitions. cyclomatic complexity: 17 Second operand has 25 states, 25 states have (on average 2.04) internal successors, (51), 25 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:30:40,991 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:30:40,991 INFO L93 Difference]: Finished difference Result 592 states and 758 transitions. [2022-11-16 11:30:40,992 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 592 states and 758 transitions. [2022-11-16 11:30:40,997 INFO L131 ngComponentsAnalysis]: Automaton has 26 accepting balls. 474 [2022-11-16 11:30:41,001 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 592 states to 592 states and 758 transitions. [2022-11-16 11:30:41,001 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 548 [2022-11-16 11:30:41,001 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 548 [2022-11-16 11:30:41,002 INFO L73 IsDeterministic]: Start isDeterministic. Operand 592 states and 758 transitions. [2022-11-16 11:30:41,007 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:30:41,007 INFO L218 hiAutomatonCegarLoop]: Abstraction has 592 states and 758 transitions. [2022-11-16 11:30:41,009 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 592 states and 758 transitions. [2022-11-16 11:30:41,020 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 592 to 86. [2022-11-16 11:30:41,023 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 86 states, 86 states have (on average 1.1395348837209303) internal successors, (98), 85 states have internal predecessors, (98), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:30:41,024 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 86 states to 86 states and 98 transitions. [2022-11-16 11:30:41,024 INFO L240 hiAutomatonCegarLoop]: Abstraction has 86 states and 98 transitions. [2022-11-16 11:30:41,024 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2022-11-16 11:30:41,027 INFO L428 stractBuchiCegarLoop]: Abstraction has 86 states and 98 transitions. [2022-11-16 11:30:41,028 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-11-16 11:30:41,028 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 86 states and 98 transitions. [2022-11-16 11:30:41,029 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 34 [2022-11-16 11:30:41,029 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:30:41,029 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:30:41,031 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [22, 22, 1, 1, 1, 1, 1, 1] [2022-11-16 11:30:41,031 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-16 11:30:41,033 INFO L748 eck$LassoCheckResult]: Stem: 2256#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(48, 2); 2232#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet4#1, main_#t~post3#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post6#1, main_#t~post5#1, main_#t~nondet10#1, main_#t~post9#1, main_#t~mem12#1, main_#t~ret13#1, main_#t~mem14#1, main_#t~ret15#1, main_#t~mem18#1, main_#t~mem19#1, main_#t~post17#1, main_#t~post16#1, main_#t~post11#1, main_#t~mem22#1, main_#t~mem23#1, main_#t~post21#1, main_#t~post20#1, main_~n~0#1, main_~#set~0#1.base, main_~#set~0#1.offset, main_~x~0#1, main_~y~0#1, main_~#values~0#1.base, main_~#values~0#1.offset, main_~v~0#1;main_~n~0#1 := 0;call main_~#set~0#1.base, main_~#set~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~x~0#1;havoc main_~y~0#1;main_~x~0#1 := 0; 2233#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 2266#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2267#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 2261#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2262#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 2307#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2306#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 2305#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2304#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 2303#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2302#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 2301#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2300#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 2299#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2298#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 2297#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2296#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 2295#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2294#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 2293#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2292#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 2291#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2290#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 2289#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2288#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 2287#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2286#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 2285#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2284#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 2283#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2282#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 2281#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2280#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 2279#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2278#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 2277#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2276#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 2275#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2274#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 2273#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2272#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 2271#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2270#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 2269#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2268#L33-3 assume !(main_~x~0#1 < 100000); 2228#L33-4 main_~x~0#1 := 0; 2229#L39-3 assume !(main_~x~0#1 < main_~n~0#1); 2248#L39-4 call main_~#values~0#1.base, main_~#values~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~v~0#1;main_~v~0#1 := 0; 2249#L47-3 [2022-11-16 11:30:41,034 INFO L750 eck$LassoCheckResult]: Loop: 2249#L47-3 assume !!(main_~v~0#1 < 100000);call write~int(main_#t~nondet10#1, main_~#values~0#1.base, main_~#values~0#1.offset + 4 * main_~v~0#1, 4);havoc main_#t~nondet10#1; 2250#L47-2 main_#t~post9#1 := main_~v~0#1;main_~v~0#1 := 1 + main_#t~post9#1;havoc main_#t~post9#1; 2249#L47-3 [2022-11-16 11:30:41,035 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:30:41,035 INFO L85 PathProgramCache]: Analyzing trace with hash 1293970900, now seen corresponding path program 3 times [2022-11-16 11:30:41,035 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:30:41,036 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1355689762] [2022-11-16 11:30:41,036 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:30:41,036 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:30:41,089 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:30:41,737 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 484 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:30:41,738 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:30:41,738 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1355689762] [2022-11-16 11:30:41,739 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1355689762] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:30:41,739 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [968554934] [2022-11-16 11:30:41,739 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-16 11:30:41,739 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:30:41,739 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:30:41,743 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:30:41,767 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Waiting until timeout for monitored process [2022-11-16 11:30:42,763 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 23 check-sat command(s) [2022-11-16 11:30:42,763 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-16 11:30:42,768 INFO L263 TraceCheckSpWp]: Trace formula consists of 297 conjuncts, 24 conjunts are in the unsatisfiable core [2022-11-16 11:30:42,771 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:30:42,884 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 484 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:30:42,884 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:30:43,883 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 484 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:30:43,884 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [968554934] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:30:43,884 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-16 11:30:43,884 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25] total 49 [2022-11-16 11:30:43,885 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1096756112] [2022-11-16 11:30:43,885 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-16 11:30:43,886 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:30:43,887 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:30:43,887 INFO L85 PathProgramCache]: Analyzing trace with hash 2851, now seen corresponding path program 3 times [2022-11-16 11:30:43,887 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:30:43,887 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [306960159] [2022-11-16 11:30:43,887 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:30:43,888 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:30:43,895 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:30:43,895 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:30:43,899 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:30:43,905 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:30:43,950 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:30:43,951 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2022-11-16 11:30:43,952 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1176, Invalid=1176, Unknown=0, NotChecked=0, Total=2352 [2022-11-16 11:30:43,952 INFO L87 Difference]: Start difference. First operand 86 states and 98 transitions. cyclomatic complexity: 17 Second operand has 49 states, 49 states have (on average 2.020408163265306) internal successors, (99), 49 states have internal predecessors, (99), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:30:46,335 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:30:46,336 INFO L93 Difference]: Finished difference Result 1192 states and 1526 transitions. [2022-11-16 11:30:46,336 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1192 states and 1526 transitions. [2022-11-16 11:30:46,343 INFO L131 ngComponentsAnalysis]: Automaton has 50 accepting balls. 954 [2022-11-16 11:30:46,350 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1192 states to 1192 states and 1526 transitions. [2022-11-16 11:30:46,350 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1100 [2022-11-16 11:30:46,351 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1100 [2022-11-16 11:30:46,351 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1192 states and 1526 transitions. [2022-11-16 11:30:46,353 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:30:46,353 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1192 states and 1526 transitions. [2022-11-16 11:30:46,354 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1192 states and 1526 transitions. [2022-11-16 11:30:46,359 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1192 to 134. [2022-11-16 11:30:46,360 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 134 states, 134 states have (on average 1.0895522388059702) internal successors, (146), 133 states have internal predecessors, (146), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:30:46,361 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 134 states to 134 states and 146 transitions. [2022-11-16 11:30:46,361 INFO L240 hiAutomatonCegarLoop]: Abstraction has 134 states and 146 transitions. [2022-11-16 11:30:46,361 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2022-11-16 11:30:46,362 INFO L428 stractBuchiCegarLoop]: Abstraction has 134 states and 146 transitions. [2022-11-16 11:30:46,362 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-11-16 11:30:46,362 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 134 states and 146 transitions. [2022-11-16 11:30:46,364 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 34 [2022-11-16 11:30:46,364 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:30:46,364 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:30:46,366 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [46, 46, 1, 1, 1, 1, 1, 1] [2022-11-16 11:30:46,366 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-16 11:30:46,367 INFO L748 eck$LassoCheckResult]: Stem: 3877#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(48, 2); 3854#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet4#1, main_#t~post3#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post6#1, main_#t~post5#1, main_#t~nondet10#1, main_#t~post9#1, main_#t~mem12#1, main_#t~ret13#1, main_#t~mem14#1, main_#t~ret15#1, main_#t~mem18#1, main_#t~mem19#1, main_#t~post17#1, main_#t~post16#1, main_#t~post11#1, main_#t~mem22#1, main_#t~mem23#1, main_#t~post21#1, main_#t~post20#1, main_~n~0#1, main_~#set~0#1.base, main_~#set~0#1.offset, main_~x~0#1, main_~y~0#1, main_~#values~0#1.base, main_~#values~0#1.offset, main_~v~0#1;main_~n~0#1 := 0;call main_~#set~0#1.base, main_~#set~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~x~0#1;havoc main_~y~0#1;main_~x~0#1 := 0; 3855#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 3885#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3886#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 3880#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3881#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 3974#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3973#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 3972#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3971#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 3970#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3969#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 3968#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3967#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 3966#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3965#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 3964#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3963#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 3962#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3961#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 3960#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3959#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 3958#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3957#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 3956#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3955#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 3954#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3953#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 3952#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3951#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 3950#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3949#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 3948#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3947#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 3946#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3945#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 3944#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3943#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 3942#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3941#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 3940#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3939#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 3938#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3937#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 3936#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3935#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 3934#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3933#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 3932#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3931#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 3930#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3929#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 3928#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3927#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 3926#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3925#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 3924#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3923#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 3922#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3921#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 3920#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3919#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 3918#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3917#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 3916#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3915#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 3914#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3913#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 3912#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3911#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 3910#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3909#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 3908#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3907#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 3906#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3905#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 3904#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3903#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 3902#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3901#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 3900#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3899#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 3898#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3897#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 3896#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3895#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 3894#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3893#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 3892#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3891#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 3890#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3889#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 3888#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 3887#L33-3 assume !(main_~x~0#1 < 100000); 3852#L33-4 main_~x~0#1 := 0; 3853#L39-3 assume !(main_~x~0#1 < main_~n~0#1); 3869#L39-4 call main_~#values~0#1.base, main_~#values~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~v~0#1;main_~v~0#1 := 0; 3870#L47-3 [2022-11-16 11:30:46,367 INFO L750 eck$LassoCheckResult]: Loop: 3870#L47-3 assume !!(main_~v~0#1 < 100000);call write~int(main_#t~nondet10#1, main_~#values~0#1.base, main_~#values~0#1.offset + 4 * main_~v~0#1, 4);havoc main_#t~nondet10#1; 3871#L47-2 main_#t~post9#1 := main_~v~0#1;main_~v~0#1 := 1 + main_#t~post9#1;havoc main_#t~post9#1; 3870#L47-3 [2022-11-16 11:30:46,368 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:30:46,368 INFO L85 PathProgramCache]: Analyzing trace with hash -675115004, now seen corresponding path program 4 times [2022-11-16 11:30:46,368 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:30:46,368 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [927700904] [2022-11-16 11:30:46,368 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:30:46,369 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:30:46,436 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:30:48,831 INFO L134 CoverageAnalysis]: Checked inductivity of 2116 backedges. 0 proven. 2116 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:30:48,832 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:30:48,832 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [927700904] [2022-11-16 11:30:48,832 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [927700904] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:30:48,832 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1575492148] [2022-11-16 11:30:48,833 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-16 11:30:48,833 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:30:48,833 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:30:48,839 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:30:48,859 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Waiting until timeout for monitored process [2022-11-16 11:30:49,046 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-16 11:30:49,046 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-16 11:30:49,049 INFO L263 TraceCheckSpWp]: Trace formula consists of 561 conjuncts, 48 conjunts are in the unsatisfiable core [2022-11-16 11:30:49,054 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:30:49,294 INFO L134 CoverageAnalysis]: Checked inductivity of 2116 backedges. 0 proven. 2116 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:30:49,294 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:30:52,492 INFO L134 CoverageAnalysis]: Checked inductivity of 2116 backedges. 0 proven. 2116 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:30:52,492 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1575492148] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:30:52,492 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-16 11:30:52,492 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [49, 49, 49] total 97 [2022-11-16 11:30:52,493 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [264327331] [2022-11-16 11:30:52,493 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-16 11:30:52,493 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:30:52,494 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:30:52,494 INFO L85 PathProgramCache]: Analyzing trace with hash 2851, now seen corresponding path program 4 times [2022-11-16 11:30:52,494 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:30:52,494 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [564871278] [2022-11-16 11:30:52,494 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:30:52,495 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:30:52,511 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:30:52,511 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:30:52,522 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:30:52,524 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:30:52,568 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:30:52,570 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 97 interpolants. [2022-11-16 11:30:52,573 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=4656, Invalid=4656, Unknown=0, NotChecked=0, Total=9312 [2022-11-16 11:30:52,574 INFO L87 Difference]: Start difference. First operand 134 states and 146 transitions. cyclomatic complexity: 17 Second operand has 97 states, 97 states have (on average 2.0103092783505154) internal successors, (195), 97 states have internal predecessors, (195), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:31:06,460 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:31:06,460 INFO L93 Difference]: Finished difference Result 2392 states and 3062 transitions. [2022-11-16 11:31:06,460 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2392 states and 3062 transitions. [2022-11-16 11:31:06,477 INFO L131 ngComponentsAnalysis]: Automaton has 98 accepting balls. 1914 [2022-11-16 11:31:06,490 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2392 states to 2392 states and 3062 transitions. [2022-11-16 11:31:06,491 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2204 [2022-11-16 11:31:06,493 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2204 [2022-11-16 11:31:06,493 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2392 states and 3062 transitions. [2022-11-16 11:31:06,496 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:31:06,496 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2392 states and 3062 transitions. [2022-11-16 11:31:06,498 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2392 states and 3062 transitions. [2022-11-16 11:31:06,509 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2392 to 230. [2022-11-16 11:31:06,509 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 230 states, 230 states have (on average 1.0521739130434782) internal successors, (242), 229 states have internal predecessors, (242), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:31:06,511 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 230 states to 230 states and 242 transitions. [2022-11-16 11:31:06,511 INFO L240 hiAutomatonCegarLoop]: Abstraction has 230 states and 242 transitions. [2022-11-16 11:31:06,516 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 96 states. [2022-11-16 11:31:06,517 INFO L428 stractBuchiCegarLoop]: Abstraction has 230 states and 242 transitions. [2022-11-16 11:31:06,517 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-11-16 11:31:06,517 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 230 states and 242 transitions. [2022-11-16 11:31:06,519 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 34 [2022-11-16 11:31:06,519 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:31:06,519 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:31:06,528 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [94, 94, 1, 1, 1, 1, 1, 1] [2022-11-16 11:31:06,540 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-16 11:31:06,541 INFO L748 eck$LassoCheckResult]: Stem: 7085#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(48, 2); 7062#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet4#1, main_#t~post3#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post6#1, main_#t~post5#1, main_#t~nondet10#1, main_#t~post9#1, main_#t~mem12#1, main_#t~ret13#1, main_#t~mem14#1, main_#t~ret15#1, main_#t~mem18#1, main_#t~mem19#1, main_#t~post17#1, main_#t~post16#1, main_#t~post11#1, main_#t~mem22#1, main_#t~mem23#1, main_#t~post21#1, main_#t~post20#1, main_~n~0#1, main_~#set~0#1.base, main_~#set~0#1.offset, main_~x~0#1, main_~y~0#1, main_~#values~0#1.base, main_~#values~0#1.offset, main_~v~0#1;main_~n~0#1 := 0;call main_~#set~0#1.base, main_~#set~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~x~0#1;havoc main_~y~0#1;main_~x~0#1 := 0; 7063#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7093#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7094#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7088#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7089#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7278#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7277#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7276#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7275#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7274#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7273#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7272#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7271#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7270#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7269#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7268#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7267#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7266#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7265#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7264#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7263#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7262#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7261#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7260#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7259#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7258#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7257#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7256#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7255#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7254#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7253#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7252#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7251#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7250#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7249#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7248#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7247#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7246#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7245#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7244#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7243#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7242#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7241#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7240#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7239#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7238#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7237#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7236#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7235#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7234#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7233#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7232#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7231#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7230#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7229#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7228#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7227#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7226#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7225#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7224#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7223#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7222#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7221#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7220#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7219#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7218#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7217#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7216#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7215#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7214#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7213#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7212#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7211#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7210#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7209#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7208#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7207#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7206#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7205#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7204#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7203#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7202#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7201#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7200#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7199#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7198#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7197#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7196#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7195#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7194#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7193#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7192#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7191#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7190#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7189#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7188#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7187#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7186#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7185#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7184#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7183#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7182#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7181#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7180#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7179#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7178#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7177#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7176#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7175#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7174#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7173#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7172#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7171#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7170#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7169#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7168#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7167#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7166#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7165#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7164#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7163#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7162#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7161#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7160#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7159#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7158#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7157#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7156#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7155#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7154#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7153#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7152#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7151#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7150#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7149#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7148#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7147#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7146#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7145#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7144#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7143#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7142#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7141#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7140#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7139#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7138#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7137#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7136#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7135#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7134#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7133#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7132#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7131#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7130#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7129#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7128#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7127#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7126#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7125#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7124#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7123#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7122#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7121#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7120#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7119#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7118#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7117#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7116#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7115#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7114#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7113#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7112#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7111#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7110#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7109#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7108#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7107#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7106#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7105#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7104#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7103#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7102#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7101#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7100#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7099#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7098#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7097#L33-3 assume !!(main_~x~0#1 < 100000);call write~int(main_#t~nondet4#1, main_~#set~0#1.base, main_~#set~0#1.offset + 4 * main_~x~0#1, 4);havoc main_#t~nondet4#1; 7096#L33-2 main_#t~post3#1 := main_~x~0#1;main_~x~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 7095#L33-3 assume !(main_~x~0#1 < 100000); 7060#L33-4 main_~x~0#1 := 0; 7061#L39-3 assume !(main_~x~0#1 < main_~n~0#1); 7077#L39-4 call main_~#values~0#1.base, main_~#values~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~v~0#1;main_~v~0#1 := 0; 7078#L47-3 [2022-11-16 11:31:06,541 INFO L750 eck$LassoCheckResult]: Loop: 7078#L47-3 assume !!(main_~v~0#1 < 100000);call write~int(main_#t~nondet10#1, main_~#values~0#1.base, main_~#values~0#1.offset + 4 * main_~v~0#1, 4);havoc main_#t~nondet10#1; 7079#L47-2 main_#t~post9#1 := main_~v~0#1;main_~v~0#1 := 1 + main_#t~post9#1;havoc main_#t~post9#1; 7078#L47-3 [2022-11-16 11:31:06,542 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:31:06,542 INFO L85 PathProgramCache]: Analyzing trace with hash -1064733596, now seen corresponding path program 5 times [2022-11-16 11:31:06,542 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:31:06,542 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1179101247] [2022-11-16 11:31:06,542 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:31:06,543 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:31:06,761 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:31:14,108 INFO L134 CoverageAnalysis]: Checked inductivity of 8836 backedges. 0 proven. 8836 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:31:14,108 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:31:14,108 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1179101247] [2022-11-16 11:31:14,108 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1179101247] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:31:14,109 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [682483473] [2022-11-16 11:31:14,109 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-16 11:31:14,109 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:31:14,109 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:31:14,111 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:31:14,113 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_568afa64-5eee-4e8c-b368-3c31979c0d46/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Waiting until timeout for monitored process